Imaging device and control method thereof

Abstract

The present invention provides an imaging apparatus and a control method thereof that can suppress image distortion caused by shutter operation while suppressing shutter operation delay. [Solution] The imaging device according to this embodiment includes a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal, a holding circuit that holds the pixel signal transferred from the photoelectric conversion unit, a plurality of pixels that can be specified by address, an AD conversion unit that AD converts the pixel signal into a digital signal, a first drive unit that reads a pixel signal from at least one pixel specified by address among the plurality of pixels to the AD conversion unit, and a controller that, when a first command to expose the plurality of pixels next is received during the AD conversion of the first pixel signal from at least one selected pixel specified by a first address among the addresses, specifies the selected pixel of the first address again after the elapsed of a first period.

Description

Technical Field

[0001] The present disclosure relates to an imaging device and a control method thereof.

Background Art

[0002] A CMOS (Complementary Metal Oxide Semiconductor) image sensor (hereinafter also referred to as CIS) may adopt a global shutter method (hereinafter referred to as GS method) in which an exposure operation is performed for all pixels at once.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the case of a GS method CIS, since the load on the power supply temporarily changes by performing a shutter operation for all pixels at once, the power supply voltage of the pixels fluctuates due to the shutter operation. When the shutter operation is executed during the AD (Analogue-to-Digital) conversion of the pixel signal reading, a phenomenon (shutter step) occurs in which the pixel signal being read changes due to the fluctuation of the power supply voltage caused by the shutter operation. The shutter step causes image distortion.

[0005] On the other hand, in order to suppress the shutter step, it is conceivable to delay the start of the shutter operation until the period of the AD conversion of the pixel signal ends when a trigger signal for the shutter operation is input. However, in this case, the delay from when the trigger signal is input until the shutter operation is executed becomes a problem.

[0006] ​This technology was developed in consideration of these challenges, and provides an imaging device and a control method therefor that can suppress image distortion caused by shutter operation while suppressing shutter operation delay. [Means for solving the problem]

[0007] An imaging device according to one aspect of this disclosure includes a photoelectric conversion unit that photoelectrically converts incident light into pixel signals, a holding circuit that holds the pixel signals transferred from the photoelectric conversion unit, a plurality of pixels that can be specified by address, an AD conversion unit that AD converts the pixel signals into digital signals, a first drive unit that reads a pixel signal from at least one pixel specified by address among the plurality of pixels to the AD conversion unit, and a controller that, if a first command to expose the plurality of pixels next is received during the AD conversion of the first pixel signal from at least one selected pixel specified by a first address among the addresses, re-specifies the selected pixel of the first address after the elapsed of a first period.

[0008] The imaging device further includes a signal processing circuit that disables the output of the first digital signal obtained by A / D conversion of the first pixel signal.

[0009] The imaging device further includes a signal processing circuit that processes a second digital signal obtained by re-specifying the selected pixel at the first address after the first period has elapsed as a valid signal.

[0010] When the controller receives the first command, it performs the exposure of multiple pixels without delay.

[0011] The holding circuit includes first and second capacitor elements, one end of which is connected to a photoelectric conversion unit and capable of receiving a pixel signal and holding the voltage of the pixel signal; a first switching element provided between the gate of an amplifying transistor that amplifies the pixel signal and outputs it to an AD conversion unit and the other end of the first capacitor element; and a second switching element provided between the other end of the second capacitor element and the gate of the amplifying transistor.

[0012] The holding circuit includes a first switch element and a second switch element connected in series between the gate of an amplifying transistor that amplifies the pixel signal and outputs it to an AD conversion unit and a photoelectric conversion unit; a first capacitive element with one end connected to a first node between the gate of the amplifying transistor and the first switch element and the other end connected to a reference voltage source; and a second capacitive element with one end connected to a second node between the first switch element and the second switch element and the other end connected to a reference voltage source.

[0013] The AD conversion unit includes a plurality of comparators that compare the pixel signal with a reference signal and invert the output signal based on the voltage between the pixel signal and the reference signal; a plurality of counters provided in correspondence with each of the plurality of comparators, which count the time from the start of driving the reference signal until the output signals of the plurality of comparators are inverted and generate a count value; and a plurality of latch circuits provided in correspondence with each of the plurality of counters, which hold the count value of the pixel in the reset state.

[0014] The counter generates a count value for the first reset signal of a pixel in the reset state of the photoelectric conversion unit among the first pixel signals, and then generates a count value for the first data signal corresponding to the exposure amount of the pixel in the exposure state. Multiple latch circuits hold the count value of the first reset signal, and if the next first command is received during the AD conversion of the first reset signal, the controller re-specifies the selected pixel at the first address after the first period has elapsed.

[0015] If the controller receives the next first command while the first reset signal is being converted to AD, it will not perform the first data signal's AD conversion.

[0016] The counter generates a count value for the first reset signal of the pixel in the reset state among the first pixel signals, and then generates a count value for the first data signal of the pixel in the exposure state. Multiple latch circuits hold the count values ​​of the first reset signal. When the next first command is received during the AD conversion of the first data signal, the controller sets the count values ​​held by the multiple latch circuits in the counter. When the controller again specifies the selected pixel at the first address, the counter counts the first data signal without counting the first reset signal.

[0017] The counter counts the first data signal by subtracting it from the count value of the first reset signal. Alternatively, another latching circuit takes the difference between the count value of the first data signal and the count value of the first reset signal.

[0018] The first period is the time from the start of exposure of multiple pixels until the voltage sources of the multiple pixels fall within a predetermined range.

[0019] A method for manufacturing an imaging device according to one aspect of the present disclosure includes a plurality of pixels that can be specified by address, including a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal and a holding circuit that holds the pixel signal transferred from the photoelectric conversion unit, an AD conversion unit that AD converts the pixel signal into a digital signal, a first drive unit that reads a pixel signal from at least one pixel specified by an address among the plurality of pixels to the AD conversion unit, and a controller that controls the AD conversion unit and the first drive unit, wherein if a first command to expose the plurality of pixels next is received during the AD conversion of the first pixel signal from at least one selected pixel specified by a first address among the addresses, the selected pixel is specified again by the first address after the first period has elapsed.

[0020] The manufacturing method further comprises invalidating the first digital signal obtained by performing AD conversion on the first pixel signal.

[0021] The manufacturing method further comprises processing, as a valid signal, a second digital signal obtained by re-designating a selected pixel at a first address after the elapse of a first period.

[0022] The manufacturing method further comprises, when receiving a first command, executing exposure of a plurality of pixels without delay.

[0023] The AD conversion unit includes a plurality of comparators that compare a pixel signal with a reference signal and invert an output signal based on the voltages of the pixel signal and the reference signal, a plurality of counters provided corresponding to each of the plurality of comparators, counting the time from the start of driving of the reference signal until the output signals of the plurality of comparators are inverted to generate a count value, and a plurality of latch circuits provided corresponding to each of the plurality of counters, holding the count value of the pixel in the reset state. The AD conversion unit generates a count value of a first reset signal of a pixel in the reset state among first pixel signals, holds the count value of the first reset signal in the plurality of latch circuits, and generates a count value of a first data signal of a pixel in the exposure state. When receiving a next first command during the AD conversion of the first reset signal, after the elapse of a first period, the selected pixel is re-designated at a first address.

[0024] The manufacturing method, when receiving a next first command during the AD conversion of the first data signal, sets the count value held in the plurality of latch circuits to the counter, and when re-designating the selected pixel at the first address, counts the first data signal without counting the first reset signal.

[0025] The manufacturing method further comprises counting the first data signal so as to subtract from the count value of the first reset signal, or taking a difference between the count value of the first data signal and the count value of the first reset signal.

Brief Description of the Drawings

[0026] [Figure 1] A block diagram showing a configuration example of an imaging device according to a first embodiment. [Figure 2] A conceptual diagram showing an example of an imaging device in which semiconductor chips for the pixel section and semiconductor chips for the processing circuit are stacked. [Figure 3] A circuit diagram showing an example of the internal configuration of a pixel according to the first embodiment. [Figure 4] A timing diagram showing an example of the operation of the imaging device according to the first embodiment. [Figure 5] A block diagram showing an example configuration of an imaging device according to the second embodiment. [Figure 6] A circuit diagram showing an example of the internal configuration of a pixel according to the second embodiment. [Figure 7] A timing diagram showing an example of the operation of the imaging device according to the second embodiment. [Figure 8] A timing diagram showing an example of the operation of the imaging device according to the second embodiment. [Figure 9] This timing diagram shows the operation of the comparator and counter when a trigger signal is activated during the reading (AD conversion) of the data signal shown in Figure 8. [Figure 10] This timing diagram shows the operation of the comparator and counter when a trigger signal is activated during the reading (AD conversion) of the data signal shown in Figure 8. [Modes for carrying out the invention]

[0027] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0028] (First Embodiment) Figure 1 is a block diagram showing an example configuration of the imaging device 100 according to the first embodiment. The imaging device 100 is a VDGS (Voltage Domain GS) type CIS used, for example, in industrial machinery. The VDGS type CIS is a GS type CIS that holds the voltage of the pixel signal and performs AD conversion for readout based on the held voltage.

[0029] The imaging device 100 includes a pixel unit 101, a controller 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) group 105, a horizontal transfer scanning circuit 106, and a signal processing circuit 108.

[0030] The pixel section 101 has a matrix arrangement of unit pixels (hereinafter also simply referred to as pixels), each containing a photoelectric conversion unit that converts incident light into an electric charge (pixel signal) corresponding to the amount of light. The specific circuit configuration of the unit pixels will be described later with reference to Figure 2. In addition, for each row of the matrix-like pixel array in the pixel section 101, pixel drive lines 109 are wired along the left-right direction in the figure (the pixel array direction of the pixel row / horizontal direction), and vertical signal lines 110 are wired along the up-down direction in the figure (the pixel array direction of the pixel column / vertical direction). One end of each pixel drive line 109 is connected to the output terminal of the vertical scanning circuit 103 corresponding to each row. The pixel drive lines 109 can be selected by address, and although Figure 1 shows one pixel drive line 109 per pixel row, two or more pixel drive lines 109 may be provided for each pixel row.

[0031] The controller 102 generates various control signals at predetermined timings. Based on the externally supplied signal CTL, the controller 102 generates various control signals and performs drive control of the vertical scanning circuit 103, DAC 104, ADC group 105, and horizontal transfer scanning circuit 106, etc.

[0032] The vertical scanning circuit 103 is composed of a shift register, an address decoder, and the like. The vertical scanning circuit 103 selectively drives one or more pixel drive lines 109 based on an address from the controller 102. As a result, the vertical scanning circuit 103 reads a pixel signal from at least one pixel specified by the address among the multiple pixels of the pixel unit 101 to the AD conversion unit. The specific configuration is not shown in the diagram, but the vertical scanning circuit 103 includes a read scanning system and a sweep scanning system.

[0033] The readout scanning system sequentially selects and scans each unit pixel in row order to read out the signal. Meanwhile, the sweep system sweeps out (resets) unwanted charges from the photoelectric conversion unit of all effective pixels in the pixel unit 101 all at once. By controlling the sweeping (reset) of unwanted charges by this sweep system, a so-called simultaneous electronic shutter operation for all effective pixels is performed. Here, electronic shutter operation refers to the operation of stopping the discharge of photoelectric charge from a state in which photoelectric charge is continuously discharged and starting a new exposure. The readout scanning starts after raising the readout operation trigger signal (XTRIG in Figure 4) and transferring the reset signal and data signal of the pixel signals of all effective pixels in the pixel unit 101 all at once to the sample-and-hold circuit (20 in Figure 3). After transferring the pixel signals to the sample-and-hold circuit 20, the readout scanning reads the pixel signals to the ADC group 105 by scanning each pixel row. The sweep operation begins after the shutter trigger signal (XTRIG in Figure 4) rises, and the reset signal and data signal are transferred to the sample-and-hold circuit (20 in Figure 3). The sweep operation is constantly performed while the control signal OFG in Figure 4 is rising. The sweep operation stops when the trigger signal XTRIG falls. The signal read out by the readout scanning system corresponds to the amount of light incident since the electronic shutter operation. The period from the end of the previous batch sweep operation by the electronic shutter to the end of the transfer of the pixel signals of all effective pixels to the sample-and-hold circuit (20 in Figure 3) becomes the photocharge accumulation time (exposure time) at a unit pixel.

[0034] The pixel signal SIG (analog signal) output from each unit pixel of the pixel row selected and scanned by the vertical scanning circuit 103 is supplied to the ADC group 105 via a plurality of vertical signal lines 110 corresponding to each column.

[0035] DAC104 generates a linearly changing ramp waveform reference signal RAMP and supplies it to ADC group 105. DAC104 is commonly connected to multiple comparators 121 via a reference signal line 114, and supplies the same reference signal RAMP to multiple comparators 121.

[0036] The ADC group 105 comprises multiple comparators 121, multiple counters 122, and multiple latch circuits 123. The ADC group 105 converts the pixel signal (analog signal) from the pixel unit 101 into a digital signal.

[0037] The comparator 121, counter 122, and latch circuit 123 are each provided corresponding to the pixel rows of the pixel section 101, and constitute an ADC.

[0038] The comparator 121 compares the pixel signal SIG output from each pixel with the reference signal RAMP and supplies an output signal indicating the comparison result to the counter 122. The comparator 121 inverts the output signal based on the relative voltages of the pixel signal SIG and the reference signal RAMP.

[0039] Counter 122 is provided in correspondence with comparator 121. Counter 122 receives the output signal of comparator 121 and counts the time from the start of driving the reference signal RAMP until the output signal of comparator 121 inverts, thereby generating a count value. This converts the analog pixel signal SIG into a digital signal represented by the count value. Counter 122 supplies the count value to latch circuit 123. Counter 122 counts the count value of the reset signal corresponding to the pixel signal at the reset level of the pixel, and then counts the data signal corresponding to the signal level of the pixel signal, subtracting this count value from the reset signal. In this way, counter 122 performs CDS (Correlated Double Sampling) between the reset signal and the data signal. Counter 122 may also count the reset signal and the data signal separately and perform CDS processing in latch circuit 123.

[0040] The latch circuit 123 holds the count value obtained by the CDS process, which is supplied from the counter 122. Alternatively, the latch circuit 123 may hold the count value of the data signal corresponding to the signal level of the pixel signal from the counter 122, and the count value of the reset signal corresponding to the reset level of the pixel signal from the counter 122, and perform CDS by taking the difference between the two.

[0041] The horizontal transfer scanning circuit 106 is composed of a shift register, an address decoder, and the like, and sequentially selects and scans the circuit portion corresponding to the pixel sequence of the ADC group 105 according to the address. Through this selective scanning by the horizontal transfer scanning circuit 106, the digital signals held in the latch circuit 123 are sequentially transferred to the signal processing circuit 108 via the horizontal transfer line 111.

[0042] The signal processing circuit 108 performs predetermined signal processing on the digital signals supplied from the ADC group 105 to generate two-dimensional image data. For example, the signal processing circuit 108 may correct vertical line defects or point defects, clamp the signal, or perform digital signal processing such as parallel-to-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 can also choose not to output any digital signal, invalidate it, and exclude it from the image data. In this case, the signal processing circuit 108 may invalidate the digital signal by not outputting it, or it may output invalid row information along with the digital signal. Invalid row information is row address information that accompanies the digital signal and indicates that the digital signal is invalid. The signal processing circuit 108 outputs the generated image data to a subsequent device.

[0043] The imaging device 100 shown in Figure 1 may be configured as a single semiconductor chip, or it may be configured as multiple semiconductor chips. When the imaging device 100 is configured as multiple semiconductor chips, the pixel section 101 and the other processing circuits may be formed as separate semiconductor chips 511 and 512, respectively, and semiconductor chip 511 and semiconductor chip 512 may be stacked.

[0044] For example, Figure 2 is a conceptual diagram showing an example of an imaging device 100 in which a semiconductor chip 511 of the pixel section 101 and a semiconductor chip 512 of the processing circuit are stacked. As shown in Figure 2, the imaging device 100 is composed of two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0045] The semiconductor chip 511 includes a pixel section 101 formed on a semiconductor substrate. The semiconductor chip 512 includes an ADC group 105, a logic circuit 516, and peripheral circuits 517 formed on another semiconductor substrate. The logic circuit 516 includes a controller 102, a vertical scanning circuit 103, a DAC 104, a horizontal transfer scanning circuit 106, etc. The peripheral circuits 517 include a processing circuit 108, etc.

[0046] Each pixel of the pixel section 101 of semiconductor chip 511 and the elements of the processing circuits (105, 516, 517) of semiconductor chip 512 may be electrically connected using through-electrodes such as TSVs (Through Silicon Vias) provided in via regions 513 and 514. The ADC group 105 can transmit and receive signals with the pixel section 101 via the TSVs. Alternatively, the two semiconductor chips may be bonded together so that the wiring of semiconductor chip 511 and the wiring of semiconductor chip 512 are in contact (Cu-Cu junction). Furthermore, although not shown, the pixel section 101 and a part of the processing circuits (105, 516, 517) may be configured as a single semiconductor chip 511, and the remaining components may be configured as other semiconductor chips 512.

[0047] Figure 3 is a circuit diagram showing an example of the internal configuration of a pixel according to the first embodiment. The pixel PX includes a photoelectric conversion unit 10 and a sample-and-hold circuit (hereinafter referred to as SH circuit) 20 as a holding unit.

[0048] The photoelectric conversion unit 10 photoelectrically converts incident light into a pixel signal SIG with a charge amount corresponding to the amount of light. The photoelectric conversion unit 10 comprises a photodiode PD, a transfer transistor Ttrg, a reset transistor Trst, an overflow transistor Tofg, an amplification transistor Tamp1, and load transistors Tpc,Tvb.

[0049] A photodiode PD generates and retains an electric charge corresponding to the amount of incident light. The anode of the photodiode PD is connected to a reference voltage source, and its cathode is connected to the drain of a transfer transistor Ttrg.

[0050] The transfer transistor Ttrg is connected between the photodiode PD and the gate of the amplification transistor Tamp1. The gate of the transfer transistor Ttrg receives the control signal TRG. When the control signal TRG is activated, the transfer transistor Ttrg transfers the charge accumulated in the photodiode PD to its gate.

[0051] The reset transistor Trst is connected between the voltage source VDD and the gate of the amplification transistor Tamp1. The gate of the reset transistor Trst receives the control signal RST. When the control signal RST is activated, the reset transistor Trst resets the gate voltage of the amplification transistor Tamp1 by removing the charge from its gate.

[0052] The overflow transistor Tofg is connected between the voltage source VDD and the photodiode PD or transfer transistor Ttrg. The gate of the overflow transistor Tofg receives the control signal OFG. When the control signal OFG is activated, the overflow transistor Tofg sweeps out the charge accumulated in the photodiode PD.

[0053] The amplification transistor Tamp1 is connected between the voltage source VDD and node N1. The gate of amplification transistor Tamp1 is connected to one end of the transfer transistor Ttrg and the reset transistor Trst, respectively.

[0054] Transistors Tpc and Tvb are connected in series between node N1 and the reference voltage source. The gate of transistor Tpc receives the control signal PC. Transistor Tpc conducts during amplification. Transistor Tvb is the load transistor. The gate of transistor Tvb receives the control signal VB and functions as a constant current source, supplying a predetermined constant current to the amplification transistor Tamp1. Transistor Tpc functions as a switch to control the constant current source function of the load transistor Tvb. By functioning as a constant current source during amplification, transistor Tvb sets the voltage at node N1 to a voltage corresponding to the conduction state of amplification transistor Tamp1.

[0055] The SH circuit 20 is provided between the photoelectric conversion unit 10 and the gate of the amplification transistor Tamp2. The SH circuit 20 temporarily holds the voltage of the pixel signal transferred from the photoelectric conversion unit 10. The SH circuit 20 comprises a first capacitance element C1, a second capacitance element C2, a transistor Ts1, and a transistor Ts2.

[0056] One end of the first capacitance element C1 is connected to the photoelectric conversion unit 10. The first capacitance element C1 receives a pixel signal transferred from the photoelectric conversion unit 10 and is capable of holding the voltage of the pixel signal. The other end of the first capacitance element C1 is connected to one end of the transistor Ts1.

[0057] One end of the second capacitance element C2 is connected to the photoelectric conversion unit 10 in common with one end of the first capacitance element C1. The second capacitance element C2 receives a pixel signal transferred from the photoelectric conversion unit 10 and is capable of holding the voltage of the pixel signal. The other end of the second capacitance element C2 is connected to one end of the transistor Ts2.

[0058] The transistor Ts1, acting as the first switching element, is connected between the other end of the first capacitance element C1 and the gate (node ​​N2) of the amplification transistor Tamp2. The gate of transistor Ts1 receives the control signal S1.

[0059] The transistor Ts2, acting as a second switching element, is connected between the other end of the second capacitance element C2 and the gate of the amplification transistor Tamp2. The gate of transistor Ts2 receives the control signal S2.

[0060] Thus, the first capacitance element C1 and transistor Ts1 are connected in series between node N1 and node N2. The second capacitance element C2 and transistor Ts2 are connected in series between node N1 and node N2. The first capacitance element C1 and transistor Ts1 are connected in parallel to the second capacitance element C2 and transistor Ts2.

[0061] When the SH circuit 20 receives a pixel signal from node N1 or outputs a pixel signal to node N2, both control signals S1 and S2 are never activated simultaneously. When one of the control signals S1 or S2 is activated, the other is inactive. That is, when one of the transistors Ts1 or Ts2 is in the ON state (conducting state), the other is in the OFF state (non-conducting state).

[0062] For example, when transferring a reset signal to the first capacitance element C1, the reset signal is read to node N1 with transistor Tpc turned off and transistor Ts1 turned on. In this state, when transistor Ts1 is turned off from on, the first capacitance element C1 retains the reset signal. At this time, transistor Ts2 remains off. When transferring a data signal to the second capacitance element C2, the data signal is read to node N1 with transistor Tpc turned off and transistor Ts2 turned on. In this state, when transistor Ts2 is turned off from on, the second capacitance element C2 retains the data signal. At this time, transistor Ts1 remains off.

[0063] Furthermore, when reading the reset signal held in the first capacitance element C1, transistor Ts1 turns ON. At this time, transistor Ts2 remains OFF. When reading the data signal held in the second capacitance element C2, transistor Ts2 turns ON. At this time, transistor Ts1 remains OFF.

[0064] Pixel PX further comprises a reset transistor TRSTb, an amplification transistor Tamp2, a selection transistor Tsel, and a load current source LD.

[0065] The reset transistor TRSTB is connected between the voltage source VREG and node N2. The gate of the reset transistor TRSTB receives the control signal RSTB. The reset transistor TRSTB is provided to reset the gate voltage of the amplification transistor Tamp to the voltage of the voltage source VREG.

[0066] The amplification transistor Tamp2 is connected between the voltage source VDD and the selection transistor Tsel. The gate of amplification transistor Tamp2 is connected to the SH circuit 20 as node N2. Amplification transistor Tamp2 amplifies the pixel signal held in the first capacitance element C1 or the second capacitance element C2.

[0067] The selection transistor Tsel is connected between the amplification transistor Tamp2 and the vertical signal line 110. The gate of the selection transistor Tsel is connected to the vertical scanning circuit 103 and receives the control signal SEL. The control signal SEL is activated, for example, to a high level by being specified by address by the vertical scanning circuit 103. When the control signal SEL is activated, the selection transistor Tsel turns on, and the load current source LD supplies a constant current to the amplification transistor Tamp2. As a result, the voltage across the vertical signal line 110 becomes a voltage corresponding to the gate voltage of the amplification transistor Tamp2 (voltage at node N2). That is, the vertical signal line 110 transmits a voltage corresponding to the pixel signal to the ADC group 105.

[0068] The load current source LD is connected between the vertical signal line 110 and the reference voltage source. The load current source LD is configured to supply a constant current to the amplification transistor Tamp2. The load current source LD may be composed of, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

[0069] The transistors Ttrg, Trst, Tamp1, Tpc, Tvb, Ts1, Ts2, Trstb, Tamp2, and Tsel may be composed of, for example, N-type MOSFETs. The first and second capacitance elements C1 and C2 may be capacitors such as MIM (Metal-Insulator-Metal).

[0070] Next, the operation of the imaging device 100 according to this embodiment will be described.

[0071] Figure 4 is a timing diagram showing an example of operation of the imaging device according to the first embodiment. The imaging device 100 operates in synchronization with the synchronization signal XHS.

[0072] The trigger signal XTRIG is a signal that instructs the start and end of exposure for the pixel unit 101. The imaging device 100 receives the trigger signal XTRIG from an external source. The controller 102, for example, starts exposure for the pixel unit 101 in response to the falling edge of the trigger signal XTRIG, and stops exposure when the data signal is transferred to the SH circuit 20 in response to the rising edge of the trigger signal XTRIG.

[0073] The AD conversion cycle is the period during which the pixel signals from one or more selected pixels selected by the vertical scanning circuit 103 are converted using the AD conversion method during the readout operation. When the controller 102 performs AD conversion on the pixel signals of the pixel section 101 obtained by one exposure (shutter operation), it sequentially specifies the address of each pixel drive line 109. At this time, the controller 102 specifies the address of one pixel drive line 109 at a time for each AD conversion cycle.

[0074] The control signal OFG, when rising, turns on the overflow transistor Tofg and performs a sweep operation to remove the charge accumulated in the photodiode PD. The period outside of the sweep operation is the exposure period of the photodiode PD. When the control signal OFG falls, it turns off the overflow transistor Tofg and starts the exposure operation of the photodiode PD. In other words, the exposure (charge accumulation) of the photodiode PD starts when the sweep operation is completed, and the exposure (charge accumulation) of the photodiode PD stops when the sweep operation is started.

[0075] The READ operation generates a digital signal by performing an A / D conversion on the pixel signal (analog value) from the selected pixel, and then reads that digital signal from the latch circuit 123 to the signal processing circuit 108. In the READ operation, the vertical scanning circuit 103 selectively drives the pixel drive line 109 for each address specified by the controller 102, and transmits the pixel signal of the selected pixel connected to the pixel drive line 109 to the ADC group 105. The pixel signals of the selected pixels specified by one address are simultaneously A / D converted and temporarily held in the latch circuit 123. Then, the horizontal transfer scanning circuit 106 selects and scans the pixel sequence of the ADC group 105 in order, thereby transferring the digital signal from the latch circuit 123 to the signal processing circuit 108.

[0076] BLANK indicates the communication time for commands and control signals. RTRANS is the period during which the reset signal from the pixel signals of each pixel PX is held in the SH circuit 20 of each pixel PX. For example, during the RTRANS period, the reset signal is held in the first capacitive element C1 in Figure 3. DTRANS is the period during which the data signal from the pixel signals of each pixel PX is held in the SH circuit 20 of each pixel PX. For example, during the DTRANS period, the data signal is held in the second capacitive element C2 in Figure 3. READ is the period during which the pixel signals (reset signal and data signal) held in the SH circuit 20 of each pixel PX of the pixel unit 101 are read out. At this time, the above read operation READ is executed for each pixel drive line 109 specified by the address. In the read operation READ, the reset signal from the pixel signals of the selected pixel is AD converted, and then the data signal is AD converted. The counter 122 reverses the direction of count increase and decrease so as to take the difference between the count value of the reset signal and the count value of the data signal. As a result, the latch circuit 123 holds a digital signal obtained by subtracting the reset signal from the data signal (CDS-processed).

[0077] Prior to t0, the overflow transistor Tofg is turned off, and exposure EXP0 is performed. Since it is a GS method, all pixels PX of the pixel section 101 are exposed, and charge is accumulated in the photodiode PD of each pixel PX.

[0078] At t0, the trigger signal XTRIG rises. This causes the overflow transistor Tofg to turn on at t3, ending the exposure EXP0.

[0079] At time t1, transistor Ts1 in Figure 3 turns ON, and the reset signal is held in the first capacitance element C1. At this time, the transfer transistor Ttrg in Figure 3 remains OFF, and the voltage at node N1 is the voltage corresponding to the reset signal.

[0080] At t2, transistor Ts2 in Figure 3 turns ON, and the data signal is held in the second capacitance element C2. At this time, transfer transistor Ttrg in Figure 3 turns ON, and the voltage at node N1 is the voltage corresponding to the data signal.

[0081] At t3, after exposure EXP0 is completed, at t4, a read operation READ is performed on the pixel signals (reset signal and data signal) obtained in exposure EXP0 and held in the SH circuit 20.

[0082] In the read operation, the controller 102 specifies one address for each AD conversion cycle. The vertical scanning circuit 103 selectively drives the pixel drive line 109 for each specified address and transmits the pixel signal of the selected pixel connected to that pixel drive line 109 to the ADC group 105. The ADC group 105 performs AD conversion on the pixel signal of the corresponding selected pixel and holds the converted digital signal.

[0083] For example, controller 102 specifies addresses "254", "255", "256", etc. in order. At this time, during the reading (AD conversion) of address "256" in t5~t6 (tx), the trigger signal XTRIG falls and is activated. In this embodiment, when the trigger signal XTRIG is activated, controller 102 immediately starts the exposure EXP1 of the pixel unit 101 without delaying, without waiting for the reading operation to finish. In this case, there is a risk that a shutter step will occur in the pixel signal and digital signal of address "256".

[0084] In contrast, in this embodiment, the signal processing circuit 108 does not output the digital signal at address "256" that was specified when the trigger signal XTRIG was activated. As a result, the digital signal at address "256" that includes the shutter step is removed from the image. Alternatively, if invalid line information is output along with the digital signal, the signal processing circuit 108 outputs the digital signal at address "256" that was specified when the trigger signal XTRIG was activated together with the invalid line information. As a result, the digital signal at address "256" that includes the shutter step can be identified as a digital signal that includes the shutter step in the image. As a result, the digital signal at address "256" that includes the shutter step can be removed from the image.

[0085] At time tx, after the exposure EXP1 has started, the controller 102 waits for a period (first period) tx to t7 until the power supply voltage (VDD voltage) of the pixel unit 101 falls within a predetermined range and stabilizes. The period tx to t7 may be a preset period.

[0086] After the power supply voltage stabilizes, at t7-t8, the controller 102 re-specifies the selected pixel at address "256". In other words, if the imaging device 100 receives an external trigger signal XTRIG while performing AD conversion on the pixel signal from the selected pixel at address "256", the controller 102 immediately starts exposure EXP1 and, after the power supply voltage stabilizes, re-specifies address "256". At this time, exposure EXP1 has started, but the SH circuit 20 in Figure 3 holds the pixel signal (reset signal and data signal) corresponding to the previous EXP0. Therefore, by re-specifying address "256", the pixel signal at address "256" corresponding to exposure EXP0 can be AD-converted again and read out.

[0087] The signal processing circuit 108 uses the digital signal at address "256", which was specified again in t7-t8, as a signal effective for image generation. The digital signal at address "256", read again in t7-t8, does not contain shutter step. Therefore, the signal processing circuit 108 can generate a high-quality image without shutter step.

[0088] In t8~t9, the controller 102 reads out (performs AD conversion on) the corresponding pixel signals by specifying addresses from "257" onwards. In t9, the reading of the pixel signal corresponding to exposure EXP0 is completed.

[0089] At t10, the trigger signal XTRIG rises and is deactivated. Accordingly, the exposure period ends at t11.

[0090] Thus, according to this embodiment, if the controller 102 receives a trigger signal XTRIG as a command for the next exposure while performing AD conversion of a pixel signal from a selected pixel specified by an address "256", it specifies the same address "256" again after the stabilization period of the voltage source VDD has elapsed. The SH circuit 20 according to this embodiment can retain the reset signal and data signal non-destructively even after reading them out. As a result, the digital signal at address "256" can be AD converted again and read out without shutter step. The signal processing circuit 108 invalidates the digital signal at address "256" that was read out the first time and includes shutter step, and effectively uses the digital signal at address "256" that was read out the second time and does not include shutter step. It is not a problem if the digital signal at address "256" read out the first time includes shutter step. Furthermore, when the trigger signal XTRIG is activated, the imaging device 100 can immediately execute the shutter operation without waiting for the shutter to operate, thereby exposing the pixel section 101. As a result, the imaging device 100 can suppress image distortion caused by the shutter operation while suppressing shutter operation delays. However, since the digital signal of one line corresponding to address "256" is reread, a readout delay of one line will occur.

[0091] (Second Embodiment) Figure 5 is a block diagram showing an example configuration of the imaging device 100 according to the second embodiment. The imaging device 100 according to the second embodiment further includes a plurality of latch circuits 112. Each latch circuit 112 is provided in correspondence with each of the plurality of counters 122. The latch circuit 112 can receive and hold the count value of the pixel PX in the reset state (the count value of the reset signal) from the corresponding counter 122. The latch circuit 112 can also output the held count value of the reset signal to the corresponding counter 122 and set it in the counter 122.

[0092] Figure 6 is a circuit diagram showing an example of the internal configuration of a pixel according to the second embodiment. Pixel PX includes a photoelectric conversion unit 10 and an SH circuit 20.

[0093] The configuration of the photoelectric conversion unit 10 is the same as that of the first embodiment. Note that the load transistors Tpc and Tvb in the first embodiment are shown as the load current source LD1.

[0094] The configuration of the SH circuit 20 differs from the configuration of the SH circuit 20 in the first embodiment.

[0095] The SH circuit 20 is provided between the photoelectric conversion unit 10 and the gate of the amplification transistor Tamp2. The SH circuit 20 temporarily holds the voltage of the pixel signal transferred from the photoelectric conversion unit 10. The SH circuit 20 comprises a first capacitance element C1, a second capacitance element C2, a transistor Ts1, and a transistor Ts2.

[0096] Transistors Ts1 and Ts2 are connected in series between the gate (node ​​N2) of the amplification transistor Tamp2 and node N1 of the photoelectric conversion unit 10. Transistor Ts1 is connected between the gate of the amplification transistor Tamp2 and transistor Ts2. Transistor Ts2 is connected between transistor Ts1 and node N1. The gate of transistor Ts1 receives control signal S1. The gate of transistor Ts2 receives control signal S2.

[0097] One end of the first capacitance element C1 is connected to the gate of the amplification transistor Tamp2. The other end of the first capacitance element C1 is connected to a reference voltage source. The first capacitance element C1 can receive pixel signals transferred from the photoelectric conversion unit 10 via transistors Ts1 and Ts2 and hold the voltage of the pixel signals.

[0098] One end of the second capacitance element C2 is connected to node N3 between transistors Ts1 and Ts2. The other end of the second capacitance element C2 is connected to a reference voltage source. The second capacitance element C2 can receive a pixel signal transferred from the photoelectric conversion unit 10 via transistor Ts2 and hold the voltage of the pixel signal.

[0099] Thus, transistors Ts1 and Ts2 are connected in series between node N1 and node N2. The first capacitor C1 is connected between node N2 and the reference voltage source. The second capacitor C2 is connected between node N3 and the reference voltage source.

[0100] The amplification transistor Tamp2, the selection transistor Tsel, and the load current source LD2 may have the same configuration as the amplification transistor Tamp2, the selection transistor Tsel, and the load current source LD in the first embodiment.

[0101] When the SH circuit 20 receives a pixel signal from node N1 or outputs a pixel signal to node N2, it activates either or both of the control signals S1 and S2.

[0102] For example, when the first capacitance element C1 holds the reset signal, both transistors Ts1 and Ts2 are turned on. This allows the first capacitance element C1 to hold a voltage corresponding to the voltage of the reset signal at node N1.

[0103] When the second capacitance element C2 holds the data signal, transistor Ts2 turns ON. At this time, transistor Ts1 remains OFF. As a result, the second capacitance element C2 can hold a voltage corresponding to the voltage of the data signal at node N1.

[0104] Furthermore, when reading the reset signal held in the first capacitance element C1, both transistors Ts1 and Ts2 may remain in the off state. This is because the reset signal held in the first capacitance element C1 is applied to the gate (node ​​N2) of the amplification transistor Tamp2. The reset signal is not corrupted when it is read.

[0105] To read the data signal held in the second capacitance element C2, transistor Ts1 is turned ON. Transistor Ts2 can remain OFF. At this time, the data signal from the second capacitance element C2 is applied to the gate (node ​​N2) of the amplification transistor Tamp2 via transistor Ts1. Therefore, the reset signal is destroyed when the data signal is read.

[0106] Thus, the SH circuit 20 according to the second embodiment can retain both the reset signal and the data signal non-destructively even when the reset signal is read. On the other hand, when the SH circuit 20 reads the data signal, the reset signal is destroyed, and only the data signal is retained.

[0107] Next, the operation of the imaging device 100 according to this embodiment will be described.

[0108] Figures 7 and 8 are timing diagrams showing an example of the operation of the imaging device according to the second embodiment. Basically, the operation of the second embodiment is the same as the operation of the first embodiment. The operation that differs from the operation of the first embodiment will be explained.

[0109] Figure 7 shows the operation of the imaging device 100 when the trigger signal XTRIG is activated to a low level while the reset signal for address "256" is being read (AD conversion). Figure 8 shows the operation of the imaging device 100 when the trigger signal XTRIG is activated to a low level while the data signal for address "256" is being read (AD conversion).

[0110] The operation from t0 to t5 is the same as the operation from t0 to t5 in Figure 4.

[0111] For example, as shown in Figure 7, suppose that in tx, the trigger signal XTRIG is activated to a low level while the reset signal at address "256" is being read (AD-to-digital conversion). In this case, the controller 102 immediately starts exposure EXP1. Furthermore, the controller 102 does not perform AD-to-digital conversion (reading) of the data signal after the AD-to-digital conversion (reading) of the reset signal at address "256" is completed. That is, the reset signal held in the second capacitor C2 is maintained while the transistor Ts2 remains in the OFF state. As a result, the reset signal is not destroyed in the SH circuit 20 of each pixel PX. Therefore, the SH circuit 20 retains both the reset signal and the data signal of the previous exposure EXP0. In this case, both the reset signal and the data signal can be repeatedly read. In this case, the latch circuit 112 may retain the count value of the reset signal at address "256", but it is not necessarily required to retain this count value of the reset signal.

[0112] After the power supply voltage of the pixel unit 101 has stabilized, at t7, the controller 102 re-specifies the selected pixel at address "256". Exposure EXP1 is started immediately by the trigger signal XTRIG, but the SH circuit 20 retains the reset signal and data signal of the pixel signal corresponding to the previous EXP0. Therefore, by re-specifying address "256", both the reset signal and data signal of address "256" corresponding to exposure EXP0 can be AD converted again and read out. As a result, the signal processing circuit 108 can obtain a digital signal that does not contain shutter step.

[0113] Subsequently, the processing from address "257" onwards (t8~) is the same as the processing described with reference to Figure 4.

[0114] On the other hand, as shown in Figure 8, assume that in tx, the trigger signal XTRIG is activated to a low level while the data signal at address "256" is being read (AD-to-digital conversion). In this case, the controller 102 immediately starts exposure EXP1. Also, because the AD-to-digital conversion (readout) of the data signal is in progress, the reset signal in the SH circuit 20 of pixel PX has already been destroyed. Therefore, after the AD-to-digital conversion (readout) of the reset signal at address "256" is completed, the controller 102 holds the count value of this reset signal at address "256" in the latch circuit 112.

[0115] After the stabilization period for the power supply voltage of the pixel unit 101 has elapsed, at t7, the controller 102 sets the count values ​​of the reset signals held in the latch circuit 112 to the corresponding counters 122.

[0116] The controller 102 re-selects the pixel at address "256". At this time, the SH circuit 20 holds only the data signal non-destructively, so only the data signal can be repeatedly read. Therefore, the counter 122 counts the data signal at address "256" without counting the reset signal at address "256".

[0117] The count value of the reset signal held in the latch circuit 112 does not include the shutter step. Therefore, the controller 102 sets the count value of the reset signal held in the latch circuit 112 to the counter 122, and then counts the data signal of the SH circuit 20. As a result, the ADC group 105 can generate a post-CDS digital signal that does not include the shutter step.

[0118] When the latch circuit 123 performs CDS processing, the controller 102 sets the count value of the reset signal held by the latch circuit 112 to the corresponding latch circuit 123. Then, the controller 102 again specifies the selected pixel at address "256", and the counter 122 counts only the data signal at address "256". The latch circuit 123 then takes the difference between the count value of the data signal at address "256" obtained at this time and the count value of the reset signal obtained from the latch circuit 112, and performs CDS processing.

[0119] Furthermore, the latch circuit 123 may also have the same function as the latch circuit 112. That is, if the trigger signal XTRIG is activated while reading (AD conversion) the data signal at address "256", the count value of the reset signal held by the latch circuit 123 may be set to the counter 122. Alternatively, if the latch circuit 123 performs CDS processing, the latch circuit 123 may simply hold the count value of the reset signal. This makes it possible to omit the latch circuit 112.

[0120] Refer to Figures 9 and 10 for a more detailed explanation of the case where the trigger signal XTRIG is activated during data signal readout (AD conversion).

[0121] Figures 9 and 10 are timing diagrams showing the operation of comparator 121 and counter 122 when the trigger signal XTRIG is activated during the reading (AD conversion) of the data signal shown in Figure 8.

[0122] The comparator 121 compares the voltage Vsig of the vertical signal line 110 with the voltage of the reference signal RAMP, and inverts the output signal when, for example, the voltage Vsig and the voltage of the reference signal RAMP cross.

[0123] Counter 122 counts a predetermined clock signal for a period from the start of voltage driving of the reference signal RAMP until the inversion of the output signal of comparator 121. Counter 122 counts the data signal by subtracting it from the count value of the reset signal. For example, counter 122 downcounts the reset signal to make the reset signal a negative value, and then upcounts the data signal from the count value of the reset signal to obtain the difference between them (count value of the data signal - count value of the reset signal). This difference is latched into latch circuit 123 as a CDS-processed digital signal.

[0124] For example, at time t5 in Figure 9, the reset signal for address "256" is set to voltage Vsig. At time t5_1, the controller 102 linearly reduces the voltage of the reference signal RAMP. Simultaneously, the counter 122 starts down-counting the clock signal.

[0125] In t5_2, when the reference signal RAMP crosses the voltage Vsig, the counter 122 stores the count value of the reset signal in the latch circuit 112.

[0126] In t5_3, the data signal at address "256" is set to voltage Vsig, and the reference signal RAMP is reset.

[0127] At t5_4, the controller 102 linearly reduces the voltage of the reference signal RAMP. Simultaneously, the counter 122 starts up-counting the clock signal.

[0128] If the trigger signal XTRIG is activated during the counting of the data signal at time tx, a shutter step occurs in the data signal. Therefore, the digital signal processed by CDS at time t6 will contain this shutter step.

[0129] Therefore, after t6, as shown in Figure 10, at t7 and beyond, the controller 102 re-specifies the address "256". However, since the data signal has already started counting, in the SH circuit 20 of the pixel PX according to the second embodiment, the reset signal is destroyed and only the data signal can be effectively used.

[0130] Therefore, in the second embodiment, after address "256" is specified again, counter 122 does not perform reset signal counting in t7 to t7_2. On the other hand, in t7_3, before the start of data signal counting, counter 122 retrieves the reset signal count value stored in latch circuit 112 and sets it as the reset signal count value for address "256".

[0131] Then, at t7_3, the controller 102 linearly reduces the voltage of the reference signal RAMP, and simultaneously, the counter 122 starts counting up the clock signal from the level of the reset signal. At this time, since the SH circuit 20 holds the data signal, the counter 122 can count the data signal without the shutter step.

[0132] As a result, the signal processing circuit 108 can obtain a CDS-processed digital signal (count value of the data signal - count value of the reset signal) that does not include shutter step.

[0133] Thus, in the second embodiment, the SH circuit 20 destroys the reset signal during AD conversion of the data signal, but the latch circuit 112 holds the count value of the reset signal. Therefore, even if the trigger signal XTRIG is activated during AD conversion of the data signal, the counter 122 performs CDS processing by using the count value of the reset signal held by the latch circuit 112 to recount the data signal held by the SH circuit 20. As a result, the ADC group 105 can generate a digital signal that does not contain shutter steps.

[0134] Other operations in the second embodiment may be the same as those in the first embodiment. Therefore, the second embodiment can also obtain the effects of the first embodiment.

[0135] Furthermore, this technology can be configured as follows:

[0136] (1) It includes a photoelectric conversion unit that converts incident light into pixel signals and a holding circuit that holds the pixel signals transferred from the photoelectric conversion unit, and has a plurality of pixels that can be specified by address, An AD conversion unit that converts pixel signals to digital signals, A first drive unit reads a pixel signal from at least one pixel specified by an address among multiple pixels to an AD conversion unit, If, during the AD conversion of the first pixel signal from at least one selected pixel specified by the first address, a first command to expose multiple pixels next is received, the controller, after the first period has elapsed, re-specifies the selected pixel of the first address, An imaging device equipped with the following features.

[0137] (2) The imaging apparatus according to (1), further comprising a signal processing circuit that invalidates a first digital signal obtained by AD conversion of a first pixel signal.

[0138] (3) The imaging apparatus according to (1) or (2), further comprising a signal processing circuit that processes a second digital signal obtained by re-specifying the selected pixel of the first address after the elapsed first period as a valid signal.

[0139] (4) The imaging apparatus described in any one of items (1) to (3), wherein the controller, upon receiving a first command, performs exposure of multiple pixels without delay.

[0140] (5) The holding circuit is, One end of each capacitor is connected to a photoelectric conversion unit, and the capacitor is a first and second capacitor capable of receiving a pixel signal and holding the voltage of the pixel signal. A first switching element is provided between the gate of an amplification transistor that amplifies the pixel signal and outputs it to the AD conversion unit and the other end of a first capacitive element, A second switching element is provided between the other end of the second capacitance element and the gate of the amplification transistor, An imaging device according to any one of (1) to (4), including the following:

[0141] (6) The holding circuit is, A first switch element and a second switch element are connected in series between the gate of an amplification transistor that amplifies the pixel signal and outputs it to the AD conversion unit and the photoelectric conversion unit, A first capacitive element, with one end connected to the first node between the gate of the amplification transistor and the first switching element, and the other end connected to a reference voltage source, A second capacitive element has one end connected to the second node between the first and second switching elements, and the other end connected to a reference voltage source, An imaging device according to any one of (1) to (4), including the following:

[0142] (7) The AD conversion unit is Multiple comparators compare the pixel signal with a reference signal and invert the output signal based on the voltage difference between the pixel signal and the reference signal. Multiple counters are provided corresponding to each of the multiple comparators, and they count the time from the start of driving the reference signal until the output signals of the multiple comparators invert, and generate a count value. Multiple latch circuits are provided corresponding to each of the multiple counters and hold the pixel count value in the reset state, An imaging device according to any one of (1) to (4) or (6), including the following.

[0143] (8) The counter generates a count value for the first reset signal of a pixel in the reset state of the photoelectric conversion unit among the first pixel signals, and then generates a count value for the first data signal corresponding to the exposure amount of the pixel in the exposure state. Multiple latch circuits hold the count value of the first reset signal, The imaging apparatus described in (7), which, if the next first command is received during the AD conversion of the first reset signal, specifies the selected pixel again at the first address after the first period has elapsed.

[0144] (9) If the next first command is received during the AD conversion of the first reset signal, the controller does not perform the AD conversion of the first data signal, as described in (8) of the imaging apparatus.

[0145] (10) The counter generates a count value for the first reset signal of the pixel in the reset state among the first pixel signals, and then generates a count value for the first data signal of the pixel in the exposure state. Multiple latch circuits hold the count value of the first reset signal, If the controller receives the next first command during the AD conversion of the first data signal, it sets the count values ​​held in multiple latch circuits into the counter. The imaging apparatus according to (8) or (9), wherein when the controller re-specifies the selected pixel at the first address, the counter counts the first data signal without counting the first reset signal.

[0146] (11) The imaging apparatus according to (9) or (10), wherein a counter counts a first data signal so as to subtract it from the count value of a first reset signal, or another latch circuit takes the difference between the count value of the first data signal and the count value of the first reset signal.

[0147] (12) The imaging apparatus according to any one of (1) to (11), wherein the first period is the period from the start of exposure of multiple pixels until the voltage sources of the multiple pixels fall within a predetermined range.

[0148] (13) A control method for an imaging device comprising: a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal; a holding circuit that holds the pixel signal transferred from the photoelectric conversion unit; a plurality of pixels that can be specified by address; an AD conversion unit that AD-converts the pixel signal into a digital signal; a first drive unit that reads a pixel signal from at least one pixel specified by address among the plurality of pixels to the AD conversion unit; and a controller that controls the AD conversion unit and the first drive unit, wherein A control method comprising, if a first command to expose multiple pixels next is received during the AD conversion of a first pixel signal from at least one selected pixel specified by a first address among the addresses, specifying the selected pixel again at the first address after the elapsed of a first period.

[0149] (14) The method according to (13), further comprising invalidating a first digital signal obtained by AD conversion of a first pixel signal.

[0150] (15) The method according to (13) or (14), further comprising processing a second digital signal obtained by re-specifying the selected pixel at the first address after the elapsed time of the first period as a valid signal.

[0151] (16) The method according to any one of (13) to (15), further comprising performing exposure of multiple pixels without delay when a first command is received.

[0152] (17) The AD conversion unit includes a plurality of comparators that compare the pixel signal with a reference signal and invert the output signal based on the voltage between the pixel signal and the reference signal; a plurality of counters provided corresponding to each of the plurality of comparators, which count the time from the start of driving the reference signal until the output signals of the plurality of comparators are inverted and generate a count value; and a plurality of latch circuits provided corresponding to each of the plurality of counters, which hold the count value of the pixel in the reset state. The first reset signal count value of the pixel in the reset state among the first pixel signals is generated, The count value of the first reset signal is held in multiple latch circuits. The system comprises generating a count value of the first data signal of a pixel in the exposure state, The method according to any one of (13) to (15), wherein if the next first command is received during the AD conversion of the first reset signal, the selected pixel is specified again at the first address after the first period has elapsed.

[0153] (18) If the next first command is received during the AD conversion of the first data signal, the count values ​​held in multiple latch circuits are set in the counter. The method according to (17), wherein when the selected pixel is specified again at the first address, the first data signal is counted without counting the first reset signal.

[0154] (19) The method according to (17) or (18), further comprising counting a first data signal so as to subtract it from the count value of a first reset signal, or taking the difference between the count value of a first data signal and the count value of a first reset signal.

[0155] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist. [Explanation of Symbols]

[0156] 100 Imaging device 101 pixel section 102 Controllers 103 Vertical scanning circuit 104 DAC 105 ADC group 106 Horizontal Transfer Scanning Circuit 108 Signal Processing Circuit 112 Latch Circuit 121 Comparator 122 counter 123 Latch Circuit 10 Photoelectric conversion element 20 SH circuit

Claims

1. It includes a photoelectric conversion unit that converts incident light into pixel signals and a holding circuit that holds the pixel signals transferred from the photoelectric conversion unit, and has a plurality of pixels that can be specified by address, An AD conversion unit that converts the aforementioned pixel signal into a digital signal using AD (Analogue-to-Digital) conversion, A first drive unit reads the pixel signal from at least one pixel specified by the address among the plurality of pixels to the AD conversion unit, If, during the AD conversion of the first pixel signal from at least one selected pixel specified by the first address among the addresses, a first command is received to expose the plurality of pixels next, a controller that, after the first period has elapsed, re-specifies the selected pixel of the first address, An imaging device equipped with the following features.

2. The imaging apparatus according to claim 1, further comprising a signal processing circuit that disables the output of a first digital signal obtained by AD conversion of the first pixel signal.

3. The imaging apparatus according to claim 1, further comprising a signal processing circuit that processes a second digital signal obtained by re-specifying the selected pixel of the first address after the elapsed time of the first period as a valid signal.

4. The imaging apparatus according to claim 1, wherein the controller, upon receiving the first command, performs the exposure of the plurality of pixels without delay.

5. The holding circuit is First and second capacitive elements, one end of which is connected to the photoelectric conversion unit, and capable of receiving the pixel signal and holding the voltage of the pixel signal, A first switching element is provided between the gate of an amplification transistor that amplifies the pixel signal and outputs it to the AD conversion unit and the other end of the first capacitive element, A second switching element is provided between the other end of the second capacitive element and the gate of the amplification transistor, The imaging apparatus according to claim 1, including the following:

6. The holding circuit is A first switch element and a second switch element are connected in series between the gate of an amplification transistor that amplifies the pixel signal and outputs it to the AD conversion unit and the photoelectric conversion unit, A first capacitive element, one end of which is connected to the first node between the gate of the amplification transistor and the first switching element, and the other end of which is connected to a reference voltage source, A second capacitive element, one end of which is connected to the second node between the first and second switching elements and the other end of which is connected to a reference voltage source, The imaging apparatus according to claim 1, including the following:

7. The aforementioned AD conversion unit is Multiple comparators compare the pixel signal with a reference signal and invert the output signal based on the voltage between the pixel signal and the reference signal, A plurality of counters are provided corresponding to each of the plurality of comparators, which count the time from the start of driving the reference signal until the output signals of the plurality of comparators invert, and generate a count value. A plurality of latch circuits are provided corresponding to each of the plurality of counters and hold the count value of the pixel in the reset state, The imaging apparatus according to claim 1, including the following:

8. The counter generates the count value of the first reset signal of the pixel in the reset state of the photoelectric conversion unit among the first pixel signals, and then generates the count value of the first data signal corresponding to the exposure amount of the pixel in the exposure state. The plurality of latch circuits hold the count value of the first reset signal, The imaging apparatus according to claim 7, wherein if the next first command is received during the AD conversion of the first reset signal, the controller re-specifies the selected pixel with the first address after the first period has elapsed.

9. The imaging apparatus according to claim 8, wherein if the controller receives the following first command during the AD conversion of the first reset signal, the controller does not perform the AD conversion of the first data signal.

10. The counter generates the count value of the first reset signal of the pixel in the reset state, and then generates the count value of the first data signal of the pixel in the exposure state. The plurality of latch circuits hold the count value of the first reset signal, If the controller receives the next first command during the AD conversion of the first data signal, it sets the count value held in the plurality of latch circuits into the counter. The imaging apparatus according to claim 8, wherein when the controller again specifies the selected pixel with the first address, the counter counts the first data signal without counting the first reset signal.

11. The imaging apparatus according to claim 9, wherein the counter counts the first data signal so as to subtract it from the count value of the first reset signal, or another latch circuit takes the difference between the count value of the first data signal and the count value of the first reset signal.

12. The imaging apparatus according to claim 1, wherein the first period is the period from the start of exposure of the plurality of pixels until the voltage sources of the plurality of pixels fall within a predetermined range.

13. A control method for an imaging device comprising: a photoelectric conversion unit that photoelectrically converts incident light into a pixel signal; a holding circuit that holds the pixel signal transferred from the photoelectric conversion unit; a plurality of pixels that can be specified by address; an AD conversion unit that AD converts the pixel signal into a digital signal; a first drive unit that reads the pixel signal from at least one pixel specified by the address among the plurality of pixels to the AD conversion unit; and a controller that controls the AD conversion unit and the first drive unit, wherein A control method comprising, if a first command to expose the plurality of pixels next is received during the AD conversion of a first pixel signal from at least one selected pixel specified by a first address among the addresses, specifying the selected pixel again by the first address after the elapsed of a first period.

14. The method according to claim 13, further comprising invalidating the first digital signal obtained by AD conversion of the first pixel signal.

15. The method according to claim 13, further comprising processing a second digital signal obtained by re-specifying the selected pixel with the first address after the elapsed time of the first period as a valid signal.

16. The method according to claim 13, further comprising, upon receiving the first command, performing the exposure of the plurality of pixels without delay.

17. The AD conversion unit includes a plurality of comparators that compare the pixel signal with a reference signal and invert the output signal based on the voltage between the pixel signal and the reference signal; a plurality of counters provided corresponding to each of the plurality of comparators, which count the time from the start of driving the reference signal until the output signals of the plurality of comparators are inverted and generate a count value; and a plurality of latch circuits provided corresponding to each of the plurality of counters, which hold the count value of the pixel in the reset state. The count value of the first reset signal of the pixel in the reset state among the first pixel signals is generated, The count value of the first reset signal is held in the plurality of latch circuits, The system comprises generating the count value of the first data signal of the pixel in the exposure state, The method according to claim 13, wherein if the next first command is received during the AD conversion of the first reset signal, the selected pixel is specified again at the first address after the first period has elapsed.

18. If the next first command is received during the AD conversion of the first data signal, the count value held in the plurality of latch circuits is set in the counter. The method according to claim 17, wherein when the selected pixel is specified again at the first address, the first data signal is counted without counting the first reset signal.

19. The method according to claim 17, further comprising counting the first data signal so as to subtract it from the count value of the first reset signal, or taking the difference between the count value of the first data signal and the count value of the first reset signal.

Images