Clamp control circuit and image sensing device including the same

Abstract

We provide an image sensing device that can prevent the black sun phenomenon. [Solution] The clamp control circuit 100 of the image sensing device 10 may include a sensing circuit 120 that senses the voltage level of a pixel signal VPX and outputs a sensing signal VSEN, and a clamping circuit 130 that controls the voltage level of a clamp voltage control signal CV in accordance with the voltage level of the sensing signal VSEN, and controls the level of a clamp voltage CLP provided to the column line CL in accordance with the voltage level of the clamp voltage control signal CV based on a clamp enable signal C_EN.

Description

Technical Field

[0001] The present disclosure relates to an image sensing device that generates image data.

Background Art

[0002] Generally, a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS) implemented in a CMOS process is rapidly expanding its market due to advantages such as low power consumption, low cost, and small size compared to other competing products. In particular, the CMOS image sensor has gradually expanded its application range to the video field that requires high resolution and high frame rate through image quality improvement that was relatively lacking compared to competing products.

[0003] However, when the amount of light in a high illumination environment is greater than the dynamic range of the pixels, a black sun phenomenon may occur in the image sensor. Here, the black sun phenomenon refers to a phenomenon where when photographing a high illumination subject such as the sun or bright lighting, due to overflow inside the pixel, the part that should be brightly represented is represented darkly and appears black like a black dot of the sun. When the illuminance of light is strong in the image sensor, there is a possibility that a black sun phenomenon occurs where signal charges exceeding the full capacity of the photodiode are generated and charges overflow into the unit pixel or the floating diffusion region.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide an image sensing device capable of preventing the black sun phenomenon by controlling the clamp voltage level corresponding to the voltage level of the pixel signal.

Means for Solving the Problems

[0005] A clamp control circuit according to an embodiment of the present invention may include a sensing circuit that senses the voltage level of a pixel signal and outputs a sensing signal, and a clamping circuit that controls the voltage level of a clamp voltage control signal in accordance with the voltage level of the sensing signal and controls the level of clamp voltage provided to the column line in accordance with the voltage level of the clamp voltage control signal based on a clamp enable signal.

[0006] An image sensing device according to another embodiment of the present invention may include: a pixel that outputs a pixel signal to a column line; a clamp control circuit that senses the voltage level of the pixel signal and outputs a sensing signal, and controls the clamp voltage provided to the column line in response to the sensing signal during clamping operation mode to a level equal to or greater than a previously set reference voltage; and an analog-to-digital converter that performs analog-to-digital conversion operation based on the voltage of the column line and a ramp signal. [Effects of the Invention]

[0007] Embodiments of the present invention can improve the dynamic range by improving the clamp margin of the pixel signal and preventing the black sun phenomenon.

[0008] Furthermore, the embodiments of the present invention are illustrative, and those skilled in the art can make various modifications, changes, substitutions, and additions based on the technical idea and scope of the appended claims, and such modifications and changes should be considered to fall within the scope of the following claims. [Brief explanation of the drawing]

[0009] [Figure 1] This is a configuration diagram of an image sensing device according to one embodiment of the present invention. [Figure 2] Figure 1 is an illustrative circuit diagram relating to a pixel. [Figure 3] Figure 1 is an illustrative circuit diagram of the clamp control circuit shown. [Figure 4]Figure 3 is a diagram illustrating the operation of the clamp control circuit. [Figure 5] Figure 3 is a diagram illustrating the operation of the clamp control circuit. [Figure 6] Figure 1 is an illustrative circuit diagram of an analog-to-digital conversion circuit. [Figure 7] This is a timing diagram illustrating the operation of the image sensing device according to the embodiment shown in Figure 3. [Figure 8] This is another embodiment of the clamp control circuit shown in Figure 1. [Figure 9] This is a timing diagram illustrating the operation of the image sensing device according to the embodiment shown in Figure 8. [Modes for carrying out the invention]

[0010] Various embodiments will be described below with reference to the attached drawings. However, this disclosure should be understood not to be limited to any particular embodiment, but to include various modifications, equivalents, and / or alternatives of the embodiments. Embodiments of this disclosure can provide a variety of effects that can be directly or indirectly recognized through this disclosure.

[0011] Figure 1 is a configuration diagram of an image sensing device according to one embodiment of the present invention.

[0012] Referring to Figure 1, the image sensing device 10 may include a pixel array (PA), a clamp control circuit 100, a lamp generator 200, an analog-to-digital converter (ADC) 300, and a timing controller 400.

[0013] Here, the pixel array (PA) may include multiple pixels (PX) arranged in multiple rows and multiple columns. In one embodiment, the multiple pixels (PX) may be arranged in a two-dimensional pixel array (PA) including rows and columns. In another embodiment, the multiple unit image pixels may be arranged in a three-dimensional pixel array (PA). The multiple pixels (PX) can convert optical signals into electrical signals on a pixel-by-pixel or pixel-group basis and output pixel signals (VPX) to column lines (CL). For example, the voltage of the pixel signal (VPX) may be a voltage generated via a reset operation of the corresponding pixel (PX) or a voltage generated via an integration operation.

[0014] Pixels (PX) within a pixel group may share at least one internal circuit. A pixel array (PA) can receive drive signals (described later) from a low driver (not shown), including a low selection signal, a pixel reset signal, and a transmission signal, and the drive signals can activate the pixel (PX) in the pixel array (PX) to perform operations corresponding to the low selection signal, the pixel reset signal, and the transmission signal.

[0015] The clamp control circuit 100 senses the voltage level of the pixel signal (VPX) based on the control signal (CON), bias voltage (VB), sensing enable signal (S_EN), sensing auto zeroing signal (S_AZ), and clamp enable signal (C_EN) applied from the timing controller 400, and can control the level of the clamp voltage (CLP) in accordance with the sensed voltage level. The clamp control circuit 100 can control the level of the clamp voltage (CLP) provided to the column line (CL) when the pixel signal (VPX) for reset sampling operation is output.

[0016] In the present disclosure, the clamp control circuit 100 can operate in one of a bias operation mode and a clamping operation mode. The clamp control circuit 100 can bias the voltage level of the pixel signal (VPX) and transmit it to the ADC 300 during the bias operation mode. The clamp control circuit 100 can control the clamp voltage (CLP) applied to the column line (CL) to be below a preset reference voltage so as not to affect the voltage level of the pixel signal (VPX) during the bias operation mode. On the other hand, the clamp control circuit 100 can sense the voltage level of the pixel signal (VPX) during the clamping operation mode, and when the sensed voltage level of the pixel signal (VPX) is less than the preset reference voltage, it can control to increase the level of the clamp voltage (CLP). That is, the clamp control circuit 100 can increase the voltage level of the column line (CL) to be above the preset reference voltage corresponding to the level of the clamp voltage (CLP) during the clamping operation mode to ensure a clamping operation margin. Here, the preset reference voltage may be set to the voltage level of a reset signal (RG signal described later).

[0017] More detailed circuits and operations of such a clamp control circuit 100 will be described later with reference to FIGS. 3 to 5 and FIG. 7.

[0018] The ramp generator 200 can generate a ramp signal (VRAMP) required for the analog-to-digital conversion operation of the ADC 300 according to a control signal (RCON) from the timing controller 400 and supply it to the ADC 300.

[0019] The ADC300 can sequentially sample and hold a reference signal and a video signal provided from each of a plurality of column lines of a pixel array (PA), and convert them into digital signals for output. The ADC300 can receive a ramp signal (VRAMP) from the ramp generator 200, receive a pixel signal (VPX) from a pixel (PX), and generate and output ADC data (ADC_OUT) based on the ramp signal (VRAMP) and the pixel signal (VPX). In one embodiment, the ADC300 may be implemented as a ramp-compare type ADC using the ramp signal (VRAMP) of the ramp generator 200.

[0020] The timing controller 400 can control at least one of the clamp control circuit 100, the ramp generator 200, and the ADC300. The timing controller 400 can generate a control signal (CON), a bias voltage (VB), a sensing enable signal (S_EN), a sensing auto-zeroing signal (S_AZ), and a clamp enable signal (C_EN) for controlling the operation of the clamp control circuit 100. The timing controller 400 can generate a control signal (RCON) for controlling the operation of the ramp generator 200. The timing controller 400 can generate an auto-zeroing signal (AZ) and a counter enable signal (CNT_EN) for controlling the operation of the ADC300.

[0021] Figure 2 is an exemplary circuit diagram regarding the pixel shown in Figure 1.

[0022] Referring to Figure 2, the pixel (PX) may be any one of a plurality of pixels included in the pixel array (PA). Although one pixel (PX) is described in Figure 2, other pixels may have substantially the same structure and operation as the pixel (PX).

[0023] A pixel (PX) may include a photoelectric element (PD), a transmission transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a first capacitor (C1), a source follower transistor (SF), and a selection transistor (SX). In Figure 2, a pixel (PX) is exemplified as including one photoelectric element (PD), but in other embodiments it may be a shared pixel having multiple photoelectric elements. In this case, multiple transmission transistors may be provided corresponding to the multiple photoelectric elements.

[0024] A photoelectric element (PD) can generate and store photocharges corresponding to the intensity of incident light. For example, a photoelectric element (PD) can be embodied as a photodiode, phototransistor, photogate, pinned photodiode, or a combination thereof. When the photoelectric element (PD) is embodied as a photodiode, it may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type).

[0025] A transmission transistor (TX) may be connected between a photoelectric converter (PD) and a floating diffusion region (FD). The transmission transistor (TX) may be turned on or turned off in response to a transmission signal (TG). A transmission transistor (TX) turned on by a logically high level transmission signal (TG) can transfer the photocharge accumulated in the photoelectric converter (PD) to the floating diffusion region (FD).

[0026] A reset transistor (RX) may be connected between the power supply voltage (VDDPX) application terminal and the floating diffusion region (FD). The reset transistor (RX) can respond to a logical high-level reset signal (RG) to reset the voltage in the floating diffusion region (FD) to the power supply voltage (VDD).

[0027] A floating diffusion region (FD) can accumulate photocharges transferred from a transmission transistor (TX). The floating diffusion region (FD) may be connected to a first capacitor (C1) connected to a ground terminal. For example, the floating diffusion region (FD) may be a region doped with an impurity of a second conductivity type (e.g., N-type) within a substrate having a first conductivity type (e.g., P-type), and the substrate and the impurity-doped region may be modeled as a first capacitor (C1) which is a junction capacitor. The floating diffusion region (FD) may be referred to as a sensing node.

[0028] In this disclosure, a logical high level may mean a voltage level that activates (e.g., turns on) the element (e.g., a transistor), and a logical low level may mean a voltage level that deactivates (e.g., turns off) the element (e.g., a transistor).

[0029] Although Figure 2 describes an embodiment in which the floating diffusion region (FD) has one capacitance, the floating diffusion region (FD) may have two or more capacitances. For example, the floating diffusion region (FD) may have two types of capacitances by being connected to a DCG (dual conversion gain) transistor to selectively provide additional capacitance.

[0030] A source follower transistor (SF) is connected between the power supply voltage (VDDPX) application terminal and the selection transistor (SX), and can amplify the change in the electrical potential of the floating diffusion region (FD) to which the photocharge accumulated in the photoelectric conversion element (PD) has been transferred, and transmit it to the selection transistor (SX).

[0031] A selection transistor (SX) may be connected between a source follower transistor (SF) and a column line (CL). The selection transistor (SX) can be turned on by a selection control signal (SEL) and output the electrical signal transmitted from the source follower transistor (SF) as a pixel signal (VPX).

[0032] In one embodiment, outputting a pixel signal (VPX) to transmit the voltage of the floating diffusion region (FD) to the column line (CL) via a source follower transistor (SF) and a selection transistor (SX) may be referred to as a readout operation. The process of receiving charge from a photoelectric converter (PD) and turning on and off a transmission transistor (TX) to reduce the voltage of the floating diffusion region (FD) may be referred to as an integration operation. The operation of charging the floating diffusion region (FD) based on the power supply voltage (VDDPX) via a reset transistor (RX) may be referred to as a reset operation.

[0033] Figure 3 is an illustrative circuit diagram of the clamp control circuit shown in Figure 1.

[0034] Referring to Figure 3, the clamp control circuit 100 may include a biasing circuit 110, a sensing circuit 120, and a clamping circuit 130.

[0035] The biasing circuit 110 can bias the column lines (CL) that output pixel signals (VPX) to the bias voltage (VB) level based on control signals (CON1~CON4) applied from the timing controller 400.

[0036] Such a biasing circuit 110 may include multiple transistors (N1 to N6). Here, the multiple transistors (N1 to N6) may be NMOS transistors. For example, the biasing circuit 110 can bias node (ND1) to the bias voltage (VB) level when the control signals (CON1 to CON4) transition to a logical high level.

[0037] Transistors (N1~N3) may be connected in series between node (N1) and the ground voltage (VSSPX) application terminal. A control signal (CON1) may be applied to transistor (N1) via its gate terminal. A control signal (CON2) may be applied to transistor (N2) via its gate terminal. The gate terminals of transistors (N3, N6) may be connected in common. Transistor (N4) may be connected between the bias voltage (VB) application terminal and transistor (N5), and a control signal (CON3) may be applied via its gate terminal. Transistor (N5) may be connected between the gate terminals of transistors (N4) and (N3), and a control signal (CON4) may be applied via its gate terminal. Transistor (N6) can operate as a MOS capacitor by having its source and drain terminals commonly connected to the ground voltage (VSSPX) application terminal.

[0038] The sensing circuit 120 can sense the voltage level of the pixel signal (VPX) applied to the sensing node (ND1) when the sensing enable signal (S_EN) is activated and output a sensing signal (VSEN). The sensing circuit 120 can then output a clamp voltage control signal (CV) corresponding to the voltage level of the sensed sensing signal (VSEN). The sensing circuit 120 can perform auto-zeroing operation based on the sensing auto-zeroing signal (S_AZ) and store the voltages of the nodes (ND1, ND2) in the capacitor (C2).

[0039] Such a sensing circuit 120 may include multiple transistors (P1, P2, N7) and a capacitor (C2). Here, the multiple transistors (P1, P2) may be PMOS transistors, and transistor (N7) may be an NMOS transistor.

[0040] Transistor (P1) is connected between the power supply voltage (VDDPX) application terminal and node (ND3), and a sensing signal (VSEN) may be applied via its gate terminal. Transistor (P2) is connected between nodes (ND2) and (ND3), and a sensing auto-zeroing signal (S_AZ) may be applied via its gate terminal. Capacitor (C2) is connected between nodes (ND1) and (ND2).

[0041] Transistor (N7) is connected between node (ND3) and the ground voltage (VSSPX) application terminal, and a sensing enable signal (S_EN) may be applied via its gate terminal. Transistor (N7) may also be referred to as a "sensing activation circuit" that controls whether or not the sensing circuit 120 is activated based on the sensing enable signal (S_EN).

[0042] Furthermore, the clamping circuit 130 can control the level of the clamp voltage (CLP) output to the column line (CL) based on the clamp voltage control signal (CV) when the clamp enable signal (C_EN) is activated.

[0043] Such a clamping circuit 130 may include multiple transistors (N8, N9). Here, the multiple transistors (N8, N9) may be NMOS transistors.

[0044] Transistors (N8, N9) may be connected in series between the power supply voltage (VDDPX) application terminal and the column line (CL). A clamp voltage control signal (CV) may be applied to transistor (N8) via its gate terminal. Transistor (N8) may be referred to as a clamp transistor for controlling the level of the clamp voltage (CLP). A clamp enable signal (C_EN) may be applied to transistor (N9) via its gate terminal.

[0045] The transistor (N8) may operate as a source follower with its input terminal connected to the sensing circuit 120. The clamp voltage (CLP) may be determined based on the voltage of the clamp voltage control signal (CV). The column line (CL) voltage may be determined based on the voltage of the pixel signal (VPX) and the clamp voltage (CLP).

[0046] In other words, when all transistors (N8, N9) are turned on, the voltage output through the column line (CL) may be the higher of the pixel signal (VPX) voltage and the clamp voltage (CLP). For example, if the pixel signal (VPX) voltage is higher than the clamp voltage (CLP), the column line (CL) voltage may be determined based on the pixel signal (VPX) voltage. On the other hand, if the pixel signal (VPX) voltage is lower than the clamp voltage (CLP), the column line (CL) voltage may be determined based on the clamp voltage (CLP).

[0047] For example, the voltage in the floating diffusion region (FD) may decrease excessively below the target voltage. This can cause the voltage of the pixel signal (VPX) to decrease excessively. In this case, the voltage of the column line (CL) may be determined based on the clamp voltage (CLP). The clamp control circuit 100 can adjust the voltage of the column line (CL) so that it does not decrease below a certain level, based on the clamp voltage control signal (CV) corresponding to the sensing signal (VSEN). A more detailed description of the operation of such a clamp control circuit 100 will be shown later in Figures 4 and 5.

[0048] Figures 4 and 5 are diagrams illustrating the operation of the clamp control circuit shown in Figure 3.

[0049] In this disclosure, the clamp control circuit 100 may operate in one of two modes: a bias operation mode and a clamping operation mode. The operating mode of the clamp control circuit 100 may be controlled based on a clamp enable signal (C_EN). For example, if the clamping circuit 130 does not operate when the clamp enable signal (C_EN) is deactivated, it may operate in a bias operation mode for sensing the voltage level of the pixel signal (VPX). On the other hand, if the clamping circuit 130 operates when the clamp enable signal (C_EN) is activated, it may operate in a clamping operation mode for clamping the voltage level of the pixel signal (VPX).

[0050] First, with reference to Figure 4, we will explain the case where the clamp control circuit 100 operates in bias mode.

[0051] When the control signals (CON1~CON4) are activated, the transistors (N1~N6) are turned on, and the node (ND1) can be biased to the bias voltage (VB) level. When the sensing voltage (VSEN) level rises in response to the pixel signal (VPX), the transistor (P1) can be turned off. When the transistor (P2) is turned on while the sensing auto-zeroing signal (S_AZ) is at a logically low level, the clamp voltage control signal (CV) can maintain a low voltage level, i.e., a voltage level at which clamping does not occur (the V2 voltage level described later).

[0052] In bias operation mode, the clamp enable signal (C_EN) is deactivated and transistor (N9) is turned off, so the clamping circuit 130 does not operate. This allows the voltage level of the pixel signal (VPX) to be biased by the voltage level of node (ND1) and transmitted to the ADC300, as in path (A).

[0053] Referring to Figure 5, the case in which the clamp control circuit 100 operates in clamping operation mode will be explained.

[0054] When the control signals (CON1~CON4) are activated, the transistors (N1~N6) are turned on, and node (ND1) can be biased to the bias voltage (VB) level. During auto-zeroing operation, if the sensing auto-zeroing signal (S_AZ) is at a logical low level, transistor (P2) is turned on, and the voltages at nodes (ND1, ND2) can be stored in capacitor (C2). Then, when the sensing auto-zeroing signal (S_AZ) transitions to a logical high level, transistor (P2) can be turned off.

[0055] Furthermore, when the clamp enable signal (C_EN) is activated to a logical high level in clamping operation mode, transistor (N9) may be turned on. When the sensing voltage (VSEN) level decreases in accordance with the voltage level of the pixel signal (VPX), transistor (P1) may be turned on. This causes the voltage level of the clamp voltage control signal (CV) to rise in accordance with the power supply voltage (VDDPX) level, and transistor (N8) may be turned on. Thus, as in path (B), the voltage level of the column line (CL) may rise above the reference voltage (V3 voltage described later) level and be transmitted to the ADC300.

[0056] To improve the reliability of image data by noise reduction in an image sensor, analog-to-digital conversion (ADC) operation using the Correlation Double Sampling (CDS) technique may be performed. Reset sampling operation may be performed for the analog-to-digital conversion operation.

[0057] When a reset sampling operation is performed, if the intensity of light incident on the image sensor is excessively high, the voltage level of the reset signal (RG) may become excessively low. This can lead to a sunspot phenomenon, or black sun phenomenon, where the image sensing device fails to reliably recognize an image in environments where the intensity of light incident on the pixels (PX) is high. When a black sun phenomenon occurs, the pixel voltage decreases, and the operating margin of the biasing circuit 110 is insufficient to adequately sense the pixel signal (VPX). To prevent this, a clamping circuit 130 may be used to prevent the voltage level of the column line from falling below a certain level.

[0058] However, if the voltage level of the clamp voltage control signal (CV) applied to the gate terminal of the transistor (N8) included in the clamping circuit 130 is fixed to a specific clamp voltage level, leakage current generated from the clamp transistor may affect the sensing of the pixel signal (VPX). As a solution, increasing the clamp margin can limit the operating area of ​​the pixel. In other words, if that power supply voltage level or a large swing range of pixel output is required, the input range of the ADC300 can be reduced.

[0059] Therefore, in this disclosure, the sensing circuit 120 can sense the voltage level of the pixel signal (VPX), and the level of the clamp voltage (CLP) of the clamp transistor can be controlled in response to the sensed sensing signal (VSEN). This not only prevents leakage current from occurring in the clamp transistor, but also ensures sufficient clamp margin under black sun conditions.

[0060] Figure 6 is an illustrative circuit diagram of the analog-to-digital conversion circuit shown in Figure 1.

[0061] Referring to Figure 6, the ADC300 can perform reset sampling and pixel sampling operations and output the difference between the results of each sampling operation as a digital signal (i.e., ADC data (ADC_OUT)). The ADC300 can obtain a reset voltage via the reset sampling operation and a data voltage via the pixel sampling operation. Here, the reset voltage may be the voltage at which the ramp signal (VRAMP) and the column line (CL) voltages become equal after the reset operation. The data voltage may be the voltage at which the ramp signal (VRAMP) and the column line (CL) voltages become equal after the cumulative operation. The ADC300 can generate a digital signal for the image based on the difference between the data voltage and the reset voltage. An input / output circuit (not shown) can receive a digital signal from the analog-to-digital converter 300 and output image data.

[0062] Such an ADC300 may include a capacitor (C3), a capacitor (C4), a comparator 310, and a counter 320.

[0063] Capacitor (C3) can receive the ramp signal (VRAMP) and transmit the delayed ramp signal (VR) to comparator 310. Capacitor (C4) can receive the pixel signal (VPX) and transmit the delayed pixel signal (VP) to comparator 310.

[0064] The comparator 310 compares the delayed ramp signal (VR) and the delayed pixel signal (VP), and generates comparison data (CMP_OUT) based on the comparison result, which can then be transmitted to the counter 320. In one embodiment, if the delayed ramp signal (VR) is greater than the delayed pixel signal (VP), the comparator 310 can generate logically high-level comparison data (CMP_OUT). Conversely, if the delayed ramp signal (VR) is less than the delayed pixel signal (VP), the comparator 310 can generate logically low-level comparison data (CMP_OUT). In other words, the comparison data (CMP_OUT) can indicate the magnitude relationship between the ramp signal (VRAMP) and the pixel signal (VPX).

[0065] On the other hand, the comparator 310 can perform auto-zeroing operation using an auto-zeroing signal (AZ). Here, auto-zeroing operation may be an operation that adjusts the voltage level of the delay ramp signal (VR) and the delay pixel signal (VP) for comparison between the delay ramp signal (VR) and the delay pixel signal (VP). The comparator 310 can perform auto-zeroing operation in the section where the auto-zeroing signal (AZ) is logically high level. The auto-zeroing signal (AZ) can be generated and supplied by the timing controller 400.

[0066] The counter 320 can be activated in response to a counter enable signal (CNT_EN) applied from the timing controller 400. The counter 320 can perform counting operations until the ramp signal (VRAMP) is matched to the analog pixel signal (VPX). The activated counter 320 can then perform counting in response to a logic high-level comparison data (CMP_OUT) and output the counting result to ADC data (ADC_OUT).

[0067] Figure 7 is a timing diagram illustrating the operation of the image sensing device according to the embodiment shown in Figure 3.

[0068] Referring to Figure 7, the operation in which the pixel signal (VPX) is converted to image data may be divided into a reset interval (RST) and a signal interval (SIG). The reset interval (RST) is the interval in which the reference signal of the pixel (PX) is converted to analog-to-digital (AD), and the signal interval (SIG) may be the interval in which the video signal of the pixel (PX) is converted to analog-to-digital (AD). The reset interval is defined as the time interval from T1 to T6, and the time intervals from T7, T8, and T9 onward are defined as the signal interval. For example, the reset sampling operation may be performed during the time interval from T1 to T6.

[0069] At time T1, a read operation may be performed to perform a reset sampling operation. A selection transistor (SX) is turned on for the read operation, and the voltage of the column line (CL) may be determined based on the pixel signal (VPX). The voltage of the pixel signal (VPX) may be determined based on the voltage level of the floating diffusion region (FD). The floating diffusion region (FD) may be in a reset state due to the reset operation. The voltage of the floating diffusion region (FD) may be a voltage that has been reset based on the power supply voltage (VDDPX). Therefore, when the selection transistor (SX) is turned on for the reset sampling operation, the voltage level of the column line (CL) may be determined based on the voltage of the reset floating diffusion region (FD).

[0070] In other words, a pixel signal (VPX) corresponding to the voltage of the reset floating diffusion region (FD) can be output from the pixel (PX) by the reset signal (RG) having a logical high level. From this, the sensing circuit 120 can output a sensing signal (VSEN) corresponding to the voltage level of the pixel signal (VPX). When the clamp enable signal (C_EN) is inactive, the clamp control circuit 100 can operate in biasing mode as shown in Figure 4 above.

[0071] Subsequently, at time T2, the reset signal (RG) can transition to a logically low level. Then, with the auto-zeroing signal (AZ) having a logically high level, the comparator 310 can perform auto-zeroing between the ramp signal (VRAMP) and the pixel signal (VPX). If the black sun phenomenon occurs, the voltage level of the sensing signal (VSEN) can drop to a negative slope.

[0072] Next, at time T3, the sensing auto-zeroing signal (S_AZ) and sensing enable signal (S_EN) can transition to a logical high level. As a result, the voltage level of the sensing signal (VSEN) can be discharged by the voltage level of the pixel signal (VPX) and gradually decrease. At time T3, the voltage level of the sensing signal (VSEN) can also momentarily increase by an offset due to transistor switching noise (NV). As the voltage level of the sensing signal (VSEN) decreases, the voltage level of the clamp voltage control signal (CV) can gradually increase.

[0073] Next, at time T4, the clamp enable signal (C_EN) can transition to a logical high level. When the clamp enable signal (C_EN) is activated, the clamp control circuit 100 can operate in clamping operation mode as shown in Figure 5 above.

[0074] When the voltage level of the sensing signal (VSEN) decreases to a low voltage level, the voltage level of the clamp voltage control signal (CV) can be maintained at the V1 voltage level. Here, the V1 voltage may be the voltage level obtained by subtracting the drain-source voltage (VDS) of the transistor (P1) from the power supply voltage (VDDPX). When the voltage level of the clamp voltage control signal (CV) rises by the V1 voltage level, the voltage level of the column line (CL) can also rise above the reference voltage (V3). Here, the reference voltage (V3) may be set to the voltage level of the reset signal (RG), as described above.

[0075] For example, in biasing operation mode, the clamping circuit 130 does not operate, so the voltage level of the pixel signal (referred to as "VPX1" in biasing operation mode) may be the V4 voltage level. Here, the V4 voltage may be the voltage level corresponding to the leakage current of the selection transistor (SX) mentioned above. As another example, the V4 voltage may be the voltage level corresponding to the bias voltage (VB).

[0076] On the other hand, in clamping operation mode, the clamping circuit 130 operates so that the voltage level of the pixel signal (referred to as "VPX2" in clamping operation mode) can be raised to above the reference voltage (V3). Thus, in clamping operation mode, the voltage level of the pixel signal (VPX) can be raised to above the reference voltage (V3) level to ensure a clamping operation margin. In other words, only when the operating margin of the pixel signal (VPX) input to the ADC300 is D1 or greater can the input range of the ADC300 ensure the maximum swing width and generate the maximum code output from the ADC300.

[0077] Subsequently, at time T5, the auto-zeroing operation of comparator 310 may be discontinued because the auto-zeroing signal (AZ) has a logically low level. This allows the pixel signal (VPX1 or VPX2) to maintain its voltage level.

[0078] Furthermore, an offset may be added to the ramp signal (VRAMP) in order to perform a reset sampling operation. As a result, the ramp generator 200 can output a ramp signal (VRAMP) that maintains a voltage level raised by the ramp offset and then descends with a negative slope. Here, the ramp offset may be a value that indicates the extent to which the level at which the ramping (rising or falling) changes from the voltage level at which auto-zeroing is performed changes, due to the characteristics of the ramp generator 200. After a predetermined time has elapsed, the ramp delay signal (VR) from the ADC 300, after a delay time due to the capacitor (C3), can descend with a negative slope in correspondence with the ramp signal (VRAMP).

[0079] Next, at time T6, the clamp operation mode can be terminated when the sensing auto-zeroing signal (S_AZ) and the clamp enable signal (C_EN) transition to low levels. The sensing voltage (VSEN) level can rise again in accordance with the voltage level of the pixel signal (VPX). Then, as the sensing voltage (VSEN) level rises, the voltage level of the clamp voltage control signal (CV) decreases and may become the clamp reference voltage (V2) level. Here, the clamp reference voltage (V2) can be set to a voltage level low enough that the transistor (N8) of the clamping circuit 130 does not turn on (does not exceed the threshold voltage). That is, the voltage of the column line (CL) with the selection transistor (SX) turned on in order to perform the reset sampling operation may be referred to as the clamp reference voltage (V2). As the signal interval (SIG) begins, the delay ramp signal (VR) can return to the upper limit of the ramp and, after a predetermined time has elapsed, may descend to a negative slope.

[0080] Then, at T7, the transmission signal (TG) temporarily has a logically high level, which may cause a pixel signal (VPX) to be output from the pixel (PX) corresponding to the voltage of the floating diffusion region (FD) where the photocharge generated by the pixel (PX) is accumulated. The voltage level of the pixel signal (VPX) may decrease in proportion to the amount of photocharge accumulated in the floating diffusion region (FD).

[0081] Subsequently, at T8, the delayed pixel signal (VP) can transition to a low level, corresponding to the voltage level of the pixel signal (VPX).

[0082] Figure 8 shows another embodiment of the clamp control circuit shown in Figure 1.

[0083] Referring to Figure 8, the clamp control circuit 100_1 may include a biasing circuit 110, a sensing circuit 120_1, and a clamping circuit 130. The clamp control circuit 100_1 according to the embodiment in Figure 8 differs from the clamp control circuit 100 in Figure 3 only in the configuration of the sensing circuit 120_1. For this reason, in the embodiment of Figure 8, redundant explanations of the same configuration and operation as in Figure 3 will be omitted, and only the differences will be explained.

[0084] The sensing circuit 120_1 may include a plurality of transistors (P1, P2, N7), a capacitor (C2), and a switch (SW). Here, the switching operation of the switch (SW) may be controlled by a switch control signal (SCON). The switch control signal (SCON) may be a signal applied from the timing controller 400 described above.

[0085] When the switch control signal (SCON) is activated, the switch (SW) may be turned on. This allows the voltage of the pixel signal (VPX) to be stored in the capacitor (C2). Conversely, when the switch control signal (SCON) is deactivated, the switch (SW) is turned off, and one end of the capacitor (C2) may become floating. This allows the voltage level of the sensing signal (VSEN) to be reduced by a certain level in accordance with the voltage stored in the capacitor (C2).

[0086] Figure 9 is a timing diagram illustrating the operation of the image sensing device according to the embodiment shown in Figure 8.

[0087] In the embodiment shown in Figure 9, redundant explanations of operations identical to those in Figure 7 are omitted, and only the operations of the different parts are described.

[0088] Referring to Figure 9, in section T3, the switch control signal (SCON) may be activated to a logical high level before the clamp enable signal (C_EN) transitions to a logical high level. This turns on the switch (SW), allowing the voltage level of the sensing signal (VSEN) to be discharged by the voltage level of the pixel signal (VPX) and gradually decrease. In section T3, the voltage level of the pixel signal (VPX) may be sensed by the turn-on of the switch (SW) and stored in the capacitor (C2).

[0089] Subsequently, in section T4, the control signal (SCON) can transition to a logically low level, and the clamp enable signal (C_EN) can transition to a logically high level. This turns off the switch (SW), reducing the voltage level of the sensing signal (VSEN) and maintaining a constant voltage level.

[0090] In section T4, the switch (SW) is turned off, which can interrupt the path between the capacitor (C2) and the column line (CL). This interrupts the path of leakage current flowing through the column line (CL), causing the voltage charged to the capacitor (C2) to rise, and the decrease in the voltage level of the sensing signal (VSEN) can be increased compared to Figure 7. As a result, in the embodiment of Figure 9, the voltage level of the pixel signal (VPX2) can be increased in clamping operation mode compared to Figure 7. [Explanation of Symbols]

[0091] 10 Image Sensing Device 100 Clamp Control Circuit 110 Biasing Circuit 120 Sensing Circuits 130 Clamping Circuit 200 Lamp Generator 310 Comparator 320 counters 400 Timing Controller

Claims

1. A sensing circuit that senses the voltage level of a pixel signal and outputs a sensing signal, A clamp control circuit comprising: a clamping circuit that controls the voltage level of a clamp voltage control signal in correspondence with the voltage level of the sensing signal; and a clamping circuit that controls the level of clamp voltage provided to a column line in correspondence with the voltage level of the clamp voltage control signal based on a clamp enable signal.

2. The aforementioned sensing circuit is A first capacitor connected between the first node and the second node to which the pixel signal is applied, A first transistor is connected between the second node and the third node, and its switching operation is controlled based on a sensing auto-zeroing signal. The clamp control circuit according to claim 1, comprising a second transistor connected between a power supply voltage application terminal and the third node, the gate terminal of which is connected to the second node.

3. The aforementioned sensing circuit is The clamp control circuit according to claim 2, further comprising a switch connected between the first node and the first capacitor, the switching operation of which is controlled by a switch control signal.

4. The aforementioned sensing circuit is The clamp control circuit according to claim 1, further comprising a sensing activation circuit that controls whether or not to activate the sensing circuit based on a sensing enable signal.

5. The clamping circuit is, A third transistor is connected between the power supply voltage application terminal and the fourth node, and the clamp voltage control signal is applied to it via the gate terminal. The clamp control circuit according to claim 4, comprising a fourth transistor connected between the fourth node and the column line, to which the clamp enable signal is applied via a gate terminal.

6. The clamp control circuit according to claim 1, wherein the clamp enable signal is deactivated during bias operation mode, and the column line is controlled to a voltage level corresponding to the pixel signal.

7. The clamp control circuit according to claim 1, wherein the clamp enable signal is activated during clamping operation mode, and the column line is controlled to the level of the clamp voltage.

8. The clamp control circuit according to claim 1, further comprising a biasing circuit for biasing the column line to a bias voltage level based on a control signal.

9. The aforementioned biasing circuit is A fifth transistor is connected between the first node and the fifth node to which the pixel signal is applied, and is controlled by the first control signal. A sixth transistor is connected between the fifth node and the sixth node and controlled by the second control signal, A seventh transistor is connected between the sixth node and the ground voltage application terminal, and its gate terminal is connected to the seventh node, An eighth transistor is connected between the bias voltage application terminal and the eighth node, to which the third control signal is applied, A ninth transistor is connected between the eighth node and the seventh node and controlled by the fourth control signal, The clamp control circuit according to claim 8, comprising a tenth transistor whose source and drain terminals are commonly connected to a ground voltage application terminal and whose gate terminal is connected to the seventh node.

10. Pixels that output pixel signals to column lines, A clamp control circuit senses the voltage level of the pixel signal and outputs a sensing signal, and controls the clamp voltage provided to the column line in response to the sensing signal during clamping operation mode to a level equal to or greater than a previously set reference voltage, An image sensing apparatus including an analog-to-digital converter that performs analog-to-digital conversion based on the voltage of the column line and a ramp signal.

11. The image sensing apparatus according to claim 10, wherein the voltage of the column line is determined based on the voltage level of the pixel signal when the reset signal is activated at the first time point.

12. The image sensing device according to claim 11, wherein, after the first time point, the auto-zeroing operation of the analog-to-digital converter is performed at the second time point based on the auto-zeroing signal.

13. The clamp control circuit is A sensing circuit that senses the voltage level of the pixel signal and outputs the sensing signal, The image sensing device according to claim 10, comprising a clamping circuit that controls the voltage level of a clamp voltage control signal in correspondence with the voltage level of the sensing signal, and controls the level of the clamp voltage in correspondence with the voltage level of the clamp voltage control signal based on a clamp enable signal.

14. The aforementioned sensing circuit is The image sensing apparatus according to claim 13, wherein the voltage level of the sensing signal is reduced by the voltage level of the pixel signal based on a sensing auto-zeroing signal.

15. The aforementioned sensing circuit is A first capacitor connected between the first node and the second node to which the pixel signal is applied, A first transistor is connected between the second node and the third node, and its switching operation is controlled based on a sensing auto-zeroing signal. The image sensing apparatus according to claim 13, further comprising: a second transistor connected between a power supply voltage application terminal and the third node, the gate terminal of which is connected to the second node.

16. The aforementioned sensing circuit is The image sensing apparatus according to claim 15, further comprising a switch connected between the first node and the first capacitor, the switching operation of which is controlled by a switch control signal.

17. The aforementioned sensing circuit is The image sensing apparatus according to claim 15, further comprising a sensing activation circuit that controls whether or not to activate the sensing circuit based on a sensing enable signal.

18. The clamping circuit is, A third transistor is connected between the power supply voltage application terminal and the fourth node, and the clamp voltage control signal is applied to it via the gate terminal. The image sensing apparatus according to claim 13, comprising a fourth transistor connected between the fourth node and the column line, to which the clamp enable signal is applied via a gate terminal.

19. The aforementioned pixel is A reset transistor that responds to a reset signal and resets the voltage in the floating diffusion region to the power supply voltage, The image sensing apparatus according to claim 10, comprising a transmission transistor that responds to a transmission signal and transmits the photocharge accumulated in the photoelectric conversion element to the floating diffusion region.

20. The previously set reference voltage is, The image sensing device according to claim 19, which is set to the voltage level of the reset signal.

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