Imaging device

Abstract

To provide an imaging device that generates high-quality image data. [Solution] The imaging device includes a first pixel including a first photoelectric converter, a second pixel including a second photoelectric converter, a third pixel including a third photoelectric converter, a fourth pixel including a fourth photoelectric converter, a fifth pixel including a fifth photoelectric converter, a sixth pixel including a sixth photoelectric converter, a first signal line electrically connected to the first and second pixels and outputting a first signal read from the first pixel and a second signal read from the second pixel, a second signal line electrically connected to the third and fourth pixels and outputting a third signal read from the third pixel and a fourth signal read from the fourth pixel, a third signal line electrically connected to the fifth and sixth pixels and outputting a fifth signal read from the fifth pixel and a sixth signal read from the sixth pixel, and a control unit that corrects the first signal output to the first signal line using the fifth signal output to the third signal line.

Description

Technical Field

[0001] The present invention relates to an imaging device.

Background Art

[0002] An image sensor that reads signals for each pixel block including a plurality of pixels is known (for example, Patent Document 1). Conventionally, improvement in the quality of an image generated from the output signals has been desired.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

[0004] According to the first embodiment, the imaging device includes a first pixel including a first photoelectric conversion unit that converts light into electric charge, a second pixel including a second photoelectric conversion unit that converts light into electric charge and is located next to the first photoelectric conversion unit in the row direction, a third pixel including a third photoelectric conversion unit that converts light into electric charge and is located next to the second photoelectric conversion unit in the row direction, a fourth pixel including a fourth photoelectric conversion unit that converts light into electric charge and is located next to the third photoelectric conversion unit in the row direction, a fifth pixel including a fifth photoelectric conversion unit that converts light into electric charge and is located next to the second photoelectric conversion unit in the column direction, and a photoelectric conversion unit that converts light into electric charge and is located next to the third photoelectric conversion unit in the column direction, and The device includes a sixth pixel, which includes a sixth photoelectric conversion unit positioned next to the fifth photoelectric conversion unit in the writing direction; a first signal line electrically connected to the first and second pixels, which outputs a first signal read from the first pixel and a second signal read from the second pixel; a second signal line electrically connected to the third and fourth pixels, which outputs a third signal read from the third pixel and a fourth signal read from the fourth pixel; a third signal line electrically connected to the fifth and sixth pixels, which outputs a fifth signal read from the fifth pixel and a sixth signal read from the sixth pixel; and a control unit that corrects the first signal output to the first signal line using the fifth signal output to the third signal line. [Brief explanation of the drawing]

[0005] [Figure 1] This is a schematic cross-sectional view showing the configuration of the imaging device. [Figure 2] This is an overall plan view of the image sensor as seen from the imaging surface side. [Figure 3] Figure 2 is a magnified view of a portion of the image sensor shown. [Figure 4] This is a circuit diagram of the pixels and readout circuit of the image sensor. [Figure 5] This diagram schematically shows an example of the output of pixels in each pixel block. [Figure 6] This is a cross-sectional view of the image sensor. [Figure 7] This figure shows a portion of the pixels of the image sensor in the modified example 1. [Figure 8] This figure shows a portion of the pixels of the image sensor in modified example 2. [Figure 9] This figure shows a portion of the pixels of the image sensor in modified example 3. [Figure 10] This figure shows a portion of the pixels of the image sensor in modified example 4. [Figure 11] This figure shows a portion of the pixels of the image sensor in another example of Modification 4. [Modes for carrying out the invention]

[0006] Referring to the drawings, an imaging device and an image sensor provided in one embodiment will be described. Figure 1 is a schematic block diagram showing the configuration of an imaging device according to an embodiment. Figure 1 shows an example configuration of an electronic camera 1 (hereinafter referred to as camera 1), which is an example of an imaging device according to an embodiment. For the sake of explanation, a Cartesian coordinate system consisting of the x, y, and z axes is provided as shown in the figure. In Figure 1, the z axis is provided along the optical axis O direction of the imaging optical system 2, and the y axis is provided perpendicular to the z axis and along the vertical direction of the paper in Figure 1. The x axis is provided along the direction perpendicular to the y and z axes. Camera 1 comprises an imaging optical system (imaging optical system) 2, an image sensor 3, a control unit 4, a memory 5, and an operation unit 7. The imaging optical system 2 has multiple lenses, including a focusing lens, and an aperture, and forms an image of the subject on the image sensor 3. The imaging optical system 2 may be detachable from camera 1.

[0007] The image sensor 3 is, for example, a CMOS image sensor. The image sensor 3 receives a light beam that has passed through the imaging optical system 2 and captures an image of the subject. The image sensor 3 has a plurality of pixels, each having a microlens and a photoelectric conversion unit, arranged in a two-dimensional manner (in the row direction and the intersecting column direction), as will be described in detail later. The photoelectric conversion unit is composed of, for example, a photodiode (PD). The image sensor 3 has imaging pixels and AF pixels (focus detection pixels). The imaging pixels photoelectrically convert the incident light and output a signal (image signal) used for image generation. The AF pixels photoelectrically convert the incident light and output a signal (focus detection signal) used for focus detection. The signals (image signal, focus detection signal) generated by the image sensor 3 are output to the control unit 4.

[0008] Memory 5 is a recording medium such as a memory card. Image data and the like are recorded in Memory 5. The control unit 4 is responsible for writing data to and reading data from Memory 5. The operation unit 7 includes various setting switches such as a release button and a power switch, and outputs operation signals corresponding to each operation to the control unit 4.

[0009] The control unit 4 is composed of a CPU, ROM, RAM, etc., and controls each part of the camera 1 based on a control program. The control unit 4 includes an image data generation unit 4a. The image data generation unit 4a generates image data by performing various image processing on the imaging signal output from the image sensor 3. Image processing includes known image processing such as grayscale conversion processing, color interpolation processing, and edge enhancement processing.

[0010] The image sensor 3 provided in the camera 1 of this embodiment will be described in detail. Figure 2 schematically shows the overall configuration of the image sensor 3 as viewed from the imaging surface side, i.e., from the +z side in Figure 1. The image sensor 3 has multiple pixels 30 arranged in the x and y directions in Figure 2. Although some parts are omitted in Figure 2, the pixels 30 may be arranged in large numbers, for example, 1000 or more, in both the x and y directions. In the region where multiple pixels 30 are arranged (imaging region), a horizontal control unit HC is provided at the left end in the figure, and a vertical control unit VC is provided at the top end in the figure.

[0011] The image sensor 3 has multiple pixel regions R. In Figure 2, one pixel region R has multiple pixels 30 arranged in the x and y directions, enclosed by a boundary line BB shown by a dashed line. Figure 2 illustrates a case where multiple pixel regions R, each consisting of 8x8 pixels totaling 64 pixels 30, are provided. Each pixel region R is arranged in a first period in the x direction and a second period in the y direction. The first and second periods, respectively, are the number of pixels in the x direction and y direction of the pixel region R, and in this embodiment, the case where there are 8 pixels is given as an example. As described later, each of the multiple pixels 30 within each pixel region R has its output unit connected to one output line and to one readout unit. Alternatively, each of the multiple pixels 30 within each pixel region R may be connected to multiple output lines and to multiple readout units. Furthermore, the outer shape of the pixel region R is not limited to the rectangle shown in Figure 2, but may be any shape that encompasses multiple pixels 30. In this case, the shape of the boundary line BB is not a simple straight line, but rather a shape formed by multiple straight lines bending and connecting.

[0012] In the example shown in Figure 2, of the 64 pixels 30 arranged in a total of 8 in the x-direction and 8 in the y-direction within the pixel region R, 16 pixels 30 with diagonal lines form one pixel block BC. Note that the number of pixels 30 arranged in each direction and the y-direction within one pixel block BC is not limited to 16; it may be 8, 32, or other numbers. Also, the number of pixels arranged in the x-direction and the y-direction may differ.

[0013] Figure 3 is a magnified view of a portion of the pixel block BC shown in Figure 2. As shown in Figure 3, multiple pixels 30 are provided with one of three color filters having different spectral characteristics, such as R (red), G (green), and B (blue). The R color filter mainly transmits light in the red wavelength range, the G color filter mainly transmits light in the green wavelength range, and the B color filter mainly transmits light in the blue wavelength range. Pixels have different spectral characteristics depending on the color filter they are fitted with. Pixels 30 include pixels sensitive to red (R) light (hereinafter referred to as R pixels 30R), pixels sensitive to green (G) light (hereinafter referred to as G pixels 30Gr or G pixels 30Gb), and pixels sensitive to blue (B) light (hereinafter referred to as B pixels 30B). These pixels 30 are arranged in a so-called Bayer array. G pixels 30Gb are G pixels positioned in the same x-direction as B pixels 30B, and G pixels 30Gr are G pixels positioned in the same x-direction as R pixels 30R.

[0014] The plurality of pixel blocks BC in this embodiment include a first pixel block group G1 and a second pixel block group G2. The first pixel block group G1 consists of a plurality of pixel blocks BC arranged in a first period in the x direction and a second period in the y direction. The first period and the second period, respectively, are the number of pixels in the x direction and the number of pixels in the y direction of the pixel region R described above, and in this embodiment, the case where there are 8 pixels is given as an example. In the following description, the pixel blocks BC that constitute the first pixel block group G1 will be referred to as the first pixel block BC1, and in Figure 3, the area enclosed by the boundary line BB1 ​​shown by a dashed line will be used as an example. Each first pixel block BC1 has 16 G pixels 30Gr each from among G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within the pixel region R1 enclosed by the boundary line BB1. In Figure 3, the G pixels 30Gr that constitute the first pixel block BC1 are shown with diagonal lines. Furthermore, in Figure 3, representative first pixel blocks BC1a, BC1b, BC1c, and BC1d are shown among the multiple first pixel blocks BC1. The first pixel blocks BC1a and BC1b, and BC1c and BC1d are aligned in the x-direction, and the first pixel blocks BC1a and BC1c, and BC1b and BC1d are aligned in the y-direction.

[0015] The second pixel block group G2 consists of a plurality of pixel blocks BC that are displaced from each pixel block BC1 of the first pixel block group G1 by a first shift amount different from the first period in the x direction and a second shift amount different from the second period in the y direction. In the following description, the pixel block BC that constitutes the second pixel block group G2 is referred to as the second pixel block BC2, and in FIG. 3, 16 pixels 30 within a pixel region R2 surrounded by a boundary line BB2 indicated by a dashed line are taken as an example. The second pixel block BC2 has 16 G pixels 30Gb each, among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within the pixel region R2 surrounded by the boundary line BB2. In FIG. 3, dots are attached to the G pixels 30Gb that constitute the second pixel block BC2. Also, in FIG. 3, among the plurality of second pixel blocks BC2, the second pixel blocks BC2a, BC2b, BC2c, and BC2d are shown as representatives. The second pixel blocks BC2a and BC2b and BC2c and BC2d are arranged in the x direction, and the second pixel blocks BC2a and BC2c and BC2b and BC2d are arranged in the y direction. The G pixel 30Gr that constitutes the first pixel block BC1 and the G pixel 30Gb that constitutes the second pixel block BC2 both have a first spectral sensitivity. The first spectral sensitivity is, as an example, a spectral sensitivity in which the sensitivity to green light is higher than the sensitivity to blue or red light.

[0016] In the present embodiment, an example is given in the case where the first shift amount and the second shift amount are each set to half the size of the pixel block BC (that is, four pixels 30, which are half of the first period and the second period) as the shift amount. For this reason, the second pixel block BC2 includes a part of the pixel region R1 corresponding to each of the plurality of pixel blocks BC1. For example, in the second pixel block BC2a, in a pixel region R2 including a part of the pixel region R1 corresponding to the first pixel block BC1a, a part of the pixel region R1 corresponding to the first pixel block BC1b, a part of the pixel region R1 corresponding to the first pixel block BC1c, and a part of the pixel region R1 corresponding to the first pixel block BC1d, a plurality of G pixels 30Gb are arranged in the x direction and the y direction. Note that the first shift amount is not limited to being half of the size of the pixel block BC (i.e., the first period), and can be a value of 40% or more and 60% or less of the first period. Similarly, the second shift amount is not limited to being half of the size of the pixel block BC (i.e., the second period), and can be a value of 40% or more and 60% or less of the second period. The first shift amount and the second shift amount may be different values.

[0017] FIG. 4 is an enlarged view schematically showing an overview of the electrical circuit of the pixels 30 included in the first pixel block BC1 and the second pixel block BC2 shown in FIG. 3. FIG. 4(a) shows the relationship between the pixel block BC and the vertical selection lines, horizontal selection lines, etc., and FIG. 4(b) shows the configuration of the electrical circuit of each pixel 30. For convenience of illustration, only an overview of the electrical circuits of the G pixels 30Gr constituting the first pixel block BC1 and the G pixels 30Gr constituting the second pixel block BC2 is shown, and the illustration of the other R pixels 30R and B pixels 30B is omitted, but the R pixels 30R and B pixels 30B have the same configuration. Also, in FIG. 4, among the plurality of first pixel blocks BC1 and the plurality of second pixel blocks BC2, the pixels 30 of the first pixel block BC1a and the second pixel block BC2a are shown as representatives.

[0018] From the vertical control unit VC (see FIG. 2), vertical selection lines VS11 to VS14, VS21 to VS24 (collectively also referred to as vertical selection lines VS) connected to the vertical selection transistors TV (described later) of each pixel 30 extend in the y direction. From the horizontal control unit HC, horizontal selection lines HS11 to HS14, HS21 to HS24 (collectively also referred to as horizontal selection lines HS) connected to the horizontal selection transistors TH (described later) of each pixel 30 extend in the x direction. Each of the vertical selection lines VS11 to VS14, VS21 to VS24 is shared by a plurality of pixels 30 arranged in the y direction, and each of the horizontal selection lines HS11 to HS14, HS21 to HS24 is shared by a plurality of pixels 30 arranged in the x direction.

[0019] In each pixel 30, the photoelectric conversion unit, the photodiode PD, converts incident light into electricity to generate charge, and temporarily stores the generated charge. The transfer transistor TX transfers the charge stored in the photodiode PD to the floating diffusion (FD) region FD where capacitance CC is formed, based on a transfer signal sent to its gate from a transfer control line (not shown). The amplification transistor TA outputs a signal corresponding to the charge generated in the photodiode PD when a voltage generated in the FD region FD by the transferred charge is applied to its gate.

[0020] The power supply voltage VDD is applied to the input side (drain) of the amplification transistor TA. The reset transistor TR resets the voltage in the FD region to the power supply voltage VDD by discharging the charge in the FD region FD to the power supply voltage VDD side.

[0021] The output side (source side) of the amplification transistor TA of each pixel 30 is connected to the input side of the vertical selection transistor TV. The gate of the vertical selection transistor TV of pixel 30 in the first pixel block BC1 is connected to the vertical selection lines VS11 to VS14, and the vertical selection transistor TV becomes conductive or non-conductive according to the control signal sent from the vertical control unit VC shown in Figure 2. The gate of the vertical selection transistor TV of pixel 30 in the second pixel block BC2 is connected to the vertical selection lines VS21 to VS24, and the vertical selection transistor TV becomes conductive or non-conductive according to the control signal sent from the vertical control unit VC shown in Figure 2.

[0022] The output side of the vertical selection transistor TV of each pixel 30 is connected to the input side of the horizontal selection transistor TH. The gate of the horizontal selection transistor TH of pixel 30 in the first pixel block BC1 is connected to horizontal selection lines HS11 to HS14, and the horizontal selection transistor TH becomes conductive or non-conductive according to the control signal sent from the horizontal control unit HC shown in Figure 2. The gate of the horizontal selection transistor TH of pixel 30 in the second pixel block BC2 is connected to horizontal selection lines HS21 to HS24, and the horizontal selection transistor TH becomes conductive or non-conductive according to the control signal sent from the horizontal control unit HC shown in Figure 2.

[0023] The output side of the horizontal selection transistor TH is connected to the output line RW, and it is an output unit that outputs a signal based on the charge generated by photoelectric conversion to the output line RW, which is a signal line. The output line RW is connected to the readout unit 100 that reads the signal from the pixel 30. The readout unit 100 has, for example, an AD conversion unit that converts the analog signal output from the pixel 30 into a digital signal, and is provided for each pixel block BC. As described above, the readout unit 100 is provided for each pixel block BC. That is, the signal output from each pixel 30 of the first pixel block BC1 is output to the readout unit 100a via the output line RW1, and the signal output from each pixel 30 of the second pixel block BC2 is output to the readout unit 100b via the output line RW2.

[0024] The imaging operation of the image sensor 3 in this embodiment, including the reset operation of the pixels 30, is substantially the same as that of a conventional 4-transistor CMOS image sensor. That is, prior to the exposure operation for imaging or focus detection, the reset transistor TR and the transfer transistor TX conduct to the power supply voltage VDD, and the FD area FD and the photodiode PD are reset to the power supply voltage VDD. Subsequently, the transfer transistor TX is deconducted, and exposure for imaging or focus detection is performed by the photodiode PD.

[0025] Next, we will explain how to read the signal from the pixels 30 of the image sensor 3. The vertical control unit VC sends signals to the vertical selection lines VS11, VS12, VS13, and VS14 connected to each of the four G pixels 30Gr in the nth row of the first pixel block BC1 shown in Figure 4(a), causing the respective vertical selection transistor TV of each G pixel 30Gr to conduct. Then, the transfer transistor TX of each G pixel 30Gr in the nth row is turned on, and the horizontal control unit HC sends signals to the horizontal selection lines HS11, HS12, HS13, and HS14, sending signals to turn on the horizontal selection transistor TH of each G pixel 30Gr. Through the above control, the signals (G signals) of each G pixel 30Gr in the nth row of the first pixel block BC1 are output to output lines RW11, RW12, RW13, and RW14. As a result, the readout unit 100a connected to the first pixel block BC1 can read the signals (G signals) of each G pixel 30Gr in the nth row of the first pixel block BC1. Subsequently, the vertical control unit VC sends signals to the vertical selection lines VS11, VS12, VS13, and VS14 to de-conduct the vertical selection transistor TV. The horizontal control unit HC sends signals to the horizontal control lines HS11, HS12, HS13, and HS4 to de-conduct the transfer transistor TX. The same process is then performed, and the reading unit 100a reads out signals (G signals) from each G pixel 30Gr in the (n+2)th row, each G pixel 30Gr in the (n+4)th row, and each G pixel 30Gr in the (n+6)th row of the first pixel block BC1.

[0026] The vertical control unit VC sends signals to the vertical selection lines VS21, VS22, VS23, and VS24 connected to each of the four G pixels 30Gb in the (n+3)th row of the second pixel block BC2 shown in Figure 4(a), causing the respective vertical selection transistor TV of each G pixel 30Gb to conduct. Then, the transfer transistor TX of each G pixel 30Gb in the (n+3)th row to conduct, and the horizontal control unit HC sends signals to the horizontal selection lines HS21, HS22, HS23, and HS24, sending signals to cause the horizontal selection transistor TH of each G pixel 30Gb to conduct. Through the above control, the signals (G signals) of each G pixel 30Gb in the (n+3)th row of the second pixel block BC2 are output to output lines RW21, RW22, RW23, and RW24. As a result, the readout unit 100b connected to the second pixel block BC2 can read the signals (G signals) of each G pixel 30Gb in the (n+3)th row of the second pixel block BC2. Subsequently, the vertical control unit VC sends signals to the vertical selection lines VS21, VS22, VS23, and VS24 to de-conduct the vertical selection transistor TV. The horizontal control unit HC sends signals to the horizontal control lines HS21, HS22, HS23, and HS24 to de-conduct the transfer transistor TX. The same process is then performed, and the reading unit 100b reads out signals (G signals) from each G pixel 30Gb in the (n+5)th row, each G pixel 30Gb in the (n+7)th row, and each G pixel 30Gb in the (n+9)th row of the second pixel block BC2.

[0027] The above describes the reading of signals from pixels 30 within one first pixel block BC1 and one second pixel block BC2. The same applies to other first pixel blocks BC1 in the first pixel block group G1 and other second pixel blocks BC2 in the second pixel block group G2. The signals from each pixel 30 within each pixel block BC are output to the output line RW provided within each pixel block BC and read out by the readout unit 100. The vertical selection line VS may be shared by multiple pixel blocks BC. For example, the vertical selection lines VS11 to VS14 may be connected to each pixel 30 in other first pixel blocks BC1 that are aligned in the y-direction with respect to the first pixel block BC1 shown in Figure 3 and Figure 4 on the right. The signals read out by the readout unit 100 of each pixel block BC are output from the image sensor 3 via an output circuit (not shown).

[0028] As described above, the output value (intensity) of the signal from each pixel block BC may fluctuate at the boundaries of the pixel block BC compared to the center of the pixel block BC, due to differences in wiring resistance and capacitance from the readout unit 100 to each pixel 30 within each pixel block BC, variations in gain for each pixel block BC, voltage unevenness, control line distortion, etc. Figure 5 schematically shows an example of the signal intensity from G pixels 30Gr and G pixels 30Gb for each pixel block BC. Figure 5(a) shows the signal intensity from two representative first pixel blocks BC1 adjacent in the x direction from the first pixel block group G1, and Figure 5(b) shows the signal intensity from two representative second pixel blocks BC2 adjacent in the x direction from the second pixel block group G2. In Figure 5, the vertical axis represents the signal intensity, and the horizontal axis represents the x-direction position (pixel row) of the pixel 30.

[0029] Figure 5 shows an example of output variation in each pixel block BC, where the signal intensity is high in the center of each pixel block BC and decreases as you approach the boundary. In Figure 5(a), the signal intensity (G signal) from the G pixel 30Gr in the mth column (see Figure 3) at the x-direction edge of the first pixel block BC1 is lower than the signal from the G pixel 30Gr of the first pixel block BC1. Similarly, in the adjacent first pixel block BC1, the signal intensity (G signal) from the G pixel 30Gr in the m+2th column (see Figure 3), which is at the edge, is lower than the signal from the G pixel 30Gr in the center. Likewise, in Figure 5(b), the signal intensity (G signal) from the G pixel 30Gb in the m+3rd column (see Figure 3) at the edge of the second pixel block BC2 is lower than the signal from the G pixel 30Gb in the center of the second pixel block BC2. In the adjacent second pixel block BC2, the signal intensity from the G pixel 30Gb in the m+5th column at the edge (see Figure 3) is lower than the signal from the G pixel Gb30 in the central part.

[0030] As described above, the second pixel block BC2 is set to a position shifted by half the size of pixel block BC relative to the first pixel block BC1. Therefore, the image data generation unit 4a interpolates the signal intensity from the G pixels 30Gr near the boundary of the first pixel block BC1 (the mth and m+2nd columns) using the signal intensity from the G pixels 30Gb in the m+1th column of the second pixel block BC2. This corrects the decrease in signal intensity from the G pixels 30Gr in the mth column (G signal) and the decrease in signal intensity from the G pixels 30Gr in the m+2nd column (G signal), thereby suppressing fluctuations in the G signal in the central part and near the boundary of the first pixel block BC1. For the signal intensity from the G pixels 30Gb near the boundary of the second pixel block BC2, the image data generation unit 4a interpolates using the signal from the G pixels 30Gr of the first pixel block BC1. After the above processing, the image data generation unit 4a generates image data by performing various image processing on the signal output from the image sensor 3. As a result, fluctuations in the G signal in pixel block BC are corrected, producing image data in which unevenness is suppressed.

[0031] Figure 6 shows a cross-section of the pixel 30 portion of the image sensor 3 in this embodiment. Note that Figure 6 shows only a portion of the cross-section of the image sensor 3 as a whole. The x and z directions shown in Figure 6 are the same as the directions shown in Figure 1. The image sensor 3 is a so-called back-illuminated image sensor. The image sensor 3 converts light incident from the plane of the paper into photoelectric power. The image sensor 3 comprises a first semiconductor substrate 7 and a second semiconductor substrate 8.

[0032] As described above, the image sensor 3 has multiple pixels 30. Each pixel 30 includes an upper part 30x provided on the first semiconductor substrate 7 and a lower part 30y provided on the second semiconductor substrate 8. The upper part 30x of each pixel includes a microlens 74, a color filter 73, a light-receiving section 31 of a photodiode PD, etc.

[0033] The first semiconductor substrate 7 comprises a light-receiving layer 71 including a light-receiving portion 31 of a photodiode PD contained in the upper part 30x of a pixel, and a wiring layer 72 on which transistors such as a transfer transistor TX and an amplification transistor TA are formed. The light-receiving layer 71 is located on the opposite side (back side) of the first semiconductor substrate 7 from the wiring layer 72. Multiple light-receiving portions 31 are arranged in a two-dimensional manner on the light-receiving layer 71.

[0034] The second semiconductor substrate 8 includes a vertical selection transistor TV, a horizontal selection transistor TH, a vertical selection line VS, a horizontal control line HS, a readout section 100, and a current source CS, all of which are located in the lower part 30y of the pixel. Multiple bumps 75 are arranged on the surface of the wiring layer 72. Multiple bumps 76 corresponding to the multiple bumps 75 are arranged on the surface of the second semiconductor substrate 8 facing the wiring layer 72. The multiple bumps 75 and the multiple bumps 76 are joined to each other. The first semiconductor substrate 7 and the second semiconductor substrate 8 are electrically connected via the multiple bumps 75 and the multiple bumps 76.

[0035] The configurations of the circuit elements arranged on the first semiconductor substrate 7 and the second semiconductor substrate 8 described above are merely examples, and some of these components may be arranged on either the first semiconductor substrate 7 or the second semiconductor substrate 8. For example, a light-receiving layer 71 including the light-receiving portion 31 of the photodiode PD, a transfer transistor TX, an amplification transistor TA, and a vertical selection transistor TV may be formed on the first semiconductor substrate 7, while a horizontal selection transistor TH, a horizontal control line HS, a readout unit 100, and a current source CS may be arranged on the second semiconductor substrate 8.

[0036] A light-receiving layer 71 including the light-receiving portion 31 of the photodiode PD, a transfer transistor TX, an amplification transistor TA, a vertical selection transistor TV, a horizontal selection transistor TH, and a horizontal control line HS may be formed on the first semiconductor substrate 7, and the readout portion 100 and the current source CS may be arranged on the second semiconductor substrate 8. The vertical control unit VC and the horizontal control unit HC may be placed on either the first semiconductor substrate 7 or the second semiconductor substrate 8. Furthermore, the pixel 30 is not limited to a stacked structure having a first semiconductor substrate 7 and a second semiconductor substrate 8, and each of the above configurations may be arranged on a single semiconductor substrate.

[0037] However, if many circuit elements are placed on the first semiconductor substrate 7, it becomes impossible to secure sufficient area or volume for placing the light-receiving unit 31 on the first semiconductor substrate 7. Therefore, it is preferable to place the reading unit 100 and the current source CS on the second semiconductor substrate 8. Each of the 30 pixels has a color filter 73 that is matched to the spectral sensitivity characteristics of that pixel.

[0038] In the above embodiments of the image sensor, the arrangement of each pixel 30 is not necessarily limited to a Bayer arrangement. Also, the horizontal control line HS may extend in the direction of the shorter side (y direction) of the image sensor 3 rather than the direction of the longer side (x direction), and the vertical selection line VS may extend in the direction of the longer side (x direction) rather than the direction of the shorter side (y direction) of the image sensor 3. Furthermore, the horizontal control line HS and vertical selection line VS that control the signal output of each pixel 30 do not necessarily have to extend in the horizontal (x direction) and vertical (y direction) directions.

[0039] According to the above-described embodiment, the following effects and advantages can be obtained. (1) Multiple pixel blocks BC include a first pixel block group G1 and a second pixel block group G2. In the first pixel block group G1, the first pixel blocks BC1 are aligned in the first direction (x direction) for a first period and in the second direction (y direction) for a second period. In the second pixel block group G2, the second pixel blocks BC2 are aligned with respect to each of the first pixel blocks BC1 of the first pixel block group G1 by a first shift amount different from the first period in the first direction (x direction) or a second shift amount different from the second period in the second direction (y direction). As a result, when the signal intensity from the first pixel block BC1 fluctuates within the pixel block BC due to differences in wiring resistance and capacitance from the readout unit 100 to each pixel 30 within the pixel block BC, variations in gain for each pixel block BC, voltage unevenness, control line distortion, etc., the signal fluctuations can be corrected using the signal from the second pixel block BC2. As a result, high-quality image data is generated in which the occurrence of unevenness caused by the boundaries of pixel blocks BC is suppressed.

[0040] (2) At least a portion of the pixels 30 included in the second pixel block BC2 and at least a portion of the pixels 30 included in the first pixel block BC1 both have the same first spectral sensitivity. This makes it possible to correct discontinuities in the intensity of the signal (G signal) from the G pixel 30Gr of the first pixel block BC1 using the signal (G signal) from the G pixel 30Gb of the second pixel block BC2 of the same color.

[0041] (3) In the second pixel block BC2a, multiple G pixels 30Gb are arranged in the x and y directions in pixel region R2 which includes a part of the pixel region R1 corresponding to the first pixel block BC1a, a part of the pixel region R1 corresponding to the first pixel block BC1b, a part of the pixel region R1 corresponding to the first pixel block BC1c, and a part of the pixel region R1 corresponding to the first pixel block BC1d. As a result, when the signal strength from the first pixel block BC1 fluctuates within the pixel block BC due to differences in wiring resistance and capacitance from the readout unit 100 to each pixel 30 within the pixel block BC, variations in gain for each pixel block BC, voltage unevenness, control line distortion, etc., the signal fluctuations can be corrected using the signal from the second pixel block BC2. As a result, high-quality image data is generated in which the occurrence of unevenness caused by the boundaries of the pixel block BC is suppressed.

[0042] The following modifications are also within the scope of the present invention, and it is possible to combine one or more of these modifications with the embodiments described above. (Variation 1) In Modification 1, a third pixel block group is included in which multiple pixel blocks BC are further arranged in the x and y directions at a predetermined period. The pixels included in the pixel blocks of the third pixel block group (third pixel block) have a second spectral sensitivity different from the G pixels 30 of the first pixel block group G1 and the second pixel block group G2. The second spectral sensitivity is, for example, a spectral sensitivity in which the sensitivity to red light is higher than the sensitivity to blue and green light. That is, in Modification 1, the R pixels 30R constitute the third pixel block.

[0043] Figure 7 shows the pixel block BC of Modification 1. Similar to the embodiment shown in Figure 3, a first pixel block group G1 has multiple first pixel blocks BC1 consisting of G pixels 30Gr in a pixel region R1 enclosed by boundary line BB1, and a second pixel block group G2 has multiple second pixel blocks BC2 consisting of G pixels 30Rb in a pixel region R2 enclosed by boundary line BB2, in addition to a third pixel block BC3. Note that in Figure 7, one of each of the multiple first pixel blocks BC1, second pixel blocks BC2, and third pixel blocks BC3 is shown as a representative example.

[0044] The third pixel block BC3 has R pixels 30R, which are indicated by 16 horizontal lines, among G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within a pixel region R1 enclosed by the same boundary line BB1 ​​as the first pixel block BC1. The third pixel block group G3 is formed by arranging multiple of these third pixel blocks BC3 in a first period in the x direction and a second period in the y direction, similar to the first pixel block BC1. As described above, each pixel block BC is provided with a readout unit 100, so each third pixel block BC3 is also provided with a readout unit 100. In the example shown in Figure 7, the R pixel 30R is shown as the pixel 30 having the second spectral sensitivity, but the third pixel block BC3 may be formed by the B pixel 30B. In this case, the second spectral sensitivity is, for example, a spectral sensitivity in which the sensitivity to blue light is higher than the sensitivity to red or green light.

[0045] (Modification 2) In Modification 2, each third pixel block BC3 of the third pixel block group G3 shown in Modification 1 is positioned with a third shift amount in the x-direction that is different from the first period, or a fourth shift amount in the y-direction that is different from the second period, relative to each of the first pixel blocks BC1 of the first pixel block group G1.

[0046] Figure 8 shows the pixel block BC in Modification 2. The first pixel block BC1 and the second pixel block BC2 are set up in the same way as in the embodiment shown in Figure 3. In Figure 8, as in Figure 7, one of each of the multiple first pixel blocks BC1, second pixel block BC2, and third pixel block BC3 is shown as a representative example. In Figure 8, the third pixel block BC3 has 16 R pixels 30R, each indicated by a horizontal line, among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within the pixel region R3 enclosed by the boundary line BB3 indicated by the dashed line.

[0047] As shown in Figure 8(a), the third pixel block BC3 is positioned in the first period with a third shift amount in the x-direction that is different from the first period relative to the first pixel block BC1. This third shift amount is half the size of the pixel block BC (i.e., four times the size of pixel 30, which is half the size of the first period). Note that the third shift amount is not limited to half the size of the pixel block BC (i.e., the first period), but can be a value of 40% or more and 60% or less of the first period.

[0048] In Figure 8(b), the third pixel block BC3 is positioned in the second period with a fourth shift amount in the y-direction that is different from the second period relative to the first pixel block BC1. This fourth shift amount is half the size of the pixel block BC (i.e., four times the size of pixel 30, which is half the second period). Note that the fourth shift amount is not limited to half the size of the pixel block BC (i.e., the second period), but can be a value of 40% or more and 60% or less of the second period. In the example shown in Figure 8, the R pixel 30R is shown as the pixel 30 having the second spectral sensitivity, but the third pixel block BC3 may be formed by the B pixel 30B.

[0049] (Variation 3) The number of R pixels 30R that make up the third pixel block BC3 may be set to a number less than the number of G pixels 30Gr that make up the first pixel block BC1 (16 pixels) (for example, 4 pixels, which is 1 / 4 of the number of G pixels 30Gr). Figure 9 shows the pixel block BC in modified example 3. Note that, as with Figures 7 and 8, in Figure 9, one representative pixel block is shown from among the multiple first pixel blocks BC1, second pixel blocks BC2, and third pixel blocks BC3. Figure 9(a) shows an example where the third pixel block BC3 is composed of R pixels 30R, which are indicated by horizontal lines arranged near the four ends of a rectangular pixel region R1 enclosed by the boundary line BB1. Furthermore, Figure 9(b) shows an example where a third pixel block BC3 is formed by four R pixels 30R, indicated by horizontal lines, from among the pixels 30 arranged in a pixel region R3 enclosed by a dashed line BB3 in the vicinity of one end of a rectangular pixel region R1 enclosed by boundary line BB1. In this case, the period of the arrangement of the multiple third pixel blocks BC3 constituting the third pixel block group G3 in the x direction is half that of the first period, and the period of the arrangement in the y direction is half that of the second period. In the example shown in Figure 9, the R pixel 30R is shown as the pixel 30 having the second spectral sensitivity, but the third pixel block BC3 may be formed by the B pixel 30B.

[0050] (Modification 4) In modified example 4, the multiple pixel blocks BC include a group of fourth pixel blocks, each of which is positioned with a fifth shift amount in the x-direction different from the first period, or a sixth shift amount in the y-direction different from the second period, relative to each of the third pixel blocks BC3. The pixels 30 included in the fourth pixel blocks have the same second spectral sensitivity as the pixels 30 of the third pixel block BC3. Figure 10 shows an example of pixel block BC in Modification 4. In Modification 4, the third pixel block BC3 has eight R pixels 30R, indicated by horizontal lines, from among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array in the pixel region R1 enclosed by the boundary line BB1. The fourth pixel block BC4 has eight R pixels 30R, indicated by vertical lines, from among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array in the pixel region R2 enclosed by the boundary line BB2 common to the second pixel block BC2 shown in Figure 3. Multiple fourth pixel blocks BC4 are arranged in the x-direction in a first period and in the y-direction in a second period, forming the fourth pixel block group G4.

[0051] As shown in the figure, the fourth pixel block BC4 is positioned relative to the third pixel block BC3 by a fifth shift amount in the x-direction that is different from the first period, and a sixth shift amount in the y-direction that is different from the second period. The fifth and sixth shift amounts are each half the size of the pixel block BC (i.e., four times the size of the first and second periods, which are half the size of the pixels 30). Furthermore, the fifth shift amount is not limited to half the size of the pixel block BC (i.e., the first period), but can be a value of 40% or more and 60% or less of the first period. Similarly, the sixth shift amount is not limited to half the size of the pixel block BC (i.e., the second period), but can be a value of 40% or more and 60% or less of the second period. The fifth shift amount and the sixth shift amount may also be different values.

[0052] As described above, since each pixel block BC is provided with a readout unit 100, each third pixel block BC3 and each fourth pixel block BC4 is also provided with a readout unit 100. The image data generation unit 4a performs the same processing as described in the embodiment on the signal (R signal) from the R pixel 30R of the third pixel block BC3 and the signal (R signal) from the R pixel 30R of the fourth pixel block BC4. As a result, fluctuations in the R signals output from the third pixel block BC3 and the fourth pixel block BC4 are corrected, and image data with suppressed unevenness on the image can be generated. In the example shown in Figure 10, the R pixel 30R is shown as the pixel 30 having the second spectral sensitivity, but the third pixel block BC3 and the fourth pixel block BC4 may be formed by the B pixel 30B.

[0053] In Figure 10, the case where there are 8 R pixels 30R in the third pixel block BC3 and the fourth pixel block BC4 is shown as an example, but the number of R pixels 30R in the third pixel block BC3 and the fourth pixel block BC4 is not limited to 8. Figure 11 shows another example: the case where there are 16 R pixels 30R each in the third pixel block BC3 and the fourth pixel block BC4. In Figure 11, the third pixel block BC3 has 16 R pixels 30R, indicated by horizontal lines, among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within a 16x16 pixel region R3 enclosed by the boundary line BB3 shown by a dashed line. The fourth pixel block BC4 has 16 R pixels 30R, indicated by vertical lines, among the G pixels 30Gb, G pixels 30Gr, R pixels 30R, and B pixels 30B arranged in a Bayer array within a 16x16 pixel region R4 enclosed by the boundary line BB4 shown by a solid line.

[0054] As shown in the figure, the fourth pixel block BC4 is positioned relative to the third pixel block BC3 by a fifth shift amount in the x-direction that is different from the first period, which is the arrangement period of the first pixel block BC1, and by a sixth shift amount in the y-direction that is different from the second period, which is the arrangement period of the second pixel block BC2. The fifth shift amount is the size of five pixels of pixel 30, and the sixth shift amount is the size of two pixels of pixel 30. Note that the fifth and sixth shift amounts are not limited to the sizes shown in the example in Figure 11, and can be values ​​of 40% or more and 60% or less of the sizes of the first pixel block BC1 and the second pixel block BC2 (i.e., the first and second periods).

[0055] (Variation 5) In the embodiments and modifications 1 to 4 described above, the image sensor 3 may be a monochrome sensor instead of a color sensor in which the pixels 30 have color filters.

[0056] Although various embodiments and modifications have been described above, the present invention is not limited to these. Other embodiments conceivable within the scope of the technical idea of ​​the present invention are also included within the scope of the present invention. [Explanation of Symbols]

[0057] 1: Imaging device, 3: Image sensor, 4a: Image data generation unit, 30 pixels, 100: Reading section, BC: Pixel block, BC1: First pixel block, BC2: Second pixel block, BC3: Third pixel block, BC4: 4th pixel block, G1: First pixel block group, G2: Second pixel block group, G3: Third pixel block group, G4: Fourth pixel block group

Claims

1. A first pixel including a first photoelectric conversion unit that converts light into electric charge, A second pixel includes a photoelectric conversion unit that converts light into electric charge and is arranged next to the first photoelectric conversion unit in the row direction, A third pixel includes a photoelectric conversion unit that converts light into electric charge and is located next to the second photoelectric conversion unit in the row direction, A fourth pixel includes a photoelectric conversion unit that converts light into electric charge and is located next to the third photoelectric conversion unit in the row direction, A fifth pixel includes a photoelectric conversion unit that converts light into electric charge and is located next to the second photoelectric conversion unit in the column direction, A sixth pixel includes a photoelectric conversion unit that converts light into electric charge, the sixth photoelectric conversion unit being located next to the third photoelectric conversion unit in the column direction and next to the fifth photoelectric conversion unit in the row direction, A first signal line is electrically connected to the first pixel and the second pixel, and outputs a first signal read from the first pixel and a second signal read from the second pixel. A second signal line is electrically connected to the third pixel and the fourth pixel, and outputs the third signal read from the third pixel and the fourth signal read from the fourth pixel. A third signal line is electrically connected to the fifth pixel and the sixth pixel, and outputs the fifth signal read from the fifth pixel and the sixth signal read from the sixth pixel. A control unit that corrects the first signal output on the first signal line using the fifth signal output on the third signal line, and An imaging device equipped with the following features.

2. In the imaging apparatus according to claim 1, The first pixel and the fifth pixel include a first filter having a first spectral characteristic, The second pixel includes a second filter having a second spectral characteristic different from the first spectral characteristic. Imaging device.

3. In the imaging device according to claim 2, The control unit performs color interpolation on the first signal output to the first signal line using the fifth signal output to the third signal line. Imaging device.

4. In the imaging apparatus according to claim 1, The control unit corrects the third signal output on the second signal line using the fifth signal output on the third signal line. Imaging device.

5. In the imaging device according to claim 4, The first pixel, the third pixel, and the fifth pixel each include a first filter having first spectral characteristics. The second and fourth pixels include a second filter having a second spectral characteristic different from the first spectral characteristic. Imaging device.

6. In the imaging device according to claim 5, The control unit performs color interpolation processing on the first signal output on the first signal line and the third signal output on the second signal line using the fifth signal output on the third signal line. Imaging device.

7. In the imaging apparatus according to any one of claims 1 to 6, A first reading unit is electrically connected to the first signal line and converts the first signal output to the first signal line and the second signal output to the first signal line into digital signals. A second reading unit is electrically connected to the second signal line and converts the third signal output to the second signal line and the fourth signal output to the second signal line into digital signals. A third reading unit is electrically connected to the third signal line and converts the fifth signal output to the third signal line and the sixth signal output to the third signal line into digital signals. An imaging device equipped with the following features.

8. In the imaging device according to claim 7, The control unit corrects the first signal, which has been converted to a digital signal by the first readout unit, using the fifth signal, which has been converted to a digital signal by the third readout unit. Imaging device.

9. In the imaging apparatus according to claim 7 or claim 8, The first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, the fourth photoelectric conversion unit, the fifth photoelectric conversion unit, and the sixth photoelectric conversion unit are arranged on the first semiconductor substrate. The first reading unit, the second reading unit, and the third reading unit are arranged on a second semiconductor substrate which is laminated together with the first semiconductor substrate. Imaging device.

10. In the imaging device according to any one of claims 1 to 9, It includes a seventh pixel which contains a seventh photoelectric conversion unit that converts light into electric charge, The fifth pixel is positioned between the sixth pixel and the seventh pixel in the row direction, and the first signal line is electrically connected to the seventh pixel and read from the seventh pixel. The seventh signal is output. Imaging device.

11. In the imaging apparatus according to any one of claims 1 to 10, The control unit corrects the fifth signal output on the third signal line using the first signal output on the first signal line. Imaging device.

12. In the imaging apparatus according to any one of claims 1 to 11, The first photoelectric conversion unit, the second photoelectric conversion unit, the third photoelectric conversion unit, the fourth photoelectric conversion unit, the fifth photoelectric conversion unit, and the sixth photoelectric conversion unit are incident on light emitted from the optical system. Imaging device.

13. In the imaging apparatus according to claim 12, An imaging device comprising a mounting portion to which the optical system is detachably attached.

14. In the imaging apparatus according to claim 12 or claim 13, An imaging device comprising the aforementioned optical system.

15. In the imaging apparatus according to any one of claims 1 to 14, The control unit generates image data based on a signal corrected using the fifth signal output to the third signal line, which is one of the first signal output to the first signal line and the second signal output to the first signal line. Imaging device.

Images