3D memory

Abstract

It provides 3D memory. [Solution] This disclosure provides a three-dimensional memory and a method for manufacturing the same, a memory system, and an electronic device. The three-dimensional memory includes a stacked structure, a plurality of first stops arranged in a first direction X, a protective layer, and a plurality of contact posts. The stacked structure includes a stepped structure, which includes a plurality of stepped structures arranged in a first direction and having different heights in a second direction. The plurality of first stops are arranged on a plurality of steps of at least one stepped structure. The protective layer covers the stepped structure and the first stops, and at least a portion of the protective layer is arranged between the first stops and the steps adjacent to the first stops. The contact posts extend through the protective layer and the first stops and are connected to a gate layer at the steps corresponding to the first stops.

Claims

1. Two array regions and a stepped region arranged along a first direction, wherein the stepped region is positioned between the two array regions, A laminated structure comprising gate layers and first dielectric layers arranged alternately along a second direction intersecting the first direction, wherein the laminated structure comprises a stepped structure and a bridge structure laterally to the stepped structure in the stepped region, and the stepped structure comprises a plurality of steps, A second dielectric layer covering the side wall of the bridge structure and at least one of the plurality of steps, A third dielectric layer disposed on the first of the plurality of stages, wherein the first stage comprises a first gate layer among the gate layers in the laminated structure, and a portion of the second dielectric layer is located between the third dielectric layer and the first stage. A fourth dielectric layer covering the third dielectric layer and the first stage, Includes a contact that extends through the fourth dielectric layer, the third dielectric layer, and the second dielectric layer and contacts the first gate layer. 3D memory.

2. The material of the third dielectric layer contains silicon nitride. The three-dimensional memory according to claim 1.

3. The material of the third dielectric layer is different from the material of the gate layer. The three-dimensional memory according to claim 1.

4. The etching selectivity ratio of the third dielectric layer is different from that of the gate layer. The three-dimensional memory according to claim 1.

5. The thickness of the third dielectric layer is greater than the thickness of the first gate layer. The three-dimensional memory according to claim 1.

6. A portion of the second dielectric layer covers the side surface of the first stage. The three-dimensional memory according to claim 1.

7. The material of the second dielectric layer contains silicon oxide. The three-dimensional memory according to claim 1.

8. The second dielectric layer covering the side wall of the bridge structure and at least one of the plurality of steps is continuous. The three-dimensional memory according to claim 1.

9. The material of the fourth dielectric layer contains silicon oxide. The three-dimensional memory according to claim 1.

10. The present invention further includes peripheral devices, which include peripheral circuits, and which are joined to the laminated structure in the second direction. The three-dimensional memory according to claim 1.

11. The laminated structure further comprises a first core array structure and a second core array structure in the two array regions, respectively. The bridge structure is located between the first core array structure and the second core array structure in the first direction and is connected to the first core array structure and the second core array structure, respectively. The three-dimensional memory according to claim 1.

12. A first semiconductor structure, A laminated structure comprising gate layers and first dielectric layers arranged alternately along a first direction, wherein the laminated structure comprises a stepped structure and a bridge structure on the side of the stepped structure, and the stepped structure comprises a plurality of steps, A second dielectric layer covering the side wall of the bridge structure and at least one of the plurality of steps, A third dielectric layer disposed on the first of the plurality of stages, wherein the first stage comprises a first gate layer among the gate layers in the laminated structure, and a portion of the second dielectric layer is located between the third dielectric layer and the first stage. A fourth dielectric layer covering the third dielectric layer and the first stage, A contact extending through the fourth dielectric layer, the third dielectric layer and the second dielectric layer, and in contact with the first gate layer, A first semiconductor structure including, A second semiconductor structure including peripheral circuits, The second semiconductor structure is joined to the first semiconductor structure in the first direction. 3D memory.

13. The first semiconductor structure includes two array regions and a step region arranged along a second direction intersecting the first direction, The aforementioned tiered region is located between the two array regions, and the tiered structure and the bridge structure are located within the tiered region. The three-dimensional memory according to claim 12.

14. The laminated structure further comprises a first core array structure and a second core array structure in the two array regions, respectively. The bridge structure is located between the first core array structure and the second core array structure in the second direction and is connected to the first core array structure and the second core array structure, respectively. The three-dimensional memory according to claim 13.

15. The material of the third dielectric layer contains silicon nitride. The three-dimensional memory according to claim 12.

16. The etching selectivity ratio of the third dielectric layer is different from that of the gate layer. The three-dimensional memory according to claim 12.

17. The thickness of the third dielectric layer is greater than the thickness of the first gate layer. The three-dimensional memory according to claim 12.

18. A portion of the second dielectric layer covers the side surface of the first stage. The three-dimensional memory according to claim 12.

19. The material of the second dielectric layer contains silicon oxide, and the material of the fourth dielectric layer contains silicon oxide. The three-dimensional memory according to claim 12.

20. The second dielectric layer covering the side wall of the bridge structure and at least one of the plurality of steps is continuous. The three-dimensional memory according to claim 12.

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