Silicon carbide substrate and method for manufacturing the same

Abstract

This invention improves the reliability of silicon carbide substrates by increasing the efficiency of converting basal plane dislocations (BPDs), which are defects that degrade electrical conductivity, into harmless through-edge dislocations (TEDs), and by preventing the injection of minority carriers into the substrate. [Solution] In a silicon carbide substrate having a SiC substrate 1 and epitaxial layers formed sequentially on the SiC substrate 1, namely a first semiconductor layer 11, a second semiconductor layer 2, and a drift layer 3, the impurity concentration of the first semiconductor layer 11 is lower than that of the SiC substrate 1 and the second semiconductor layer 2, and the second semiconductor layer 2 is formed with a high impurity concentration or as a thick film.

Description

[Technical Field]

[0001] This invention relates to a silicon carbide substrate and a method for producing the same. [Background technology]

[0002] Semiconductor power devices require high voltage resistance, low on-resistance, and low switching losses, but silicon (Si) power devices, which are currently the mainstream, are approaching their theoretical performance limits. Silicon carbide (SiC) has a dielectric breakdown field strength that is about an order of magnitude higher than that of Si, so by making the drift layer that maintains the voltage resistance about 1 / 10th thinner and increasing the impurity concentration by about 100 times, the device resistance can be theoretically reduced by more than three orders of magnitude. In addition, because its band gap is about three times larger than that of Si, it can operate at high temperatures, and SiC semiconductor devices are expected to have performance that surpasses that of Si semiconductor devices.

[0003] Because SiC has several stable crystal structures with similar energy levels, crystal rearrangement occurs relatively easily. It is known that when current is applied, the BPDs (Basal Plane Dislocations) in the crystal receive the recombination energy of injected holes and electrons, causing them to expand into stacking faults. Stacking faults reduce the minority carrier lifetime and trap majority carriers, so if they expand significantly, resistance increases and device characteristics deteriorate. This phenomenon undermines the reliability of the device, so efforts are being made to reduce BPDs.

[0004] Patent Document 1 (International Publication No. 2018 / 150861) describes a SiC substrate with an impurity concentration lower than that of the SiC substrate and higher than that of the drift layer, with an impurity concentration of 1 × 10⁻¹⁶. 17 cm -3 The following describes forming a first semiconductor layer (first epitaxial layer) to convert BPDs into TEDs (Threading Edge Dislocations). Furthermore, a second semiconductor layer (second epitaxial layer) with a higher impurity concentration than the first semiconductor layer is formed on top of the first semiconductor layer to suppress the expansion of the depletion layer.

[0005] Patent Document 2 (International Publication No. 2016 / 092887) describes a method for controlling the expansion of stacking faults by sequentially forming a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer on a SiC substrate, where the density of the second epitaxial layer is set to 1 × 10⁻¹⁶. 17 cm -3 The document describes a structure that, by increasing the voltage and thinning the film thickness, can suppress the increase in on-resistance without reducing the breakdown voltage. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] International Publication No. 2018 / 150861 [Patent Document 2] International Publication No. 2016 / 092887 [Overview of the project] [Problems that the invention aims to solve]

[0007] A large number of BPDs (Ballpoint Dispersion Factors) exist in a SiC substrate. Even if the BPDs are converted to TEDs (Targeted Electron Dispersion Factors) by an epitaxial film formed on the substrate, when holes are injected into the substrate during device operation, hole-electron recombination occurs in the substrate, resulting in the growth of stacking faults from the substrate's BPDs. These stacking faults expand into the epitaxial layer, leading to a problem of increased resistance in the device.

[0008] While it is possible to set operating conditions to prevent excessive hole flow to the substrate portion of the element, surge currents or imbalances between parallel elements can cause more hole injection than expected. Furthermore, the amount of holes injected into the substrate during element operation will vary depending on the element's rated voltage or maximum current density.

[0009] As described herein, methods for increasing the efficiency of converting BPD present in a substrate into TED by an epitaxial film formed on the substrate and preventing holes from being injected into the substrate during device operation are not disclosed in Patent Documents 1 and 2.

[0010] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0011] Among the embodiments disclosed in the present application, the outline of representative ones will be briefly described as follows.

[0012] The silicon carbide substrate in one embodiment includes a first substrate of a predetermined conductivity type containing silicon carbide, a first semiconductor layer of the conductivity type containing silicon carbide formed on the first substrate, a second semiconductor layer of the conductivity type containing silicon carbide formed on the first semiconductor layer, and a third semiconductor layer of the conductivity type containing silicon carbide formed on the second semiconductor layer. The first semiconductor layer is in contact with the upper surface of the first substrate, and the first impurity concentration of the first semiconductor layer is lower than both the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first substrate. The second impurity concentration N2 [cm -3 , the film thickness W2 [μm] of the second semiconductor layer, and the rated voltage Vn [V] of the device formed on the silicon carbide substrate satisfy the following formula (1), W2 ≧ (-2.69×10 12 ln(Vn) + 2.22×10 13 )N2 -0.65 ···(1).

[0013] In the silicon carbide substrate in one embodiment, the first impurity concentration is greater than 1×10 16 cm -3 and less than or equal to 1×10 17 cm​​​​​In one embodiment, the silicon carbide substrate has a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

[0015] A silicon carbide substrate in one embodiment comprises a first substrate of a predetermined conductivity type containing silicon carbide, a first semiconductor layer of the same conductivity type containing silicon carbide formed on the first substrate, a second semiconductor layer of the same conductivity type containing silicon carbide formed on the first semiconductor layer, and a third semiconductor layer of the same conductivity type containing silicon carbide formed on the second semiconductor layer, wherein the first semiconductor layer is in contact with the upper surface of the first substrate, and the first impurity concentration of the first semiconductor layer is lower than the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first substrate, and the second impurity concentration N2[cm -3 The thickness W2 [μm] of the second semiconductor layer and the rated voltage Vn [V] of the element formed on the silicon carbide substrate are given by the following equation (2), W2 ≥ (-2.53 × 10 12 ln(Vn) + 2.16 × 10 13 )N2 -0.65 ...(2) The conditions shown are met.

[0016] In one embodiment, the silicon carbide substrate has a first impurity concentration of 1 × 10 16 cm -3 Larger, 1 x 10 17 cm -3 The following are the items.

[0017] In one embodiment, the silicon carbide substrate has a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

[0018] A silicon carbide substrate in one embodiment comprises a first substrate of a predetermined conductivity type containing silicon carbide, a first semiconductor layer of the same conductivity type containing silicon carbide formed on the first substrate, a second semiconductor layer of the same conductivity type containing silicon carbide formed on the first semiconductor layer, and a third semiconductor layer of the same conductivity type containing silicon carbide formed on the second semiconductor layer, wherein the first semiconductor layer is in contact with the upper surface of the first substrate, and the first impurity concentration of the first semiconductor layer is lower than the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first substrate, and the second impurity concentration N2[cm -3 ], the film thickness W2 [μm] of the second semiconductor layer, and the maximum current density J [A / cm²] when the element formed on the silicon carbide substrate is in use. 2 ] and the following equation (3), W2 ≥ (2.52 × 10 12 ln(J)-1.31×10 13 )N2 -0.65 ...(3) The conditions shown are met.

[0019] In one embodiment, the silicon carbide substrate has a first impurity concentration of 1 × 10 16 cm -3 Larger, 1 x 10 17 cm -3 The following are the items.

[0020] In one embodiment, the silicon carbide substrate has a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

[0021] A method for manufacturing a silicon carbide substrate in one embodiment comprises: (a) preparing a first substrate of a predetermined conductivity type containing silicon carbide; (b) forming a first epitaxial layer of the conductivity type containing silicon carbide on the first substrate; (c) forming a second epitaxial layer of the conductivity type containing silicon carbide on the first epitaxial layer; and (d) forming a third epitaxial layer of the conductivity type containing silicon carbide on the second epitaxial layer. Here, the first impurity concentration of the first epitaxial layer is lower than the second impurity concentration of the second epitaxial layer and the fourth impurity concentration on the upper surface of the first substrate, and the second impurity concentration N2 [cm -3 The thickness W2 [μm] of the second epitaxial layer and the rated voltage Vn [V] of the element formed on the silicon carbide substrate are given by the following equation (1), W2 ≥ (-2.69 × 10 12 ln(Vn) + 2.22 × 10 13 )N2 -0.65 ...(1) The conditions shown are met.

[0022] A method for manufacturing a silicon carbide substrate in one embodiment comprises: (a) preparing a first substrate of a predetermined conductivity type containing silicon carbide; (b) forming a first epitaxial layer of the conductivity type containing silicon carbide on the first substrate; (c) forming a second epitaxial layer of the conductivity type containing silicon carbide on the first epitaxial layer; and (d) forming a third epitaxial layer of the conductivity type containing silicon carbide on the second epitaxial layer. Here, the first impurity concentration of the first epitaxial layer is lower than the second impurity concentration of the second epitaxial layer and the fourth impurity concentration on the upper surface of the first substrate, and the second impurity concentration N2 [cm -3 ], the film thickness W2 [μm] of the second epitaxial layer, and the maximum current density J [A / cm²] when the element formed on the silicon carbide substrate is in use. 2 ] and the following equation (3), W2 ≥ (2.52 × 10 12 ln(J)-1.31×10 13 )N2 -0.65 ...(3) The conditions shown are met. [Effects of the Invention]

[0023] According to a typical embodiment, the reliability of the silicon carbide semiconductor substrate can be improved. [Brief explanation of the drawing]

[0024] [Figure 1] This is a plan view showing a stage in which a unit cell has been formed using a semiconductor chip with a silicon carbide substrate, which is Embodiment 1 of the present invention. [Figure 2] This is a cross-sectional view of a semiconductor chip along line AA in Figure 1. [Figure 3] This is a plan view of a semiconductor chip using a silicon carbide substrate, which is Embodiment 1 of the present invention. [Figure 4] This is a cross-sectional view showing the manufacturing process of a semiconductor chip using a silicon carbide substrate, which is Embodiment 1 of the present invention. [Figure 5] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 4. [Figure 6] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 5. [Figure 7] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 6. [Figure 8] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 7. [Figure 9] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 8. [Figure 10] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 9. [Figure 11] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 10. [Figure 12] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 11. [Figure 13] This is a cross-sectional view showing the semiconductor chip manufacturing process, following Figure 12. [Figure 14] This graph shows the relationship between the impurity concentration and film thickness of the second semiconductor layer of a silicon carbide substrate, which is Embodiment 1 of the present invention. [Figure 15]This graph shows the relationship between a coefficient that defines the relationship between the impurity concentration and film thickness of the second semiconductor layer of a silicon carbide substrate, which is Embodiment 1 of the present invention, and the rated voltage. [Figure 16] This graph shows the relationship between the impurity concentration and film thickness of the second semiconductor layer of a silicon carbide substrate, which is Embodiment 2 of the present invention. [Figure 17] This graph shows the relationship between a coefficient that defines the relationship between the impurity concentration and film thickness of the second semiconductor layer of a silicon carbide substrate, which is Embodiment 2 of the present invention, and the rated voltage. [Figure 18] This graph shows the relationship between the film thickness of the first semiconductor layer and the ratio of its resistance in an embodiment of the present invention. [Figure 19] This graph shows the relationship between the film thickness of the first semiconductor layer and the ratio of its resistance in an embodiment of the present invention. [Figure 20] This graph shows the relationship between the impurity concentration and film thickness of the second semiconductor layer of a silicon carbide substrate, which is Embodiment 3 of the present invention. [Figure 21] This graph shows the relationship between the coefficient that defines the relationship between the impurity concentration and film thickness of the second semiconductor layer of the silicon carbide substrate, which is Embodiment 3 of the present invention, and the current density. [Modes for carrying out the invention]

[0025] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0026] Furthermore, the signs "-" and "+" represent the relative concentrations of impurities with conductivity types n-type or p-type. For example, in the case of n-type impurities, the impurity concentration increases in the order of "n--", "n-", "n", "n+", and "n++".

[0027] In this application, the term "substrate" can refer to either a semiconductor substrate that does not include an epitaxial layer, or a substrate having a laminated structure that includes a semiconductor substrate and an epitaxial layer on the semiconductor substrate. In the following embodiments, when simply referred to as "SiC substrate," "semiconductor substrate," or "SiC semiconductor substrate," these substrates refer to substrates that do not include an epitaxial layer. In contrast, when simply referred to as "silicon carbide substrate" in the following embodiments, this substrate refers to a laminated substrate that includes a semiconductor substrate and an epitaxial layer on the semiconductor substrate. The following description will mainly focus on Embodiment 1, and in this application, when referred to as "this embodiment," it refers to Embodiment 1. However, Figures 16 and 17 and their descriptions, as well as formula (2), correspond to Embodiment 2. Furthermore, the modifications described later can be applied to either Embodiment 1 or 2.

[0028] (Embodiment 1) <Silicon Carbide Substrate Composition> The structure of the semiconductor chip using the silicon carbide substrate of this embodiment will be described below with reference to Figures 1 to 3. Figure 1 is a plan view of the semiconductor chip using the silicon carbide substrate of this embodiment at the stage in which a unit cell 70 has been formed. Figure 2 is a cross-sectional view of the semiconductor chip along line AA in Figure 1. Figure 3 is a plan view of the semiconductor chip using the silicon carbide substrate of this embodiment, showing the pad formation layer above the region where the multiple elements shown in Figure 1 are formed.

[0029] As shown in Figure 1, the semiconductor chip 60 has a drift layer 3, which is an epitaxial layer formed on the surface side of the semiconductor substrate, on the semiconductor substrate. Figure 1 mainly shows the upper surface of the drift layer 3, and the gate insulating film, gate electrode, interlayer insulating film, silicide layer, contact plug, passivation film, and pads on the drift layer 3 are omitted from the illustration. Figure 1 shows the upper surface of the drift layer 3 and various semiconductor regions formed on the upper surface.

[0030] The left side of Figure 2 is a cross-sectional view along line AA in Figure 1, showing the structure of the central element region of the semiconductor chip 60 (see Figures 1 and 3), which includes SiC (silicon carbide) MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In other words, the cross-sectional view on the left side of Figure 2 shows cross-sections of multiple SiC MOSFETs (hereinafter sometimes simply referred to as MOSFETs) in the active region of the semiconductor chip 60.

[0031] On the right side of Figure 2, a graph shows the relationship between the depth direction and impurity concentration of the cross-sectional structure shown on the left side of Figure 2. In other words, the horizontal axis of the graph represents the impurity concentration Nd (here, the concentration of n-type impurities), and the vertical axis represents the depth. Here, depth refers to the depth from the top surface to the bottom surface of the stacked structure consisting of the SiC substrate (semiconductor substrate, semiconductor layer) 1, the first semiconductor layer (basal plane dislocation conversion layer, epitaxial layer) 11, the second semiconductor layer (epitaxial layer) 2, and the drift layer (semiconductor layer, epitaxial layer) 3 that constitute the semiconductor chip 60. Furthermore, depth refers to the distance from top to bottom in the direction perpendicular to the main surface of the SiC substrate 1. In this graph, only the impurity concentrations of the SiC substrate 1, the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3 are shown, and the impurity concentrations of other areas where contact regions, well regions, source regions, and drain regions are formed are not shown.

[0032] The SiC substrate 1 is an n++ type hexagonal semiconductor substrate, and the SiC substrate 1, the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3 are all composed of n-type semiconductors made of SiC (silicon carbide). The silicon carbide substrate in this embodiment is composed of a laminated structure consisting of the SiC substrate 1, the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3 that constitute the semiconductor chip 60.

[0033] Furthermore, the term "silicon carbide substrate" in this application does not refer only to the disc-shaped substrate before dicing, but also to the substrate that constitutes the semiconductor chip obtained after the dicing process is performed on the epitaxial layer on the substrate in which elements have been formed.

[0034] As shown in Figure 1, the silicon carbide substrate of this embodiment is equipped with multiple MOSFETs, each consisting of a cell structure, and the individual silicon carbide substrates constitute a semiconductor chip 60. The gate electrodes (not shown) and pads used to supply potential to the source region 81 that constitute these MOSFETs are shown in Figure 3.

[0035] As shown in Figure 3, a gate pad 61 is formed on the upper surface of the semiconductor chip 60, to which a gate voltage is applied from an external control circuit (not shown). The gate pad 61 is electrically connected to the gate electrode 92 (see Figure 2) that constitutes the MOSFET. In addition, the source regions of each of the multiple MOSFETs formed on the semiconductor chip 60 are electrically connected in parallel and connected to the source pad 62. In other words, one source pad 62 is electrically connected to multiple source regions.

[0036] In the central element region (active region) 65 of the semiconductor chip 60 shown in Figure 1, multiple unit cells 70, which are the smallest unit structures of a MOSFET, are arranged. The gate voltage applied to the gate pad 61 shown in Figure 3 is supplied to the gate electrode (not shown) of each unit cell 70 through the gate pad 61. Note that the position and number of gate pads 61, or the shape of the source pad 62, shown in Figure 3, can vary widely, but this does not affect the effect of the silicon carbide substrate in this embodiment.

[0037] As shown in Figure 1, the semiconductor chip 60 has a rectangular shape in plan view. In plan view, an element region 65 exists in the center of the semiconductor chip 60, and a peripheral region 66 and a termination region 67 surround the element region 65. In other words, in plan view, the element region 65, peripheral region 66, and termination region 67 exist in order from the center of the upper surface of the drift layer 3 on the semiconductor substrate constituting the semiconductor chip 60 toward the edge of the upper surface of the drift layer 3.

[0038] The termination region 67 includes the peripheral region 66. The peripheral region 66 is a power supply section for supplying potential to the JTE (Junction Termination Extension) region 85 formed in the termination region 67. Both the peripheral region 66 and the termination region 67 have annular structures that extend along each side of the rectangular semiconductor chip 60. The JTE region 85 is a p-type semiconductor region formed on the upper surface of the drift layer 3.

[0039] Multiple unit cells 70, each consisting of a well region 80, a source region 81, and a first contact region 82, are arranged in the element region 65, which is the region surrounded by the peripheral region 66. A unit cell 70 is the smallest unit structure of a MOSFET. On the upper surface of the drift layer 3, the multiple unit cells 70 are spaced apart from each other. In a plan view, within each unit cell 70, the first contact region 82 is at the center, with the source region 81 and the well region 80 arranged in order around it.

[0040] In other words, in a plan view, the source region 81 is formed so as to surround the outside of the first contact region 82, and the well region 80 is formed so as to surround the outside of the source region 81. In a plan view, the first contact region 82, the source region 81, and the well region 80 all have a rectangular structure.

[0041] The first contact region 82 and the source region 81 are adjacent to each other, and a silicide layer 95 (see Figure 2) is formed on the upper surfaces of the first contact region 82 and the source region 81 so as to straddle the boundary between the first contact region 82 and the source region 81.

[0042] Here, the unit cell 70 is shown as having a square structure in a plan view, but it is not limited to this; for example, the shape of the unit cell 70 may be rectangular or polygonal. Also, although only five unit cells 70 are shown in Figure 1, in reality, many more unit cells 70 are arranged within the element region 65.

[0043] Furthermore, in this configuration, multiple unit cells 70 are arranged in a first direction parallel to two parallel edges of the semiconductor chip 60, and multiple such rows are arranged in a direction perpendicular to the first direction. In addition, unit cells 70 in adjacent rows in the second direction are arranged alternately with a half-cycle shift in the first direction. However, the configuration is not limited to this; multiple unit cells 70 may be arranged at equal pitches in both the vertical and horizontal directions. In other words, multiple unit cells 70 may be arranged in a matrix.

[0044] Within the peripheral region 66, an annular second contact region 83 is formed on the upper surface of the drift layer 3. The peripheral region 66 here refers to the region that overlaps with the second contact region 83 in a plan view. In other words, the layout of the peripheral region 66 is determined by the formation region of the second contact region 83. The second contact region 83 is a p+ type semiconductor region formed on the upper surface of the drift layer 3. The second contact region 83 is a region formed to fix the potential of the termination region 67, and also a region for supplying potential to the JTE region 85.

[0045] By applying a potential to the JTE region 85 via the second contact region 83, electric field concentration in the termination region when a reverse voltage is applied can be mitigated, and the breakdown voltage of the semiconductor chip can be maintained at a high level. Here, a structure in which a JTE region is formed as the termination structure of the semiconductor chip is described, but in order to mitigate the electric field of the semiconductor chip, the termination structure may also be an FLR (Field Limiting Ring) structure having multiple p-type semiconductor regions that surround the element region in a ring shape in a plan view.

[0046] As shown in Figure 2, the semiconductor chip 60 of this embodiment (see Figure 1) has a SiC substrate 1 which is an n++ type hexagonal semiconductor substrate. An n- type first semiconductor layer 11 made of SiC with a lower impurity concentration than the SiC substrate 1 is formed on the SiC substrate 1. An n+ type second semiconductor layer 2 is formed on the first semiconductor layer 11, with a higher impurity concentration than the first semiconductor layer 11. An n-- type drift layer 3 made of SiC with a lower impurity concentration than the first semiconductor layer 11 is formed on the second semiconductor layer 2.

[0047] The SiC substrate 1, the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3 contain n-type impurities (e.g., nitrogen (N) or phosphorus (P)). The impurity concentrations of the SiC substrate 1, the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3 all refer to the concentrations of n-type impurities. In the device region, multiple n-channel type MOSFET cell structures are formed on the upper surface of the drift layer 3.

[0048] As shown in the graph on the right side of Figure 2, the relative impurity concentrations are SiC substrate 1, second semiconductor layer 2 > first semiconductor layer 11 > drift layer 3. There is no specified relationship between the impurity concentrations of SiC substrate 1 and second semiconductor layer 2, but the main feature of this embodiment is that a first semiconductor layer (basal plane defect conversion layer) 11 with a lower impurity concentration than SiC substrate 1 is formed on a high-concentration SiC substrate 1 so as to be in contact with the main surface of SiC substrate 1, and the impurity concentration N2 of the second semiconductor layer 2 formed thereon, the film thickness W2 of the second semiconductor layer 2, and the rated voltage Vn of the device satisfy the following equation (1). W2 ≥ (-2.69 × 10 12 ln(Vn) + 2.22 × 10 13 )N2 -0.65 ...(1) In this application, the coefficient refers to the part multiplied by N2 in equation (1), that is, "(-2.69 × 10 12 ln(Vn) + 2.22 × 10 13 This is the part that says ")". The rated voltage is set with a margin relative to the input voltage for each application, for example, 1700V, 3300V, 6500V for railway applications, and 600V, 1200V for automotive applications. In the case of MOSFETs, the breakdown voltage when a voltage is applied between the source and drain electrodes in the off state with 0V or a negative voltage applied to the gate is designed and manufactured to be higher than the rated voltage.

[0049] Another feature of this embodiment is that the impurity concentration of the first semiconductor layer 11 is higher than the impurity concentration of the drift layer 3 having an element on its upper surface. In Figure 2, the impurity concentration of the second semiconductor layer 2 is shown to be constant in the film thickness direction, but it may vary in the film thickness direction within a range that satisfies the relationship between the magnitudes of the impurity concentrations, in which case the average concentration is considered to be N2.

[0050] The concentration of n-type impurities in the SiC substrate 1 is, for example, 1 × 10⁻⁶ 18 cm -3 Larger, 1 x 10 19 cm -3The following applies: The main surface of the SiC substrate 1 is, for example, a {0001} plane tilted at 4 to 8 degrees in the <11-20> direction. For example, the film thickness of the first semiconductor layer 11 is several hundred nm to 2 μm. The n-type impurity concentration of the first semiconductor layer 11 is 1 × 10⁻⁶ 16 cm -3 Larger, 1 x 10 17 cm -3 The following applies: The film thickness of the second semiconductor layer 2 is, for example, 0.5 μm or more, and the n-type impurity concentration of the second semiconductor layer 2 is 1 × 10⁻¹⁶. 17 cm -3 The above conditions satisfy equation (1). The thickness of the drift layer 3 is, for example, 3 to 120 μm. The n-type impurity concentration of the drift layer 3 can be arbitrarily set according to the specifications of the power device formed on top of the drift layer 3, for example, 1 × 10⁻⁶ 14 cm -3 ~5×10 16 cm -3 It is less than.

[0051] Although there is some overlap in the numerical values ​​of the impurity concentrations of the substrate and each semiconductor layer exemplified here, in the silicon carbide substrate of this embodiment, it is preferable that the order of impurity concentrations is SiC substrate 1 > first semiconductor layer 11 > drift layer 3. For example, if the impurity concentration of drift layer 3 is 2 × 10⁻⁶ 16 cm -3 In that case, the impurity concentration of the first semiconductor layer 11 is always 2 × 10⁻⁶. 16 cm -3 Larger.

[0052] Furthermore, on the back side opposite the main surface of the semiconductor chip 60 (see Figure 1), the drain wiring electrode 90 for the MOSFET is formed. Specifically, on the back surface of the SiC substrate 1, a drain region 84, which is an n-type semiconductor region with a higher impurity concentration than the SiC substrate 1, is formed, and a third silicide layer 100 is formed in contact with the bottom surface of the drain region 84. In other words, the back surface of the SiC substrate 1 is covered by the third silicide layer 100. The bottom surface of the third silicide layer 100, that is, the surface opposite to the SiC substrate 1 side, is covered by the drain wiring electrode 90.

[0053] In the device region, multiple well regions 80, which are p-type semiconductor regions, are formed at a predetermined depth from the upper surface of the drift layer 3. Each well region 80 is a semiconductor region into which p-type impurities (e.g., aluminum (Al) or boron (B)) have been introduced. Within each well region 80, a source region 81, which is an n+-type semiconductor region, is formed at a predetermined depth from the upper surface of the drift layer 3. Each source region 81 is a semiconductor region into which n-type impurities (e.g., nitrogen (N) or phosphorus (P)) have been introduced.

[0054] Furthermore, within each well region 80, a first contact region 82, which is a p+ type semiconductor region, is formed at a predetermined depth from the upper surface of the drift layer 3. The first contact region 82 is a region provided to fix the potential of the well region and has approximately the same depth as the source region 81. The first contact region 82 is a semiconductor region into which p-type impurities (e.g., aluminum (Al) or boron (B)) have been introduced. The first contact region 82 is positioned so as to be sandwiched on both sides by adjacent source regions 81. In addition, the bottom of the first contact region 82, as well as the bottom and sides of the source region 81, are covered by the well region.

[0055] Multiple unit cells 70, each consisting of a well region 80, a source region 81, and a first contact region 82, are formed on the upper surface of the drift layer 3, and the unit cells 70 are spaced apart from each other. Between adjacent unit cells 70, gate electrodes 92 are formed on the drift layer 3 via gate insulating film 91, and the upper surface of the ends of the gate insulating film 91, and the sides and upper surface of the gate electrodes 92 are covered by interlayer insulating film 93. In the openings 68 between the interlayer insulating films 93 covering each gate electrode 92, the first contact region 82 and the source region 81 are not covered by the gate insulating film 91, the gate electrode 92, and the interlayer insulating film 93. In other words, the gate insulating film 91, the gate electrode 92, and the interlayer insulating film 93 have openings 68 that reach the upper surface of the unit cells 70, and the first contact region 82 and the source region 81 are exposed at the bottom of the openings 68.

[0056] A silicide layer 95 is formed on the surface of a portion of the source region 81 and the first contact region 82 that are exposed at the opening 68 of the interlayer insulating film 93 in the element region, i.e., at the bottom of the contact hole. Contact plugs 94, which are connecting parts, are embedded in the opening 68 on the silicide layer 95 that is in contact with a portion of the source region 81 and the first contact region 82. Each of the multiple contact plugs 94 embedded in the multiple openings 68 is integrated with a source wiring electrode 96 formed in the interlayer insulating film 93. The source wiring electrode 96 is electrically connected to a source pad 62 (see Figure 3). Here, the upper surface of the source wiring electrode 96 exposed from the passivation film (not shown) covering the upper part of the termination region constitutes the source pad 62.

[0057] A portion of the source region 81 and the first contact region 82 are electrically connected to the contact plug 94 via the silicide layer 95 in an ohmic manner. Thus, a portion of the source region 81 and the first contact region 82 are connected to the source pad 62 via the silicide layer 95, the contact plug 94, and the source wiring electrode 96. Similarly, a contact plug is connected to the gate electrode 92 in a region not shown, and the gate electrode 92 is electrically connected to the gate pad 61 (see Figure 3) via the contact plug and the gate wiring electrode.

[0058] The MOSFET formed on the semiconductor chip of this embodiment has at least a gate electrode 92, a source region 81, and a drain region 84. When operating the MOSFET, a predetermined voltage is applied to the gate electrode 92 to turn on the MOSFET, causing current to flow from the drain, which has a higher potential, to the source, which has a lower potential. The channel region of the MOSFET is formed in the upper part of the well region 80, which is a p-type semiconductor region. In other words, the current used to drive the MOSFET flows from the drain wiring electrode 90, through the region in the drift layer 3 near the gate insulating film 91, through the region in the well region 80 near the upper surface of the drift layer 3, which is directly below the gate electrode 92, and then flows to the source region 81.

[0059] In this embodiment, when potential is supplied to the first contact region 82, a pn current flows through the pn junction of the MOSFET's built-in diode (built-in pn diode). When potential is supplied to the second contact region 83, a pn current flows through the pn junction of the built-in diode in the termination region. The built-in diode of the MOSFET referred to here is, for example, the pn junction between the p-type well region 80 connected to the p+-type first contact region 82 and the n---type drift layer 3. The built-in diode of the termination region referred to here is, for example, the pn junction between the p-type JTE region 85 (see Figure 1) connected to the p+-type second contact region 83 (see Figure 1) and the n----type drift layer 3. In this application, the current flowing through the pn connections in the substrate including the drift layer 3 is called the pn current.

[0060] <Method for manufacturing silicon carbide substrates> The silicon carbide substrate and the method for manufacturing a semiconductor device including the substrate in this embodiment will be described in order of steps using Figures 4 to 13. Figures 4 to 13 are cross-sectional views showing the manufacturing process of a semiconductor chip using the silicon carbide substrate of this embodiment. Figures 4 to 13 show cross-sections of the element region where a MOSFET is formed. The cross-sections of the element region in Figures 4 to 13 are cross-sections at the same positions as those described using Figure 2.

[0061] First, as shown in Figure 4, an n+ type SiC substrate 1 is prepared. The SiC substrate 1 contains a relatively high concentration of n-type impurities. These n-type impurities are, for example, nitrogen (N), and the impurity concentration of these n-type impurities is, for example, 10 18 cm -3 Larger, 1 x 10 19 cm -3 The following applies: The main surface of the SiC substrate 1 is, for example, a {0001} surface tilted at 4 to 8 degrees in the <11-20> direction. Both the main surface and the back surface opposite the main surface of the SiC substrate 1 are polished by the CMP (Chemical Mechanical Polishing) method to a mirror finish.

[0062] Next, as shown in Figure 5, a first semiconductor layer 11, a second semiconductor layer 2, and a drift layer 3 are formed sequentially on the SiC substrate 1. In other words, various semiconductor layers (epitaxial layers, epitaxial growth layers) made of SiC are formed sequentially by the epitaxial growth method as follows.

[0063] First, the SiC substrate 1 is RCA cleaned and then placed in the susceptor inside the furnace of the chemical vapor deposition (CVD) apparatus. Next, the furnace is filled with 1 × 10 -4 The furnace is evacuated until the vacuum level is below Pa. Next, hydrogen, which is the carrier gas, is introduced into the furnace, and the pressure inside the furnace is set to approximately 1 to 40 kPa. While introducing hydrogen in this manner, the susceptor is maintained at the set temperature. The set temperature of the susceptor is, for example, 1400 to 1700°C. Next, the raw material gas is introduced into the furnace. Silane and propane are used as the raw material gas, and nitrogen is used as the impurity dopant gas. With the supply of these raw material gases, the growth of the epitaxial layer made of SiC begins.

[0064] By performing epitaxial growth while arbitrarily changing the gas flow rate, susceptor setting temperature, and furnace pressure, a first semiconductor layer (first epitaxial layer) 11, a second semiconductor layer (second epitaxial layer) 2, and a drift layer (third epitaxial layer) 3 are sequentially formed on the SiC substrate 1 with desired impurity concentrations and film thicknesses.

[0065] The first semiconductor layer 11 is a layer provided at the interface between the SiC substrate 1 and the first semiconductor layer 11 to improve the efficiency of the conversion of BPD to TED. This improvement in conversion efficiency is achieved by utilizing the property that when impurities propagate from a layer with a high impurity concentration to a layer with a low impurity concentration, the conversion from BPD to TED becomes more likely due to the concentration difference between those layers. Therefore, the first semiconductor layer 11 is formed with a lower impurity concentration than the SiC substrate 1.

[0066] The n-type impurity concentration in the first semiconductor layer 11 is 1 × 10⁻⁶ 16 cm-3 Larger, 1 x 10 17 cm -3 The following is the case. In order to improve the efficiency of BPD conversion to TED at the interface between the SiC substrate 1 and the semiconductor layer 11, it is desirable that the impurity concentration of the first semiconductor layer 11 be low. However, as the concentration of the first semiconductor layer 11 decreases, the resistance increases, so in power devices where the current path is between the top surface of the epitaxial layer and the back surface of the substrate, the device characteristics deteriorate. For this reason, the impurity concentration of the first semiconductor layer 11 is 1 × 10⁻⁶. 16 cm -3 It needs to be made larger.

[0067] Furthermore, the thickness of the first semiconductor layer 11 is preferably 2 μm or less. This is to prevent excessively thick film thickness, which would result in high resistance, since resistance is proportional to film thickness. However, the conversion from BPD to TED does not occur only at the interface between the SiC substrate 1 and the first semiconductor layer 11, but also progresses within the first semiconductor layer 11. Therefore, it is desirable for the first semiconductor layer 11 to have a relatively large film thickness, preferably 0.5 μm or more.

[0068] The second semiconductor layer 2 needs to have the function of attenuating minority carriers injected from the power device formed on top of the drift layer 3 to a sufficiently small amount. Therefore, the impurity concentration N2 of the second semiconductor layer 2, the film thickness W2 of the second semiconductor layer 2, and the rated voltage Vn of the device must satisfy the relationship given by equation (1).

[0069] On the other hand, if the impurity concentration of the second semiconductor layer 2 is too low, it leads to an increase in device resistance. Also, if the impurity concentration of the second semiconductor layer 2 is too high, many morphological defects (such as triangular defects) will be formed in the drift layer 3 formed on top of it. Therefore, in this case, the n-type impurity concentration of the second semiconductor layer 2 is 1 × 10⁻⁶. 17 cm -3 The above is 1 x 10 19 cm -3 It is less than [value missing]. The film thickness of the second semiconductor layer 2 is, for example, 0.5 μm or more.

[0070] The impurity concentration and film thickness of drift layer 3 are arbitrarily set according to the specifications of the power device being fabricated. For example, the impurity concentration of drift layer 3 is 1 × 10⁻⁶. 14 cm -3 ~5×10 16 cm -3 It is less than [a certain value]. The film thickness of drift layer 3 is, for example, 3 to 120 μm.

[0071] In the formation process of each layer—the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3—the flow rate of the raw material gas, the set temperature of the susceptor, and the pressure inside the furnace may be changed. Alternatively, after the deposition of each layer is completed, the supply of the raw material gas may be stopped to halt deposition, and then the supply of the raw material gas may be restarted to deposit the next layer. This allows the deposition of the next layer to proceed only after the flow rate of the raw material gas, the set temperature of the susceptor, and the pressure inside the furnace have stabilized, thereby reducing variations in impurity concentration and film thickness for each layer.

[0072] After forming the first semiconductor layer 11, the second semiconductor layer 2, and the drift layer 3, the supply of raw material gas is stopped, and hydrogen is introduced into the furnace while the susceptor is cooled. After the temperature of the susceptor has dropped sufficiently, the introduction of hydrogen is stopped, the furnace is evacuated, and the susceptor is removed. This completes the silicon carbide substrate of this embodiment.

[0073] Next, although not shown in the diagram, a mask is formed on the upper surface of the drift layer 3. The mask is a film that exposes a portion of the upper surface of the drift layer 3 in the termination region. For the mask material, for example, SiO2 (silicon oxide) or photoresist is used. Subsequently, p-type impurities (for example, aluminum (Al)) are ion-implanted into the drift layer 3 in the termination region. This forms a p-type semiconductor region, the JTE region (not shown; see JTE region 85 in Figure 1), on the upper surface of the drift layer 3 in the termination region. The depth of the JTE region from the upper surface of the drift layer 3 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the JTE region is, for example, 1 × 10⁻⁶. 16 ~5×10 19 cm -3 That is the case.

[0074] Next, as shown in Figure 6, after removing the mask, a mask 17 is formed on the upper surface of the drift layer 3. The mask 17 is a film that exposes multiple locations on the upper surface of the drift layer 3 in the element region. The thickness of the mask 17 is, for example, about 1.0 to 5.0 μm. For the material of the mask 17, for example, SiO2 or photoresist can be used.

[0075] Next, p-type impurities (e.g., aluminum (Al)) are ion-implanted into the drift layer 3, on which the mask 17 is formed at the top. This forms multiple well regions 80, which are p-type semiconductor regions, on the upper surface of the drift layer 3 in the device region. The depth of the well regions 80 from the upper surface of the drift layer 3 is, for example, about 0.5 to 2.0 μm. The impurity concentration of the well regions 80 is, for example, 1 × 10⁻¹⁶. 16 ~1 × 10 19 cm -3 That is the case.

[0076] Next, as shown in Figure 7, after removing mask 17, mask 12 is formed on the upper surface of drift layer 3. The thickness of mask 12 is, for example, about 0.5 to 2.0 μm. For the material of mask 12, for example, SiO2 or photoresist can be used.

[0077] Next, n-type impurities (e.g., nitrogen (N)) are ion-implanted into the drift layer 3, on which the mask 12 is formed at the top. This forms multiple source regions 81, which are n+-type semiconductor regions, on the upper surface of the drift layer 3 in the device region. Each source region 81 is formed in the central part of the well region 80 in a plan view. The depth of each source region 81 from the upper surface of the drift layer 3 is, for example, about 0.05 to 1.0 μm. The impurity concentration of the source region 81 is, for example, 1 × 10⁻⁶. 18 ~1 × 10 20 cm -3 That is the case.

[0078] Next, as shown in FIG. 8, after removing the mask 12, a mask 13 is formed on the upper surface of the drift layer 3. The thickness of the mask 13 is, for example, about 0.5 to 2.0 μm. For the material of the mask 13, for example, SiO2 or photoresist is used.

[0079] Next, for the drift layer 3 with the mask 13 formed thereon, p-type impurities (for example, aluminum (Al)) are ion-implanted. As a result, a plurality of first contact regions 82, which are p+-type semiconductor regions, are formed on the upper surface of the drift layer 3 in the element region, and a second contact region (not shown; refer to the second contact region 83 shown in FIG. 1), which is a p+-type semiconductor region, is formed on the upper surface of the drift layer 3 in the termination region. Each first contact region 82 is formed at the central portion in a plan view of each source region 81. The second contact region is formed on the upper surface of the JTE region 85. In a plan view, the second contact region has a rectangular annular structure and is formed so as to surround the element region.

[0080] The depth of the first contact region 82 and the second contact region from the upper surface of the drift layer 3 is, for example, about 0.05 to 2.0 μm. Also, the impurity concentration of the first contact region 82 and the second contact region is, for example, 1×10 18 ~1×10 20 cm -3 −3

[0081] Next, as shown in FIG. FIG. 9, after removing the mask 13, a mask 14 serving as a protective film is formed on the upper surface of the drift layer 3. Then, n-type impurities (for example, nitrogen (N)) are ion-implanted into the back surface of the SiC substrate 1. As a result, a drain region 84, which is an n+-type semiconductor region, is formed on the back surface of the SiC substrate 1. The depth of the drain region 84 from the back surface of the SiC substrate 1 is, for example, about 0.05 to 2.0 μm. Also, the impurity concentration of the drain region 84 is 1×10 19 ~1×10 21 cm -3 −3

[0082] Next, although not shown in the diagram, all masks are removed, and a carbon (C) film is deposited, for example, using plasma CVD, so as to be in contact with the upper surface of the drift layer 3 and the back surface of the SiC substrate 1. The thickness of the carbon (C) film is, for example, about 0.03 to 0.05 μm. After coating the upper surface of the drift layer 3 and the back surface of the SiC substrate 1 with the carbon (C) film as described above, a heat treatment is performed at a temperature of 1500 degrees Celsius or higher for about 2 to 3 minutes. This activates the impurities that were ion-implanted on the upper surface of the drift layer 3 and the back surface of the SiC substrate 1. After that, the carbon (C) film is removed, for example, by plasma treatment.

[0083] Next, as shown in Figure 10, an insulating film 89 and an n-type polycrystalline Si film are sequentially formed on the upper surface of the drift layer 3, and then a mask 15 is formed on the polycrystalline Si film. The insulating film 89 and the polycrystalline Si film are formed, for example, by CVD. The mask 15 is formed between adjacent first contact regions 82 on the upper surface of the drift layer 3. Subsequently, a gate electrode 92 made of polycrystalline Si film is formed by processing the polycrystalline Si film using a dry etching method with the mask 15. The thickness of the insulating film 89 is, for example, about 0.05 to 0.15 μm. The thickness of the gate electrode 92 is, for example, about 0.2 to 0.5 μm.

[0084] Next, after removing the mask 15, an interlayer insulating film 93 is formed on the upper surface of the drift layer 3, for example by plasma CVD, so as to cover the gate electrode 92 and the insulating film 89. Then, using the mask 16, the interlayer insulating film 93 and the insulating film 89 are processed by dry etching to expose the upper surface of the drift layer 3.

[0085] As a result, as shown in Figure 11, a gate insulating film 91 made of insulating film 89 is formed in the element region directly beneath the gate electrode 92 and the interlayer insulating film 93. Furthermore, the etching process creates an opening 68 in the interlayer insulating film 93 of the element region, exposing a part of the upper surface of the source region 81 and the first contact region 82, respectively. In the interlayer insulating film 93 of the termination region, an opening (not shown) is formed, exposing a part of the upper surface of the second contact region (not shown).

[0086] As a result, multiple unit cells 70, which are the smallest unit structures of a MOSFET, are formed. Each of the multiple unit cells 70 has a well region 80, a source region 81, and a first contact region 82 adjacent to each other, and a gate electrode 92 formed directly above the well region 80 via a gate insulating film 91.

[0087] Next, as shown in Figure 12, after removing the mask 16, a silicide layer 95 is formed at the bottom of the opening 68 in the element region, and a silicide layer (not shown) is formed on the bottom surface of the opening in the termination region.

[0088] When forming the silicide layer 95, first, a first metal (e.g., nickel (Ni)) film is deposited, for example, by sputtering, so as to cover the exposed drift layer 3. The thickness of this first metal film is, for example, about 0.05 μm. Subsequently, by performing a silicide heat treatment at 600 to 1000°C, the first metal film and the drift layer 3 are reacted at the bottom surface of the opening 68 in the element region to form a silicide layer 95 made of, for example, nickel silicide (NiSi). Through this process, a silicide layer is also formed at the bottom surface of the opening in the termination region.

[0089] Next, as shown in Figure 13, a second metal ( For example, a titanium (Ti) film, a titanium nitride (TiN) film, and an aluminum (Al) film are laminated in order. The thickness of the aluminum (Al) film is preferably 1.0 μm or more. Subsequently, the laminated film consisting of the second metal film, the titanium nitride film, and the aluminum film is processed to form a contact plug 94, a source wiring electrode 96, and a gate wiring electrode (not shown) made of the laminated film.

[0090] The source wiring electrode 96 or the gate wiring electrode is made of the laminated film on the interlayer insulating film 93, and the contact plug 94 is made of the laminated film within the opening 68. The source wiring electrode 96 is electrically connected to the first contact region 82 via the silicide layer 95 in an ohmic manner. In the termination region (not shown), the source wiring electrode 96 is connected to the second contact region via the silicide layer. The gate wiring electrode (not shown) is electrically connected to the gate electrode 92.

[0091] Next, an insulating film made of SiO2 or polyimide is deposited to cover the gate wiring electrode and the source wiring electrode 96, and the insulating film is processed to form a passivation film (not shown). The passivation film covers the termination region and has an opening in the device region.

[0092] Next, a third metal film is deposited on the back surface of the SiC substrate 1, for example by sputtering, and a laser silicide heat treatment is applied to react the third metal film with the SiC substrate 1, thereby forming a third silicide layer 100. The third silicide layer 100 is in contact with the lower surface of the drain region 84. The thickness of the third metal film is, for example, about 0.1 μm. Subsequently, a drain wiring electrode 90 is formed so as to cover the bottom surface of the third silicide layer 100. The drain wiring electrode 90 is composed of a 0.5 to 1 μm thick laminated film formed by stacking titanium (Ti) film, nickel (Ni) film, and gold (Au) film in order from the third silicide layer 100 side.

[0093] Subsequently, the SiC substrate 1 is cut into individual pieces by a dicing process, thereby obtaining multiple semiconductor chips. This completes the semiconductor chip 60 of this embodiment, including the SiCMOSFET shown in Figures 1, 2, and 3.

[0094] <Effects of this embodiment> Next, the effect of the silicon carbide substrate according to Embodiment 1 will be explained using Figures 14 to 17. In Figures 14 and 16, the plots are data interpolated by calculation based on actual measurements, and the dashed lines are approximation curves that model the plots. In Figures 15 and 17, the plots are data extracted from the approximation curves in Figures 14 and 16, and the dashed lines are approximation curves of the plots. Note that Figures 16 and 17 correspond to Embodiment 2.

[0095] A large number of BPDs (Block Deposition Factors) exist in the SiC substrate 1. If these BPDs are carried over to the drift layer 3, the minority carriers injected during normal operation of the device cause the BPDs to expand as stacking faults, resulting in an increase in device resistance. By forming a first semiconductor layer 11 on the SiC substrate 1 with a large difference in impurity concentration from the SiC substrate 1, the BPDs can be converted to TEDs (Tilted Deposition Factors), improving the reliability of the device during normal operation. The conversion efficiency from BPD to TED can be increased as the impurity concentration of the first semiconductor layer 11 decreases and as the thickness of the first semiconductor layer 11 increases.

[0096] On one hand, in a situation where a larger number of minority carriers than normal, such as a current surge, are injected, when the minority carriers reach the SiC substrate 1, stacking defects expand from the substrate, leading to an increase in the element resistance. In this situation, reducing the BPD in the drift layer 3 has no effect. FIG. 14 is a graph showing the relationship between the impurity concentration and film thickness of the second semiconductor layer 2 that can prevent the expansion of stacking defects from the substrate for elements in each rated voltage class. The vertical axis of the graph shown in FIG. 14 indicates the film thickness of the second semiconductor layer 2, and the horizontal axis indicates the n-type impurity concentration of the second semiconductor layer 2. FIG. 14 shows a graph of the rated voltage of 1.2 kV represented by circular plots, a graph of the rated voltage of 1.7 kV represented by triangular plots, and a graph of the rated voltage of 3.3 kV represented by square plots. These graphs indicate that if the relationship between the impurity concentration and film thickness described in FIG. 14 is satisfied, the number of minority carriers injected into the element can be sufficiently attenuated in the second semiconductor layer 2. Therefore, the impurity concentration or film thickness of the second semiconductor layer 2 in elements of each rated voltage class may be equal to or greater than the values shown in FIG. 14.

[0097] The higher the rated voltage class, the larger the impurity concentration or film thickness required for the second semiconductor layer 2. When the relationship between the impurity concentration and film thickness is represented by a power function (film thickness ∝ impurity concentration -0.65 ), the relationship between the coefficient and the rated voltage is as shown in the graph of FIG. 15. That is, if the relationship of Equation (1) is satisfied, the expansion of stacking defects from the substrate can also be prevented, and the long-term reliability of the element can be improved. The vertical axis of the graph shown in FIG. 15 indicates the coefficient, and the horizontal axis indicates the rated voltage of the element. Among the coefficients described on the vertical axis of FIG. 15, for example, "1" means 1×10 12 . This is the same for FIG. 17 used in the later description.

[0098] The physical meaning of Figure 14 is explained below. Minority carriers decay exponentially with time at exp(-t / relaxation time). The relationship is time t = film thickness / thermal velocity, relaxation time = 1 / (thermal velocity × capture cross-section × recombination center density), and in the second semiconductor layer 2, the recombination center density can be considered as the impurity density, so minority carriers decay at exp(-capture cross-section × impurity density × film thickness). In other words, the second semiconductor layer 2 that satisfies the relationship where capture cross-section × impurity density × film thickness is constant is the desired structure. The capture cross-section depends on the energy level of the impurity, and in the situation where donor impurities are considered as recombination centers, the energy level of the impurity depends on the impurity density. That is, since the capture cross-section depends on the impurity density, the relationship where capture cross-section × impurity density × film thickness is constant can be reduced to the relationship between impurity density and film thickness, showing the relationship shown in Figure 14.

[0099] Furthermore, situations in which a larger current flows through an element compared to the current when a single element is operating normally include current imbalances caused by variations in the characteristics of elements when multiple elements are connected in parallel. Figure 16 shows the relationship between the impurity concentration and film thickness of the second semiconductor layer 2, which can prevent the expansion of stacking faults from the substrate in such cases. In the graph shown in Figure 16, the vertical axis represents the film thickness of the second semiconductor layer 2, and the horizontal axis represents the n-type impurity concentration of the second semiconductor layer 2. Figure 16 shows graphs for a rated voltage of 1.2kV represented by circular plots, a rated voltage of 1.7kV represented by triangular plots, and a rated voltage of Vn3.3kV represented by square plots. The relationship between impurity concentration and film thickness is expressed as a power (film thickness ∝ impurity concentration). -0.65 Figure 17 shows the relationship between the coefficient and the rated voltage when expressed as ). In the graph shown in Figure 17, the vertical axis represents the coefficient, and the horizontal axis represents the rated voltage of the element. In such a case, the impurity concentration N2 [cm³] of the second semiconductor layer 2 -3Furthermore, if the relationship between the film thickness W2 [μm] of the second semiconductor layer 2 and the rated voltage Vn [V] of the device satisfies the following equation (2) derived from Figures 16 and 17, the long-term reliability of the component can be further enhanced. Figures 16 and 17 correspond to Embodiment 2. The manufacturing process in Embodiment 2 can be the same as the manufacturing process described using Figures 4 to 13. W2 ≥ (-2.53 × 10 12 ln(Vn) + 2.16 × 10 13 )N2 -0.65 ...(2) <Example 1> Here, the lower the impurity concentration of the first semiconductor layer 11 is compared to the impurity concentration of the SiC substrate 1, and the thicker the film thickness of the first semiconductor layer 11, the higher the conversion efficiency from BPD to TED. However, if the impurity concentration of the first semiconductor layer 11 is excessively low, or if the film thickness of the first semiconductor layer 11 is excessively thick, the resistance of the first semiconductor layer 11 will increase. In this case, in a power element that flows current in a direction perpendicular to the main surface of the SiC substrate 1, such as the MOSFET shown in Figure 2, the resistance between the source region 81 and the drain region 84 increases, which leads to a problem of degraded element characteristics.

[0100] Figures 18 and 19 show that the impurity concentration of the first semiconductor layer 11 is 1 × 10⁻⁶. 16 , 3 x 10 16 , 1 x 10 17 cm -3 The relationship between the film thickness of the first semiconductor layer 11 and its resistance ratio is shown. The solid lines in Figures 18 and 19 represent calculated values. In Figures 18 and 19, the vertical axis represents the ratio of the resistance of the first semiconductor layer 11 to the total resistance of the device, and the horizontal axis represents the film thickness of the first semiconductor layer 11. The total resistance of the device, in the case of a MOSFET, is the resistance between the source and drain when a sufficient positive voltage (e.g., about 15V) is applied to the gate to turn it on. Figure 18 is a graph when the rated voltage of the device is 3300V, and Figure 19 is a graph when the rated voltage of the device is 1200V. In Figures 18 and 19, the n-type impurity concentration of the first semiconductor layer 11 is 1 × 10⁻⁶. 16 cm -3 , 3 x 10 16cm -3 , 1 x 10 17 cm -3 The graphs show the cases for each of the above.

[0101] From the measurement results shown in Figures 18 and 19, in the silicon carbide substrate of this modified example, the n-type impurity concentration of the first semiconductor layer 11 is 1 × 10⁻⁶. 16 cm -3 Larger, 1 x 10 17 cm -3 The thickness of the first semiconductor layer 11 is set to 0.5 to 2 μm. This prevents an increase in the resistance of the first semiconductor layer 11. Setting the thickness of the first semiconductor layer 11 to 0.5 to 1 μm is even more effective as it suppresses the increase in resistance.

[0102] Therefore, in this modified example, it is possible to prevent the increase in resistance of the silicon carbide substrate due to the growth of BPD caused by current flow, and the increase in resistance of the silicon carbide substrate due to the reduction in density and thickness of the first semiconductor layer 11. In other words, by using a semiconductor device using a silicon carbide substrate, it is possible to prevent the deterioration of the characteristics of both the silicon carbide substrate and the semiconductor device, thereby improving the reliability of the silicon carbide substrate.

[0103] In this modified example, the propagation of basal plane dislocations (BPDs) within the epitaxial layer is suppressed, so the basal plane dislocation density in drift layer 3 is 0.03 dislocations / cm³. 2 The following is true. Furthermore, when the impurity concentration of the first semiconductor layer 11 is used at a low concentration, the basal plane dislocation density of the drift layer 3 is 0.01 dislocations / cm³. 2 The following applies:

[0104] (Embodiment 3) In the above embodiment, the case where the impurity concentration N2 of the second semiconductor layer 2, the film thickness W2 of the second semiconductor layer 2, and the rated voltage Vn of the device satisfy the relationship given by equation (1) was described. In this third embodiment, it will be explained that the conversion efficiency from BPD to TED and the reliability of the device can be improved by satisfying the relationship given by a predetermined equation between the impurity concentration N2 of the second semiconductor layer 2 (see Figure 2), the film thickness W2 of the second semiconductor layer 2, and the maximum current density J when the device is in use.

[0105] The silicon carbide substrate and the configuration of the semiconductor device using the silicon carbide substrate in this third embodiment are the same as in the above embodiment. As shown in the graph on the right side of Figure 2, the relative impurity concentrations are SiC substrate 1, second semiconductor layer 2 > first semiconductor layer 11 > drift layer 3. There is no specified relationship between the impurity concentrations of the SiC substrate 1 and the second semiconductor layer 2, but the main feature of this third embodiment is that a first semiconductor layer (basal plane defect conversion layer) 11 with a lower impurity concentration than the SiC substrate 1 is formed on the high-concentration SiC substrate 1 so as to be in contact with the main surface of the SiC substrate 1, and the impurity concentration N2 of the second semiconductor layer 2 formed thereon, the film thickness W2 of the second semiconductor layer 2, and the maximum current density J when the device is in use satisfy the following equation (3). W2 ≥ (2.52 × 10 12 ln(J)-1.31×10 13 )N2 -0.65 ...(3) In this application, when simply referring to current density, it refers to the maximum current density when the element is in use. The rated voltage of the element is set with a margin relative to the input voltage for each application, for example, 1700V, 3300V, 6500V for railway applications, and 600V, 1200V for automotive applications.

[0106] In the silicon carbide substrate of this third embodiment, the relationship of impurity concentrations is preferably SiC substrate 1 > second semiconductor layer 2 > first semiconductor layer 11 > drift layer 3. For example, the impurity concentration of the drift layer 3 is 2 × 10⁻¹⁶. 16 cm -3 In that case, the impurity concentration of the first semiconductor layer 11 is always 2 × 10⁻⁶. 16 cm -3 It is larger. Also, the impurity concentration of the second semiconductor layer 2 is 1 × 10 17 cm -3 In that case, the impurity concentration of the first semiconductor layer 11 is always 1 × 10⁻⁶. 17 cm -3 Smaller.

[0107] The second semiconductor layer 2 needs to have the function of attenuating minority carriers injected from the power device formed on top of the drift layer 3 to a sufficiently small amount. Therefore, the impurity concentration N2 of the second semiconductor layer 2, the film thickness W2 of the second semiconductor layer 2, and the current density J of the device need to satisfy the relationship given by equation (3).

[0108] <Effects of this embodiment 3> Next, the effect of the silicon carbide substrate according to this third embodiment will be explained using Figures 20 and 21. In Figure 20, the plots are data interpolated by calculation based on actual measurements, and the dashed line is an approximation curve modeling the plots. In Figure 21, the plots are data extracted from the approximation curve in Figure 20, and the dashed line is an approximation curve of the plots.

[0109] A large number of BPDs (Block Deposition Factors) exist in the SiC substrate 1. If these BPDs are carried over to the drift layer 3, the minority carriers injected during normal operation of the device cause the BPDs to expand as stacking faults, resulting in an increase in device resistance. By forming a first semiconductor layer 11 on the SiC substrate 1 with a large difference in impurity concentration from the SiC substrate 1, the BPDs can be converted to TEDs (Tilted Deposition Factors), improving the reliability of the device during normal operation. The conversion efficiency from BPD to TED can be increased as the impurity concentration of the first semiconductor layer 11 decreases and as the thickness of the first semiconductor layer 11 increases.

[0110] On the other hand, in situations where more minority carriers than usual are injected, such as during current surges, if the minority carriers reach the SiC substrate 1, stacking faults expand from the substrate, leading to an increase in device resistance. In this situation, reducing the BPD in the drift layer 3 is ineffective. Figure 20 is a graph illustrating the relationship between the impurity concentration and film thickness of the second semiconductor layer 2 that can prevent the expansion of stacking faults from the substrate for devices of each current density class. In the graph shown in Figure 20, the vertical axis represents the film thickness of the second semiconductor layer 2, and the horizontal axis represents the n-type impurity concentration of the second semiconductor layer 2. In Figure 20, the current density of 600 A / cm² is represented by a circle plot. 2 The graph and the current density of 400 A / cm² are represented by a triangular plot. 2The graph and the diamond-shaped plot represent the current density of 300 A / cm². 2 The graph and the rectangular plot represent the current density of 200 A / cm². 2 The graphs show that if the relationship between impurity concentration and film thickness described in Figure 20 is satisfied, the number of minority carriers injected into the device can be sufficiently attenuated in the second semiconductor layer 2. Therefore, the impurity concentration or film thickness of the second semiconductor layer 2 in devices of each current density class should be greater than or equal to the values ​​shown in Figure 20.

[0111] The higher the current density class, the larger the required impurity concentration or film thickness for the second semiconductor layer 2, and the relationship between impurity concentration and film thickness is expressed as an exponent (film thickness ∝ impurity concentration). -0.65 The relationship between the coefficient and current density when expressed as ) is shown in the graph in Figure 21. In other words, if the relationship in equation (1) is satisfied, the expansion of stacking faults from the substrate can be prevented, and the long-term reliability of the device can be improved. In the graph in Figure 21, the vertical axis shows the coefficient, and the horizontal axis shows the maximum current density of the device. Among the coefficients listed on the vertical axis of Figure 21, for example, "1" means 1 × 10 12 It means...

[0112] Although the present inventors have described the invention in detail based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0113] 1 SiC substrate 2. Second semiconductor layer (epitaxial layer) 3. Drift layer (epitaxial layer) 11. First semiconductor layer (basis plane dislocation transformation layer, epitaxial layer)

Claims

1. Silicon carbide substrates are A first semiconductor substrate of a predetermined conductivity type containing silicon carbide, A conductive first semiconductor layer containing silicon carbide is formed on the first semiconductor substrate, A second conductive semiconductor layer containing silicon carbide is formed on the first semiconductor layer, A conductive third semiconductor layer containing silicon carbide is formed on the second semiconductor layer, It has, The first semiconductor layer is in contact with the upper surface of the first semiconductor substrate. The first impurity concentration of the first semiconductor layer is lower than both the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first semiconductor substrate. The second impurity concentration N2 [cm] －３ The thickness W2 [μm] of the second semiconductor layer and the rated voltage Vn [V] of the element formed on the silicon carbide substrate are given by the following equation (1): W2≧(-2.69×10 １２ +.(V.)+2.22×10 １３ )N2 －０．６５ ・・・(1) A silicon carbide substrate that satisfies the conditions shown.

2. In the silicon carbide substrate according to claim 1, The first impurity concentration is 1 × 10⁻⁶ １６ cm －３ Larger, 1 x 10 １７ cm －３ The following is a silicon carbide substrate.

3. In the silicon carbide substrate according to claim 2, A silicon carbide substrate having a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

4. Silicon carbide substrates are A first semiconductor substrate of a predetermined conductivity type containing silicon carbide, A conductive first semiconductor layer containing silicon carbide is formed on the first semiconductor substrate, A second conductive semiconductor layer containing silicon carbide is formed on the first semiconductor layer, A conductive third semiconductor layer containing silicon carbide is formed on the second semiconductor layer, It has, The first semiconductor layer is in contact with the upper surface of the first semiconductor substrate. The first impurity concentration of the first semiconductor layer is lower than both the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first semiconductor substrate. The second impurity concentration N2 [cm －３ , the film thickness W2 [μm] of the second semiconductor layer, and the rated voltage Vn [V] of the element formed on the silicon carbide substrate satisfy the following formula (2) W2≧(-2.53×10 １２ +n(Vn)+2.16×10 １３ )N2 －０．６５ ・・・(2) A silicon carbide substrate that satisfies the conditions shown.

5. In the silicon carbide substrate according to claim 4, The first impurity concentration is 1 × 10⁻⁶ １６ cm －３ Larger, 1 x 10 １７ cm －３ below This is a silicon carbide substrate.

6. In the silicon carbide substrate according to claim 5, A silicon carbide substrate having a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

7. Silicon carbide substrates are A first semiconductor substrate of a predetermined conductivity type containing silicon carbide, A conductive first semiconductor layer containing silicon carbide is formed on the first semiconductor substrate, A second conductive semiconductor layer containing silicon carbide is formed on the first semiconductor layer, A conductive third semiconductor layer containing silicon carbide is formed on the second semiconductor layer, It has, The first semiconductor layer is in contact with the upper surface of the first semiconductor substrate. The first impurity concentration of the first semiconductor layer is lower than both the second impurity concentration of the second semiconductor layer and the fourth impurity concentration of the upper surface of the first semiconductor substrate. The first impurity concentration is 1 × 10⁻⁶ １６ cm －３ Larger, 1 x 10 １７ cm －３ The following: The second impurity concentration N2 [cm] －３ ], the film thickness W2 [μm] of the second semiconductor layer, and the maximum current density J [A / cm²] when the element formed on the silicon carbide substrate is in use. ２ ] and the following equation (3) W2≧(2.52×10) １２ -n(J)-1.31×10 １３ )N2 －０．６５ ・・・(3) A silicon carbide substrate that satisfies the conditions shown.

8. In the silicon carbide substrate according to claim 7, A silicon carbide substrate having a first semiconductor layer thickness of 0.5 μm or more and 2 μm or less.

9. (a) A step of preparing a first semiconductor substrate of a predetermined conductivity type containing silicon carbide, (b) A step of forming the first conductive epitaxial layer containing silicon carbide on the first semiconductor substrate, (c) A step of forming the conductive second epitaxial layer containing silicon carbide on the first epitaxial layer, (d) A step of forming the conductive third epitaxial layer containing silicon carbide on the second epitaxial layer. It has, The first impurity concentration of the first epitaxial layer is lower than both the second impurity concentration of the second epitaxial layer and the fourth impurity concentration on the upper surface of the first semiconductor substrate. The second impurity concentration N2 [cm] －３ The thickness W2 [μm] of the second epitaxial layer and the rated voltage Vn [V] of the element formed on the silicon carbide substrate are given by the following equation (1) W2≧(-2.69×10 １２ +.(V.)+2.22×10 １３ )N2 －０．６５ ・・・(1) A method for manufacturing a silicon carbide substrate that satisfies the conditions shown.

10. (a) A step of preparing a first semiconductor substrate of a predetermined conductivity type containing silicon carbide, (b) A step of forming the first conductive epitaxial layer containing silicon carbide on the first semiconductor substrate, (c) A step of forming the conductive second epitaxial layer containing silicon carbide on the first epitaxial layer, (d) A step of forming the conductive third epitaxial layer containing silicon carbide on the second epitaxial layer. It has, The first impurity concentration of the first epitaxial layer is lower than both the second impurity concentration of the second epitaxial layer and the fourth impurity concentration on the upper surface of the first semiconductor substrate. The first impurity concentration is 1 × 10⁻⁶ １６ cm －３ Larger, 1 x 10 １７ cm －３ The following: The second impurity concentration N2 [cm] －３ ], the film thickness W2 [μm] of the second epitaxial layer, and the maximum current density J [A / cm²] when the element formed on the silicon carbide substrate is in use. ２ ] and the following equation (3) W2≧(2.52×10) １２ -n(J)-1.31×10 １３ )N2 －０．６５ ・・・(3) A method for manufacturing a silicon carbide substrate that satisfies the conditions shown.

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