Imaging device and method for driving the imaging device

Abstract

The present invention provides an imaging device that can further improve the frame rate while canceling the effects of reset noise. [Solution] The imaging device comprises multiple pixels, an AD conversion circuit that converts analog signals read from each of the multiple pixels into digital signals, a frame memory, and an image processing circuit. The analog signals include a reset signal representing the reset level and a pixel signal representing the image of the subject. The length of the first horizontal scanning period, which includes the period during which the AD conversion circuit converts the reset signal, is different from the length of the second horizontal scanning period, which includes the period during which the AD conversion circuit converts the pixel signals. The frame memory temporarily holds the first digital signal corresponding to the reset signal from the output of the AD conversion circuit. The image processing circuit outputs the difference between the second digital signal corresponding to the pixel signal for the pixel from which the reset signal was read from the output of the AD conversion circuit and the first digital signal held in the frame memory.

Description

[Technical Field]

[0001] This disclosure relates to an imaging device. This disclosure also relates to a method for driving an imaging device. [Background technology]

[0002] Patent Document 1, described below, discloses an image sensor having an organic photoelectric conversion layer supported on a semiconductor substrate via an insulating layer. As in the technology described in Patent Document 1, a configuration in which a photoelectric conversion unit having multiple pixel electrodes is placed on top of a semiconductor substrate instead of an embedded photodiode is sometimes called a "stacked type." In such a configuration, the semiconductor substrate supporting the photoelectric conversion unit has multiple readout circuits corresponding to multiple pixels, each having a pixel electrode. As shown in Figure 1 of Patent Document 1, the pixel electrode of each pixel is connected to one of the multiple readout circuits via a via placed in the insulating layer.

[0003] In the field of imaging devices, there is a demand for noise reduction. In particular, there is a demand to reduce kTC noise that occurs when the charge generated by photoelectric conversion is reset. This kTC noise is also called "reset noise."

[0004] Patent Document 2, described below, discloses an imaging device in which a transistor is interposed as a transfer means between a photoelectric conversion means for generating signal charges and a memory means for storing signal charges. The imaging device of Patent Document 2 further includes noise suppression means including a frame memory and an adder. In the technology described in Patent Document 2, the effect of shot noise caused by dark current generated in the memory means in each pixel is canceled by digital processing to subtract a reset level held in the frame memory from the signal level.

[0005] The following Patent Document 3 discloses an imaging device related to the reading of signals from pixels, which has two systems: a first system including a first output signal line and a second system including a second output signal line. By having two systems, the imaging device of Patent Document 3 can execute the reading of a reset signal from a certain pixel and the reading of pixel signals from other pixels in parallel with respect to a certain pixel column. Therefore, since the interval between the period of reading the reset signal in units of rows and the period of reading the pixel signal in units of rows can be reduced, it is possible to improve the frame rate while canceling the influence of reset noise.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0007] There is a need for an imaging device that can further improve the frame rate while canceling the influence of reset noise.

Means for Solving the Problems

[0008] According to certain exemplary embodiments of the present disclosure, for example, the following is provided. An imaging device comprising: a plurality of pixels arranged in a plurality of rows and columns; an AD conversion circuit that converts analog signals read from each of the plurality of pixels into digital signals; a frame memory; and an image processing circuit, wherein the analog signals include a reset signal representing a reset level and a pixel signal representing an image of a subject; the length of a first horizontal scanning period including the period during which the AD conversion circuit converts the reset signal is different from the length of a second horizontal scanning period including the period during which the AD conversion circuit converts the pixel signal; the frame memory temporarily holds a first digital signal corresponding to the reset signal from the output of the AD conversion circuit; and the image processing circuit outputs the difference between a second digital signal corresponding to the pixel signal for the pixel from which the reset signal was read from the output of the AD conversion circuit and the first digital signal held in the frame memory.

[0009] A comprehensive or specific embodiment may be implemented by elements, devices, systems, integrated circuits, or computer programs. Alternatively, a comprehensive or specific embodiment may be implemented by any combination of elements, devices, apparatus, systems, integrated circuits, methods, and computer programs.

[0010] Additional effects and benefits of the disclosed embodiments will become apparent from the specification and drawings. Effects and / or benefits are provided individually by the various embodiments or features disclosed in the specification and drawings, and it is not necessary to obtain all of them to obtain one or more of these. [Effects of the Invention]

[0011] According to one embodiment of the present disclosure, an imaging device is provided that can further improve the frame rate while canceling the effects of reset noise. [Brief explanation of the drawing]

[0012] [Figure 1] This figure schematically shows an exemplary configuration of an imaging device according to the first embodiment of the present disclosure. [Figure 2]This figure schematically shows an exemplary circuit configuration of an imaging device according to the first embodiment of the present disclosure. [Figure 3] This is a schematic cross-sectional view showing an exemplary device structure of the first pixel Px1. [Figure 4] This diagram illustrates an example of a method for driving an imaging device using a comparative example. [Figure 5] This is a flowchart illustrating a comparative example and an example of a method for driving an imaging device according to the first embodiment of this disclosure. [Figure 6] This figure schematically shows the operation of the pixel readout circuit 20 for the first row R1 and the pixel readout circuit for the sixth row R6 during a 1H period from time t8 to time t9, as shown in Figure 4. [Figure 7] This is a schematic diagram illustrating an example of a method for driving an imaging device according to the first embodiment of the present disclosure. [Figure 8] This is a schematic diagram illustrating an example of a method for driving an imaging device according to the first embodiment of the present disclosure. [Figure 9] This is a schematic diagram illustrating a method for driving an imaging device according to a modified example of the first embodiment of the present disclosure. [Figure 10] This is a block diagram showing an example of signal processing of an imaging device according to a first embodiment of the present disclosure. [Figure 11] This is a schematic diagram illustrating an example of a driving method for an imaging device according to the first embodiment of this disclosure, and schematically shows the state of the digital memory storing the data after AD conversion, the state of the interface, the output format of the interface, and the output state of the serial pixel data. [Figure 12A] This figure schematically shows the configuration of an imaging device according to a modified example of the first embodiment of the present disclosure. [Figure 12B] This is a schematic diagram illustrating an example of a method for driving an imaging device according to a modification of the first embodiment of the present disclosure. [Figure 13] This diagram schematically illustrates the operation of a parallel-to-serial conversion circuit in which 16-bit parallel pixel data is converted to serial pixel data. [Figure 14] This diagram schematically illustrates the operation of a parallel-to-serial conversion circuit in which 12-bit parallel pixel data is converted to serial pixel data. [Figure 15] This diagram schematically illustrates an example of operation when the analog gains for reading out the pixel signal and reading out the reset signal are different. [Figure 16] This diagram schematically illustrates an example of operation when the analog gains for reading out the pixel signal and reading out the reset signal are different. [Figure 17] This is a schematic diagram illustrating an example of a method for driving an imaging device according to a second embodiment of the present disclosure. [Figure 18] This is a schematic diagram illustrating another example of a method for driving an imaging device according to a second embodiment of the present disclosure. [Figure 19] This is a schematic diagram illustrating another example of a method for driving an imaging device according to a second embodiment of the present disclosure. [Figure 20A] This figure schematically shows the configuration of an imaging device according to a third embodiment of the present disclosure. [Figure 20B] This is a schematic diagram illustrating an example of a method for driving an imaging device according to a third embodiment of the present disclosure. [Figure 20C] This is a schematic diagram illustrating an example of a method for driving an imaging device according to a third embodiment of the present disclosure. [Modes for carrying out the invention]

[0013] (Knowledge that forms the basis of this disclosure) In the imaging device described in Patent Document 2, although the readout of the reset signal representing the reset level is performed in parallel with the exposure to the photoelectric conversion means, the transfer of the signal charge to the memory means via the transfer means must be performed after the readout of the reset signal for all rows is completed. Therefore, the readout of the pixel signal representing the image of the subject is performed after the readout of the reset signal for all rows is completed. In other words, it is not possible to reduce the interval between the readout of the reset signal and the readout of the pixel signal for each row of multiple pixels, making it difficult to improve the frame rate. The inventors focused on the fact that by time-dividing the readout of the reset signal and the readout of the pixel signal on a line, the length of the period for AD conversion of the reset signal and the pixel signal can be arbitrarily set, and arrived at the configuration of the present disclosure which can further improve the frame rate while canceling the effect of reset noise.

[0014] An overview of one aspect of this disclosure is as follows:

[0015] [Item 1] Multiple pixels arranged in multiple rows and columns, An AD conversion circuit that converts analog signals read from each of the aforementioned multiple pixels into digital signals, Frame memory and Image processing circuit and Equipped with, The analog signal includes a reset signal that represents the reset level and a pixel signal that represents the image of the subject. The length of the first horizontal scanning period, which includes the period during which the AD conversion circuit converts the reset signal, is different from the length of the second horizontal scanning period, which includes the period during which the AD conversion circuit converts the pixel signal. The frame memory temporarily holds the first digital signal corresponding to the reset signal from the output of the AD conversion circuit. The image processing circuit outputs the difference between a second digital signal corresponding to the pixel signal for the pixel from which the reset signal was read out of the output of the AD conversion circuit, and the first digital signal held in the frame memory. Imaging device.

[0016] According to the configuration of item 1, an AD conversion circuit is provided in the imaging device, and the first digital signal corresponding to the reset signal is stored in the frame memory from the output of this circuit, and the difference between it and the second digital signal corresponding to the pixel signal is calculated, thereby effectively canceling the effects of reset noise. Furthermore, since the length of the first horizontal scanning period, which includes the period for converting the reset signal, and the length of the second horizontal scanning period, which includes the period for converting the pixel signal, are different from each other, it is possible to further increase the frame rate.

[0017] [Item 2] The length of the first horizontal scanning period is shorter than the length of the second horizontal scanning period. The imaging device described in item 1.

[0018] [Item 3] The length of the first horizontal scanning period is longer than the length of the second horizontal scanning period. The imaging device described in item 1.

[0019] [Item 4] A digital memory that temporarily holds the first digital signal and the second digital signal, A line buffer that temporarily holds the signal output by the aforementioned digital memory and An imaging device further comprising any one of items 1 to 3.

[0020] [Item 5] Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to item 4, wherein the line buffer outputs the first digital signal or the second digital signal generated by the AD conversion circuit in the horizontal scan period two horizontal scan periods prior to each horizontal scan period to the frame memory.

[0021] [Item 6] The system further comprises a digital memory for temporarily holding the first digital signal and the second digital signal, Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to any one of items 1 to 3, wherein the digital memory outputs the first digital signal or the second digital signal generated by the AD conversion circuit in the immediately preceding horizontal scanning period to the frame memory during each horizontal scanning period.

[0022] [Item 7] The imaging apparatus according to any one of items 1 to 6, wherein the AD conversion circuit alternately performs the conversion of the reset signal read from the pixels included in one or more rows and the conversion of the pixel signal read from the pixels included in one or more rows.

[0023] [Item 8] The imaging apparatus according to item 7, wherein the AD conversion circuit alternately performs, for each horizontal scanning period, the conversion of the reset signal read from the pixels included in one or more rows and the conversion of the pixel signals read from the pixels included in one or more other rows.

[0024] [Item 9] The imaging apparatus according to item 7, wherein the AD conversion circuit alternately performs, for each horizontal scanning period, the conversion of the reset signal read from the pixel in one row and the conversion of the pixel signal read from the pixel in another row.

[0025] [Item 10] Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to item 9, wherein the AD conversion circuit converts the reset signal or the pixel signal read out during each horizontal scanning period.

[0026] [Item 11] The imaging apparatus according to item 7, wherein the AD conversion circuit performs, during one horizontal scanning period, the conversion of the pixel signal read from the pixels included in two or more rows, or the conversion of the reset signal read from the pixels included in two or more rows.

[0027] [Item 12] The system further comprises a sample-and-hold circuit that temporarily holds the reset signal or the pixel signal read from the plurality of pixels, The imaging apparatus according to any one of items 1 to 11, wherein the AD conversion circuit converts the reset signal or the pixel signal read out in the immediately preceding horizontal scanning period during each horizontal scanning period.

[0028] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in a separate claim indicating a higher-level concept will be described as optional components. In the following description, components having substantially the same function will be indicated by a common reference numeral and their description may be omitted. Also, to avoid making the drawings excessively complex, some elements may be omitted from the illustration.

[0029] (First Embodiment) Figure 1 schematically shows an exemplary configuration of an imaging device according to a first embodiment of the present disclosure. The imaging device 100A shown in Figure 1 includes a plurality of pixels Px, each having a photoelectric conversion unit supported on a semiconductor substrate 110 as part of its structure. That is, below, the imaging device 100A is exemplified as an imaging device having a so-called stacked configuration. As will be explained in detail later with reference to the figures, the semiconductor substrate 110 has a plurality of readout circuits formed corresponding to each pixel Px.

[0030] The plurality of pixels Px form an imaging region by being two-dimensionally arranged on the semiconductor substrate 110. In an embodiment of the present disclosure, the plurality of pixels Px are arranged in a plurality of rows and columns. In FIG. 1, the plurality of pixels Px are arranged in m rows and n columns. Here, m and n independently represent integers of 2 or more.

[0031] The imaging device 100A has a plurality of row signal lines Ri and a plurality of output signal lines. The plurality of row signal lines R i are m row signal lines R1, R2, R3,..., R arranged corresponding to the plurality of rows of pixels Px m-1 , R m and include. Each of the plurality of row signal lines R i is electrically connected to one or more pixels Px belonging to the same row. The pixel rows connected to the row signal lines R1, R2, R3,..., R m-1 , R m are sometimes referred to as the pixel rows of the first row, the second row, the third row,..., the (m - 1)th row, and the mth row, respectively. These row signal lines R i are connected to the row scanning circuit 130. Note that two or more signal lines may be provided for each row of the plurality of pixels Px.

[0032] In the example shown in FIG. 1, the plurality of output signal lines include the plurality of output signal lines Sj. The plurality of output signal lines S j are n output signal lines S1, S2, S3,..., S arranged corresponding to the plurality of columns of pixels Px n-1 , S n and include. The pixel columns connected to the output signal lines S1, S2, S3,..., S n-1 , S n are sometimes referred to as the pixel columns of the first column, the second column, the third column,..., the (n - \alpha)th column, and the nth column, respectively.

[0033] Each of the plurality of output signal lines S j is electrically connected to the readout circuit of one or more pixels Px belonging to the same column. As shown in the figure, the plurality of output signal lines S j It should be noted that there seems to be an error in the original Japanese text where it says "第(n - \alpha)th column" in item . I translated it as "第(n - \alpha)列" as per the original text. If this is a mistake in the original, you may want to correct it before using this translation for practical purposes.An analog-to-digital conversion circuit 141 and a digital output interface 161 are connected to it. From the digital output interface 161, the output signal line S j The signal read from the pixel Px via the A / D converter and converted from analog to digital by the analog-to-digital conversion circuit 141 is output. For simplicity, below we will refer to the analog-to-digital conversion circuit simply as the "AD conversion circuit," the analog-to-digital conversion simply as "AD conversion," and the digital output interface simply as the "interface."

[0034] In the configuration illustrated in Figure 1, the imaging device 100A has an output signal line S j It further includes a digital memory 151 connected between the AD conversion circuit 141 and the interface 161.

[0035] The digital memory 151 temporarily holds one row of digital signals read from multiple pixels Px and converted by the AD conversion circuit 141. By interposing the digital memory between the AD conversion circuit and the interface, as in this example, it becomes possible to hold the result of one row's AD conversion in the digital memory while the AD conversion circuit performs AD conversion for the next row. In other words, row-by-row AD conversion can be processed at a higher speed.

[0036] An image processing circuit 170A is connected to interface 161. The image processing circuit 170A performs processing such as gamma correction, color interpolation, spatial interpolation, and auto white balance on the digital signal output from interface 161 as needed. The image processing circuit 170A can be implemented using, for example, a DSP (Digital Signal Processor), an ISP (Image Signal Processor), or an FPGA (field-programmable gate array).

[0037] In this example, the control circuit 220 is electrically connected to the image processing circuit 170A. The image processing circuit 170A provides control signals to the control circuit 220, such as vertical synchronization signals and horizontal synchronization signals. The row scanning circuit 130 and the AD conversion circuit 141 are connected to the control circuit 220. The control circuit 220 is implemented by a microcontroller, for example, including one or more processors, and typically has a timing generator. The control circuit 220 supplies drive signals to the row scanning circuit 130 and the AD conversion circuit 141, and controls the entire imaging device 100A. In Figure 1, the arrows extending toward and from the control circuit 220 schematically represent the input signals to and from the control circuit 220, respectively. The control circuit 220 may include one or more memories.

[0038] The imaging device 100A may include a display device 180, such as a liquid crystal display or an organic EL display, connected to the image processing circuit 170A. The display device 180 presents the user of the imaging device 100A with an image based on the digital signal obtained by imaging.

[0039] In the configuration illustrated in Figure 1, the image processing circuit 170A has a frame memory 171. The frame memory 171 temporarily holds digital data corresponding to one frame of image output from the interface 161. In the embodiment of this disclosure, the frame memory 171 temporarily holds a first digital signal corresponding to a reset signal representing the reset level. The first digital signal is a digital signal output from the AD conversion circuit 141, with the reset signal, which is an analog signal read from each pixel Px, as input. As will be described later, the image processing circuit 170A outputs the difference between the first digital signal held in the frame memory 171 and a second digital signal corresponding to a pixel signal representing the image of the subject. The difference between the digital signals can substantially cancel the effects of random noise caused by the reset operation performed immediately before the exposure period.

[0040] (Example circuit configuration of pixel Px) Figure 2 shows an exemplary circuit configuration of the imaging device 100A. For simplicity, Figure 2 schematically shows four pixels Px selected from the multiple pixels Px included in the imaging region shown in Figure 1. These four pixels Px include the first pixel Px1, second pixel Px2, third pixel Px3, and fourth pixel Px4, arranged in a 2x2 grid. Of these, the first pixel Px1 and the second pixel Px2 are located in the same row, while the third pixel Px3 and the fourth pixel Px4 are located in the same row but different from the first pixel Px1 and the second pixel Px2. The first pixel Px1 and the second pixel Px2 are located in even rows of the pixel array, for example, while the third pixel Px3 and the fourth pixel Px4 are located in odd rows of the pixel array. The basic circuit configuration of the pixels is common among these pixels Px1 to Px4, and therefore, below we will focus on the first pixel Px1 and describe the exemplary configuration of each pixel.

[0041] The first pixel Px1 includes a photoelectric conversion unit 10 and a readout circuit 20 electrically connected to the photoelectric conversion unit 10. As will be described later, the photoelectric conversion unit 10 has a pixel electrode, a counter electrode, and a photoelectric conversion layer sandwiched between these electrodes. The photoelectric conversion unit 10 of each pixel has an electrical connection to a voltage line 192 connected to a voltage supply circuit 190, and is configured to apply a predetermined voltage between the pixel electrode and the counter electrode when the imaging device 100A is in operation. The voltage supply circuit 190 is not limited to a specific power supply circuit, as long as it is configured to apply a predetermined voltage to the photoelectric conversion unit 10 of each pixel when the imaging device 100A is in operation. The voltage supply circuit 190 may be a circuit that generates a predetermined voltage, or a circuit that converts a voltage supplied from another power source to a predetermined voltage. The voltage supply circuit 190 may be part of the row scanning circuit 130.

[0042] In the configuration illustrated in Figure 2, the readout circuit 20 includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. The signal detection transistor 22, the address transistor 24, and the reset transistor 26 are typically field-effect transistors formed on a semiconductor substrate 110, and below, an example in which N-channel MOSFETs are used for these transistors will be described.

[0043] The gate of the signal detection transistor 22 is connected to the pixel electrode of the photoelectric conversion unit 10. The source of the signal detection transistor 22 is connected to the corresponding output signal line via the address transistor 24. Here, for each of the multiple rows of multiple pixels Px, the output signal line S j As shown in Figure 2, the output signal line Sj is connected to the AD conversion circuit 141.

[0044] The analog signal read from each pixel Px includes a reset signal representing the reset level and a pixel signal representing the image of the subject. As will be described later, the reset signal and pixel signal read from each pixel Px are signals superimposed with kTC noise that occurs when the pixel is reset.

[0045] As schematically shown in Figure 2, the AD conversion circuit 141 may have multiple elements, such as a column signal processing circuit 145, provided for each output signal line. Each of these multiple elements is connected to a corresponding one of the multiple output signal lines. On the other hand, the drain of the signal detection transistor 22 of each pixel is connected to the power supply line 194. The power supply line 194 functions as a source follower power supply when a power supply voltage VDD of approximately 3.3V is applied when the imaging device 100A is in operation.

[0046] The gate of address transistor 24 has a row signal line R i The row scanning circuit 130 is connected to the row signal line R i The on and off states of the address transistor 24 are switched by controlling the voltage level applied to it. This allows the row scanning circuit 130 to read signals from pixels belonging to the selected row to the corresponding output signal lines.

[0047] In this example, the readout circuit 20 includes a reset transistor 26. One of the drains and sources of the reset transistor 26 is connected to node FD, which electrically connects the photoelectric conversion unit 10 to the gate of the signal detection transistor 22. The other drain and source of the reset transistor 26 is connected to a reset voltage line 196. The reset voltage line 196 is connected to a reset voltage supply circuit 198. When the imaging device 100A is in operation, a predetermined reset voltage V RST The reset voltage V is applied from the reset voltage supply circuit 198 to the reset voltage line 196. RST For example, a voltage of 0V or near 0V is used. The reset voltage supply circuit 198 only needs to be configured to apply a predetermined reset voltage to each pixel when the imaging device 100A is operating, and like the voltage supply circuit 190, it is not limited to a specific power supply circuit. The reset voltage supply circuit 198 may be a circuit independent of the voltage supply circuit 190, and one of the reset voltage supply circuit 198 and the voltage supply circuit 190 may be part of the other.

[0048] Multiple reset signal lines Q correspond to multiple pixels Px. i A reset signal line is provided. As shown in the figure, typically, one reset signal line is connected in common to the gates of the reset transistors 26 of multiple pixels Px belonging to the same row. In this example, the reset signal line Q i It has a connection to the row scanning circuit 130. Therefore, the row scanning circuit 130 has a reset signal line Q i By controlling the voltage level applied, the reset transistor 26 is turned on in row units of multiple pixels Px, and the potential of node FD of the pixel Px for which the reset transistor 26 is turned on is set to V RST It can be reset.

[0049] (Device structure of pixel Px) Figure 3 schematically shows the device structure of the first pixel Px1. The first pixel Px1 generally includes a semiconductor substrate 110 on which a readout circuit 20 is formed, and a photoelectric conversion unit 10 supported by the semiconductor substrate 110. As shown in Figure 3, typically an insulating layer 50 covering the readout circuit 20 is placed between the semiconductor substrate 110 and the photoelectric conversion unit 10.

[0050] The photoelectric conversion unit 10 includes a pixel electrode 11 supported by an insulating layer 50, a translucent counter electrode 13, and a photoelectric conversion layer 12 located between the pixel electrode 11 and the counter electrode 13. The pixel electrode 11 is located closer to the semiconductor substrate 110 than the photoelectric conversion layer 12 and can be formed from a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to impurity to provide conductivity. As shown in Figure 3, the pixel electrode 11 is electrically isolated from the pixel electrodes 11 of other adjacent pixels by being spatially separated from them.

[0051] The counter electrode 13 is located on the side from which light from the subject arrives. The counter electrode 13 is a translucent electrode formed from a conductive material such as ITO. In this specification, the term "translucent" means that at least a portion of the wavelengths of light that the photoelectric conversion layer 12 can absorb are transmitted, and it is not necessary for light to be transmitted across the entire visible light wavelength range. Optical filters such as color filters, microlenses, etc., may be placed on the main surface of the counter electrode 13 opposite to the photoelectric conversion layer 12.

[0052] The counter electrode 13 is typically provided in the form of a single continuous electrode layer spanning multiple pixels. The aforementioned voltage line 192 is connected to the counter electrode 13 of the photoelectric conversion unit 10. In Figure 2, the voltage line 192 is shown as being connected to each of the multiple pixel photoelectric conversion units 10, but typically, the counter electrode 13 of each pixel is part of a single continuous translucent electrode between the multiple pixels. Therefore, the counter electrode 13 of each pixel is essentially at the same potential, and it is not necessary for the voltage line 192 to be a wiring that branches into multiple lines.

[0053] The photoelectric conversion layer 12 is formed from an organic material or an inorganic material such as amorphous silicon, and generates charge pairs upon incident light that has passed through the counter electrode 13. Similar to the counter electrode 13, the photoelectric conversion layer 12 is typically provided in the form of a single continuous photoelectric conversion structure spanning multiple pixels. That is, the photoelectric conversion layer 12 in each pixel may be part of a photoelectric conversion layer formed continuously across multiple pixels.

[0054] By selecting one or more suitable materials as photoelectric conversion materials and forming the photoelectric conversion layer 12, it is possible to obtain a photoelectric conversion layer 12 that is sensitive to both the visible and infrared regions, for example. Examples of such materials are described in detail, for example, in International Publication No. 2018 / 025544. For reference, the entirety of the disclosure in International Publication No. 2018 / 025544 is incorporated herein by reference. The photoelectric conversion layer 12 may consist of quantum dots and / or nanotubes. Alternatively, the photoelectric conversion layer 12 may contain quantum dots and / or nanotubes as photoelectric conversion materials. The photoelectric conversion layer 12 may include a layer composed of an organic material and a layer composed of an inorganic material.

[0055] The insulating layer 50 located between the semiconductor substrate 110 and the photoelectric conversion unit 10 includes, for example, a plurality of insulating layers, each formed from silicon dioxide. As schematically shown in Figure 3, a multilayer wiring is provided inside the insulating layer 50, which includes at least a conductive structure 52, one end of which is connected to the pixel electrode 11 of the photoelectric conversion unit 10. The conductive structure 52 may include vias and wiring formed from a metal such as copper, and plugs formed from polysilicon. In the illustrated example, the other end of the conductive structure 52 is electrically connected to an impurity region 111 formed in the semiconductor substrate 110.

[0056] The semiconductor substrate 110 has impurity regions 112, 113, 114, and 115 in addition to the impurity region 111. The semiconductor substrate 110 also has element isolation regions 116 that electrically isolate the readout circuits 20 provided for each pixel Px between pixels Px. In the following, a P-type silicon substrate is used as an example of the semiconductor substrate 110. The semiconductor substrate 110 may also be an insulating substrate with a semiconductor layer provided on its surface.

[0057] Each of the impurity regions 111, 112, 113, 114, and 115 is typically an N-type diffusion region. Of these impurity regions, impurity region 111, to which the conductive structure 52 is connected, functions as one of the source and drain regions of the reset transistor 26. The reset transistor 26 further includes impurity region 112, which functions as the other of the source and drain regions, a gate insulating layer 26g on the semiconductor substrate 110, and a gate electrode 26e on the gate insulating layer 26g. Although not shown in Figure 3, the reset voltage line 196 described above is connected to impurity region 112.

[0058] The signal detection transistor 22 includes an impurity region 113 and an impurity region 114, a gate insulating layer 22g on the semiconductor substrate 110, and a gate electrode 22e on the gate insulating layer 22g. The impurity region 113 functions as the drain region of the signal detection transistor 22, and the impurity region 114 functions as the source region of the signal detection transistor 22. The power supply line 194 described above is connected to the impurity region 113. As schematically shown in Figure 3, an element isolation region 116 is also provided between the signal detection transistor 22 and the reset transistor 26.

[0059] The address transistor 24 includes an impurity region 114 and an impurity region 115, a gate insulating layer 24g on the semiconductor substrate 110, and a gate electrode 24e on the gate insulating layer 24g. The impurity region 114 and the impurity region 115 function as the drain region and source region of the address transistor 24, respectively. In the configuration illustrated in Figure 3, the address transistor 24 shares the impurity region 114 with the signal detection transistor 22. One of the multiple output signal lines Sj and Tj described above is connected to the impurity region 115.

[0060] The insulating layer 50 covers the signal detection transistor 22, address transistor 24, and reset transistor 26. As schematically shown in Figure 3, the conductive structure 52 in the insulating layer 50 also has an electrical connection with the gate electrode 22e of the signal detection transistor 22. That is, the conductive structure 52 in each pixel has the function of electrically connecting the pixel electrode 11 of the photoelectric conversion unit 10 and the readout circuit 20, which includes the signal detection transistor 22 formed on the semiconductor substrate 110.

[0061] Furthermore, the conductive structure 52 also functions as part of a charge storage region that temporarily stores the charge collected by the pixel electrode 11, i.e., the signal charge. As explained with reference to Figure 2, the voltage supply circuit 190 applies a predetermined voltage to the photoelectric conversion unit 10 of each pixel via the voltage line 192. For example, by applying a voltage to the counter electrode 13 of the photoelectric conversion unit 10, a predetermined potential difference ΔV can be applied between the counter electrode 13 and the pixel electrode 11 during the exposure period. For example, by applying a voltage to the counter electrode 13 such that the potential of the counter electrode 13 is higher than that of the pixel electrode 11, with the pixel electrode 11 as the reference, positive polarity charges, such as holes, among the positive and negative charges generated in the photoelectric conversion layer 12 by the incidence of light can be collected by the pixel electrode 11 as signal charges. The signal charges are temporarily stored in a charge storage region that includes the conductive structure 52 as part of it. Similar to the conductive structure 52, the impurity region 111 formed on the semiconductor substrate 110, the pixel electrode 11 of the photoelectric conversion unit 10, and the gate electrode 22e of the signal detection transistor 22 also function as part of the charge storage region that temporarily stores signal charge.

[0062] (Comparative example of driving method) Before describing the driving method of the imaging apparatus according to the first embodiment of this disclosure, a driving method of a comparative example will be described. Unless otherwise specified, the structure of the imaging apparatus using the driving method of the comparative example may be the same as that of the imaging apparatus according to the first embodiment of this disclosure described above.

[0063] Figures 4 and 5 illustrate an example of a driving method for an imaging device of a comparative example. In Figure 4, the top chart shows the pulses of the vertical sync signal VD. The rising edge of the vertical sync signal VD pulses represents the start of the period for reading out the pixel signal. In Figure 4, the second chart from the top shows the pulses of the horizontal sync signal HD. The period from the rising edge of one pulse to the rising edge of the next pulse corresponds to one horizontal scanning period, or 1H. In Figure 4, times t0 to t29 are shown in 2H increments. That is, for example, the time between time t0 and time t1 is 2H. The time between time t0 and time t1 is bisected at time u0. That is, in the example in Figure 4, the time between time t0 and time u0, and the time between time u0 and time t1 are both 1H.

[0064] Figure 4 also shows multiple blocks illustrating the operation of multiple pixels Px included in the imaging region, all in one figure. For simplicity, here we assume that there are six rows of multiple pixels Px, from row 1 R1 to row 6 R6, and the operation of the pixels Px is schematically represented by multiple rectangular blocks. Row 1 R1 of the multiple pixels Px includes, for example, the first pixel Px1 and the second pixel Px2 mentioned above, and row 2 R2 includes, for example, the third pixel Px3 and the fourth pixel Px4 mentioned above. In Figure 4, for example, white rectangular blocks schematically represent the exposure period within the frame period, rectangular blocks with hatching with horizontal lines represent the readout period of the reset level corresponding to the signal level in darkness, and rectangular blocks with hatching with diagonal lines represent the readout period of the pixel signal representing the image of the subject. As will be explained below, the readout period of the reset signal representing the reset level shown in Figure 4 includes the period for resetting the potential of the charge storage region of the pixel.

[0065] The driving method of the imaging device illustrated in Figure 5 generally includes the steps of: resetting the potential of the charge storage region of the pixel (step St1); reading a reset signal corresponding to the potential of the charge storage region after the pixel reset (step St2); generating a first digital signal corresponding to the reset signal by analog-to-digital conversion (step St3); storing the first digital signal in frame memory (step St4); accumulating the signal charge generated by the photoelectric conversion unit in the charge storage region after the pixel reset (step St5); reading a pixel signal corresponding to the amount of charge accumulated in the step of accumulating the signal charge in the charge storage region (step St6); generating a second digital signal corresponding to the pixel signal by analog-to-digital conversion (step St7); and obtaining the difference between the second digital signal and the first digital signal (step St8). The details of the exemplary driving method of the imaging device of the comparative example will be described below with reference to Figure 4.

[0066] <Step to reset the potential of the charge storage region> Figure 4 shows an example of operation based on a so-called rolling shutter, where exposure and signal readout are performed for each row of pixels. Here, we first focus on the first row R1 of the first row R1 to the sixth row R6. In image acquisition, the charge storage area of ​​each pixel Px is reset first. In the example shown in Figure 4, where k is a non-negative integer, the reset of multiple pixels belonging to the first row R1 is started at time u3 for the k-th frame period. The "frame period" refers to the period from the reset of the first row of multiple pixels Px until the readout of the pixel signal of the last row is completed. In the illustrated example, the first row R1 is the first row and the sixth row R6 is the last row. Note that the length of each frame period can differ from one another because the reset timing may differ depending on the length of the exposure period.

[0067] Specifically, by turning on the reset transistor 26 of the pixel belonging to the row to be reset, the potential of node FD is aligned with the potential of the reset voltage line 196. That is, the voltage of the pixel electrode 11 of the photoelectric conversion unit 10 is set to the reset voltage VRST As can be seen from Figures 2 and 3, the signal detection transistor 22 of the readout circuit 20 outputs a signal corresponding to the potential of the pixel electrode 11 by electrically connecting its gate electrode 22e to the pixel electrode 11 via the conductive structure 52. In other words, the readout circuit 20 outputs an analog signal corresponding to the potential of the pixel electrode 11 by a source follower including the signal detection transistor 22.

[0068] <Process for reading the reset signal> After turning off the reset transistor 26, the reset voltage V is applied to the gate electrode 22e of the signal detection transistor 22 by turning on the address transistor 24 of the pixel belonging to the same row. RST A corresponding signal is output to the corresponding output signal line. The signal output to the output signal line at this time is an analog signal representing the reset level and usually contains reset noise that occurs when the reset transistor 26 is turned off. For example, in the circuit configuration example described with reference to Figure 2, the reset signal read from the pixel belonging to the first row R1 is output to the output signal line S j It is input to the AD conversion circuit 141 via one of the corresponding devices.

[0069] <Process for generating the first digital signal corresponding to the reset signal> The reset signal input to the AD conversion circuit 141 is converted into a first digital signal by the AD conversion circuit 141. After reading the reset signal, the address transistor 24 is turned off. Turning off the address transistor 24 of the pixels belonging to the first row R1 completes the reading of the reset signal from the pixels belonging to the first row R1.

[0070] <Process of storing the first digital signal in frame memory> As schematically shown in Figure 4, the pixel reset and reset signal reading described above are performed sequentially row by row in synchronization with the horizontal synchronization signal HD. For each row, the pixel reset and reset signal reading are performed within the interval of the pulses of the horizontal synchronization signal HD, i.e., 1H period (1 horizontal scan period). In this example, the reset of the pixel belonging to the first row R1 and the reading of the reset signal from the pixel are performed from time u3 to time t4, and the reading of the pixel signal of the pixel belonging to the fifth row R5 is performed from time t4 to time u4. Subsequently, the reset of the pixel belonging to the second row R2 and the reading of the reset signal from the pixel are performed from time u4 to time t5, and the reading of the pixel signal of the pixel belonging to the sixth row R6 is performed from time t5 to time u5. Pixel reset and reset signal reading and pixel signal reading are performed alternately every 1H period. 1 horizontal scan period represents the period from when one row is selected to when another row is selected. When a row is selected, it can be defined as the moment when the address transistor 24 of the pixels included in that row switches from off to on. Note that the timing of the address transistor 24 switching from off to on may not strictly coincide with the pulses of the horizontal synchronization signal HD, but for the sake of clarity, the pulse interval of the horizontal synchronization signal HD is shown as a 1H period.

[0071] In the example circuit configuration described with reference to Figure 2, the reset signal read from the pixel belonging to the second row R2 is output to the output signal line S jThe reset signal is input to the AD conversion circuit 141 via one of the corresponding inputs. The reset signal input to the AD conversion circuit 141 is converted into a first digital signal by AD conversion. The first digital signal output from the AD conversion circuit 141 is input to the image processing circuit 170A via the digital memory 151 and interface 161. In Figure 4, the first digital signals corresponding to the reset signals read between time u3 and time t9 are temporarily held in the frame memory 171 within the image processing circuit 170A. In Figure 4, the first digital signals corresponding to the reset signals read between time u3 and time t9 can also be temporarily held in the digital memory 151, one line at a time.

[0072] <Process for accumulating signal charge generated by photoelectric conversion> Let us again focus on the pixels belonging to the first row R1. After the reset signal is read, the reset transistor 26 is turned off and the exposure period begins. In this example, focusing on the first row R1, the period from time t4 to time t8 (i.e., the 8H period) is defined as the exposure period in the k-th frame period. The exposure period is the period for accumulating signal charges in the charge storage region, which are generated by the photoelectric conversion unit 10 according to the amount of exposure to the pixels. The length of the exposure period for each row of multiple pixels Px is, for example, in the range of 1 / 60 second to 1 / 16000 second.

[0073] At this time, the counter electrode 13 of the photoelectric conversion unit 10 of each pixel Px receives a predetermined voltage V1 from the voltage supply circuit 190 via the voltage line 192, thereby being brought to a high potential relative to the pixel electrode 11. The potential of the pixel electrode 11 immediately after reset is the reset voltage V RST Determined by this, immediately after the reset, there is (V1-V) between the pixel electrode 11 and the counter electrode 13. RST The bias voltage of ) is applied.

[0074] By making the potential of the counter electrode 13 relatively higher than that of the pixel electrode 11, the positive charge of the charge pair generated by photoelectric conversion is collected by the pixel electrode 11. The PN junction formed in the semiconductor substrate 110 by the formation of the impurity region 111 functions as a junction capacitance that temporarily stores the positive charge collected by the pixel electrode 11. When holes are used as signal charges, the potential of the impurity region 111 as a charge storage area increases as signal charges accumulate in the impurity region 111. In a typical embodiment of this disclosure, (V1-V RST Although )>0, it is of course possible to use electrons as signal charges, for example, by applying a voltage to the counter electrode 13 such that the potential of the counter electrode 13 becomes lower than that of the pixel electrode 11.

[0075] <Process for reading out pixel signals corresponding to the amount of accumulated charge> After a predetermined time has elapsed, the pixel signal is read out. In this example, based on the vertical synchronization signal VD, the reading of signals from pixels belonging to the first row R1 is started at time t8. As described above, the readout circuit 20 for each pixel belonging to the first row R1 outputs an analog signal corresponding to the potential of the pixel electrode 11 to one of the multiple output signal lines. The signal read out from the pixels of the first row R1 at this time is an analog signal corresponding to the amount of charge accumulated in the charge storage region during the exposure period for the first row R1, and is a pixel signal that represents the image of the subject based on ambient light such as sunlight. This pixel signal contains reset noise generated by the reset operation performed before the exposure period. After the pixel signal is read out, the address transistor 24 is turned off again. For each row, the pixel signal is also read out within a 1H period.

[0076] <Process for generating a second digital signal corresponding to the pixel signal> As shown in Figure 4, exposure to each pixel and reading out the pixel signal from each pixel are performed sequentially in rows of multiple pixels. The k-th frame period ends when the reading of pixel signals from row 1 R1 to row 6 R6 is completed.

[0077] Similar to the readout of the reset signal, here, the pixel signals read from the pixels of row 1 R1 to row 6 R6 are output to the output signal line S j The signal is sent to the AD conversion circuit 141 via the interface 161. The AD conversion circuit 141 performs AD conversion on the received pixel signals row by row and generates a second digital signal corresponding to the pixel signal. The generated second digital signal is sent to the image processing circuit 170A via the interface 161.

[0078] <Process for obtaining the difference between the first digital signal and the second digital signal> The image processing circuit 170A calculates the difference between a second digital signal corresponding to the pixel signal and a first digital signal corresponding to the reset signal, and outputs this difference as pixel value data. As described above, the reset signal read from the pixel after the potential of the charge storage region is reset has reset noise superimposed on it. Furthermore, the readout of the reset signal is non-destructive, and the potential of the charge storage region is not reset again during the period until the pixel signal is readout. Therefore, the pixel signal corresponding to the amount of charge stored in the charge storage region during the exposure period also has reset noise superimposed on it. According to the embodiment of this disclosure, a first digital signal corresponding to the reset signal and a second digital signal corresponding to the pixel signal are obtained, and then the difference between these digital signals is obtained. Therefore, by subtracting the first digital signal corresponding to the reset signal, the reset noise is substantially subtracted from the second digital signal corresponding to the pixel signal, and as a result, the effect of the reset noise is effectively canceled.

[0079] In the example shown in Figure 4, if we focus on the period from time t8 to time t9 (i.e., a 2H period), the reading of the pixel signal from the first row R1 pixel is performed before the reading of the reset signal from the sixth row R6 pixel. The 1H period from time t8 to time u8 includes the period of reading the pixel signal from the first row R1 pixel, and the subsequent 1H period from time u8 to time t9 includes the period of resetting the sixth row R6 pixel and reading the reset signal. Figure 6 schematically shows the operation of the pixel reading circuit 20 for the first row R1 pixel and the operation of the pixel reading circuit 20 for the sixth row R6 pixel during the 2H period from time t8 to time t9 shown in Figure 4. In Figure 6, φ S The graph shows the waveform of the address control signal applied to the gate of the address transistor 24 of the read circuit 20, φ R The graph shows the waveform of the reset control signal applied to the gate of the reset transistor 26 of the readout circuit 20. The graph of V1 shows the waveform indicating the period during which the pixel signal read from the pixel of the first row R1 is being converted by the AD conversion circuit 141, in other words, the output waveform from the AD conversion circuit 141. Similarly, the graph of V6 shows the waveform indicating the period during which the reset signal read from the pixel of the sixth row R6 is being converted by the AD conversion circuit 141, in other words, the output waveform from the AD conversion circuit 141. The length of the period during which the pixel signal read from the pixel or the reset signal is being converted by the AD conversion circuit 141 is defined by the length of the period during which the output waveform V1 or V6 from the AD conversion circuit 141 is high. In the comparative example driving methods shown in Figures 4 and 6, the length of the horizontal scanning period (1H) included in each frame period is the same. Therefore, in each frame period, the length of the horizontal scanning period including the period during which the reset signal is being converted by the AD conversion circuit 141 and the length of the horizontal scanning period including the period during which the pixel signal is being converted by the AD conversion circuit 141 are equal to each other, that is, both are 1H.

[0080] In the example in Figure 6, the period for reading the pixel signal from the pixel in the first row R1 and the period for AD conversion of the pixel signal read from the pixel in the first row R1 are included in the same 1H period (i.e., the 1H period from time t8 to time u8). Also, the period for resetting the pixel in the sixth row R6 and reading the reset signal and the period for AD conversion of the reset signal read from the pixel in the sixth row R6 are included in the same 1H period (i.e., the 1H period from time u8 to time t9). The period for reading the pixel signal from the pixel in the first row R1 is defined as the period during which the address transistor 24 of the pixel in the first row R1 is ON. The period for reading the reset signal from the pixel in the sixth row R6 is defined as the period after the reset transistor 26 of the pixel in the sixth row R6 is OFF and the address transistor 24 of the pixel in the sixth row R6 is ON.

[0081] As can be seen from Figures 4 and 6, pixel reset and readout of the reset signal and readout of the pixel signal are performed alternately every 1H period. Also, AD conversion of the reset signal and AD conversion of the pixel signal are performed alternately every horizontal scanning period. The AD conversion circuit 141 performs AD conversion of the reset signal and AD conversion of the pixel signal alternately every horizontal scanning period.

[0082] (Method for driving an imaging device according to the first embodiment) Figure 7 is a schematic diagram illustrating the driving method of an imaging device according to the first embodiment of the present disclosure, and corresponds to Figure 6. In the driving methods of comparative examples described with reference to Figures 4 and 6, the length of the horizontal scanning period (1H) included in each frame period is the same. In contrast, as shown in Figure 7, in the driving method of an imaging device according to the first embodiment of the present disclosure, each frame period includes a first horizontal scanning period and a second horizontal scanning period of different lengths. The horizontal scanning period including the period during which the reset signal is AD converted is defined as the first horizontal scanning period, and the horizontal scanning period including the period during which the pixel signal is AD converted is defined as the second horizontal scanning period, and are denoted as "1H(r)" and "1H(s)", respectively. In the example in Figure 7, since AD ​​conversion of the signals of the pixel rows read out during that horizontal scanning period is performed, the first horizontal scanning period 1H(r) is a horizontal scanning period including the pixel reset and reset signal readout period, and the second horizontal scanning period 1H(s) is a horizontal scanning period including the pixel signal readout period.

[0083] In the following, we will mainly explain the differences between the driving method of the imaging device according to the first embodiment of this disclosure and the driving method of the imaging device of the comparative example, and will omit explanations of points that are common to the driving method of the imaging device of the comparative example. For example, the steps shown in the flowchart of Figure 5 also apply to the driving method of the imaging device according to the embodiment of this disclosure.

[0084] In the example in Figure 7, the first horizontal scanning period 1H(r) is shorter than the second horizontal scanning period 1H(s). For example, the length of the first horizontal scanning period 1H(r), which includes the reset of the pixel in the sixth row R6 and the reading of the reset signal, i.e., the length of the 1H(r) period from time u8 to time t9, is shorter than the length of the second horizontal scanning period 1H(s), which includes the period of reading the pixel signal from the pixel in the first row R1, i.e., the length of the 1H(s) period from time t8 to time u8. Consequently, in the driving method of Figure 7, in each frame period, the length of the first horizontal scanning period 1H(r), which includes the period during which the reset signal is AD converted by the AD conversion circuit 141, is shorter than the length of the second horizontal scanning period 1H(s), which includes the period during which the pixel signal is AD converted by the AD conversion circuit 141.

[0085] In the driving method according to the first embodiment of this disclosure, the frame period can be shortened, i.e., the frame rate can be improved, compared to the driving method of the comparative example. The reset signal is a signal read out immediately after resetting the potential of the target pixel, and therefore mainly contains kTC noise components and manufacturing variation components of the pixel output transistor, and has a relatively small amplitude. Therefore, it is possible to shorten the time required for AD conversion of the reset signal. As illustrated in Figure 7, by making the first horizontal scanning period, which includes the readout period of the reset signal, shorter than the second horizontal scanning period, which includes the readout period of the pixel signal, the length of the frame period can be shortened, thereby enabling higher speed, i.e., an improvement in the frame rate.

[0086] Figure 8 is a diagram illustrating an example of a driving method for an imaging device according to the first embodiment of the present disclosure, where (a) shows an example of a driving method for an imaging device according to the first embodiment of the present disclosure, and (b) shows a driving method of a comparative example for comparison. Similar to Figure 4, for simplicity, it is assumed here that the number of rows of multiple pixels Px is 6, from the first row R1 to the sixth row R6.

[0087] As shown in Figure 8(a), in the driving method of this embodiment, similar to the example in Figure 7, each frame period alternately includes a first horizontal scanning period and a second horizontal scanning period of different lengths, with the first horizontal scanning period 1H(r), which includes the reset signal readout period and the AD conversion period, being shorter than the second horizontal scanning period 1H(s), which includes the pixel signal readout period and the AD conversion period. In contrast, as shown in Figure 8(b), in the driving method of the comparative example, the lengths of the horizontal scanning periods included in each frame period are all equal. In the illustrated example, the length 1H of the horizontal scanning period included in each frame period in Figure 8(b) is equal to the length 1H(s) of the second horizontal scanning period in Figure 8(a). By comparing Figures 8(a) and (b), it can be seen that the driving method of this embodiment shortens the frame period length compared to the driving method of the comparative example, i.e., the frame rate is improved.

[0088] (Method for driving an imaging device according to a modified example of the first embodiment) A method for driving an imaging device according to a modified example of the first embodiment of this disclosure will be described with reference to Figure 9. Figure 9 is a schematic diagram for illustrating a method for driving an imaging device according to a modified example of the first embodiment of this disclosure, and corresponds to Figure 6.

[0089] In the example in Figure 7, the length of the first horizontal scanning period 1H(r), which includes the reset signal readout period and the AD conversion period, is shorter than the length of the second horizontal scanning period 1H(s), which includes the pixel signal readout period and the AD conversion period. In contrast, in the example in Figure 9, the length of the second horizontal scanning period 1H(s), which includes the pixel signal readout period and the AD conversion period, is shorter than the length of the first horizontal scanning period 1H(r), which includes the reset signal readout period and the AD conversion period. For example, when photographing subjects with small pixel signal amplitudes, i.e., low-light subjects, it is possible to shorten the time required to perform AD conversion on the pixel signal. The length of the frame period can also be shortened by the driving method according to a modification of the first embodiment, that is, by making the second horizontal scanning period, which includes the pixel signal readout period and the AD conversion period, shorter than the first horizontal scanning period, which includes the reset signal readout period and the AD conversion period, thereby enabling higher speed, i.e., an improved frame rate.

[0090] As explained with reference to Figures 7 and 9, if the length of the first horizontal scanning period, which includes the reset signal readout period and the AD conversion period, and the length of the second horizontal scanning period, which includes the pixel signal readout period and the AD conversion period, are different from each other, the frame duration can be shortened compared to the driving method of the comparative example, and thus the frame rate can be improved.

[0091] In the examples in Figures 7 and 9, AD conversion of the signal of the pixel row read out during each horizontal scanning period is performed. That is, if p1 is an integer between 1 and m, then the p1 row R p1 The period for reading out the pixel signal from the pixel, and the p1 row R p1The period during which the pixel signal read from the pixel is undergoing AD conversion is included in the same horizontal scanning period. Furthermore, if p2 is an integer between 1 and m, then the p2 row R p2 The period for resetting the pixels and reading the reset signal, and the p2 row R p2 The period during which the reset signal read from the pixel is undergoing AD conversion is included in the same horizontal scanning period. Embodiments of this disclosure are not limited thereto, and as shown in Figures 20B and 20C later, for example, the period during which the pixel signal or reset signal is read and the period during which the read pixel signal or reset signal is undergoing AD conversion may be included in different horizontal scanning periods. Even in such cases, by having different lengths for the first horizontal scanning period and the second horizontal scanning period, the frame period can be shortened compared to the driving method of the comparative example, that is, the frame rate can be improved.

[0092] Figure 10 is a block diagram illustrating an example of signal processing in an imaging device according to this embodiment. The signal processing will be described below with reference to Figure 10. Note that, for clarity, Figure 10 only shows the components necessary for explaining the signal processing, and does not depict all components of the imaging device 100A. As shown in Figure 10, the imaging device 100A may further include a digital processing unit 124 between the AD conversion circuit 141 and the interface 161. The first digital signal and the second digital signal output from the AD conversion circuit 141 are input to the digital processing unit 124, for example, via a digital memory 151. The digital processing unit 124 includes, for example, an OB (optical black) correction circuit 166 and a parallel-to-serial conversion circuit 168. The digital processing unit 124 may also include an image processing circuit that performs image processing such as gamma processing, either in place of or in addition to the parallel-to-serial conversion circuit 168.

[0093] The voltage supply circuit 190 has a set voltage V based on the control of the control circuit 220. ITOThis is supplied to the opposing electrode 13 of each of the multiple pixels Px. For each of the multiple pixels Px, the reset operation, readout of the reset signal, exposure, and readout of the pixel signal are performed as described above. The reset signal and pixel signal read out from each pixel Px are converted by the AD conversion circuit 141 into a first digital signal and a second digital signal. At this time, the AD conversion circuit 141 performs AD conversion of the reset signal and the pixel signal at the number of gradations of the digital output set by the control circuit 220. The control circuit 220 uses a voltage V ITO The number of grayscale levels in the digital output of the AD conversion is changed accordingly.

[0094] The imaging device 100A includes optical black (OB) pixels (not shown) at, for example, the edges of the imaging area. The OB correction circuit 166 included in the digital processing unit 124 receives the second digital signal and performs OB correction on the first and second digital signals using the OB pixels. In OB correction, the difference between the first or second digital signal and the signal output from the OB pixel is calculated. By performing OB correction on the first and second digital signals of each of the multiple pixels Px, the black levels of each first and second digital signal are aligned. Note that the imaging device 100A does not necessarily have to perform OB correction.

[0095] Next, the first and second digital signals, which have undergone OB correction, are output to the parallel-to-serial conversion circuit 168 included in the digital processing unit 124. The parallel-to-serial conversion circuit 168 converts the parallel digital signals to serial signals. In the parallel-to-serial conversion circuit 168, the number of bits of serial data to be converted per pixel data is determined by the output bit setting register. The number of output bits (number of gradations) determined by the output bit setting register is set, for example, based on the control of the control circuit 220. The control circuit 220 controls, for example, voltage V ITO The number of output bits is set according to the number of gradations of the digital output of the AD conversion of the reset signal and pixel signal by the AD conversion circuit 141, and / or according to the number of gradations of the AD conversion of the digital output.

[0096] The serial pixel data converted by the parallel-to-serial conversion circuit 168 is output by an interface 161 such as LVDS (Low Voltage Differential Signaling) or SLVS (Scalable Low Voltage Signaling).

[0097] Figure 11 schematically shows the state of the digital memory 151 that stores the AD-converted data, the state of the interface 161, the output format of the interface 161, and the output state of the serial pixel data when using the driving method of Figure 7. The "vertical scan address" indicates the row to be scanned, that is, the address transistor 24 provided on the pixel of that row is turned on to select that row. As shown in Figure 11, the readout of the reset signal and the readout of the pixel signal are performed alternately with each horizontal scan period. In addition, AD conversion of the signal of the pixel row read out during each horizontal scan period is performed, so the AD conversion of the reset signal and the AD conversion of the pixel signal are performed alternately with each horizontal scan period. Specifically, during the horizontal scan period at the left end of Figure 11, the pixel signal of the first row R1 is read out, and the read pixel signal of the first row R1 is AD-converted by the AD conversion circuit 141. The second digital signal generated by the AD conversion of the pixel signal is held in the digital memory 151. In the next horizontal scanning period, row (N+1) R N+1 Readout of the reset signal, and the readout (N+1)th row R N+1 The AD conversion of the reset signal is performed, and the second digital signal generated by the AD conversion of the pixel signal in the previous horizontal scanning period is read from the digital memory 151, and after parallel-to-serial conversion, is output from the interface 161 to the frame memory 171. In the next horizontal scanning period, the pixel signal of the second row R2 is read and AD converted, and the (N+1) row R2 that was AD converted in the previous horizontal scanning period is read. N+1The first digital signal corresponding to the reset signal is read from the digital memory 151, converted from parallel to serial, and output to the frame memory 171 from the interface 161. The same process is repeated during subsequent horizontal scanning periods. In this example, the reset signal is output from the interface 161 as a first digital signal with 12 bits per pixel, and the pixel signal is output as a second digital signal with 16 bits per pixel. Generally, the pixel signal is output with a higher number of bits than the reset signal.

[0098] As shown in Figure 11, the length of the second horizontal scanning period 1H(s), which includes the pixel signal readout period and the AD conversion period, is longer than the length of the first horizontal scanning period 1H(r), which includes the reset signal readout period and the AD conversion period. In the example in Figure 11, each frame period alternates between a first horizontal scanning period and a second horizontal scanning period of different lengths. During each horizontal scanning period, the reset signal is read out and the pixel signal is read out alternately. In each horizontal scanning period, the AD conversion of the signal of the pixel row read out during that horizontal scanning period is performed, and the digital signal generated in the previous horizontal scanning period is output to the frame memory 171. Therefore, the output of the second digital signal, which is the result of AD conversion of the pixel signal, occurs within the first horizontal scanning period 1H(r), and the output of the first digital signal, which is the result of the reset signal, occurs within the second horizontal scanning period 1H(s). In other words, the length of the horizontal scanning period including the period during which the second digital signal corresponding to the pixel signal is output is shorter than the length of the horizontal scanning period including the period during which the first digital signal corresponding to the reset signal is output. As in this example, when the pixel signal is output with a higher number of bits than the reset signal, the output time of the second digital signal corresponding to the pixel signal can become the rate-limiting factor.

[0099] Figure 12A schematically shows the configuration of an imaging device 100A1 according to a modification of the first embodiment of the present disclosure. The imaging device 100A1 differs from the imaging device 100A in that it further has a line buffer 191 that temporarily holds the signals output by the digital memory 151. The line buffer 191 temporarily holds one line of digital signals output from the digital memory 151. Figure 12B schematically shows the state of the digital memory 151 that stores the AD-converted data, the state of the interface 161, the output format of the interface 161, and the output state of the serial pixel data when the driving method of Figure 7 is applied to the imaging device 100A1. As shown in Figure 12B, the imaging device 100A1, by having the line buffer 191, can shift the output phase of the digital signal from the interface 161 by one horizontal scanning period. In each horizontal scanning period, the digital signal generated in the two previous horizontal scanning periods is output to the frame memory 171. In other words, the output of the second digital signal corresponding to the pixel signal occurs within the second horizontal scanning period 1H(s), and the output of the first digital signal corresponding to the reset signal occurs within the first horizontal scanning period 1H(r). Therefore, the length of the horizontal scanning period during which the output of the second digital signal corresponding to the pixel signal occurs is longer than the length of the horizontal scanning period during which the output of the first digital signal corresponding to the reset signal occurs. Thus, the problem in the example in Figure 11, where the output time of the second digital signal corresponding to the pixel signal can be the rate-limiting factor, can be solved. The imaging device 100A1 can achieve a further improvement in frame rate compared to the imaging device 100A. Next, we will explain the parallel-to-serial conversion process.

[0100] Figure 13 schematically illustrates the operation of the parallel-to-serial conversion circuit 168 in converting 16-bit parallel pixel data to serial pixel data. Figure 13 also shows the operation of converting so that the number of bits in the parallel pixel data (i.e., the number of bits in the AD conversion) and the number of output bits in the serial pixel data are the same. Hereafter, the number of output bits in the converted serial pixel data may be referred to as the "sensor output bit count." As shown in Figure 13, in the parallel-to-serial conversion of one parallel pixel data that has been AD converted to 16 bits, a speed is required such that 16T of the serial pixel data transfer clock SCLK corresponds to 1T of the parallel pixel data transfer clock PCLK. 1T is one cycle of the clock that alternates between high and low levels, and is the interval between the rising (or falling) edges of the clock. In the example shown in Figure 13, the serial pixel data is output sequentially from the LSB (Least Significant Bit), but it may also be output sequentially from the MSB (Most Significant Bit). Also, although the pixel data is packed in 16-bit increments, it may also be packed in 8-bit increments.

[0101] Figure 14 schematically illustrates the operation of the parallel-to-serial conversion circuit 168 in converting 12-bit parallel pixel data to serial pixel data. Figure 14 also shows the operation of converting so that the number of bits in the parallel pixel data and the number of output bits in the serial pixel data are the same. As shown in Figure 14, for the parallel-to-serial conversion of one parallel pixel data that has been AD-converted with 12 bits, a speed is required such that the transfer clock SCLK of the serial pixel data corresponds to 12T for every 1T of the transfer clock PCLK of the parallel pixel data. In the case shown in Figure 14, compared to the case shown in Figure 13, if the speed of the transfer clock SCLK of the serial pixel data is the same, the time required per pixel data conversion is reduced to 12 / 16. Since the number of bits in the AD conversion corresponds to the number of bits in the parallel pixel data, if the number of bits in the AD conversion and the number of sensor output bits are the same, reducing the number of bits in the AD conversion will shorten the time required for the parallel-to-serial conversion of one pixel data.

[0102] As illustrated in Figures 15 and 16, the analog gains for reading the pixel signal and reading the reset signal may be different. Since the reset signal is read after the reset operation of each pixel and before the exposure period, it mainly contains manufacturing variations and dark current components of the transistors (e.g., the signal detection transistor 22 that constitutes the source follower) in the readout circuit 20 of each pixel, and the signal amplitude is smaller compared to the pixel signal. In order to read out such a small-amplitude reset signal with high accuracy and low noise, the analog gain when reading the reset signal can be set higher than the analog gain when reading the pixel signal. On the other hand, the pixel signal read out after the exposure period contains a signal corresponding to the charge corresponding to the exposure amount for each pixel, so the appropriate analog gain may differ depending on the exposure period. The analog gain when reading the pixel signal can be switched depending on the scene. For example, in the example in Figure 15, the analog gain when reading the pixel signal is 0 dB, and in the example in Figure 16, the analog gain when reading the pixel signal is 12 dB. In both the examples in Figure 15 and Figure 16, the analog gain during reset signal readout is 18 dB, which is higher than the analog gain during pixel signal readout. For example, the analog gain during pixel signal readout may be varied for each frame period. In this case, the analog gain during reset signal readout may be kept constant.

[0103] (Method for driving an imaging device according to the second embodiment) In the driving method according to the first embodiment described with reference to Figure 11, the reading of one row of reset signals and the reading of one row of pixel signals are performed alternately in each horizontal scanning period, and AD conversion of the signals of the pixel rows read in that horizontal scanning period is performed in each horizontal scanning period. In contrast, as shown in Figure 17, in the driving method of the imaging device according to the second embodiment of this disclosure, the reading of one row of pixel signals is performed in one horizontal scanning period, and then the reading of two rows of reset signals is performed in two horizontal scanning periods, and this is repeated. In this embodiment as well, AD conversion of the signals of the pixel rows read in that horizontal scanning period is performed in each horizontal scanning period.

[0104] During the horizontal scanning period at the left edge of Figure 17, the pixel signals of the first row R1 are read out, and the read out pixel signals of the first row R1 are converted by the AD conversion circuit 141. In the next horizontal scanning period, the (N+1) row R N+1 Readout of the reset signal, and the readout (N+1)th row R N+1 The AD conversion of the reset signal is performed. In the next horizontal scanning period, the (M+1) row R M+1 Readout of the reset signal, and the readout (N+1)th row R N+1 AD conversion of the reset signal is performed. In the next horizontal scanning period, the pixel signal of the second row R2 is read out, and AD conversion of the read out pixel signal of the second row R2 is performed. The same process is repeated in subsequent horizontal scanning periods. As shown in Figure 17, each frame period alternates between one second horizontal scanning period 1H(s) and two first horizontal scanning periods 1H(r). In frame periods where the exposure time changes significantly, there may be situations where the readout of the reset signal overlaps, so it is necessary to read out the reset signal for two rows.

[0105] As shown in the example in Figure 18, after reading out and performing AD conversion of one row of pixel signals in one horizontal scanning period, the reading out and performing AD conversion of two rows of reset signals in one horizontal scanning period may be repeated. The reading out and AD conversion of two rows of reset signals may be performed in parallel and simultaneously. To perform the reading out and AD conversion of two rows of reset signals (or pixel signals) in parallel, as in the imaging device of Patent Document 3, the device may have two systems for reading out the reset signal or pixel signal from each pixel: a first system including a first output signal line and a second system including a second output signal line, and may have a first AD conversion circuit connected to the first output signal line and a second AD conversion circuit connected to the second output signal line. For reference, the entirety of the disclosure of Patent Document 3 is incorporated herein by reference.

[0106] In the horizontal scanning period at the left edge of Figure 18, the pixel signal of the first row R1 is read out and AD conversion is performed. In the next horizontal scanning period, the (N+1)th row R N+1and the (M+1)th row R M+1 The reset signal is read out and AD conversion is performed. In the next horizontal scanning period, the pixel signal of the second row R2 is read out and AD conversion is performed. The same process is repeated in subsequent horizontal scanning periods. As shown in Figure 18, each frame period alternates between a second horizontal scanning period 1H(s) and a first horizontal scanning period 1H(r) for each horizontal scanning period.

[0107] In the example in Figure 19, the reading and AD conversion of two rows of reset signals and the reading and AD conversion of two rows of pixel signals are performed alternately during each horizontal scanning period. Compared to a driving method where the reading and AD conversion of one row of reset signals and the reading and AD conversion of one row of pixel signals are performed alternately during each horizontal scanning period, as in the example in Figure 11, it is possible to double the frame rate.

[0108] In the horizontal scanning period at the left edge of Figure 19, the pixel signals of the first row R1 and the second row R2 are read out and AD conversion is performed. In the next horizontal scanning period, the (N+1)th row R N+1 and the (N+2)th row R N+2 The reset signal is read out and AD conversion is performed. In the next horizontal scanning period, the pixel signals of the third row R3 and the fourth row R4 are read out and AD conversion is performed. The same process is repeated in subsequent horizontal scanning periods. As shown in Figure 19, each frame period alternates between a second horizontal scanning period 1H(s) and a first horizontal scanning period 1H(r) for each horizontal scanning period.

[0109] (Imaging device and its driving method according to the third embodiment) Figure 20A schematically shows the configuration of the imaging device 100A2 according to the third embodiment of the present disclosure. The imaging device 100A2 has a plurality of output signal lines S jThe imaging device differs from the imaging device 100A in that it further has a sample-and-hold circuit 193 connected to the AD conversion circuit 141. The sample-and-hold circuit 193 temporarily holds one row of reset signals or pixel signals read from multiple pixels Px. The sample-and-hold circuit 193 may be configured to temporarily hold two or more rows of signals.

[0110] Figure 20B schematically shows the state of the sample-and-hold circuit 193 that holds the signal read from the pixel, the state of the AD conversion circuit 141, the state of the digital memory 151 that stores the data after AD conversion, and the state of the interface 161 when the driving method of Figure 11 is applied to the imaging device 100A2. As shown in Figure 20B, the imaging device 100A2 has a sample-and-hold circuit 193 that allows it to perform AD conversion on a row of reset signals or pixel signals read from multiple pixels Px in one horizontal scanning period in the next horizontal scanning period. That is, in the example of Figure 20B, the pixel reset and reset signal readout period is included in the second horizontal scanning period 1H(s) which includes the AD conversion period of the pixel signal, and the pixel signal readout period is included in the first horizontal scanning period 1H(r) which includes the AD conversion period of the reset signal. In the horizontal scanning period at the left end of Figure 20B, the pixel signal of the first row R1 is read out. The read out pixel signal of the first row R1 is held in the sample-and-hold circuit 193. In the next horizontal scanning period, row (N+1) R N+1 The reset signal is read out, and the pixel signal of the first row R1 read out in the previous horizontal scanning period is read out from the sample-and-hold circuit 193 and converted by the AD conversion circuit 141. The second digital signal generated by the AD conversion of the pixel signal is held in the digital memory 151. In the next horizontal scanning period, the pixel signal of the second row R2 is read out, and the (N+1) row R read out in the previous horizontal scanning period is read out. N+1The reset signal is converted from digital to audio (AD) signals. Furthermore, the second digital signal generated by the AD conversion during the previous horizontal scanning period is read from the digital memory 151 and output from the interface 161. This process is repeated in subsequent horizontal scanning periods.

[0111] In the example shown in Figure 20B, the length of the second horizontal scanning period 1H(s), which includes the AD conversion period of the pixel signal and the readout period of the reset signal, is shorter than the length of the first horizontal scanning period 1H(r), which includes the AD conversion period of the reset signal and the readout period of the pixel signal. In this case, the readout period of the pixel signal can be made longer than the readout period of the reset signal, and the output period of the second digital signal corresponding to the pixel signal can be made longer than the output period of the first digital signal corresponding to the reset signal.

[0112] In contrast, as shown in Figure 20C, if the sample-and-hold circuit 193 can hold two rows of signals, then one row of reset signals or pixel signals read from multiple pixels Px in a given horizontal scanning period can be AD-converted in the next horizontal scanning period. That is, in the example in Figure 20C, the pixel reset and reset signal readout periods are included in the first horizontal scanning period 1H(r), which includes the AD conversion period of the reset signals, and the pixel signal readout period is included in the second horizontal scanning period 1H(s), which includes the AD conversion period of the pixel signals. In the example in Figure 20C, since the length of the second horizontal scanning period 1H(s) is longer than the length of the first horizontal scanning period 1H(r), the pixel signal readout period can be made longer than the reset signal readout period, and the pixel signal AD conversion period can be made longer than the reset signal AD conversion period.

[0113] Figure 1 illustrates a configuration in which the row scanning circuit 130, control circuit 220, AD conversion circuit 141, digital memory 151, and interface 161 are arranged on a semiconductor substrate 110 on which multiple pixels Px are formed. That is, the semiconductor substrate 110 on which multiple pixels Px are formed, the row scanning circuit 130, the control circuit 220, the AD conversion circuit 141, the digital memory 151, and the interface 161 can be provided in the form of an integrated package. Some or all of these circuits may be integrally formed on the semiconductor substrate 110 in addition to the read circuit 20 for each pixel Px. That is, these circuits can be formed on the semiconductor substrate 110 by applying a process similar to the process for forming the read circuit 20 for each pixel Px. For example, the control circuit 220 may be an integrated circuit formed on the semiconductor substrate 110. However, it is not essential that all of these circuits be integrally formed on the semiconductor substrate 110 together with each pixel Px. Some or all of these circuits may be arranged on a substrate different from the semiconductor substrate 110 on which each pixel Px is formed.

[0114] The functions of the control circuit 220 and the image processing circuit 170A described above may be realized by a combination of general-purpose processing circuits and software, or by hardware specialized for such processing. The control circuit 220 may be configured to receive exposure time settings from the image processing circuit 170A according to the processing results of the image processing circuit 170A, and to supply drive signals corresponding to the exposure time settings to the row scanning circuit 130, the AD conversion circuit 141, etc.

[0115] Furthermore, the image processing circuit 170A may be provided in the imaging device in the form of a separate chip or package from the group of circuits arranged on the semiconductor substrate 110. These substrates, including the semiconductor substrate 110, may be provided in a stacked form. The frame memory 171 may be arranged in the imaging device in the form of a separate chip or package from the image processing circuit 170A. Alternatively, the image processing circuit 170A may be arranged on the semiconductor substrate 110. The image processing circuit 170A may be part of the control circuit 220. The image processing circuit 170A or the control circuit 220 may be configured to perform processing such as distance measurement calculation and wavelength information separation.

[0116] The imaging device according to the embodiments of the present disclosure may be provided in the form of a package in which a semiconductor substrate 110 on which a plurality of pixels Px are formed and an image processing circuit 170A are integrated. The imaging device according to the embodiments of the present disclosure may be in the form of an image sensor chip or in the form of a camera. [Industrial applicability]

[0117] Embodiments of this disclosure can be used in various cameras and camera systems, such as digital still cameras, digital video cameras, medical cameras, security cameras, cameras used mounted on vehicles, rangefinder cameras, microscope cameras, cameras for unmanned aerial vehicles called drones, and cameras for robots. Vehicle-mounted cameras can be used, for example, as inputs to control devices to ensure the safe operation of a vehicle. Alternatively, they can be used to assist an operator in ensuring the safe operation of a vehicle. [Explanation of Symbols]

[0118] 10...Photoelectric conversion unit, 20...Readout circuit, 100A, 100A1, 100A2...Imaging device, 110...Semiconductor substrate, 120...Circuit board, 130...Row scanning circuit, 141...AD conversion circuit, 151...Digital memory, 161...Interface, 170A...Image processing circuit, 171...Frame memory, 220...Control circuit, Px, Px1~Px4...Pixels

Claims

1. Multiple pixels arranged in multiple rows and columns, An AD conversion circuit that converts analog signals read from each of the aforementioned multiple pixels into digital signals, Frame memory and Image processing circuit and Equipped with, The analog signal includes a reset signal that represents the reset level and a pixel signal that represents the image of the subject. The length of the first horizontal scanning period, which includes the period during which the AD conversion circuit converts the reset signal, is different from the length of the second horizontal scanning period, which includes the period during which the AD conversion circuit converts the pixel signal. The frame memory temporarily holds the first digital signal corresponding to the reset signal from the output of the AD conversion circuit. The image processing circuit outputs the difference between a second digital signal corresponding to the pixel signal for the pixel from which the reset signal was read out of the output of the AD conversion circuit, and the first digital signal held in the frame memory. Imaging device.

2. The length of the first horizontal scanning period is shorter than the length of the second horizontal scanning period. The imaging apparatus according to claim 1.

3. The length of the first horizontal scanning period is longer than the length of the second horizontal scanning period. The imaging apparatus according to claim 1.

4. A digital memory that temporarily holds the first digital signal and the second digital signal, A line buffer that temporarily holds the signal output by the aforementioned digital memory and The imaging apparatus according to any one of claims 1 to 3, further comprising:

5. Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to claim 4, wherein the line buffer outputs the first digital signal or the second digital signal generated by the AD conversion circuit in the horizontal scan period two horizontal scan periods prior to each horizontal scan period to the frame memory.

6. The system further comprises a digital memory for temporarily holding the first digital signal and the second digital signal, Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to any one of claims 1 to 3, wherein the digital memory outputs the first digital signal or the second digital signal generated by the AD conversion circuit in the immediately preceding horizontal scanning period to the frame memory during each horizontal scanning period.

7. The imaging apparatus according to any one of claims 1 to 3, wherein the AD conversion circuit alternately performs the conversion of the reset signal read from the pixels included in one or more rows and the conversion of the pixel signal read from the pixels included in one or more rows.

8. The imaging apparatus according to claim 7, wherein the AD conversion circuit alternately performs, for each horizontal scanning period, the conversion of the reset signal read from the pixels included in one or more rows and the conversion of the pixel signals read from the pixels included in one or more other rows.

9. The imaging apparatus according to claim 7, wherein the AD conversion circuit alternately performs, for each horizontal scanning period, the conversion of the reset signal read from the pixel in one row and the conversion of the pixel signal read from the pixel in another row.

10. Each frame period alternately includes the first horizontal scanning period and the second horizontal scanning period. The imaging apparatus according to claim 9, wherein the AD conversion circuit converts the reset signal or the pixel signal read out during each horizontal scanning period.

11. The imaging apparatus according to claim 7, wherein the AD conversion circuit performs, during one horizontal scanning period, conversion of the pixel signals read from the pixels included in two or more rows, or conversion of the reset signals read from the pixels included in two or more rows.

12. The system further comprises a sample-and-hold circuit that temporarily holds the reset signal or the pixel signal read from the plurality of pixels, The imaging apparatus according to any one of claims 1 to 3, wherein the AD conversion circuit converts the reset signal or the pixel signal read out in the immediately preceding horizontal scanning period during each horizontal scanning period.

Images