Method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Abstract

The present invention provides a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of forming a narrow-width, high-density region around a source region. [Solution] A method for manufacturing a nitride semiconductor device includes the steps of: forming a first well region of a second conductivity type on a nitride semiconductor substrate of a first conductivity type; forming a source region of a first conductivity type by ion implanting impurities of a first conductivity type into the first well region; forming a second well region of a second conductivity type at a position on the nitride semiconductor substrate that is isolated from the source region by the first well region, in contact with the first well region, and having a higher concentration of impurities of a second conductivity type than the first well region; and subjecting the nitride semiconductor substrate including the first well region, the source region, and the second well region to heat treatment to diffuse impurities of a second conductivity type from the second well region to the area around the source region, thereby forming a high-concentration region of a second conductivity type around the source region, where the concentration of impurities of a second conductivity type is higher than that of the first well region.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

Background Art

[0002] In a GaN_MOSFET, the threshold value is low with respect to the Mg concentration in the body layer, and it tends to operate in a normally-on state. Although it is possible to increase the threshold value by increasing the Mg concentration in the body layer, the mobility decreases as a trade-off. Patent Document 1 discloses a technique of introducing an impurity (boron) of the same conductivity type as the impurity for adjusting the threshold voltage into the boundary region between the element isolation region and the channel region of the MOS transistor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Applying the technique disclosed in Patent Document 1 to a GaN_MOSFET, a method of locally ion-implanting Mg into the channel region to form a high-concentration Mg region can be considered. However, in this method, since Mg diffuses during the heat treatment after the Mg ion implantation, the Mg concentration decreases and the dimensional width increases. An object of the present disclosure is to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device capable of forming a high-concentration region with a narrow width around the source region.

Means for Solving the Problems

[0005] To solve the above problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes the steps of: forming a first well region of a second conductivity type on a nitride semiconductor substrate of a first conductivity type; forming a source region of a first conductivity type by ion implanting an impurity of a first conductivity type into the first well region; forming a second well region of a second conductivity type at a position on the nitride semiconductor substrate that is isolated from the source region by the first well region, in contact with the first well region, and having a higher concentration of impurities of a second conductivity type than the first well region; and subjecting the nitride semiconductor substrate, including the first well region, the source region, and the second well region, to heat treatment to diffuse impurities of a second conductivity type from the second well region to the periphery of the source region, thereby forming a high-concentration region of a second conductivity type around the source region, where the concentration of impurities of a second conductivity type is higher than that of the first well region.

[0006] A nitride semiconductor device according to one aspect of the present disclosure comprises: a nitride semiconductor substrate of a first conductivity type; a first well region of a second conductivity type provided on the nitride semiconductor substrate; a source region of a first conductivity type provided in the first well region; a second well region of a second conductivity type provided on the nitride semiconductor substrate at a position away from the source region and having a higher impurity concentration of the second conductivity type than the first well region; an impurity diffusion region of a second conductivity type provided on the nitride semiconductor substrate at a position interposed between the second well region and the source region, in contact with the second well region, and having a higher impurity concentration of the second conductivity type than the first well region; a high-concentration region of a second conductivity type provided around the source region and having a higher impurity concentration of the second conductivity type than the first well region; and a gate insulating film provided on the surface side of the nitride semiconductor substrate. The second well region, the impurity diffusion region, the high-concentration region, and the source region face the surface of the nitride semiconductor substrate. The gate insulating film is in contact with the high-concentration region. [Effects of the Invention]

[0007] According to one aspect of this disclosure, a method for manufacturing a nitride semiconductor device and a nitride semiconductor device can be provided that enable the formation of a narrow-width, high-density region around a source region. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing an example of the configuration of a GaN semiconductor device according to Embodiment 1 of this disclosure. [Figure 2] Figure 2 is a cross-sectional view showing an example of the configuration of a GaN semiconductor device according to Embodiment 1 of this disclosure. [Figure 3] Figure 3 is an enlarged view of the cross-sectional view in Figure 2, and shows an example of the configuration of a single vertical MOSFET (unit structure). [Figure 4] Figure 4 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 1 of Embodiment 1 of this disclosure. [Figure 5] Figure 5 is a plan view showing the configuration of a vertical MOSFET according to a modified example 2 of Embodiment 1 of this disclosure. [Figure 6] Figure 6 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 2 of Embodiment 1 of this disclosure. [Figure 7] Figure 7 is a cross-sectional view showing the configuration of the embedded well region according to a modified example 3 of Embodiment 1 of this disclosure. [Figure 8] Figure 8 is a graph showing the analysis results of impurity concentrations at locations along arrows A and B in Figure 7. [Figure 9] Figure 9 is a plan view showing the configuration of a vertical MOSFET according to a modified example 4 of Embodiment 1 of this disclosure. [Figure 10] Figure 10 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 4 of Embodiment 1 of this disclosure. [Figure 11] Figure 11 is a cross-sectional view showing the configuration of a vertical MOSFET 1 according to a modified example 4 of Embodiment 1 of this disclosure. [Figure 12] Figure 12 is a plan view showing the configuration of a vertical MOSFET according to a modified example 5 of Embodiment 1 of this disclosure. [Figure 13]Figure 13 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 5 of Embodiment 1 of this disclosure. [Figure 14] Figure 14 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 5 of Embodiment 1 of this disclosure. [Figure 15] Figure 15 is a cross-sectional view showing the configuration of a vertical MOSFET according to a modified example 5 of Embodiment 1 of this disclosure. [Figure 16A] Figure 16A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16B] Figure 16B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16C] Figure 16C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16D] Figure 16D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16E] Figure 16E is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16F] Figure 16F is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 16G] Figure 16G is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 2 of this disclosure, in order of steps. [Figure 17A] Figure 17A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 3 of this disclosure, in order of steps. [Figure 17B] Figure 17B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 3 of this disclosure, in order of steps. [Figure 18A] Figure 18A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 4 of this disclosure, in order of steps. [Figure 18B] Figure 18B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 4 of this disclosure, in order of steps. [Figure 18C]Figure 18C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 4 of this disclosure, in order of steps. [Figure 19A] Figure 19A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 5 of this disclosure, in order of steps. [Figure 19B] Figure 19B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 5 of this disclosure, in order of steps. [Figure 19C] Figure 19C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 5 of this disclosure, in order of steps. [Figure 19D] Figure 19D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 5 of this disclosure, in order of steps. [Figure 19E] Figure 19E is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 5 of this disclosure, in order of steps. [Figure 20A] Figure 20A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20B] Figure 20B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20C] Figure 20C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20D] Figure 20D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20E] Figure 20E is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20F] Figure 20F is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20G] Figure 20G is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 20H] Figure 20H is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 6 of this disclosure, in order of steps. [Figure 21A]Figure 21A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21B] Figure 21B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21C] Figure 21C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21D] Figure 21D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21E] Figure 21E is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21F] Figure 21F is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21G] Figure 21G is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 21H] Figure 21H is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 7 of this disclosure, in order of steps. [Figure 22A] Figure 22A is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 8 of this disclosure, in order of steps. [Figure 22B] Figure 22B is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 8 of this disclosure, in order of steps. [Figure 22C] Figure 22C is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 8 of this disclosure, in order of steps. [Figure 22D] Figure 22D is a cross-sectional view showing the manufacturing method of a GaN semiconductor device according to Embodiment 8 of this disclosure, in order of steps. [Figure 23] Figure 23 is a cross-sectional view showing a modified example of the manufacturing method according to Embodiment 8 of this disclosure. [Modes for carrying out the invention]

[0009] Embodiments of the present disclosure are described below. In the following drawings, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and component, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following explanation. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.

[0010] Furthermore, in the following explanation, the terms X-axis direction, Y-axis direction, and Z-axis direction may be used to describe directions. For example, the X-axis direction and Y-axis direction are directions parallel to the surface 10a of the GaN substrate 10, which will be described later. The X-axis direction and Y-axis direction are also called the horizontal direction. The Z-axis direction is a direction perpendicular to the surface 10a of the GaN substrate 10. The X-axis direction, Y-axis direction, and Z-axis direction are mutually orthogonal.

[0011] Furthermore, in the following explanation, the direction of the Z-axis arrow may be referred to as "up," and the opposite direction of the Z-axis arrow may be referred to as "down." "Up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions to specify the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical concept of this disclosure. For example, it goes without saying that if the paper is rotated 180 degrees, "up" becomes "down" and "down" becomes "up."

[0012] Furthermore, in the following explanation, the + and - attached to p and n indicating conductivity types mean that the semiconductor region has a relatively higher or lower impurity concentration compared to semiconductor regions without + and - attached. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of each semiconductor region are exactly the same.

[0013] <Embodiment 1> Figure 1 is a plan view showing an example configuration of a gallium nitride (GaN) semiconductor device 100 according to Embodiment 1 of the present disclosure. Figure 2 is a cross-sectional view showing an example configuration of a GaN semiconductor device 100 according to Embodiment 1 of the present disclosure. Figure 2 shows a cross-section obtained by cutting the plan view of Figure 1 with the line X2-X2' parallel to the X axis. Figure 3 is an enlarged view of the cross-sectional view of Figure 2, showing an example configuration of one vertical MOSFET 1 (unit structure).

[0014] The GaN semiconductor device 100 shown in Figures 1 and 2 is an example of a "nitride semiconductor device" of this disclosure and is a power device. As shown in Figures 1 and 2, the GaN semiconductor device 100 comprises a GaN substrate 10 (an example of a "nitride semiconductor substrate" of this disclosure) having a front surface 10a and a back surface 10b, and a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 provided on the GaN substrate 10. For example, the plurality of vertical MOSFETs 1 are repeatedly provided in one direction (for example, in the X-axis direction). One vertical MOSFET 1 is a repeating unit structure, and these unit structures are arranged in a line in one direction.

[0015] As shown in Figures 1 to 3, the GaN substrate 10 comprises an n+-type GaN single crystal substrate 11 and an n-type GaN layer 12 provided on the GaN single crystal substrate 11. The GaN single crystal substrate 11 is, for example, an n+-type c-plane GaN single crystal substrate. The n-type impurities contained in the GaN single crystal substrate 11 are, for example, one or more of silicon (Si), oxygen (O), and germanium (Ge). For example, the GaN single crystal substrate 11 contains Si as an n-type impurity, and the Si impurity concentration in the GaN single crystal substrate 11 is 5 × 10⁻¹⁶. 17 cm -3 That's all.

[0016] The GaN single crystal substrate 11 has a dislocation density of 1 × 10⁻⁶ 7 cm -2The substrate may be a low-dislocation self-supporting substrate with a dislocation density of less than 10. Because the GaN single-crystal substrate 11 is a low-dislocation self-supporting substrate, the dislocation density of the GaN layer 12 formed on the GaN single-crystal substrate 11 is also reduced. Furthermore, by using a low-dislocation self-supporting substrate, leakage current in the power device can be reduced even when a large-area power device is formed on the GaN substrate 10. This allows the manufacturing equipment to produce power devices with a high yield rate. Additionally, during heat treatment, it is possible to prevent ion-implanted impurities from deeply diffusing along the dislocations.

[0017] The GaN layer 12 is a single-crystal GaN layer epitaxially grown on one surface of the GaN single-crystal substrate 11. The GaN layer 12 is formed by doping with n-type impurities during the epitaxial growth process. The n-type impurities are, for example, Si. The GaN layer 12 is doped with, for example, Si as n-type impurities, 1 × 10⁻¹⁶ 15 cm -3 The above 5 x 10 16 cm -3 It contains the following concentrations.

[0018] The vertical MOSFET 1 has a p-type well region 13 (an example of the "first well region" in this disclosure) provided on the surface 10a side of the GaN substrate 10, a p+-type contact region 15 (an example of the "second well region" in this disclosure), an n+-type source region 23, a p+-type impurity diffusion region 16 interposed between the contact region 15 and the source region 23, and a p+-type high-concentration region 17 provided around the source region 23. Although both are p+-type, the high-concentration region 17 has a higher concentration of p-type impurities than the impurity diffusion region 16.

[0019] In the GaN layer 12, the n-type region excluding the well region 13 and the contact region 15 is the drift region. The drift region is located between the surface 10a of the GaN substrate 10 (i.e., the surface of the GaN layer 12) and the back surface of the GaN layer 12. The drift region is in contact with the n+-type GaN single crystal substrate 11 provided on the back surface side of the GaN layer 12. Further, the vertical MOSFET 1 includes a gate insulating film 21 provided on the surface 10a side of the GaN substrate 10, a gate electrode 22 provided on the gate insulating film 21, a source electrode 25 provided on the surface 10a side of the GaN substrate 10 and in contact with the n+-type source region 23 and the p+-type contact region 15, and a drain electrode 26 provided on the back surface 10b side of the GaN substrate 10 and in contact with the n+-type GaN single crystal substrate 11.

[0020] The well region 13 is, for example, a p-type layer formed by ion-implanting a p-type impurity such as Mg on the surface 10a side of the GaN substrate 10 and activating the p-type impurity by heat treatment. The well region 13 contains, as the p-type impurity, for example, Mg at a concentration of 1×10 17 cm -3 or more and 3×10 18 cm -3 or less. The well region 13 faces the surface 10a of the GaN substrate 10 and is in contact with the gate insulating film 21.

[0021] The contact region 15 is, for example, a p+-type layer formed by ion-implanting a p-type impurity such as Mg on the surface 10a side of the GaN substrate 10 and activating the p-type impurity by heat treatment. The contact region 15 contains Mg as the p-type impurity at a concentration of 3×10 18 cm -3 or more and 1×10 21 cm -3 or less, more preferably 1×10 19 cm -3 or more and 2×10 20 cm -3 or less. The contact region 15 faces the surface 10a of the GaN substrate 10. The contact region 15 is located inside the well region 13 and is in contact with the well region 13. Further, the contact region 15 is also in contact with the source region 23.

[0022] The well region 13 is connected to the source electrode 25 via the contact region 15. As a result, the potential of the well region 13 is fixed to the potential of the source electrode 25 (for example, a reference potential such as ground potential (GND)).

[0023] The source region 23 is an n+ type layer formed by ion implantation of n-type impurities such as Si or O on the surface 10a side of the GaN substrate 10, and activation of the n-type impurities by heat treatment. For example, Si is used as the n-type impurity in the source region 23, resulting in a layer of 1 × 10⁻¹⁶ n+ type impurities. 19 cm -3 The above 5 x 10 20 cm -3 The following concentrations are included. The source region 23 is located in the well region 13 below both sides of the gate electrode 22 and faces the surface 10a of the GaN substrate 10. The source region 23 is located inside the well region 13 and is in contact with the well region 13.

[0024] The p+-type impurity diffusion region 16 is located in the well region 13 at a position in contact with the contact region 15 and interposed between the contact region 15 and the source region 23. The impurity diffusion region 16 is formed by the thermal diffusion of p-type impurities (e.g., Mg) from the p+-type contact region 15. The impurity diffusion region 16 has a higher p-type impurity concentration than the p-type well region 13 and a lower p-type impurity concentration than the p+-type contact region 15. The impurity diffusion region 16 faces the surface 10a of the GaN substrate 10 and is in contact with the source electrode 25.

[0025] The high-concentration p+ region 17 is located within the GaN substrate 10, surrounding the entire source region 23. The high-concentration region 17 is formed by the thermal diffusion of p-type impurities (e.g., Mg) from the p-type contact region 15. The high-concentration region 17 is formed by, for example, 3 × 10⁻¹⁶ Mg as the p-type impurity. 17 cm -3 The above 3 x 10 19 cm -3The following concentrations are present. The high-concentration region 17 has a higher p-type impurity concentration than the p-type well region 13 and a higher p-type impurity concentration than the p+-type impurity diffusion region 16. The high-concentration region 17 faces the surface 10a of the GaN substrate 10 and is in contact with the gate insulating film 21.

[0026] Since the source region 23 is formed by ion implantation, defects occur in and around the source region 23. The defect surface density in the high-concentration region 17 surrounding the source region 23 is also high. For example, the defect surface density in the high-concentration region 17 is higher than that of the impurity diffusion region 16. To give one example, the defect surface density in the high-concentration region 17 is 1 × 10⁻⁶. 15 cm -2 Therefore, the defect surface density in the impurity diffusion region 16 is 1 × 10⁻⁶. 15 cm -2 It is less than.

[0027] The gate insulating film 21 is, for example, an SiO2 film with a thickness of 100 nm. The gate electrode 22 is adjacent to the region where the channel is formed (hereinafter referred to as the channel region) via the gate insulating film 21. The gate electrode 22 faces the well region 13, the high-concentration region 17, and the source region 23 via the gate insulating film 21, with the high-concentration region 17 included in the channel region. The gate electrode 22 is made of polysilicon doped with metals such as Al, titanium (Ti), nickel (Ni), and tungsten (W), or impurities. Alternatively, the gate electrode 22 may be made of silicides such as WSi and NiSi.

[0028] The source electrode 25 is ohmic-connected to the source region 23, which is an n+-type layer, and the contact region 15, which is a p+-type layer. The drain electrode 26 is ohmic-connected to the other side of the n+-type GaN single crystal substrate 11 (i.e., the side opposite to the side in contact with the GaN layer 12).

[0029] The source electrode 25 and drain electrode 26 are made of Al or Al-Si alloy, Ni, Ni alloy, Ti-Al alloy, Ni-gold (Au) alloy, etc. The source electrode 25 may also have a barrier metal layer between it and the source region 23. The drain electrode 26 may also have a barrier metal layer between it and the n+ type GaN single crystal substrate 11. The barrier metal layer may be made of Ti (titanium).

[0030] In other words, the source electrode 25 and the drain electrode 26 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al-Si alloy layer. The source electrode 25 and the drain electrode 26 may be made of different materials or have different laminated structures. The source electrode 25 may also be an electrode that serves as a source pad (not shown), or it may be an electrode provided separately from the source pad. The drain electrode 26 may also be an electrode that serves as a drain pad (not shown), or it may be an electrode provided separately from the drain pad.

[0031] (Effects of Embodiment 1) As described above, the GaN semiconductor device 100 according to Embodiment 1 of the present disclosure comprises an n-type GaN substrate 10, a p-type well region 13 provided on the GaN substrate 10, an n-type source region 23 provided in the well region 13, a p+-type contact region 15 provided on the GaN substrate 10 at a position away from the source region 23, a p+-type impurity diffusion region 16 provided on the GaN substrate 10 at a position interposed between the contact region 15 and the source region 23, in contact with the contact region 15 and having a higher p-type impurity concentration than the well region 13, a p+-type high-concentration region 17 provided around the source region 23 and having a higher p-type impurity concentration than the well region 13, and a gate insulating film 21 provided on the surface 10a side of the GaN substrate 10. The contact region 15, the impurity diffusion region 16, the high-concentration region 17, and the source region 23 face the surface 10a of the GaN substrate 10. The gate insulating film 21 is in contact with the high-concentration region 17.

[0032] According to this, during the ion implantation process when forming the n+ type source region 23, defects are formed around the source region 23. In the heat treatment process, these defects act as guides for the diffusion of a second conductivity type impurity (e.g., Mg) from the p+ type contact region to the area around the source region 23, forming a p+ type high-concentration region 17 around the source region 23. Since the high-concentration region 17 is formed by Mg segregating into the defects formed around the source region 23, the high-concentration region 17 is formed with a narrower (tinier) width compared to the case where Mg is directly ion-implanted around the source region 23 to form the high-concentration region. For example, the high-concentration region 17 is formed with a narrow width of 30 nm to 70 nm, preferably 40 nm to 60 nm, and more preferably 45 nm to 55 nm. As a result, the vertical MOSFET 1 can raise the threshold while suppressing a decrease in channel mobility.

[0033] (Variation 1) Figure 4 is a cross-sectional view showing the configuration of a vertical MOSFET 1A according to a modification 1 of Embodiment 1 of the present disclosure. The GaN semiconductor device 100 according to Embodiment 1 of the present disclosure may include the vertical MOSFET 1A shown in Figure 4. For example, the GaN semiconductor device 100 includes a plurality of vertical MOSFETs 1A. The plurality of vertical MOSFETs 1A are repeatedly arranged in one direction (for example, in the X-axis direction). One vertical MOSFET 1A is a repeating unit structure, and these unit structures are arranged in a line in one direction.

[0034] In the vertical MOSFET 1A shown in Figure 4, the difference from the vertical MOSFET 1 shown in Figure 3 is that the vertical MOSFET 1A further includes a p+-type embedded well region 115 and a p+-type impurity diffusion region 116. In this modified example 1, the p+-type contact region 15 and the p+-type embedded well region 115 are examples of the "second well region" of this disclosure. The p+-type impurity diffusion regions 16 and 116 are examples of the "impurity diffusion regions" of this disclosure.

[0035] The embedded well region 115 is located in the GaN substrate 10 at a depth distance from the source region 23, and is located deeper from the surface 10a of the GaN substrate 10 than the well region 13. That is, the embedded well region 115 is located below the well region 13. The embedded well region 115 is, for example, a p+ type layer formed by ion implantation of p-type impurities such as Mg on the surface 10a side of the GaN substrate 10, and activation of the p-type impurities by heat treatment. Alternatively, the embedded well region 115 may be a p+ type GaN layer formed by epitaxial growth.

[0036] The embedded well region 115 contains Mg as a p-type impurity, with a concentration of 3 × 10⁻⁶. 17 cm -3 The above 3 x 10 19 cm -3 It contains the following concentrations, more preferably 3 × 10 18 cm -3 The above 1 x 10 19 cm -3 The following concentrations are included. The thickness of the embedded well region 115 is, for example, 10 nm to 2 μm. The thickness of the embedded well region 115 can be thick or thin, but a thinner thickness can reduce the number of defects generated by ion implantation.

[0037] The impurity diffusion region 116 is located in the well region 13 at a position in contact with the embedded well region 115, and interposed between the embedded well region 115 and the source region 23. The impurity diffusion region 116 is formed by the thermal diffusion of p-type impurities (e.g., Mg) from the embedded well region 115. For example, if Mg is used as the p-type impurity in the impurity diffusion region 116, then 3 × 10⁻¹⁶ of Mg will be formed. 17 cm -3 The above 3 x 10 19 cm -3 It contains the following concentrations. The Mg concentration in impurity diffusion region 116 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 19 cm -3The following is possible: The impurity diffusion region 116 has a higher concentration of p-type impurities than the p-type well region 13, and a lower concentration of p-type impurities than the p+-type embedded well region 115.

[0038] In this modified example 1, the p+-type high-concentration region 17 is located around the entire circumference of the source region 23 in the GaN substrate 10. The high-concentration region 17 is located between the impurity diffusion region 16 and the source region 23 in the horizontal direction parallel to the surface 10a of the GaN substrate 10 (e.g., the X-axis direction), and between the impurity diffusion region 116 and the source region 23 in the depth direction of the GaN substrate 10 (e.g., the Z-axis direction). The high-concentration region 17 is formed by thermal diffusion of Mg from the impurity diffusion regions 16 and 116, respectively. The high-concentration region 17 has a higher concentration of p-type impurities than the p+-type impurity diffusion regions 16 and 116.

[0039] This modified example 1 achieves the same effects as the embodiment 1 described above. Furthermore, when forming the high-concentration region 17, Mg is supplied to the area around the source region 23 not only from the horizontal direction but also from the vertical direction. For example, by heat treatment, Mg diffuses vertically from the p+-type embedded well region 115 to form a p+-type impurity diffusion region 116. Then, Mg further diffuses from the impurity diffusion region 116 to the area around the source region 23, and Mg segregates into defects (e.g., ion implantation defects) present in this area, forming the p+-type high-concentration region 17. Since Mg is supplied to the area around the source region 23 from both the horizontal and vertical directions, it becomes easier to further increase the concentration and homogenize the concentration of Mg in the high-concentration region 17.

[0040] The isolation distance (hereinafter referred to as distance A) between the source region 23 and the embedded well region 115, which serves as the Mg supply source, is, for example, 0.4 μm to 1 μm. On the other hand, the separation distance (hereinafter referred to as distance B) between the source region 23 and the contact region 15, which serves as the Mg supply source, is, for example, 0.2 μm to 0.8 μm. When the embedded well region 115 is formed by ion implantation, defects due to ion implantation occur between the source region 23 and the embedded well region 115. If there are defects in the GaN substrate 10, Mg tends to diffuse more easily than when there are no defects. For this reason, when the embedded well region 115 is formed by ion implantation, it is preferable to make distance A longer than distance B (distance A > distance B). This makes it easier to match the amount of Mg supplied from the embedded well region 115 to the source region 23 with the amount of Mg supplied from the contact region 15 to the source region 23. Further homogenization of the Mg concentration in the high-concentration region 17 can be expected.

[0041] (Modification 2) Figures 5 and 6 are a plan view and a cross-sectional view, respectively, showing the configuration of a vertical MOSFET 1B according to a modified example 2 of Embodiment 1 of this disclosure. The cross-sectional view in Figure 6 is obtained by cutting the plan view in Figure 5 along the line X6-X6'. The GaN semiconductor device 100 according to Embodiment 1 of this disclosure may include the vertical MOSFET 1B shown in Figure 5. For example, the GaN semiconductor device 100 includes a plurality of vertical MOSFETs 1B. The plurality of vertical MOSFETs 1B are repeatedly arranged in one direction (for example, in the X-axis direction). One vertical MOSFET 1B is a repeating unit structure, and these unit structures are arranged in a line in one direction.

[0042] In the vertical MOSFET 1B shown in Figure 5, the difference from the vertical MOSFET 1 shown in Figure 3 is that the vertical MOSFET 1B has a p+ type embedded well region 115 instead of a p+ type contact region 15, and a p+ type impurity diffusion region 116 instead of a p+ type impurity diffusion region 16. In this modified example 2, the p+ type embedded well region 115 is an example of the "second well region" of this disclosure, and the p+ type impurity diffusion region 116 is an example of the "impurity diffusion region" of this disclosure.

[0043] The configurations of the embedded well region 115 and the impurity diffusion region 116 are as described in the above-described modification 1. However, in this modification 2, the embedded well region 115 extends vertically from the inside of the GaN substrate 10 to the surface 10a at a position in the foreground or depth direction of Figure 6 (i.e., a position outside the X6-X6' line in Figure 5), and faces the surface 10a. At this position facing the surface 10a, the embedded well region 115 is in contact with the source electrode 25. The embedded well region 115 is also in contact with the well region 13. The well region 13 is connected to the source electrode 25 via the embedded well region 115.

[0044] The high-concentration region 17 is formed by heat treatment, which supplies Mg from the embedded well region 115 to the area around the source region 23 via the impurity diffusion region 116. The numerical range of the Mg concentration in the high-concentration region 17 is the same as the numerical range described in, for example, Embodiment 1 or Modification 1 above.

[0045] This modified example 2 achieves the same effects as the embodiment 1 described above. In this modified example 2, the p+ type region that contacts the source electrode 25 is the embedded well region 115, not the contact region 15. As shown in Figure 5, on the surface of the GaN substrate, the embedded well region 115 is adjacent to the source region 23 in the Y-axis direction, not the X-axis direction. This makes it possible to further reduce the size of the vertical MOSFET 1B in the X-axis direction and shorten the cell pitch.

[0046] (3) Modification example 3 Figure 7 is a cross-sectional view showing the configuration of the embedded well region 115 according to a modification 3 of Embodiment 1 of this disclosure. Note that the gate insulating film 21, gate electrode 22, source electrode 25, and drain electrode are not shown in Figure 7. As shown in Figure 7, the p+ type embedded well region 115 may be formed wider horizontally (for example, in the X-axis direction) than the source region 23. The embedded well region 115 may be formed wider so as to be in contact with the entire bottom of the well region 13. Such embodiments may be applied to the vertical MOSFET 1A shown in Figure 4 and the vertical MOSFET 1B shown in Figure 5, respectively.

[0047] Figure 8 is a graph showing the analysis results of impurity concentrations at positions along arrows A and B in Figure 7. The horizontal axis of Figure 8 represents the analysis depth (μm) from the surface 10a of the GaN substrate 10, and the vertical axis represents the impurity concentration (at%). at% means atomic percent. The discloser prepared the sample shown in Figure 7 and conducted an experiment to measure the Mg concentration and Si concentration at position A, and the Mg concentration at position B along arrow B.

[0048] The Mg and Si concentrations at the location along arrow A in Figure 7 are shown by lines a and b in Figure 8, respectively. In Figure 8, the intersection of lines a and b marks the boundary between the n+ type source region 23 and the p+ type high-concentration region 17. A peak P, where the Mg concentration is maximum, was observed near this boundary in the high-concentration region 17. This peak P is thought to have been caused by Mg segregation around the source region 23. On the other hand, at the location along arrow B, there is no source region 23, and therefore, no peak P was observed at a depth corresponding to the periphery of the source region 23.

[0049] (4) Modification 4 Figures 9 to 11 are plan views and cross-sectional views showing the configuration of a vertical MOSFET 1C according to a modification 4 of Embodiment 1 of this disclosure. Figure 10 shows a cross-section obtained by cutting the plan view of Figure 9 with the X10-X10' line parallel to the X-axis direction passing through the p+ type contact region 15. Figure 11 shows a cross-section obtained by cutting the plan view of Figure 9 with the X11-X11' line parallel to the X-axis direction passing through a region outside the contact region 15.

[0050] In the modified example 4 shown in Figures 9 to 11, the p+ type contact region 15 is positioned adjacent to the source region 23 in the horizontal direction (e.g., in the X-axis direction) via a p+ type impurity diffusion region 16. When forming the high-concentration region 17 around the source region 23, Mg is supplied from the contact region 15 to the source region 23 located in the X-axis direction, similar to the case of the vertical MOSFET 1 shown in Figure 3. For example, by heat treatment, Mg diffuses horizontally from the p+ type contact region 15 to form the p+ type impurity diffusion region 16. Then, Mg further diffuses from the impurity diffusion region 16 to the adjacent source region 23 in the X-axis direction, and Mg segregates into defects (e.g., ion implantation defects) present around the source region 23, forming the p+ type high-concentration region 17.

[0051] Modification 4 achieves the same effects as Embodiment 1 described above. Furthermore, according to Modification 4, by reducing the area of ​​the p+ type contact region 15, it is possible to reduce the area of ​​the parasitic diode formed by the p+ type contact region 15 and the n- type GaN layer 12 (e.g., the drift region), thereby reducing parasitic capacitance.

[0052] (5) Variation 5 Figures 12 to 15 are plan views and cross-sectional views showing the configuration of a vertical MOSFET 1D according to Modification 5 of Embodiment 1 of this disclosure. Figure 13 shows a cross-section obtained by cutting the plan view of Figure 12 with the X13-X13' line parallel to the X axis passing through the p+ type contact region 15. Figure 14 shows a cross-section obtained by cutting the plan view of Figure 12 with the X14-X14' line parallel to the X axis passing through the n+ type source region 23. Figure 15 shows a cross-section obtained by cutting the plan view of Figure 12 with the Y15-Y15' line parallel to the Y axis passing through the contact region 15 and the source region 23.

[0053] In the modified example 5 shown in FIGS. 12 to 15, the p+-type contact region 15 is arranged adjacent to the source region 23 in the horizontal direction (for example, the Y-axis direction) via the p+-type impurity diffusion region 16. When forming the high-concentration region 17 around the source region 23, Mg is supplied from the contact region 15 to the periphery of the source region 23 located in the Y-axis direction. For example, by heat treatment, Mg diffuses horizontally from the p+-type contact region 15 to form the p+-type impurity diffusion region 16. Then, Mg further diffuses from the impurity diffusion region 16 to the periphery of the source region 23 adjacent in the Y-axis direction, and Mg segregates to the defects (for example, ion implantation defects) existing around the source region 23 to form the p+-type high-concentration region 17.

[0054] The modified example 5 has the same effects as those of the above-described embodiment 1. Further, according to the modified example 5, it becomes easy to arrange the p+-type contact region 15 close to the n+-type source region 23.

[0055] For example, if the distance between the contact region 15 and the source region 23 in the Y-axis direction is t1, and the distance between the contact region 15 and the n-type GaN layer 12 (for example, the JFET region) in the X-axis direction is t2, then t1 < t2. By arranging the contact region 15 serving as the supply source of Mg between the source regions 23 in the Y-axis direction rather than in the JFET region, it becomes easy to reduce the diffusion distance of Mg from the contact region 15 to the high-concentration region 17, and it becomes possible to increase the Mg concentration of the high-concentration region 17.

[0056] <Embodiment 2> Next, as a method for manufacturing the GaN semiconductor device 100 according to the second embodiment of the present disclosure, the manufacturing method of the vertical MOSFET 1 shown in FIG. 3 will be described. The GaN semiconductor device 100 is manufactured by various devices such as a film forming device, a lithography device, an ion implantation device, a heat treatment device, and an etching device. Hereinafter, these devices will be collectively referred to as manufacturing devices.

[0057] Figures 16A to 16G are cross-sectional views showing a manufacturing method for a GaN semiconductor device 100 according to Embodiment 2 of the present disclosure, in order of steps. As shown in Figure 16A, the manufacturing apparatus ion-implants Mg as a p-type impurity into the region 13' where well regions are to be formed (hereinafter referred to as the well-forming region) on the GaN substrate 10. For example, the manufacturing apparatus forms a mask M1 on the surface 10a of the GaN substrate 10. The mask M1 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M1 has a shape that opens above the well-forming region 13' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M1 is formed. After ion implantation, the manufacturing apparatus removes the mask M1 from the GaN substrate 10.

[0058] In the ion implantation process shown in Figure 16A, the Mg concentration in the well formation region 13' is 1 × 10⁻¹⁶. 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 16A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0059] Next, as shown in Figure 16B, the manufacturing apparatus ion-implants Si as an n-type impurity into the region 23' where the source region is to be formed (hereinafter referred to as the source formation region) on the GaN substrate 10. For example, the manufacturing apparatus forms a mask M2 on the GaN substrate 10. The mask M2 is an SiO2 film or a photoresist. The mask M2 has a shape that opens above the source formation region 23' and covers the top of other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M2 has been formed. After ion implantation, the manufacturing apparatus removes the mask M2 from the GaN substrate 10.

[0060] In the ion implantation process shown in Figure 16B, the Si concentration in the source formation region 23' of the Si to be ion-implanted is 1 × 10⁻¹⁶ 19 cm -3The Si injection energy (acceleration voltage) and dose are set accordingly.

[0061] Next, as shown in Figure 16C, the manufacturing apparatus ion-implants Mg as a p-type impurity into the area 15' where the contact region is to be formed (hereinafter referred to as the contact formation region) on the GaN substrate 10. For example, the manufacturing apparatus forms a mask M3 on the surface 10a of the GaN substrate 10. The mask M3 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M3 has a shape that opens above the contact formation region 15' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M3 has been formed. After ion implantation, the manufacturing apparatus removes the mask M3 from the GaN substrate 10.

[0062] In the Mg ion implantation process shown in Figure 16C, the Mg concentration in the contact formation region 15' is 3 × 10⁻¹⁰. 19 cm -3 The Mg injection energy (acceleration voltage) and dose are set accordingly.

[0063] Next, as shown in Figure 16D, the manufacturing apparatus deposits a nitride film containing Al, such as an aluminum nitride (AlN) film 51, as a protective film on the surface 10a of the GaN substrate 10. The thickness of the AlN film 51 is, for example, 100 nm to 500 nm. The method for depositing the AlN film 51 is not particularly limited, but examples include the MOCVD (Metal Organic Chemical Vapor Deposition) method, sputtering method, ALD (Atomic Layer Deposition) method, or PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0064] Next, as shown in Figure 16E, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the AlN film 51. This heat treatment is, for example, a rapid heating treatment. The maximum temperature of this heat treatment is, for example, 1000°C to 1500°C, preferably 1200°C to 1400°C. The heat treatment time at the maximum temperature is, for example, 1 minute to 60 minutes, and the heat treatment atmosphere is, for example, N2.

[0065] This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming a p-type well region 13, an n+-type source region 23, and a p+-type contact region 15. Furthermore, this heat treatment causes Mg to diffuse from the p+-type contact region 15, forming a p+-type impurity diffusion region 16, and also forms a p+-type high-concentration region 17 around the source region 23.

[0066] This heat treatment can, to some extent, recover defects in the GaN substrate 10 caused by ion implantation. Furthermore, the AlN film 51 has the function of suppressing the release of nitrogen atoms from the GaN substrate 10 during heat treatment. Nitrogen vacancies are formed at the locations where nitrogen atoms are released from the GaN substrate 10. Since nitrogen vacancies can function as donor defects, the expression of p-type properties may be inhibited. Because the GaN substrate 10 is heat-treated while covered with the AlN film 51, the release of nitrogen atoms can be suppressed, and the expression of p-type properties can be prevented from being inhibited.

[0067] Furthermore, this heat treatment causes the Al contained in the AlN film 51 to diffuse from the AlN film 51 to the surface 10a of the GaN substrate 10 and its vicinity (for example, a range from the surface 10a to a depth of 50 nm, and more preferably a range from the surface 10a to a depth of 5 nm). As a result, at least a portion of the area where the well region 13 and the gate insulating film 21 are in contact contains Al. For example, the well region 13 is formed into a first region where Al is not added and a second region where Al is added. The second region is Al-added GaN, i.e., AlGaN.

[0068] A second region (AlGaN) containing added Al faces the surface 10a of the GaN substrate 10, with the first region (GaN) located beneath it. In the second region (AlGaN), the Al concentration is highest on the surface of the second region (i.e., the surface 10a of the GaN substrate 10), and decreases continuously or stepwise from surface 10a toward the first region. The Al concentration on the surface of the second region is, for example, between 5 at% and 30 at%. The presence of the second region (AlGaN) in the well region 13 allows for the formation of a three-dimensional channel within the crystal of the second region (AlGaN), so that the channel mobility approaches the bulk mobility, making it less likely for minority carriers (e.g., electrons) to be trapped. Further increases in channel mobility can be expected.

[0069] In this heat treatment, Al diffuses from the AlN film 51 to areas other than the well region 13, such as the contact region 15, the impurity diffusion region 16, the high-concentration region 17, and the source region 23. Therefore, Al is also added to the surface and vicinity of each of these regions. As shown in Figure 16F, after the heat treatment, the manufacturing apparatus removes the AlN film 51 from the GaN substrate 10.

[0070] Next, as shown in Figure 16G, the manufacturing apparatus forms a gate insulating film 21 on the surface 10a of the GaN substrate 10. For example, an SiO2 film is deposited as the gate insulating film 21 to a thickness of 100 nm.

[0071] Next, the manufacturing apparatus forms the gate electrode 22 and the source electrode 25. For example, a Ti film and an Al film are sequentially deposited on the surface 10a side of the GaN substrate 10 on which the gate insulating film 21 is formed, and these are patterned to form the gate electrode 22 and the source electrode 25. The manufacturing apparatus also forms the drain electrode 26 on the back surface 10b side of the GaN substrate 10. For example, a Ti film and an Al film are sequentially deposited on the back surface 10b side of the GaN substrate 10, and these are patterned to form the drain electrode 26. Through these steps, for example, the vertical MOSFET 1 shown in Figure 3 is completed.

[0072] As described above, the method for manufacturing a vertical MOSFET according to Embodiment 2 of the present disclosure includes the steps of: forming a p-type well region 13 on an n-type GaN substrate 10; ion implanting n-type impurities (e.g., Si) into the well region 13 to form an n+-type source region 23; forming a p+-type contact region 15 on the GaN substrate 10 at a position isolated from the source region 23 by the well region 13, in contact with the well region 13 and having a higher p-type impurity concentration (e.g., Mg concentration) than the well region 13; and subjecting the GaN substrate 10 including the well region 13, source region 23, and contact region 15 to heat treatment to diffuse Mg from the contact region 15 to the area around the source region 23, thereby forming a p+-type high-concentration region 17 around the source region 23 with a higher Mg concentration than the well region 13.

[0073] According to the above manufacturing method, ion implantation during the formation of the source region 23 creates defects around the source region 23. During the heat treatment process, Mg segregates in these defects, forming a p+-type high-concentration region 17. This makes it possible to form a narrow-width high-concentration region 17 in the channel region of the vertical MOSFET 1. By having a narrow-width high-concentration region 17, the vertical MOSFET 1 can suppress a decrease in channel mobility while increasing the threshold value.

[0074] <Embodiment 3> The vertical MOSFET according to the embodiment of this disclosure may include an AlGaN layer between the p-type well region and the gate insulating film. Embodiment 3 describes a method for manufacturing a vertical MOSFET including an AlGaN layer. Figures 17A and 17B are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 3 of this disclosure in order of steps. In Figure 17A, the steps up to the step of removing the AlN film 51 as a protective film from the GaN substrate 10 are the same as those described with reference to Figures 16A to 16F of Embodiment 2. In Embodiment 3, after removing the AlN film 51, as shown in Figure 17A, the manufacturing apparatus deposits a thin film of AlGaN layer 53 on the surface 10a of the GaN substrate 10. The method for depositing the AlGaN layer 53 is not particularly limited, but examples include atomic layer deposition (ALD), molecular beam epitaxy (MBE), or metal-organic vapor deposition (MOCVD). Instead of forming the AlGaN layer 53, the AlGaN layer 53 may be formed by heat-treating the GaN substrate 10 covered with the AlN film 51 so that the Al contained in the AlN film 51 diffuses to the surface 10a of the GaN substrate 10 and its vicinity. In either case, the thickness of the AlGaN layer 53 is, for example, 5 nm to 50 nm. The surface Al composition of the AlGaN layer 53 is, for example, 5 at% to 30 at%.

[0075] The subsequent steps are the same as those described with reference to Figure 16G of Embodiment 2. As shown in Figure 17B, the manufacturing apparatus forms a gate insulating film 21 and a gate electrode 22 on the AlGaN layer 53. For example, a Ti film and an Al film are sequentially deposited on the surface 10a side of the GaN substrate 10 on which the gate insulating film 21 is formed, and these are patterned to form the gate electrode 22 and the source electrode 25. The manufacturing apparatus also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. For example, a Ti film and an Al film are sequentially deposited on the back surface 10b side of the GaN substrate 10, and these are patterned to form the drain electrode 26. After these steps, the vertical MOSFET 1E according to Embodiment 2 is completed.

[0076] The vertical MOSFET 1E, like the vertical MOSFET 1 according to Embodiments 1 and 2, has a p+ type high-density region 17 surrounding an n+ type source region 23. Because the width of the high-density region 17 is narrow, the vertical MOSFET 1E can raise the threshold while suppressing a decrease in channel mobility. Furthermore, since embedded channels are formed at and near the interface between the surface 10a of the GaN substrate 10 and the AlGaN layer 53, surface scattering is reduced, and thus high mobility can be expected.

[0077] <Embodiment 4> The vertical MOSFET according to the embodiment of this disclosure may have n-type JFET regions between adjacent p-type well regions in the horizontal direction. Embodiment 4 describes a method for manufacturing a vertical MOSFET having JFET regions. Figures 18A to 18C are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 4 of this disclosure in order of steps. In Figure 18A, the steps up to ion implanting Mg as a p-type impurity into the well formation region 13' of the GaN substrate 10, ion implanting Si as an n-type impurity into the source formation region 23', and ion implanting Mg as a p-type impurity into the contact formation region 15' are the same as the steps described with reference to Figures 16A to 16C of Embodiment 2. After ion implanting Mg into the contact formation region 15', the manufacturing apparatus removes the mask M3 (see Figure 16C).

[0078] Next, as shown in Figure 18A, the manufacturing apparatus ion-implants Si as an n-type impurity into the region 55' where the JFET region is to be formed (hereinafter referred to as the JFET formation region) on the GaN substrate 10. For example, the manufacturing apparatus forms a mask M4 on the surface 10a of the GaN substrate 10. The mask M4 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M4 has a shape that opens above the JFET formation region 55' and covers above other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M4 has been formed. After ion implantation, the manufacturing apparatus removes the mask M4 from the GaN substrate 10.

[0079] In the ion implantation process shown in Figure 18A, the Si concentration in the JFET formation region 55' of the Si being ion-implanted is 3 × 10⁻¹⁶ 17 cm -3 The Si injection energy (acceleration voltage) and dose are set accordingly.

[0080] The subsequent steps are the same as those shown in Figure 16D and later of Embodiment 2. That is, as shown in Figure 18B, the manufacturing apparatus deposits a nitride film containing Al, such as an AlN film 51, as a protective film on the surface 10a of the GaN substrate 10. Next, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the AlN film 51. The maximum temperature for this heat treatment is, for example, 1000°C to 1500°C, preferably 1200°C to 1400°C. The heat treatment time at the maximum temperature is, for example, 1 minute to 60 minutes, and the heat treatment atmosphere is, for example, N2.

[0081] This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming a p-type well region 13, an n+-type source region 23, a p+-type contact region 15, and a p-type JFET region 55, as shown in Figure 18C. Furthermore, this heat treatment causes Mg to diffuse from the p+-type contact region 15, forming a p+-type impurity diffusion region 16, and also forms a p+-type high-concentration region 17 around the source region 23. This heat treatment also allows for some degree of recovery of defects caused by ion implantation in the GaN substrate 10. After the heat treatment, the manufacturing apparatus removes the AlN film 51 from the GaN substrate 10.

[0082] Next, the manufacturing apparatus forms a gate insulating film 21 on the surface 10a of the GaN substrate 10. Then, a gate electrode 22 and a source electrode 25 are formed on the surface 10a side of the GaN substrate 10. The manufacturing apparatus also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. After these steps, the vertical MOSFET 1F according to Embodiment 2 is completed.

[0083] The vertical MOSFET 1F, like the vertical MOSFET 1 according to Embodiments 1 and 2, has a p+-type high-concentration region 17 surrounding an n+-type source region 23. Because the width of the high-concentration region 17 is narrow, the vertical MOSFET 1F can raise the threshold while suppressing a decrease in channel mobility. Furthermore, the vertical MOSFET 1F has an n-type JFET region 55 sandwiched between two adjacent well regions 13 in the horizontal direction (e.g., the X-axis direction). The JFET region 55 has a higher n-type impurity concentration than the n-type GaN layer 12 (drift region) located between the JFET region 55 and the back surface 10b of the GaN substrate 10. As a result, the vertical MOSFET 1F can reduce the JFET resistance and thus reduce the on-resistance.

[0084] <Embodiment 5> Embodiment 5 describes a method for forming a high-concentration p+ region by diffusing Mg from a p+-type embedded well region 115 formed by epitaxial growth to the periphery of a source region 23. Figures 19A to 19E are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 5 of this disclosure in order of steps. In Figure 19A, the manufacturing apparatus epitaxially grows a p-type GaN layer 12, a p+-type GaN layer (i.e., an embedded well region) 115, and a p-type GaN layer 12 on an n+-type GaN single crystal substrate 11 in this order. The Mg concentration in the embedded well region 115 is, for example, 3 × 10⁻⁶. 19 cm -3 That is the case.

[0085] Next, as shown in Figure 19B, the manufacturing apparatus ion-implants Mg as a p-type impurity into the well-forming region 13' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M5 on the surface 10a of the GaN substrate 10. The mask M5 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M5 has a shape that opens above the well-forming region 13' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M5 has been formed.

[0086] In this example, Mg is ion-implanted into the GaN layer 12 located above the p+-type embedded well region 115. The Mg concentration in the well-forming region 13' is 1 × 10⁻¹⁶. 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 16B may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. After ion implantation, the manufacturing apparatus removes the mask M5 from the GaN substrate 10.

[0087] Next, as shown in Figure 19C, the manufacturing apparatus ion-implants Si as an n-type impurity into the source formation region 23' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M6 on the GaN substrate 10. The mask M6 is an SiO2 film or a photoresist. The mask M6 has a shape that opens above the source formation region 23' and covers the top of other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M6 is formed. In this example, the well formation region 13' is located in the GaN layer 12 above the embedded well formation region 115'. Si is ion-implanted into this well formation region 13'. After ion implantation, the manufacturing apparatus removes the mask M6 from the GaN substrate 10.

[0088] In the ion implantation process shown in Figure 19C, the Si concentration in the source formation region 23' of the Si to be ion-implanted is 1 × 10⁻¹⁶ 19 cm -3 The Si injection energy (acceleration voltage) and dose are set accordingly.

[0089] Next, as shown in Figure 19D, the manufacturing apparatus ion-implants Si as an n-type impurity into the JFET formation region 55' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M7 on the surface 10a of the GaN substrate 10. The mask M7 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M7 has a shape that opens above the JFET formation region 55' and covers the other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M7 has been formed. After ion implantation, the manufacturing apparatus removes the mask M7 from the GaN substrate 10.

[0090] In the ion implantation process shown in Figure 19D, the effective donor concentration of the Si to be ion-implanted is 1 × 10⁻¹⁶, obtained by offsetting the acceptor concentration from the donor concentration in the JFET formation region 55'. 17 cm -3 The Si injection energy (acceleration voltage) and dose are set accordingly. Furthermore, the Si injection energy (acceleration voltage) and dose are set so that the bottom of the JFET formation region 55' is below the bottom surface of the embedded well region 115 (i.e., the JFET formation region 55' penetrates the embedded well region 115 in the thickness direction).

[0091] The subsequent steps are the same as those shown in Figure 18B and later of Embodiment 2. Specifically, the manufacturing apparatus deposits an AlN film 51 as a protective film on the surface 10a of the GaN substrate 10. Next, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the AlN film 51. The maximum temperature for this heat treatment is, for example, 1000°C to 1500°C, preferably 1200°C to 1400°C. The heat treatment time at the maximum temperature is, for example, 1 minute to 60 minutes, and the heat treatment atmosphere is, for example, N2.

[0092] This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming a p-type well region 13, an n+-type source region 23, a p+-type contact region 15, and a p-type JFET region 55, as shown in Figure 19E. Furthermore, this heat treatment causes Mg to diffuse from the p+-type contact region 15, forming a p+-type impurity diffusion region 16, and also forms a p+-type high-concentration region 17 around the source region 23. This heat treatment also allows for some degree of recovery of defects caused by ion implantation in the GaN substrate 10. After the heat treatment, the manufacturing apparatus removes the AlN film 51 from the GaN substrate 10.

[0093] Next, the manufacturing apparatus forms a gate insulating film 21 on the surface 10a of the GaN substrate 10. Then, a gate electrode 22 and a source electrode 25 are formed on the surface 10a side of the GaN substrate 10. The manufacturing apparatus also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. After these steps, the vertical MOSFET 1G according to Embodiment 2 is completed.

[0094] The vertical MOSFET 1G, like the vertical MOSFET 1 according to Embodiment 1, has a p+-type high-concentration region 17 surrounding an n+-type source region 23. Because the width of the high-concentration region 17 is narrow, the vertical MOSFET 1G can raise the threshold while suppressing a decrease in channel mobility. Furthermore, in Embodiment 5, since the p+-type embedded well region 115 is formed by epitaxial growth, it is easier to control the thickness of the embedded well region 115 and the Mg concentration compared to when it is formed by ion implantation (see, for example, Figure 16A of Embodiment 2).

[0095] <Embodiment 6> Embodiment 6 describes a method for forming a high-concentration p+ type region by diffusing Mg from a p+ type embedded well region 115 formed by ion implantation to the periphery of a source region 23. Figures 20A to 20H are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 6 of this disclosure in order of steps. As shown in Figure 20A, the manufacturing apparatus ion implants Mg as a p-type impurity into the embedded well formation region 115' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M8 on the surface 10a of the GaN substrate 10. The mask M8 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M8 has a shape that opens above the embedded well formation region 115' and covers above other regions. The manufacturing apparatus ion implants Mg into the GaN substrate 10 on which the mask M8 is formed. After ion implantation, the manufacturing apparatus removes the mask M8 from the GaN substrate 10.

[0096] In the ion implantation process shown in Figure 20A, the Mg concentration in the embedded well formation region 115' is 1 × 10⁻¹⁶ for the Mg being implanted. 19 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 20A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0097] Next, as shown in Figure 20B, the manufacturing apparatus ion-implants Mg as a p-type impurity into the well-forming region 13'. For example, the manufacturing apparatus forms a mask M8 on the surface 10a of the GaN substrate 10. The mask M8 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M8 has a shape that opens above the well-forming region 13' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M8 is formed. After ion implantation, the manufacturing apparatus removes the mask M8 from the GaN substrate 10.

[0098] In the ion implantation process shown in Figure 20B, the Mg concentration in the well formation region 13' is 1 × 10⁻¹⁶. 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 20B may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0099] Next, as shown in Figure 20C, the manufacturing apparatus ion-implants Si as an n-type impurity into the source formation region 23' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M9 on the GaN substrate 10. The mask M9 is an SiO2 film or a photoresist. The mask M9 has a shape that opens above the source formation region 23' and covers the top of other regions. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M9 is formed. In this example, the well formation region 13' is located in the GaN layer 12 above the embedded well formation region 115'. Si is ion-implanted into this well formation region 13'. After ion implantation, the manufacturing apparatus removes the mask M6 from the GaN substrate 10.

[0100] In the ion implantation process shown in Figure 20C, the Si concentration in the source formation region 23' of the Si to be ion-implanted is 1 × 10⁻¹⁶. 19 cm -3 The Si injection energy (acceleration voltage) and dose are set accordingly.

[0101] Next, as shown in Figure 20D, the manufacturing apparatus ion-implants Mg as a p-type impurity into the contact formation region 15' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M10 on the surface 10a of the GaN substrate 10. The mask M10 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M10 has a shape that opens above the contact formation region 15' and covers the other areas. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M10 is formed. After ion implantation, the manufacturing apparatus removes the mask M10 from the GaN substrate 10.

[0102] In the ion implantation process shown in Figure 20D, the Mg concentration in the contact formation region 15' is 3 × 10⁻¹⁶. 19 cm -3 The Mg injection energy (acceleration voltage) and dose are set accordingly.

[0103] The subsequent steps are the same as those shown in Figure 16D and later of Embodiment 2. That is, as shown in Figure 20E, the manufacturing apparatus deposits an AlN film 51 as a protective film on the surface 10a of the GaN substrate 10. Next, as shown in Figure 20F, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the AlN film 51. The maximum temperature for this heat treatment is, for example, 1000°C to 1500°C, preferably 1200°C to 1400°C. The heat treatment time at the maximum temperature is, for example, 1 minute to 60 minutes, and the heat treatment atmosphere is, for example, N2.

[0104] This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming a p-type well region 13, an n+-type source region 23, a p+-type contact region 15, and a p+-type embedded well region 115. Furthermore, this heat treatment causes Mg to diffuse from the p+-type contact region 15 to form a p+-type impurity diffusion region 16, and Mg to diffuse from the p+-type embedded well region 115 to form a p+-type impurity diffusion region 116, forming a p+-type high-concentration region 17 around the source region 23. This heat treatment also allows for some degree of recovery of defects caused by ion implantation in the GaN substrate 10. After the heat treatment, as shown in Figure 20G, the manufacturing apparatus removes the AlN film 51 from the GaN substrate 10.

[0105] Next, as shown in Figure 20H, the manufacturing apparatus forms a gate insulating film 21 on the surface 10a of the GaN substrate 10. Then, a gate electrode 22 and a source electrode 25 are formed on the surface 10a side of the GaN substrate 10. The manufacturing apparatus also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. After these steps, the vertical MOSFET 1H according to Embodiment 2 is completed.

[0106] The vertical MOSFET 1H, like the vertical MOSFET 1 in Embodiments 1 and 2, has a p+ type high-concentration region 17 surrounding an n+ type source region 23. Because the width of the high-concentration region 17 is narrow, the vertical MOSFET 1H can raise the threshold while suppressing a decrease in channel mobility. Furthermore, in Embodiment 6, since Mg can be diffused from both the contact region 15 and the embedded well region 115 to the area around the source region 23, it becomes easier to further increase the concentration and uniformity of Mg in the high-concentration region 17.

[0107] <Embodiment 7> The vertical MOSFET according to the embodiments of this disclosure is not limited to a planar gate structure, but may also have a trench gate structure. Embodiment 7 describes a method for manufacturing a vertical MOSFET having a trench gate structure. Figures 21A to 21H are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 7 of this disclosure in order of steps. As shown in Figure 21A, the manufacturing apparatus ion-implants Mg as a p-type impurity into the well formation region 13' of the GaN substrate 10. For example, the manufacturing apparatus ion-implants Mg into the entire surface 10a side of the GaN substrate 10 where a mask is not formed.

[0108] In the ion implantation process shown in Figure 21A, the Mg concentration in the well formation region 13' is 1 × 10⁻¹⁶ for the Mg being implanted. 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 21A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions.

[0109] Next, as shown in Figure 21B, the manufacturing apparatus ion-implants Mg as a p-type impurity into the contact formation region 15' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M11 on the surface 10a of the GaN substrate 10. The mask M11 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M11 has a shape that opens above the contact formation region 15' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M11 has been formed. After ion implantation, the manufacturing apparatus removes the mask M11 from the GaN substrate 10.

[0110] In the ion implantation process shown in Figure 21B, the Mg concentration in the contact formation region 15' is 3 × 10⁻¹⁶. 19 cm -3 The Mg injection energy (acceleration voltage) and dose are set accordingly.

[0111] Next, as shown in Figure 21C, the manufacturing apparatus ion-implants Si as an n-type impurity into the source formation region 23' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M12 on the GaN substrate 10. The mask M12 is an SiO2 film or a photoresist. The mask M12 has a shape that opens above the source formation region 12' and covers the top of other regions. The mask M12 may also have a shape that opens above the region where the trench H (see Figure 21D), described later, is formed. The manufacturing apparatus ion-implants Si into the GaN substrate 10 on which the mask M12 is formed.

[0112] In the ion implantation process shown in Figure 21C, the Si concentration in the source formation region 23' of the Si to be ion-implanted is 1 × 10⁻¹⁶ 20 cm -3 The Si injection energy (acceleration voltage) and dose are set accordingly.

[0113] Next, as shown in Figure 21D, the manufacturing apparatus forms a trench H on the surface 10a side of the GaN substrate 10. For example, the manufacturing apparatus forms the trench H by partially removing the source formation region 23', the well formation region 13', and the n-type GaN layer 12 which becomes the drift region, in that order, using photolithography and etching techniques.

[0114] Next, as shown in Figure 21E, the manufacturing apparatus deposits a protective film, such as an AlN film 51, on the surface 10a side of the GaN substrate 10. In this example, the AlN film 51 is continuously deposited from the surface 10a of the GaN substrate 10 to the sides and bottom of the trench H. The thickness of the AlN film 51 is, for example, 100 nm to 500 nm. Similar to Embodiment 2, the method for depositing the AlN film 51 is not particularly limited, but examples include MOCVD, sputtering, ALD, or PECVD.

[0115] Next, as shown in Figure 21F, the manufacturing apparatus heat-treats the GaN substrate 10 covered with the AlN film 51. This heat treatment is, for example, a rapid heating treatment. The maximum temperature of this heat treatment is, for example, 1000°C to 1500°C, preferably 1200°C to 1400°C. The heat treatment time at the maximum temperature is, for example, 1 minute to 60 minutes, and the heat treatment atmosphere is, for example, N2.

[0116] This heat treatment activates the Mg and Si introduced into the GaN substrate 10, forming a p-type well region 13, an n+-type source region 23, and a p+-type contact region 15. Furthermore, this heat treatment causes Mg to diffuse from the p+-type contact region 15, forming a p+-type impurity diffusion region 16, and also forms a p+-type high-concentration region 17 around the source region 23.

[0117] This heat treatment can, to some extent, recover defects in the GaN substrate 10 caused by ion implantation. Furthermore, the AlN film 51 has the function of suppressing the release of nitrogen atoms from the GaN substrate 10 during heat treatment. Nitrogen vacancies are formed at the locations where nitrogen atoms are released from the GaN substrate 10. Since nitrogen vacancies can function as donor defects, the expression of p-type characteristics may be inhibited. Because the GaN substrate 10 is heat-treated while covered with the AlN film 51, the release of nitrogen atoms can be suppressed, and the expression of p-type characteristics can be prevented from being inhibited. As shown in Figure 21G, after heat treatment, the manufacturing apparatus removes the AlN film 51 from the GaN substrate 10.

[0118] Next, as shown in Figure 21H, the manufacturing apparatus forms a gate insulating film 21 on the surface 10a side of the GaN substrate 10. In this example, an AlN film 51 is continuously deposited from the surface 10a of the GaN substrate 10 to the side and bottom surfaces of the trench H. The gate insulating film 21 is, for example, an SiO2 film, and its thickness is 100 nm. As shown in Figure 21H, the thickness of the gate insulating film 21 may be thicker on the surface 10a of the GaN substrate 10 and thinner on the side and bottom surfaces of the trench H. In this case, the thickness of the portion of the gate insulating film 21 that covers the side and bottom surfaces of the trench H may be 100 nm.

[0119] Next, the manufacturing apparatus forms a gate electrode 22 on the gate insulating film 21. In this example, the gate electrode 22 is formed on the side and bottom surfaces of the trench H via the gate insulating film 21. For example, a Ti film and an Al film are sequentially deposited on the surface 10a side of the GaN substrate 10 on which the gate insulating film 21 is formed, and these are patterned to form the gate electrode 22 and source electrode 25. The manufacturing apparatus also forms a drain electrode 26 on the back surface 10b side of the GaN substrate 10. For example, a Ti film and an Al film are sequentially deposited on the back surface 10b side of the GaN substrate 10, and these are patterned to form the drain electrode 26. Through these steps, the vertical MOSFET 1I is completed.

[0120] The vertical MOSFET 1I, like the vertical MOSFET 1 according to Embodiments 1 and 2, has a p+ type high-concentration region 17 surrounding an n+ type source region 23. In the vertical MOSFET 1I, the well region 13, the high-concentration region 17, and the source region 23 face the side surface of the trench H. Within the trench H, the gate insulating film 21 is in contact with the high-concentration region 17, and the gate electrode 22 is provided within the trench H via the gate insulating film 21. The high-concentration region 17 is included in the channel region formed on the side surface of the trench H. Because the width of the high-concentration region 17 in contact with the gate insulating film 21 on the side surface of the trench H is narrow, the vertical MOSFET 1I can raise the threshold while suppressing a decrease in channel mobility. Furthermore, because the vertical MOSFET 1I has a trench gate structure, the cell pitch can be shortened compared to a planar gate structure, and on-resistance can be reduced by shortening the cell pitch.

[0121] <Embodiment 8> A vertical MOSFET according to the embodiments of this disclosure may have a drift region with an SJ (Super Junction) structure having a p-type column and an n-type column. Embodiment 8 describes a method for manufacturing a vertical MOSFET having an SJ structure drift region. Figures 22A to 22D are cross-sectional views showing the manufacturing method of a GaN semiconductor device 100 according to Embodiment 8 of this disclosure in order of steps. As shown in Figure 22A, the manufacturing apparatus ion-implants Mg as a p-type impurity into the region 61' of the GaN substrate 10 where a p-type column is to be formed (hereinafter referred to as the p-type column formation region). For example, the manufacturing apparatus forms a mask M13 on the surface 10a of the GaN substrate 10. The mask M13 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M13 has a shape that opens above the p-type column formation region 61' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M13 is formed. This ion implantation is performed by multi-stage ion implantation with multiple acceleration energy conditions. After ion implantation, the manufacturing apparatus removes the mask M13 from the GaN substrate 10.

[0122] Next, as shown in Figure 22B, the manufacturing apparatus epitaxially grows n-type GaN on the surface 10a of the GaN substrate 10 to create a thick GaN layer 12. Then, as shown in Figure 22C, the manufacturing apparatus ion-implants Mg as a p-type impurity into the well-forming region 13' of the GaN substrate 10. For example, the manufacturing apparatus forms a mask M14 on the surface 10a of the GaN substrate 10. The mask M14 is an SiO2 film or photoresist that can be selectively removed from the GaN substrate 10. The mask M14 has a shape that opens above the well-forming region 13' and covers above other regions. The manufacturing apparatus ion-implants Mg into the GaN substrate 10 on which the mask M14 is formed.

[0123] In this ion implantation process, the Mg concentration in the well formation region 13' is 1 × 10⁻⁶ 17 cm -3 The Mg implantation energy (acceleration voltage) and dose are set accordingly. The ion implantation process shown in Figure 16A may be performed as a single-stage ion implantation with one acceleration energy condition, or as a multi-stage ion implantation with multiple acceleration energy conditions. After ion implantation, the manufacturing apparatus removes the mask M14 from the GaN substrate 10.

[0124] The subsequent steps are the same as those shown in Figure 16B and later of Embodiment 2. The vertical MOSFET 1J shown in Figure 22D is completed through the same manufacturing process as described with reference to Figures 16B to 16G.

[0125] The vertical MOSFET 1J, like the vertical MOSFET 1 according to Embodiments 1 and 2, is equipped with a p+ type high-concentration region 17 surrounding an n+ type source region 23. Because the width of the high-concentration region 17 is narrow, the vertical MOSFET 1J can raise the threshold while suppressing a decrease in channel mobility.

[0126] Furthermore, the vertical MOSFET 1J has a p-type column 61 in the GaN layer 12, extending from the bottom of the well region 13 toward the back surface 10b of the GaN substrate 10. This allows for a higher impurity concentration in the n-type column 62 while suppressing a decrease in breakdown voltage, thereby reducing drift resistance. This makes it possible to reduce the on-resistance of the vertical MOSFET. It is possible to improve the breakdown voltage-impurity concentration trade-off in the drift region.

[0127] In Embodiment 8, as shown in Figure 22A, the p-type column 61 was formed by ion implantation, but the method of forming the p-type column 61 is not limited to this. Figure 23 is a cross-sectional view showing a modified example of the manufacturing method according to Embodiment 8 of this disclosure. As shown in Figure 23, the p-type column 61 may be formed by epitaxial growth. The p-type column 61 may be stacked in multiple stages by epitaxial growth. Even with such a method, the drift region of the SJ structure can be formed in the same way as in manufacturing method 7.

[0128] Furthermore, the vertical MOSFET 1J may have a p+ type embedded well region 115 at the bottom of the well region 13. In that case, the p-type column 61 may be provided from the bottom of at least one of the well region 13 and the embedded well region 115 toward the back surface 10b of the GaN substrate 10.

[0129] <Other Embodiments> As described above, this disclosure is based on embodiments 1 and 2 and their modifications, but the discussions and drawings that form part of this disclosure should not be understood as limiting this disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure. For example, the above embodiments and modifications describe the case in which Mg is used as the p-type impurity, but Be (beryllium) may also be used as the p-type impurity.

[0130] In the above embodiments, the p-type well region 13 and the embedded well region 113 were described as being formed by ion implantation or epitaxial growth (an example of atomic deposition), but these may also be formed by CVD (e.g., organic CVD including Mg) or sputtering (e.g., sputtering of p-type GaN). Furthermore, the gate insulating film 21 is not limited to Si oxides such as SiO2. The gate insulating film 21 may be Al oxide, or a mixture containing at least one of Si oxide and Al oxide.

[0131] In the above embodiments and modifications, the p-type impurity concentration (e.g., Mg concentration) may be interpreted as the effective p-type concentration (e.g., effective Mg concentration) obtained by offsetting n-type impurities from p-type impurities. Similarly, the n-type impurity concentration (e.g., Si concentration) may be interpreted as the effective n-type concentration (e.g., effective Si concentration) obtained by offsetting p-type impurities from n-type impurities.

[0132] Thus, this technology naturally includes various embodiments and modifications not described herein. Within the scope of the embodiments and modifications described above, at least one of various omissions, substitutions, and modifications of the components can be made. Furthermore, the effects described herein are merely illustrative and not limiting, and other effects may also exist.

[0133] Furthermore, this disclosure may also adopt the following structure. (1) A step of forming a first well region of a second conductivity type on a first conductivity type nitride semiconductor substrate, The process involves ion implanting a first conductivity type impurity into the first well region to form a first conductivity type source region, The process of forming a second well region of a second conductivity type in the nitride semiconductor substrate at a position isolated from the source region by the first well region, in contact with the first well region, and having a higher concentration of impurities of the second conductivity type than the first well region, A method for manufacturing a nitride semiconductor device, comprising the steps of: heat-treating the nitride semiconductor substrate including the first well region, the source region, and the second well region to diffuse a second conductivity type impurity from the second well region to the periphery of the source region, thereby forming a second conductivity type high-concentration region around the source region where the concentration of the second conductivity type impurity is higher than that of the first well region. (2) The method for manufacturing a nitride semiconductor device according to (1), wherein the maximum temperature of the heat treatment is 1200°C or more and 1400°C or less. (3) The method for manufacturing a nitride semiconductor device according to (1) or (2), wherein the heat treatment is performed with an AlN (aluminum nitride) film formed as a protective film on the surface of the nitride semiconductor substrate. (4) A method for manufacturing a nitride semiconductor device according to any one of (1) to (3), wherein at least one of the first well region and the second well region is formed by ion implantation, atomic deposition, CVD, or sputtering. (5) A method for manufacturing a nitride semiconductor device according to any one of (1) to (4), wherein the thickness of the second well region is 10 nm or more and 2 μm or less. (6) The concentration in the second well region is 3 × 10 17 cm -3 The above 3 x 10 19 cm -3 A method for manufacturing a nitride semiconductor device according to any one of the above items (1) to (5). (7) In the thickness direction of the nitride semiconductor substrate, the second well region is formed at a position adjacent to the source region via the first well region, A method for manufacturing a nitride semiconductor device according to any one of (1) to (6), wherein the isolation distance between the source region and the second well region is 0.4 μm or more and 1 μm or less. (8) In a direction intersecting the thickness direction of the nitride semiconductor substrate, the second well region is formed at a position adjacent to the source region via the first well region. A method for manufacturing a nitride semiconductor device according to any one of (1) to (7), wherein the isolation distance between the source region and the second well region is 0.2 μm or more and 0.8 μm or less. (9) A first-type conductive nitride semiconductor substrate, A first well region of the second conductivity type provided on the nitride semiconductor substrate, A first conductivity type source region provided in the first well region, In the nitride semiconductor substrate, a second well region of a second conductivity type is provided at a position away from the source region, and the impurity concentration of the second conductivity type is higher than that of the first well region. In the nitride semiconductor substrate, a second conductivity type impurity diffusion region is provided at a position interposed between the second well region and the source region, is in contact with the second well region, and has a higher concentration of second conductivity type impurities than the first well region, A high-concentration region of the second conductivity type is provided around the source region, and the impurity concentration of the second conductivity type is higher than that of the first well region. The nitride semiconductor substrate comprises a gate insulating film provided on the surface side, The second well region, the impurity diffusion region, the high-concentration region, and the source region face the surface of the nitride semiconductor substrate. The gate insulating film is in contact with the high-concentration region in a nitride semiconductor device. (10) The nitride semiconductor device according to (9), wherein the defect surface density in the high-concentration region is higher than the defect surface density in the impurity diffusion region. (11) The nitride semiconductor device according to (9) or (10), wherein the high-concentration region is provided all around the source region inside the nitride semiconductor substrate. (12) A nitride semiconductor device according to any one of (9) to (11), wherein Al (aluminum) is included in at least a portion of the region in contact with the first well region and the gate insulating film. (13) The nitride semiconductor device according to any one of (9) to (12), further comprising the first well region, the high-concentration region, and the source region, and a gate electrode facing the source region via the gate insulating film. (14) The nitride semiconductor substrate further comprises trenches provided on the surface side, The first well region, the high-concentration region, and the source region face the side surface of the trench. Within the trench, the gate insulating film is in contact with the high-concentration region. The nitride semiconductor device according to (13), wherein the gate electrode is provided in the trench via the gate insulating film. (15) The nitride semiconductor substrate is In a direction intersecting the thickness direction of the nitride semiconductor substrate, the JFET region of a first conductivity type is sandwiched between one adjacent first well region and the other adjacent first well region. The nitride semiconductor device according to any one of (9) to (14), wherein the JFET region has a higher concentration of first conductivity type impurities than the drift region of the first conductivity type located between the JFET region and the back surface of the nitride semiconductor substrate. (16) The nitride semiconductor device according to any one of (9) to (15), wherein the nitride semiconductor substrate has a column of second conductivity type provided from the bottom of at least one of the first well region and the second well region toward the back surface of the nitride semiconductor substrate. (17) The nitride semiconductor device according to any one of (9) to (16), wherein the gate insulating film is a silicon oxide, an aluminum oxide, or a mixture containing at least one of the silicon oxide and the aluminum oxide. [Explanation of symbols]

[0134] 1. 1A to 1J Vertical MOSFET 10 GaN substrates 10a surface 10b back side 11 GaN single crystal substrate 12 GaN layer 12 Source formation region 13 well area 13' Well-forming region 15 Contact Area 15' Contact formation region 16 Impurity Diffusion Region 17 High concentration area 21 Gate insulating film 22 Grid cells 23 Source Area 23' Source formation region 25 Source electrodes 26 Drain electrode 51 AlN film 53 AlGaN layer 55 JFET area 55´ JFET formation area 61 p-type column 61' p-type column formation region 62 n-type columns 62' n-type column formation region 100 GaN semiconductor device 115 Embedded well area 115' Embedding well formation region 116 Impurity diffusion region H Trench M1 to M14 Mask

Claims

1. A step of forming a first well region of a second conductivity type on a first conductivity type nitride semiconductor substrate, The process involves ion implanting an impurity of a first conductivity type into the first well region to form a source region of a first conductivity type, The process of forming a second well region of a second conductivity type at a position isolated from the source region by the first well region in the nitride semiconductor substrate, the second well region being in contact with the first well region and having a higher impurity concentration of the second conductivity type than the first well region, A method for manufacturing a nitride semiconductor device, comprising the steps of: heat-treating the nitride semiconductor substrate including the first well region, the source region, and the second well region to diffuse a second conductivity type impurity from the second well region to the periphery of the source region, thereby forming a second conductivity type high-concentration region around the source region where the concentration of the second conductivity type impurity is higher than that in the first well region.

2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the maximum temperature of the heat treatment is 1200°C or more and 1400°C or less.

3. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the heat treatment is performed with an AlN (aluminum nitride) film formed as a protective film on the surface of the nitride semiconductor substrate.

4. A method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein at least one of the first well region and the second well region is formed by ion implantation, atomic deposition, CVD, or sputtering.

5. The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the thickness of the second well region is 10 nm or more and 2 μm or less.

6. The concentration in the second well region is 3 × 10 １７ cm －３ The above 3 x 10 １９ cm －３ The method for manufacturing a nitride semiconductor device according to claim 1 or 2, as follows:

7. In the thickness direction of the nitride semiconductor substrate, the second well region is formed at a position adjacent to the source region via the first well region. A method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the isolation distance between the source region and the second well region is 0.4 μm or more and 1 μm or less.

8. In a direction intersecting the thickness direction of the nitride semiconductor substrate, the second well region is formed at a position adjacent to the source region via the first well region. A method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the isolation distance between the source region and the second well region is 0.2 μm or more and 0.8 μm or less.

9. A first-type conductivity nitride semiconductor substrate and A first well region of the second conductivity type provided on the nitride semiconductor substrate, A first conductivity type source region provided in the first well region, In the nitride semiconductor substrate, a second well region of a second conductivity type is provided at a position away from the source region, and the impurity concentration of the second conductivity type is higher than that of the first well region. In the nitride semiconductor substrate, a second conductivity type impurity diffusion region is provided at a position interposed between the second well region and the source region, is in contact with the second well region, and has a higher concentration of second conductivity type impurities than the first well region, A high-concentration region of the second conductivity type is provided around the source region, and the impurity concentration of the second conductivity type is higher than that of the first well region. The nitride semiconductor substrate comprises a gate insulating film provided on the surface side, The second well region, the impurity diffusion region, the high-concentration region, and the source region are facing the surface of the nitride semiconductor substrate. The gate insulating film is in contact with the high-concentration region in a nitride semiconductor device.

10. The nitride semiconductor device according to claim 9, wherein the defect surface density in the high-concentration region is higher than the defect surface density in the impurity diffusion region.

11. The nitride semiconductor device according to claim 9 or 10, wherein the high-concentration region is provided all around the source region within the nitride semiconductor substrate.

12. The nitride semiconductor device according to claim 9 or 10, wherein at least a portion of the region in contact with the first well region and the gate insulating film contains Al (aluminum).

13. The nitride semiconductor device according to claim 9 or 10, further comprising the first well region, the high-concentration region, and the source region, and a gate electrode facing the gate insulating film.

14. The nitride semiconductor substrate further comprises trenches provided on the surface side, The first well region, the high-concentration region, and the source region face the side surface of the trench. Within the trench, the gate insulating film is in contact with the high-concentration region. The nitride semiconductor device according to claim 13, wherein the gate electrode is provided in the trench via the gate insulating film.

15. The nitride semiconductor substrate is In a direction intersecting the thickness direction of the nitride semiconductor substrate, the JFET region of a first conductivity type is sandwiched between one adjacent first well region and the other adjacent first well region. The nitride semiconductor device according to claim 9 or 10, wherein the JFET region has a higher concentration of first conductivity type impurities than the first conductivity type drift region located between the JFET region and the back surface of the nitride semiconductor substrate.

16. The nitride semiconductor device according to claim 9 or 10, wherein the nitride semiconductor substrate has a column of second conductivity type provided from the bottom of at least one of the first well region and the second well region toward the back surface of the nitride semiconductor substrate.

17. The nitride semiconductor device according to claim 9 or 10, wherein the gate insulating film is a silicon (Si) oxide, an aluminum (Al) oxide, or a mixture containing at least one of the silicon oxide and the Al oxide.

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