Silicon carbide semiconductor equipment

Abstract

The present invention provides a silicon carbide semiconductor device that can reduce the contact resistance between the n-type semiconductor region, the p-type semiconductor region, and the metal layer. [Solution] The silicon carbide semiconductor device comprises a silicon carbide substrate having a first main surface in which an n-type semiconductor region and a p-type semiconductor region are exposed, a first metal layer containing titanium provided on the n-type semiconductor region, and a second metal layer containing nickel provided on the p-type semiconductor region.

Claims

1. A silicon carbide substrate having a first main surface in which an n-type semiconductor region and a p-type semiconductor region are exposed, A first metal layer containing titanium is provided on the aforementioned n-type semiconductor region, A second metal layer containing nickel is provided on the aforementioned p-type semiconductor region, A silicon carbide semiconductor device comprising the above features.

2. The first metal layer is mainly composed of titanium, The second metal layer is mainly composed of nickel, The silicon carbide semiconductor device according to claim 1.

3. The interlayer insulating film is provided on the first main surface, The interlayer insulating film includes a BPSG film and has openings that expose the n-type semiconductor region and the p-type semiconductor region. The silicon carbide semiconductor device according to claim 1.

4. A first transition layer is provided between the n-type semiconductor region and the first metal layer, and contains 90% or more titanium and 1% or more silicon. A second transition layer is provided between the p-type semiconductor region and the second metal layer, and contains 90% or more nickel and 1% or more silicon. Equipped with, The thickness of the first transition layer is 0 nm or more and 20 nm or less. The thickness of the second transition layer is 0 nm or more and 20 nm or less. A silicon carbide semiconductor device according to any one of claims 1 to 3.

5. The effective concentration of n-type impurities in the aforementioned n-type semiconductor region is 3 × 10⁻⁶ １９ cm －３ The above 3 x 10 ２０ cm －３ The following: The effective concentration of p-type impurities in the aforementioned p-type semiconductor region is 1 × 10⁻⁶ ２０ cm －３ The above 1 x 10 ２１ cm －３ The following is: A silicon carbide semiconductor device according to any one of claims 1 to 3.

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