Memory device, method for manufacturing a memory device

Abstract

To provide a storage device that can be manufactured at low cost. [Solution] A memory device having a vertical transistor and a vertical capacitive element. The vertical capacitive element is provided on top of the vertical transistor. The vertical transistor has a columnar gate electrode and a gate insulating layer covering the top and sides of the gate electrode. The lower electrode of the vertical transistor is provided on the gate insulating layer, and its top surface is lower than the top surface of the gate electrode. The semiconductor layer covers the gate electrode via the gate insulating layer and has a region in contact with the top surface of the lower electrode. An interlayer insulating layer having an opening that overlaps with the gate electrode is provided on the semiconductor layer. The upper electrode of the vertical transistor and one of the pair of electrodes of the vertical capacitive element are the same conductive layer, and the conductive layer is provided such that it has a region located inside the opening. The conductive layer has a region inside the opening that is in contact with the top surface of the semiconductor layer.

Claims

1. It comprises a transistor, a capacitive element, a first insulating layer, and a second insulating layer. The transistor has a first conductive layer, a second conductive layer, a third conductive layer, a third insulating layer, and a semiconductor layer. The capacitive element comprises the third conductive layer, the fourth conductive layer, and the fourth insulating layer. The first conductive layer is located on the first insulating layer, The third insulating layer is provided on the first insulating layer so as to cover the upper and side surfaces of the first conductive layer. The second conductive layer is located on the third insulating layer, The upper surface of the second conductive layer is lower than the upper surface of the first conductive layer. The semiconductor layer has a region in contact with the upper surface of the second conductive layer, a region in contact with the side surface of the third insulating layer, and a region in contact with the upper surface of the third insulating layer that overlaps with the first conductive layer. The second insulating layer has a region located on the semiconductor layer and a region in contact with the side surface of the semiconductor layer. The bottom surface of the second insulating layer is lower than the top surface of the second conductive layer. The second insulating layer has a first opening that overlaps with the first conductive layer, The third conductive layer has a region inside the first opening that is in contact with the upper surface of the semiconductor layer, The fourth insulating layer is provided such that it covers the third conductive layer and has a region located on the second insulating layer. A memory device wherein the fourth conductive layer is located on the fourth insulating layer and has a region facing the side surface of the third conductive layer with the fourth insulating layer in between.

2. In claim 1, The second conductive layer has a second opening, A memory device having regions located inside the second opening, wherein the first conductive layer and the third insulating layer are located inside the second opening.

3. In claim 1 or claim 2, It has a fifth conductive layer, The fifth conductive layer has a region in contact with the bottom surface of the first conductive layer, A memory device in which the angle between the side surface of the first conductive layer and the upper surface of the fifth conductive layer is 90 degrees or more.

4. In claim 3, The aforementioned angle is greater than 110 degrees for the memory device.

5. In claim 3, The second conductive layer extends in the first direction in a plan view, The fifth conductive layer extends in the second direction in the plan view, A storage device wherein the second direction is perpendicular or substantially perpendicular to the first direction.

6. In claim 1 or claim 2, A storage device having a region where the fourth insulating layer and the fourth conductive layer are located inside the first opening.

7. In claim 1 or claim 2, The aforementioned semiconductor layer is a crystalline oxide semiconductor containing indium and oxygen, in a memory device.

8. A first conductive layer is formed on the first insulating layer. A second insulating layer is formed so as to cover the upper and side surfaces of the first conductive layer. A second conductive layer is formed on the second insulating layer. By processing the second conductive layer, the upper surface of the second conductive layer is made lower than the upper surface of the first conductive layer. A semiconductor layer is formed on the second insulating layer such that it has a region in contact with the upper surface of the second conductive layer. A third insulating layer is formed such that it has a region in contact with the upper surface of the semiconductor layer and a region in contact with the side surface of the semiconductor layer. A first opening is formed in the third insulating layer, which overlaps with the first conductive layer and reaches the upper surface of the semiconductor layer. A third conductive layer is formed inside the first opening such that it has a region in contact with the upper surface of the semiconductor layer. A fourth insulating layer is formed so as to cover the third conductive layer. A method for manufacturing a memory device, comprising forming a fourth conductive layer on the fourth insulating layer such that it has a region facing the side surface of the third conductive layer with the fourth insulating layer in between.

9. In claim 8, The first conductive layer is formed by depositing a conductive film, forming a first resist mask on the conductive film to process the conductive film into a strip shape, removing the first resist mask, and then forming a second resist mask on the conductive film and the first insulating layer to process the conductive film into an island shape. The first resist mask is formed to extend in a first direction in a plan view, The second resist mask is formed to extend in a second direction in a plan view, A method for manufacturing a storage device, wherein the second direction is perpendicular or substantially perpendicular to the first direction.

10. In claim 8 or claim 9, Prior to the formation of the first conductive layer, a fifth conductive layer is formed on the first insulating layer. A sacrificial layer is formed on the fifth conductive layer described above. A second opening is formed in the sacrificial layer, reaching the upper surface of the fifth conductive layer, such that the angle between the side surface of the second opening in the sacrificial layer and the bottom of the second opening is greater than 90 degrees. The first conductive layer is formed to fill the second opening, A method for manufacturing a memory device, comprising removing the sacrificial layer and then forming the second insulating layer.

11. In claim 10, A method for manufacturing a memory device, comprising forming the second opening such that the angle is greater than 110 degrees.

12. In claim 10, The deposition of the second insulating layer and the semiconductor layer is carried out using the ALD method. A method for manufacturing a memory device, wherein the second conductive layer is formed using a sputtering method or a CVD method.

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