Wafer management methods

Abstract

To provide a novel wafer management method that can inspect the physical properties of packaged device chips. [Solution] The method includes an ID reading step of reading the ID 10 of wafer 2, a processing step of processing wafer 2 to divide it into individual device chips, a chip storage step of storing unused remaining chips 6a in a tray 38 equipped with an identification code 40 associated with the ID 10 read in the ID reading step, and an inspection step of taking out the tray 38 corresponding to the identification code 40 as needed and inspecting the remaining chips.

Description

Technical Field

[0001] The present invention relates to a method for managing wafers.

Background Art

[0002] A wafer on which a plurality of devices such as ICs and LSIs are partitioned by a dicing line and formed on the surface is thinned by grinding the back surface, and then divided into individual device chips by a dicing device or a laser processing device, and used in electrical devices such as mobile phones and personal computers.

[0003] Also, before the device chips are divided into individual device chips, they are classified into good products and defective products by electrical inspection, and the good device chips are used in electrical devices.

[0004] When a failure occurs in an electrical device, each device chip constituting the electrical device is inspected, and the manufacturing history of the device chip that caused the failure (that is, a series of processes from an ingot to a sliced wafer, double-sided grinding, patterning, back-surface grinding, dicing, chip sorting, packaging, and then incorporated into an electrical device) is traced and inspected, and improvement of the manufacturing process that caused the failure is required (for example, see Patent Document 1 below).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, when the failure is caused by physical characteristics including the flexural strength of the device chip, there is a problem that it is difficult to inspect the physical characteristics of the packaged device chip.

[0007] Therefore, there are issues that need to be addressed regarding wafer management methods. [Means for solving the problem]

[0008] According to the present invention, as a wafer management method that solves the above problems, a wafer management method is provided in which a plurality of devices are partitioned by division lines and formed on the surface, The ID reading process involves reading the ID of the wafer, A processing step in which wafers are processed and divided into individual device chips, A chip storage step involves storing unused chips in a tray equipped with an identification code linked to the ID read in the ID reading step, An inspection process in which, if necessary, the tray corresponding to the identification code is removed and the remaining chips are inspected, A wafer management method including the following is provided.

[0009] Preferably, the processing step includes a grinding step of thinning the back surface of the wafer by grinding it, a cutting step of dividing the wafer by cutting along the division line with a cutting blade, or a laser processing step of dividing the wafer by irradiating the division line with a laser beam. Preferably, the dividing step includes a frame unit forming step of forming a frame unit in which the wafer is placed in the opening of a frame having an opening in the center for accommodating the wafer, and the frame and wafer are integrated with tape. The tray is preferably made of a transparent material so that the remaining chips can be observed from all sides while they are placed in the tray. It is convenient to perform the ID reading step before the processing step. [Effects of the Invention]

[0010] The wafer management method according to the present invention is a method for managing a wafer on which multiple devices are partitioned by division lines and formed on the surface, and includes an ID reading step of reading the ID of the wafer, a processing step of processing the wafer to divide it into individual device chips, a chip storage step of storing unused remaining chips in trays equipped with identification codes linked to the IDs read in the ID reading step, and an inspection step of taking out the tray corresponding to the identification code as needed and inspecting the remaining chips. As a result, the manufacturing process information held by the remaining chips that were not used as device chips can be effectively utilized at any time, and for example, if a failure is due to physical characteristics including the flexural strength of the device chip, it is possible to apply stress to the remaining chips and measure the flexural strength, thus resolving the problem of difficulty in inspecting the physical characteristics of packaged device chips. [Brief explanation of the drawing]

[0011] [Figure 1] A perspective view showing a preferred embodiment of the ID reading step in a wafer management method configured according to the present invention. [Figure 2] A perspective view showing a step in the processing steps of a wafer management method configured according to the present invention, in which protective tape is applied to the surface of a wafer. [Figure 3] A perspective view showing a preferred embodiment of the grinding step in the processing steps of a wafer management method configured according to the present invention. [Figure 4] A perspective view showing a preferred embodiment of a frame unit formed in a processing step in a wafer management method configured according to the present invention. [Figure 5] A perspective view showing a preferred embodiment of a division step in a wafer management method configured according to the present invention. [Figure 6] Figure 5 is a perspective view showing the state after the splitting step has been completed and the required device chip has been removed from the frame. [Figure 7] A perspective view showing a preferred embodiment of a tray for storing remaining chips. [Figure 8] A diagram showing an example of information regarding the manufacturing history associated with an identification code arranged on a tray shown in FIG. 7. [Figure 9] A perspective view showing a preferred embodiment of a storage vault in which the tray shown in FIG. 7 is stored.

Embodiments for Carrying out the Invention

[0012] Hereinafter, a preferred embodiment of a wafer management method configured according to the present invention will be described in more detail with reference to the accompanying drawings.

[0013] The wafer management method configured according to the present invention includes an ID reading step, a processing step, a chip storage step, and an inspection step.

[0014] <ID Reading Step> In FIG. 1, a preferred embodiment of a wafer to which the wafer management method configured according to the present invention is applied is shown. This wafer, which is entirely designated by the number 2, can be formed from an appropriate semiconductor material such as silicon, for example. The wafer 2 is generally in the shape of a thin disk, and a notch 4 indicating the crystal orientation is locally formed on the outer peripheral surface. On the surface 2a of the wafer 2, a plurality of devices 6 such as ICs and LSIs are partitioned and formed by dicing lines 8. On the surface 2a of the wafer 2, an ID 10 such as a barcode indicating individual identification information is also arranged. In the illustrated embodiment, the ID 10 is arranged at the outer peripheral edge where the devices 6 are not formed and near the notch 4. FIG. 1 also shows an ID reader 12. The ID reader 12 is a device for reading the ID 10 formed on the surface 2a of the wafer 2. Since the ID reader 12 itself is a well-known device, a detailed description thereof will be omitted in this specification. In the ID reading step, the ID 10 of the wafer 2 is read by the ID reader 12. The ID reading step is preferably carried out before the processing step described below.

[0015] <Processing Step> In the processing step, the wafer 2 is processed and divided into individual device chips. In the illustrated embodiment, the processing step includes a grinding step and a dividing step, and the dividing step further includes a frame unit forming step.

[0016] <Grinding step of the processing step> As shown in FIG. 2, in the grinding step, first, a step of attaching a protective tape 14 to the surface 2a of the wafer 2 is performed. The protective tape 14 may be a well-known one. Thereafter, as shown in FIG. 3, the wafer 2 is held on the upper surface of the first holding means 16 via the protective tape 14 attached to the surface 2a, and the back surface 2b of the wafer 2 is exposed. Then, the back surface 2b of the wafer 2 is ground with a well-known grinding means 18 such as a grinder. The grinding means 18 includes a rotary spindle 20 rotated about a central axis extending in the Z-axis direction shown by an arrow Z in the figure by a rotary drive mechanism (not shown), a mount 22 attached to the lower end of the rotary spindle 20, a grinding wheel 24 attached to the lower surface of the mount 22, and a moving means (not shown) for moving the grinding wheel 24 in the vertical direction, that is, in the Z-axis direction. A plurality of grinding wheels 25 are annularly arranged on the lower surface of the grinding wheel 24. Then, the rotary drive mechanism and the moving means are operated to cause the grinding wheel 25 to act on the back surface 2b of the wafer 2 and grind the back surface 2b. The grinding conditions may be arbitrary. For example, while the first holding means 16 rotates at 300 rpm in the direction shown by an arrow R1 in the figure, the grinding means 18 contacts the grinding wheel 25 against the back surface 2b of the wafer 2 and rotates at 6000 rpm in the direction shown by an arrow R2 in the figure while grinding and feeding at 1.0 μm / s. Thus, the back surface 2b of the wafer 2 is ground by a required amount, and the wafer 2 is thinned.

[0017] <Dividing step of the processing step> In the splitting step, the frame unit formation process is performed first. Referring to Figure 4, the wafer 2 is housed in an opening in the center of the frame indicated by number 26. A tape 28 is placed in this opening, and the back surface 2b of the wafer 2 is adhered to the tape 28. After that, the protective tape 14 that was attached in the grinding step is peeled off. The frame unit 30 is formed by integrating the frame 26 and the wafer 2 with the tape 28.

[0018] Let's continue with a further explanation of the splitting step. The splitting step includes cutting or laser processing. Figure 5 shows a preferred embodiment in which cutting is performed using a well-known cutting means 32 such as a dicer as the splitting step. Referring to Figure 5, the frame unit 30 is held on the upper surface of a second holding means (not shown) with the surface 2a of the wafer 2 exposed. The second holding means includes a moving means for moving the frame unit 30 in the X-axis direction indicated by arrow X in the figure, and a rotating means for rotating it around a central axis extending in the Z-axis direction indicated by arrow Z in the figure. On the other hand, the cutting means 32 includes a spindle 34 that is rotated around a central axis extending in the Y-axis direction indicated by arrow Y in the figure by a rotational drive mechanism (not shown), an annular cutting blade 36 held at the tip of the spindle 34, and a moving means (not shown) for moving the cutting blade 36 in the Y-axis direction and the Z-axis direction indicated by arrow Z in the figure. Then, after performing appropriate alignment, the moving mechanism is activated to position the cutting blade 36 at the required position on the surface 2a of the wafer 2, and the rotational drive mechanism is activated to cause the cutting blade 36 to act on the division lines 8 on the surface 2a of the wafer 2, thereby cutting the division lines 8. By cutting all the division lines 8 in this manner, the wafer 2 is divided along the division lines 8, and thus a large number of device chips are generated. The device chips are removed from the frame 26 by any means and transported to the next process.

[0019] <Chip storage process> Figure 6 shows the state after the above splitting step has been completed and the required device chips have been removed from the frame 26. Only normal, or good, device chips are removed, and defective device chips and chips on the outer edge of the wafer 2 where device 6 was not formed (collectively referred to as "remaining chips" and denoted by reference numeral 6a) are left behind. In the chip storage process, the remaining chips 6a are stored in a tray 38. Figure 7 shows a preferred embodiment of the tray 38 for storing the remaining chips 6a. The tray 38 is equipped with an identification code 40 linked to the ID read in the ID reading process. The identification code 40 is linked to the manufacturing history of the wafer 2, that is, information such as the grinder and dicer used, as shown in Figure 8. This information is stored in an arbitrary information terminal such as a server (not shown). In the illustrated embodiment, the tray 38 is made of a transparent acrylic material. As shown in Figure 9, the tray 38 containing the remaining chips 6a is stored in a storage cabinet 42. The trays 38 stored in the storage unit 42 can be removed as needed from the retrieval opening 46 by operating the control panel 44 of the storage unit 42.

[0020] <Inspection Process> In the inspection process, if necessary, a tray 38 corresponding to the identification code 40 is taken out from the opening 46 of the storage unit 42 and the remaining chips 6a are inspected. In such inspections, the bending strength of the remaining chips 6a may also be tested using a bending strength test.

[0021] The wafer management method according to the present invention is a method for managing a wafer on which a plurality of device chips are partitioned by division lines and formed on the surface, and includes an ID reading step of reading the ID 10 of the wafer 2, a processing step of processing the wafer 2 to divide it into individual device chips, a chip storage step of storing the remaining chips 6a that were not used in a tray 38 equipped with an identification code 40 linked to the ID 10 read in the ID reading step, and an inspection step of taking out the tray 38 corresponding to the identification code 40 as needed and inspecting the remaining chips 6a. As a result, the manufacturing process information held by the remaining chips 6a that were not used as device chips can be effectively utilized at any time, and for example, if a failure is due to physical characteristics including the flexural strength of the device chip, it is possible to apply stress to the remaining chips 6a and measure the flexural strength, thus resolving the problem of difficulty in inspecting the physical characteristics of packaged device chips. In the illustrated embodiment, since the tray 38 is made of a transparent material, the cross-section and thickness of the remaining chips 6a can be observed from the outside of the tray 38 without directly touching them with fingers. If, based on the results of such observations, it is presumed that the above-mentioned failure is caused by a processing means such as a grinding means (grinder) or a cutting means (dicer), the processing means such as a grinding means (grinder) or a cutting means (dicer) that processed the device chip in which the failure occurred can also be identified from the information linked to the identification code 40.

[0022] Although a wafer management method configured according to the present invention has been described in detail above with reference to the attached drawings, the present invention is not limited to the embodiments described above, and appropriate modifications and changes can be made without departing from the present invention. In the embodiments described above, the processing process included a grinding step, but this may be omitted. The ID reading step may be performed immediately before the splitting step is carried out in the processing process, that is, the ID reader 12 may read the ID 10 of the wafer 2 attached to the frame unit 30. [Explanation of symbols]

[0023] 2: Wafer 6: Devices 6a: Remaining chips 8: Planned division line 10:ID 12: ID Leader 38: Tray 40: Identification code

Claims

1. A method for managing a wafer in which multiple devices are partitioned by division lines and formed on the surface, The ID reading process involves reading the ID of the wafer, A processing step in which wafers are processed and divided into individual device chips, A chip storage step involves storing unused chips in a tray equipped with an identification code linked to the ID read in the ID reading step, An inspection process in which, if necessary, the tray corresponding to the identification code is removed and the remaining chips are inspected, A method for managing wafers, including [specific data / features].

2. The processing step is, Grinding step to thin the back surface of the wafer, A division step including a cutting process in which the division line is cut with a cutting blade to divide it, or a laser process in which a laser beam is irradiated onto the division line to divide it, A wafer management method according to claim 1, comprising:

3. The wafer management method according to claim 2, further comprising a frame unit forming step in which, in the dividing step, a wafer is placed in the opening of a frame having an opening in the center for accommodating a wafer, and the frame and wafer are integrated with tape to form a frame unit.

4. The wafer management method according to claim 1, wherein the tray is made of a transparent material, and the remaining chips can be observed from all sides while contained in the tray.

5. The wafer management method according to claim 1, wherein the ID reading step is performed before the processing step.

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