Semiconductor equipment

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor device includes a plurality of pads 11, a plurality of rewirings 21 connected to the plurality of pads 11, terminals provided on the land portion of each of the plurality of rewirings 21, and conductive films connected to the terminals and the land portions, respectively. The plurality of rewirings 21 include rewirings 21A having a land portion 2L1 and rewirings 21B having a wiring portion 2E2. The planar shape of the conductive film is circular. The planar shape of the land portion 2L1 is non-circular. In plan view, the land portion 2L1 is arranged adjacent to the wiring portion 2E2 extending in the Y direction and has a side L1S1 that extends linearly in the Y direction along the wiring portion 2E2.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] There is a semiconductor device in which pads provided at the peripheral portion of a semiconductor chip are connected to solder balls via rewiring (Japanese Unexamined Patent Application Publication No. 2010-278040 (Patent Document 1)). In the case of the semiconductor device described in Patent Document 1, the layout of a plurality of solder balls is in a lattice pattern. Further, there is a semiconductor device in which a conductor layer is disposed between the land portion of the rewiring and the solder ball (Japanese Unexamined Patent Application Publication No. 2017-183571 (Patent Document 2)). Further, when the number of terminals of a semiconductor device increases, a plurality of rewirings may be disposed between adjacent terminals (Japanese Unexamined Patent Application Publication No. 2012-191123 (Patent Document 3)).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

[0006] A semiconductor device according to one embodiment includes a plurality of pads, a plurality of rewirings connected to the plurality of pads, terminals provided on land portions of each of the plurality of rewirings, and conductive films connected to each of the terminals and land portions. The plurality of rewirings include a first rewiring having a first land portion and a second rewiring having a second wiring portion. The planar shape of the conductive film is circular. The planar shape of the first land portion is non-circular. In plan view, the first land portion is arranged adjacent to the second wiring portion extending in a first direction and has a first side extending linearly along the second wiring portion. [Effects of the Invention]

[0007] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of the mounting surface of a semiconductor device, which is one embodiment of the device. [Figure 2] This is a cross-sectional view of line AA in Figure 1. [Figure 3] This is an enlarged plan view of section B shown in Figure 1. [Figure 4] Figure 3 is an enlarged cross-sectional view of the CC line. [Figure 5] This is an enlarged plan view showing a modified version of Figure 3. [Figure 6] This is an enlarged plan view showing another variation of Figure 3. [Figure 7] This is an enlarged plan view showing the region shown in Figure 3 and its surrounding areas. [Figure 8] Figure 7 is an enlarged cross-sectional view of the DD line. [Figure 9]Figure 3 is an enlarged plan view showing the outlines of the conductor layer and solder balls placed on the land area. [Modes for carrying out the invention]

[0009] (Explanation of format, basic terminology, and usage in this application) In this application, the descriptions of the embodiments are divided into multiple sections for convenience. These are not independent of each other, but rather one is a detail of the other, or one is a variation of the other. In principle, similar parts will be omitted from repeated explanations. Furthermore, each component in the embodiments is not essential unless it is explicitly indicated as an essential component, its number is theoretically limited to that, or it is clearly essential from the context.

[0010] Similarly, in descriptions of the implementation, etc., even if it says "X consisting of A" regarding materials, composition, etc., unless it is clearly limited or clearly limited from the context, elements other than A are not excluded. For example, in terms of components, it means "X containing A as the main component." For example, even if it says "silicon component," it is not limited to pure silicon, but also includes components containing SiGe (silicon-germanium) alloys, other multi-component alloys with silicon as the main component, and other additives. Also, even if it says gold plating, Cu layer, nickel plating, etc., unless it is specifically stated otherwise, it is meant to include not only pure materials but also components with gold, Cu, nickel, etc. as the main components, respectively.

[0011] Furthermore, when specific numbers or quantities are mentioned, unless explicitly limited or clearly limited by the context, those numbers are listed as examples only.

[0012] Furthermore, in each figure of the embodiment, identical or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions are generally not repeated.

[0013] In the accompanying drawings, conversely, in cases where it becomes complicated or the distinction from voids is clear, hatching or the like may be omitted even for cross-sections. In relation to this, in cases where it is clear from the description or the like, even for holes that are planar and closed, the background contour lines may be omitted. Further, even if it is not a cross-section, hatching or dot patterns may be added to clarify that it is not a void or to clarify the boundary of a region.

[0014] <Semiconductor device> First, the semiconductor device of the present embodiment will be described. FIG. 1 is a plan view of the mounting surface of the semiconductor device of the present embodiment. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 3 is an enlarged plan view showing an example of rewiring in portion B shown in FIG. 1. In FIG. 3, the contour of pad 11 is shown by a dotted line. FIG. 4 is an enlarged cross-sectional view taken along line C-C of FIG. 3.

[0015] In FIGS. 1 to 3, any one of the X direction (see FIGS. 1 to 3), Y direction (see FIGS. 1 and 3), and Z direction (see FIG. 2) is described. The Y direction is a direction that intersects the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is the normal direction (or the perpendicular direction) with respect to the X-Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means a plan view seen from the X-Y plane.

[0016] In the present embodiment, a semiconductor device applying a rewiring technique in which a rewiring layer is formed on a semiconductor chip to provide terminals at positions different from the electrode pads of the semiconductor chip in a plan view will be described. As an example of this, a semiconductor package called WPP or WLCSP will be taken up and described.

[0017] The semiconductor device PKG1 shown in FIG. 1 has a main surface PMSt and a main surface PMSb (see FIG. 2) located opposite to the main surface PMSt. In plan view, the main surface PMSt forms a quadrilateral. Specifically, the main surface PMSt includes a side PS1 extending in the X direction, a side PS2 located opposite to the side PS1, a side PS3 extending in the Y direction intersecting the X direction, and a side PS4 located opposite to the side PS3. The side PS1 intersects each of the side PS3 and the side PS4, and the side PS2 intersects each of the side PS3 and the side PS4.

[0018] The semiconductor device PKG1 has a plurality of terminals (external terminals, bump electrodes) SB arranged on the main surface PMSt. In the case of this embodiment, each of the plurality of terminals SB is a solder ball made of a solder material formed in a ball shape. In the semiconductor device PKG1, although a solder ball is taken as an example of the terminal SB for explanation, there are various modifications to the structure of the terminal SB. For example, a columnar conductor (pillar bump) formed in a columnar shape may be used. In the case of a columnar conductor, for example, a solder layer is laminated on the tip of a columnar conductor mainly composed of copper (Cu).

[0019] Also, in the example shown in FIG. 1, the plurality of terminals SB are arranged along the X direction and the Y direction. A semiconductor device in which a plurality of external terminals are arranged on the main surface PMSt, such as the semiconductor device PKG1, is called an area array type semiconductor device. The area array type semiconductor device is mounted in a state where the main surface PMSt faces the mounting surface of a mounting substrate not shown. In this case, the mounting area of the semiconductor device can be reduced, and the number of terminals can be increased.

[0020] In the example shown in FIG. 1, the semiconductor device PKG1 has a total of 64 terminals SB arranged in 8 rows × 8 columns. However, the number of terminals SB is not limited to 64, and there are various modifications. Also, regarding the number of arrangements, there are various modifications in addition to the aspect shown in FIG. 1. Although not shown, for example, there may be a case where there are a total of 90 terminals SB arranged in 10 rows × 9 columns, or a number of terminals SB more than that.

[0021] As shown in Figure 2, the semiconductor device PKG1 includes a semiconductor chip 10 and a rewiring section 20 formed on the semiconductor chip 10. The semiconductor chip 10 includes a plurality of semiconductor elements, such as transistors and diodes, and a plurality of pads 11 (see Figure 4) electrically connected to the plurality of semiconductor elements. The rewiring section 20 is positioned between a plurality of terminals SB and the semiconductor chip 10 and includes rewiring 21 (see Figure 4) that electrically connects the semiconductor chip 10 and the terminals SB. In a plan view, the semiconductor device PKG1 having the rewiring section 20 allows the terminals SB to be positioned at different locations from the pads 11 of the semiconductor chip 10.

[0022] As in this embodiment, in a semiconductor device in which a redistribution section 20 is arranged on a semiconductor chip 10, the redistribution section 20 is formed in the wafer process before the semiconductor wafer is diced to obtain the semiconductor chip. For this reason, it is called a WPP (Wafer Process Package). Furthermore, the semiconductor device in this embodiment is obtained by dicing the semiconductor wafer on which the redistribution section has been formed. In this case, the planar size of the semiconductor device PKG1 is approximately the same as the planar size of the semiconductor chip 10. A package in which the planar size of the semiconductor device and the planar size of the semiconductor chip are approximately the same is called a WLCSP (Wafer Level Chip Scale Package).

[0023] WLCSPs are semiconductor devices that have the advantage of a small planar size, or in other words, a small mounting area. Therefore, even if the number of terminals on a WLCSP increases as the functionality of semiconductor devices increases, it is necessary to suppress the corresponding increase in the planar size of the WLCSP. Accordingly, a technology is needed to improve the arrangement density of conductor patterns in the redistribution section of a WLCSP.

[0024] The semiconductor chip 10 shown in Figure 4 has a semiconductor substrate 12 made of a semiconductor material such as silicon (Si). The semiconductor substrate 12 is the base material for the semiconductor chip 10 and the semiconductor device package 1. The semiconductor substrate 12 also has a semiconductor element formation surface (main surface) 12t, on which the above-mentioned semiconductor elements are formed. Although not shown in Figure 4, the semiconductor substrate 12 also has a main surface opposite to the semiconductor element formation surface 12t. The main surface opposite to the semiconductor element formation surface 12t is the same surface as the main surface PMSb shown in Figure 2.

[0025] On the semiconductor element formation surface 12t, wiring layers (chip wiring layers) 13 and insulating films 14 are alternately stacked. The wiring layers 13 are made of, for example, copper or a copper alloy mainly composed of copper. The insulating films 14 are insulating films (inorganic insulating films) made of inorganic insulating materials such as silicon dioxide (SiO2).

[0026] The wiring layer 13 is electrically connected to the semiconductor element formation surface 12t of the semiconductor substrate 12 via a plug 13P. The wiring layer 13 is also electrically connected to the pads (electrode pads) 11 via via wiring 13V. In other words, the wiring layer 13 is a conductive path for electrically connecting the semiconductor elements formed on the semiconductor element formation surface 12t to the pads 11. Note that the wiring layer 13 and the insulating film 14 are not limited to a single layer; multiple wiring layers 13 and multiple insulating films 14 may be alternately stacked.

[0027] Each of the multiple pads 11 of the semiconductor chip 10 is formed on an insulating film 14 (or the uppermost insulating film 14 if multiple layers are stacked). The pads 11 are made of, for example, aluminum. Considering the versatility of the semiconductor chip 10, it is preferable that, for example, wires (not shown) can be bonded to the pads 11 for use. When wires are bonded, it is preferable that the pads 11 are made of aluminum.

[0028] Each of the multiple pads 11 formed on the main surface 13t of the wiring layer 13 is made of aluminum. An insulating film 15 is also formed on the main surface 13t. The insulating film 15 is an insulating film (passivation film) that protects the main surface 13t (of the wiring layer 13) of the semiconductor chip 10. The insulating film 15 is an inorganic insulating film made of an inorganic insulating material such as silicon oxide (SiO2) or silicon nitride (SiN), or a laminate of these.

[0029] The insulating film 15 overlaps the peripheral edge of the pad 11. An opening is formed in the insulating film 15. The central part of the pad 11 is exposed from the insulating film 15 at the opening. The portion of the pad 11 exposed from the insulating film 15 functions as a terminal of the semiconductor chip 10. For example, in this embodiment, the portion of the pad 11 exposed from the insulating film 15 is connected to the contact portion 2C1 of the rewiring 21.

[0030] Furthermore, as shown in Figure 3, the multiple pads 11 are arranged along the edges of the periphery of the main surface PMSt. In the example shown in Figure 3, the multiple pads 11 are arranged along edge PS2. Although not shown, in the case of semiconductor device PKG1, the multiple pads 11 (see Figure 3) are arranged along each of the edges PS2, PS3, and PS4 shown in Figure 1. However, in some cases, the pads 11 may be arranged along only some of the edges PS1, PS2, PS3, and PS4 shown in Figure 1.

[0031] The main circuitry (core circuitry) of the semiconductor chip 10 is positioned in a location that overlaps with the central region of the main surface PMSt shown in Figure 1. On the other hand, the input / output circuitry, which includes multiple pads 11, is positioned in a location that overlaps with the peripheral region of the main surface PMSt. In the case of the semiconductor device PKG1, each of the multiple terminals SB is arranged in a region inside the multiple pads 11 in a plan view. However, as a modified example, some of the multiple terminals SB may be positioned in a location that overlaps with the pads 11, or outside the pads 11.

[0032] In this embodiment, the multiple pads 11 are arranged only in the peripheral region of the main surface PMSt. By connecting rewiring 21 (see Figure 3) to each of the multiple pads 11, the multiple terminals SB provided by the semiconductor device PKG1 can be arranged in a grid pattern. The rewiring section 20 (see Figure 4) is a component for positioning the terminals SB at a different location from the position of the pads 11 on the semiconductor chip 10 in a plan view.

[0033] As shown in Figure 4, terminal SB and pad 11 are electrically connected via rewiring 21 of rewiring section 20. Rewiring section 20 includes rewiring 21, insulating film 22 formed on insulating film 15 of semiconductor chip 10, and insulating film 23 formed on insulating film 22. Rewiring 21 is formed on insulating film 22. However, a portion of contact portion 2C1 of rewiring 21 is connected to pad 11 without going through insulating film 22. Also, rewiring 21 is covered by insulating film 23.

[0034] Terminal SB is provided on the land portion 2L1 of the rewiring 21 via a conductive film (underbump metal, conductive layer) UBM. The conductive film UBM is formed between terminal SB and land portion 2L1 and is connected to terminal SB and land portion 2L1, respectively.

[0035] The rewiring 21 is a metal pattern made of, for example, copper or a copper alloy. The rewiring 21 consists of, for example, a metal film laminated on a seed layer (not shown) formed on an insulating film 22. In Figure 4, the laminate of the seed layer and the metal film described above is shown as the rewiring 21.

[0036] As described above, the conductive film UBM is an intermediate layer placed between the terminal SB and the land portion 2L1. By using a material with higher solderability than the land portion 2L1 as the conductive film UBM, the connection reliability between the terminal SB and the rewiring 21 can be improved.

[0037] Furthermore, by using a material with high solder barrier properties as the conductive film UBM, the diffusion of solder from the terminal SB can be suppressed. Examples of metals that constitute a conductive film UBM with the above characteristics include nickel or gold. In addition, the conductive film UBM may be a laminated film of multiple metal films.

[0038] The insulating film 22 constitutes the underlying layer of the rewiring 21. It is made of an organic material with a lower dielectric constant than the insulating film 15, which is made of an inorganic material. In this embodiment, the insulating film 22 is made of, for example, a polyimide resin. By using an organic insulating film as the insulating film 22, the parasitic capacitance formed between the rewiring 21 and the wiring layer 13 can be reduced.

[0039] The insulating film 22 has an opening 22H that penetrates the insulating film 22 in the thickness direction. The contact portion 2C1 of the rewiring 21 is embedded in the opening 22H. The opening 22H is formed on the pad 11. A portion of the pad 11 is exposed from the insulating film 22 at the opening 22H. This configuration allows the contact portion 2C1 and the pad 11 to be electrically connected.

[0040] The insulating film 23 is formed to cover the rewiring 21 and functions as a protective film to protect the rewiring 21. The insulating film 23 is made of an organic insulating film, such as a polyimide film. The insulating film 23 has the main surface PMSt of the semiconductor device PKG1. By making the insulating film 23 an organic insulating film, the adhesion to the insulating film 22 can be improved.

[0041] Furthermore, the insulating film 23 has an opening 23H that penetrates the insulating film 23 in the thickness direction. The conductive film UBM is embedded in the opening 23H. The opening 23H is also formed on the land portion 2L of the rewiring 21. A portion of the land portion 2L is exposed from the insulating film 23 at the opening 23H. This configuration allows the conductive film UBM and the land portion 2L to be electrically connected.

[0042] As shown in Figure 3, the rewiring 21A has a contact portion 2C1 electrically connected to the pad 11. The rewiring 21A has a land portion 2L1 connected to the terminal SB via a conductive film UBM. The rewiring 21A also has a wiring portion 2E1 connecting the contact portion 2C1 and the land portion 2L1.

[0043] As shown in Figure 4, the contact portion 2C1 is located on the pad 11. The land portion 2L1 is the portion for connecting terminal SB and is located away from the contact portion 2C1. As shown in Figure 3, the wiring portion 2E1 is the portion routed to connect the contact portion 2C1 and the land portion 2L1. The wiring portion 2E1 is an extended portion patterned in a strip shape.

[0044] Furthermore, as shown in Figure 3, the rewiring 21B has a contact portion 2C2, a land portion 2L2, and a wiring portion 2E2. That is, each of the multiple rewirings 21 has a contact portion 2C, a land portion 2L, and a wiring portion 2E.

[0045] Here, as shown in Figure 3, the wiring portion 2E of each of the multiple rewirings 21 extends inward from the periphery of the semiconductor device PKG1. If the number of terminals SB on the semiconductor device PKG1 is increased, the number of land portions 2L and wiring portions 2E will increase, making it easier for areas with a high local density of land portions 2L and wiring portions 2E to occur.

[0046] In the example shown in Figure 3, assuming that the shape of the land portion 2L1 of the rewiring 21A is circular, as indicated by the dashed line, there will be locations where the distance between the land portion 2L1 and the wiring portion 2E2 becomes extremely small. In this case, there is a concern that the rewiring 21A and rewiring 21B may be short-circuited, or that the current flowing through the rewiring 21A and the current flowing through the rewiring 21B may interfere with each other.

[0047] Therefore, in the case of the semiconductor device PKG1 of this embodiment, as shown in Figure 3, the land portion 2L1 is arranged adjacent to the wiring portion 2E2 that extends in the Y direction. In addition, the land portion 2L1 has a side L1S1 that extends linearly along the wiring portion 2E2.

[0048] By providing a side L1S1 that extends linearly along the wiring section 2E2 in the portion of the outer edge of the land section 2L1 adjacent to the wiring section 2E2, a sufficient separation distance SLE1 between the land section 2L1 and the wiring section 2E2 can be secured.

[0049] For example, in the example shown in Figure 3, the distance SLE1 between the land portion 2L1 and the wiring portion 2E2 is greater than or equal to the width W2E2 of the wiring portion 2E2 (length in the X direction perpendicular to the Y direction, which is the extension direction).

[0050] The minimum value of the separation distance SLE1 is defined by design rules. These design rules consider factors such as whether the degree of interference between electrically isolated and adjacent transmission paths is within an acceptable range. Hereinafter, the minimum value of the separation distance SLE1 defined by the design rules will be referred to as the "design minimum value."

[0051] In this embodiment, both the side L1S1 and the wiring section 2E2 extend in the Y direction. In other words, side L1S1 and wiring section 2E2 are parallel to each other. From the viewpoint of ensuring that the separation distance SLE1 is at or above the design minimum, it is particularly preferable that side L1S1 and wiring section 2E2 are parallel to each other. However, even if side L1S1 and wiring section 2E2 are not parallel, it is acceptable as long as the separation distance SLE1 is at or above the design minimum.

[0052] The value of the width W2E2 is determined by the product specifications, and therefore various variations exist depending on the product specifications. For example, if the product specifications require an extremely large value for the width W2E2, the value of the spacing distance SLE1 may be smaller than the value of the width W2E2.

[0053] However, even in this case, as already mentioned, the value of the separation distance SLE1 between the land portion 2L1 and the wiring portion 2E2 can be increased by providing the edge L1S1. Therefore, according to this embodiment, it is possible to set the value of the separation distance SLE1 to a value that does not cause mutual interference between the current flowing through the rewiring 21A and the current flowing through the rewiring 21B (i.e., the minimum design value).

[0054] Incidentally, in the example shown in Figure 1, the wiring section 2E2 extends linearly in the Y direction near the land section 2L1, but at positions away from the land section 2L1, there are parts that extend in a direction different from the Y direction. Depending on the layout of the wiring section 2E2, it may be preferable for the land section 2L1 to have multiple sides that extend linearly. Figure 5 is an enlarged plan view showing a modified example of Figure 3. Figure 6 is an enlarged plan view showing yet another modified example of Figure 3.

[0055] The semiconductor device PKG2 shown in Figure 5 differs from the semiconductor device PKG1 shown in Figure 3 in the following respects. In the modified example shown in Figure 5, the wiring portion 2E2 of the rewiring 21B includes a portion 2EP1 extending in the Y direction and a portion 2EP2 extending in the θ direction intersecting the X direction. The land portion 2L1 has an edge L1S1 that is positioned adjacent to portion 2EP1 of the wiring portion 2E2 and extends linearly along portion 2EP1 of the wiring portion 2E2, and an edge L1S2 that is positioned adjacent to portion 2EP2 of the wiring portion 2E2 and extends linearly along portion 2EP2 of the wiring portion 2E2.

[0056] In the case of semiconductor device PKG2, since the land portion 2L1 has a side L1S2, the value of the separation distance SLE2 between the land portion 2L1 and portion 2EP2 of the wiring portion 2E2 of the rewiring 21B can be adjusted. For this reason, for example, it is possible to set the value of the separation distance SLE2 to a value that does not cause mutual interference between the current flowing through the rewiring 21A and the current flowing through the rewiring 21B (i.e., the design minimum value).

[0057] Furthermore, in the example shown in Figure 5, it is preferable that side L1S1 and portion 2EP1 of wiring section 2E2 are parallel to each other. In other words, it is preferable that side L1S1 and portion 2EP1 of wiring section 2E2 each extend linearly in the Y direction. Similarly, it is preferable that side L1S2 and portion 2EP2 of wiring section 2E2 are parallel to each other. In other words, it is preferable that side L1S2 and portion 2EP2 of wiring section 2E2 each extend linearly in the θ direction.

[0058] The semiconductor device PKG3 shown in Figure 6 differs from the semiconductor device PKG1 shown in Figure 3 in the following respects. Specifically, the planar shape of the land portion 2L1 on the semiconductor device PKG3 is polygonal. In the example shown in Figure 6, the planar shape of the land portion 2L1 is hexagonal. In addition to the hexagonal shape shown in Figure 6, there are various other variations of the planar shape of the land portion 2L1. Depending on the direction in which the wiring portion 2E2 adjacent to the land portion 2L1 extends, it can be, for example, a pentagon, a heptagon, or an octagon.

[0059] As will be explained in detail later, from the viewpoint of preventing delamination of the adhesion interface between the land portion 2L shown in Figure 4 and the insulating film 22 or insulating film 23 that adheres to it, it is preferable to avoid stress concentration occurring in a part of the outer circumference of the land portion 2L. In the case of a polygon, stress may concentrate at multiple vertices. From the viewpoint of equalizing the stress concentrated at each vertex, it is preferable that the planar shape of the land portion 2L is a regular polygon. Also, if the interior angles of the polygon are acute angles (i.e., less than 90 degrees), stress concentration is likely to occur at the acute angle vertices. Therefore, it is preferable that each of the multiple interior angles of the polygon is greater than 90 degrees.

[0060] Next, we will explain the advantages of making the planar shape of the land portion 2L circular. As shown in Figure 4, the land portion 2L is in close contact with both the insulating film 22 and the insulating film 23. Here, we focus on preventing delamination at the contact interface between the land portion 2L and the insulating film 22, and at the contact interface between the land portion 2L and the insulating film 23. Figure 7 is an enlarged plan view showing the region shown in Figure 3 and the surrounding region.

[0061] The delamination of the adhesion interface described above occurs due to stress caused by the difference in the coefficients of thermal expansion of each component. In particular, if stress concentration occurs at a specific location on the outer circumference of land portion 2L, that location becomes the starting point for delamination. Furthermore, once a starting point for delamination occurs, the delamination progresses along the adhesion interface where the starting point is located.

[0062] Therefore, from the viewpoint of preventing delamination of the adhesion interface, it is preferable to suppress the occurrence of stress concentration. When the planar shape of the land portion 2L is circular, stress concentration is less likely to occur. If the occurrence of stress concentration can be suppressed, the starting point of delamination described above is less likely to occur. If the starting point of delamination does not occur, delamination will not progress. In other words, when the planar shape of the land portion 2L is circular, it is preferable in that it can suppress delamination of the adhesion interface caused by the difference in the coefficient of linear expansion between the land portion 2L and the insulating film 22 (or insulating film 23).

[0063] As shown in Figure 7, in a plan view, the land portion 2L2 of the rewiring 21B is located further from the outer edge of the semiconductor device PKG1 (for example, side PS2 shown in Figure 7) than the land portion 2L1. The planar shape of the land portion 2L2 is circular.

[0064] In this embodiment, in areas where the density of multiple rewirings 21 is high, the non-circular shape of the land area 2L allows the spacing between adjacent rewirings to be greater than or equal to the design minimum. On the other hand, even when the land area 2L has a circular shape, the land area 2L has a circular shape in areas where the spacing between adjacent rewirings can be greater than or equal to the design minimum.

[0065] As shown in Figure 7, the multiple pads 11 are arranged along the outer periphery of the semiconductor device PKG1. Each of the multiple rewirings 21 has a contact portion 2C along the outer periphery of the semiconductor device PKG1. The multiple land portions 2L are located inward (closer to the center of the semiconductor device PKG1) than the multiple contact portions 2C. Therefore, focusing on the arrangement density of the multiple wiring portions 2E, the following can be said.

[0066] In other words, in a plan view, the arrangement density of multiple wiring sections 2E is low near the center of the semiconductor device PKG1, while the arrangement density of multiple wiring sections 2E is high near the outer edge of the semiconductor device PKG1.

[0067] Therefore, in this embodiment, the shape of the land portion 2L1 where the arrangement density of the wiring portion 2E is relatively high is non-circular, and the shape of the land portion 2L2 where the arrangement density of the wiring portion 2E is relatively low is circular.

[0068] As a result, in the land portion 2L2, delamination of the contact interface caused by the difference in the coefficient of linear expansion between the land portion 2L2 and the insulating film 22 (or insulating film 23) shown in Figure 4 can be suppressed. Delamination between the rewiring 21 and the insulating film 22 (or insulating film 23) becomes a particular problem if it progresses over a wide area, but the impact is small if it remains in a localized area. In this embodiment, the planar shape of the land portion 2L is selectively made non-circular in areas where the arrangement density of the wiring portion 2E is particularly high, while the planar shape of the land portion 2L is circular in other areas. Therefore, the number of starting points for the progression of delamination can be reduced, and the spread of delamination over a wide area can be suppressed.

[0069] Furthermore, among the multiple land sections 2L, the number of wiring sections 2E located between land section 2L1 and land section 2L3, which are located on the outermost periphery, tends to be large (3 in the example shown in Figure 7). On the other hand, the number of wiring sections 2E located between land section 2L2 and land section 2L4, which are located on the second periphery from the outermost periphery, is smaller compared to the wiring sections between the land sections 2L located on the outermost periphery (2 in the example shown in Figure 7).

[0070] For example, consider the 64 land portions 2L (see Figure 3) located directly beneath each of the multiple terminals SB shown in Figure 1. In this embodiment, the planar shape of the land portions 2L arranged from the second circle onward from the outermost edge can be circular. The planar shape of the 28 land portions 2L located on the outermost edge is non-circular, while the 36 land portions 2L located from the second circle onward are circular. In other words, of the multiple land portions 2L of the semiconductor device PKG1, the number of land portions 2L with a circular planar shape is greater than the number of land portions 2L with a non-circular planar shape.

[0071] Furthermore, a high density of wiring sections 2E can be indicated by the number of wiring sections 2E located between adjacent land sections 2L. For example, in the case shown in Figure 7, it can be expressed as follows.

[0072] In other words, each of the multiple rewirings 21 includes a rewiring 21C which comprises a land portion 2L3 located next to a land portion 2L1 among the multiple land portions 2L formed on the insulating film 22 (see Figure 4). The land portions 2L1 and 2L3 are adjacent to each other in the X direction, which is the direction in which the edge PS2 extends.

[0073] In a plan view, three or more wiring sections 2E, including the wiring section 2E2, are formed between the land section 2L1 and the land section 2L3. In the example shown in Figure 7, it is preferable that the planar shape of at least one of the land sections 2L adjacent to each other via the three or more wiring sections 2E is non-circular.

[0074] In the example shown in Figure 7, the planar shapes of both adjacent land portions 2L connected by three or more wiring portions 2E are non-circular. Specifically, the three or more wiring portions 2E are electrically isolated from each of the land portions 2L1 and 2L3, and include a wiring portion 2E3 extending in the Y direction. The land portion 2L3 is located adjacent to the wiring portion 2E3 and has a side L3S1 that extends linearly along the wiring portion 2E3.

[0075] According to this embodiment, the arrangement density of the rewiring 21 can be improved, thereby increasing the number of terminals per unit area. For example, if all the terminals increased by applying this embodiment are used as signal transmission terminals, the number of signal transmission terminals per unit area can be increased.

[0076] Furthermore, in the example shown in Figure 7, two wiring sections 2E are placed between adjacent land sections 2L2 and 2L4 in the X direction. In Figure 7, if the number of wiring sections 2E placed between adjacent land sections 2L is two or less, the distance between the wiring sections 2E and the land sections 2L can be made greater than or equal to the design minimum value, even if the planar shape of the land sections 2L is not non-circular.

[0077] Furthermore, from the viewpoint of improving the quality of the signal flowing through the signal transmission path, the following configuration is preferable. Figure 8 is an enlarged cross-sectional view of the DD line in Figure 7. In Figure 8, the signal or reference potential flowing through each wiring section is schematically illustrated using dashed-dotted arrows.

[0078] In Figure 7, the three wiring sections 2E located between land section 2L1 and land section 2L3 are, as shown in Figure 8, a signal wiring section 2ESG through which signal SG1 is transmitted, and are located on both sides of the signal wiring section 2ESG. The three wiring sections 2E also include two reference potential wiring sections 2EVS through which reference potential VSS is transmitted.

[0079] The reference potential VSS is a fixed potential. In this embodiment, the reference potential VSS is, for example, the ground potential. As shown in Figure 8, a structure in which reference potential wiring sections 2EVS are arranged on both sides of the signal wiring section 2ESG is called a coplanar structure, and the reference potential wiring sections 2EVS function as electromagnetic shields.

[0080] For example, electromagnetic noise directed towards the signal wiring section 2ESG is attenuated by the reference potential wiring section 2EVS. As a result, the signal transmission path including the signal wiring section 2ESG becomes less susceptible to external electromagnetic noise. In other words, the reference potential wiring section 2EVS functions as an electromagnetic shield that suppresses the intrusion of external electromagnetic noise into the signal transmission path including the signal wiring section 2ESG.

[0081] For example, electromagnetic noise generated in the signal wiring section 2ESG is attenuated by the reference potential wiring section 2EVS. In other words, the reference potential wiring section 2EVS functions as an electromagnetic shield to suppress the electromagnetic noise generated in the signal wiring section 2ESG from affecting the surrounding signal transmission path.

[0082] Next, a preferred embodiment of the conductive film UBM shown in Figure 4 will be described. Figure 9 is an enlarged plan view showing the contours of the conductor layer and solder balls arranged on the land area in the enlarged plan view shown in Figure 3.

[0083] As shown in Figure 9, in a plan view, the planar shape of the conductive film UBM is circular. The planar shape of terminal SB is also circular. In a plan view, the diameter of terminal SB is smaller than the diameter of the conductive film UBM.

[0084] As already explained, the shape of the land portion 2L1 is non-circular. The planar shape of the conductive film UBM may also be non-circular, following the shape of the land portion 2L1, but it is preferable that it be circular, as shown in Figure 9.

[0085] As shown in Figure 4, the lower surface of the conductive film UBM is in close contact with the insulating film 23. Here, from the viewpoint of suppressing delamination at the adhesion interface between the conductive film UBM and the insulating film 23, it is preferable to avoid localized stress concentration on a part of the outer edge of the conductive film UBM.

[0086] Similar to the planar shape of the land portion 2L described earlier, stress concentration can be suppressed in the case of the conductive film UBM by making its planar shape circular. As a result, it is possible to prevent localized stress concentration in a part of the outer edge of the conductive film UBM, thereby suppressing delamination at the adhesion interface between the conductive film UBM and the insulating film 23.

[0087] Furthermore, in the example shown in Figure 9, the entire conductive film UBM overlaps with the land portion 2L1. In a plan view, the land portion 2L1 is larger than the conductive film UBM. By increasing the planar area of ​​the land portion 2L1, stress can be distributed at the outer edge of the land portion 2L1. As a result, delamination at the contact interface between the land portion 2L and the insulating film 22, and at the contact interface between the land portion 2L and the insulating film 23, as shown in Figure 4, can be prevented.

[0088] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0089] For example, in the above embodiment, an embodiment was described in which the planar shape of some of the multiple land portions 2L is non-circular, and the planar shape of the other portions is circular. However, as a modification, there is a case in which the planar shape of all of the multiple land portions 2L is non-circular.

[0090] Furthermore, in the example explained using Figure 7, the planar shapes of land portion 2L1 and land portion 2L3 are both non-circular, but they are different planar shapes. However, as a modified example, there may be cases where multiple land portions 2L, each with a non-circular planar shape, have the same shape as each other.

[0091] Furthermore, for example, the various modifications described above may be combined with each other. [Explanation of symbols]

[0092] 2C, 2C1, 2C2 Contact Section 2E,2E1,2E2,2E3 Wiring section 2EP1,2EP2 part 2ESG signal wiring section 2EVS Reference potential wiring section 2L, 2L1, 2L2, 2L3, 2L4 Land section 10 Semiconductor Chips 11 pads (electrode pads) 12 Semiconductor substrates 12t Semiconductor device formation surface (main surface) 13. Wiring Layer (Chip Wiring Layer) 13P plug 13t main surface 13V via wiring 14, 15, 22, 23 Insulating film (insulating layer) 20 Rewiring section 21,21A,21B,21C rewiring 22H,23H opening L1S1, L1S2, L3S1 edges PKG1, PKG2, PKG3 Semiconductor Device PMSb,PMSt main surface PS1, PS2, PS3, PS4 SB terminal (external terminal, protruding electrode, solder ball) SG1 signal SLE1,SLE2 separation distance UBM conductive film (underbump metal, conductive layer) VSS reference potential W2E2 Width

Claims

1. The first insulating film and A plurality of pads formed on the first insulating film, A second insulating film is formed on the first insulating film and overlaps the peripheral edges of each of the plurality of pads, A plurality of rewirings formed on the second insulating film, Each of the aforementioned multiple rewirings has a terminal provided on its land portion, A conductive film formed between the terminal and the land portion, and connected to the terminal and the land portion, It has, The plurality of pads include a first pad, a second pad, and The aforementioned multiple rewirings are A first rewiring comprising a first contact portion disposed on and connected to the first pad, a first land portion located away from the first contact portion, and a first wiring portion located between the first contact portion and the first land portion, A second rewiring comprising a second contact portion disposed on and connected to the second pad, a second land portion located away from the second contact portion, and a second wiring portion located between the second contact portion and the second land portion, Includes, The planar shape of the conductive film connected to the first land portion is circular. The planar shape of the first land portion is non-circular, A semiconductor device in which, in a plan view, the first land portion is arranged adjacent to the second wiring portion extending in a first direction and has a first side that extends linearly along the second wiring portion.

2. In the semiconductor device described in claim 1, The second wiring section is, A first portion extending in the first direction, A second portion extending in a second direction intersecting the first direction, Includes, The first side extends along the first portion of the second wiring section, In a plan view, the first land portion is, The first side of the second wiring portion is arranged adjacent to the first portion of the second wiring portion and extends linearly along the first portion of the second wiring portion, A second side is positioned adjacent to the second portion of the second wiring section and extends linearly along the second portion of the second wiring section, A semiconductor device having

3. In the semiconductor device described in claim 2, The planar shape of the first land portion is a polygon, wherein the semiconductor device is a semiconductor device.

4. In the semiconductor device described in claim 3, A semiconductor device in which each of the multiple interior angles of the aforementioned polygon is greater than 90 degrees.

5. In the semiconductor device described in claim 1, In a plan view, the second land portion is positioned further from the outer edge of the semiconductor device than the first land portion. The planar shape of the conductive film connected to the second land portion is circular. The planar shape of the second land portion is circular, in the semiconductor device.

6. In the semiconductor device described in claim 1, The plurality of rewirings further include a third rewiring having a third land portion located next to the first land portion in a plan view, In a plan view, three or more rewiring sections, including the second rewiring section, are arranged between the first land section and the third land section. In a plan view, the second wiring portion is the wiring portion located closest to the first land portion among the three or more rewiring wiring portions, in a semiconductor device.

7. In the semiconductor device described in claim 6, The wiring portion of the three or more rewirings is electrically isolated from the first land portion and the third land portion, and includes a third wiring portion extending in the first direction. The third land portion is positioned adjacent to the third wiring portion and has a third side that extends linearly along the third wiring portion. In a plan view, the third wiring portion is the wiring portion located closest to the third land portion among the three or more rewiring wiring portions, in a semiconductor device.

8. In the semiconductor device described in claim 6, The wiring portion of the three or more rewirings is The signal wiring section through which the signal is transmitted, Two reference potential wiring sections are located on either side of the aforementioned signal wiring section and transmit the reference potential, Semiconductor equipment, including

9. In the semiconductor device described in claim 2, The first side and the first portion of the second wiring section are parallel to each other. A semiconductor device in which the second side and the second portion of the second wiring section are parallel to each other.

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