Semiconductor device and method for manufacturing the same
By forming metal silicide layers and using a plating resist to separate electrode layers, the semiconductor manufacturing process is simplified, reducing complexity and chemical usage without compromising device reliability.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SHINDENGEN ELECTRIC MANUFACTURING CO LTD
- Filing Date
- 2024-12-06
- Publication Date
- 2026-06-18
AI Technical Summary
The conventional manufacturing process of semiconductor devices involves complex photographic steps, increasing costs and process complexity.
The manufacturing process is simplified by forming metal silicide layers on the silicon wafer surfaces and using a plating resist to separate electrode layers without the need for photographic processes, allowing for the formation of solder layers without photolithography.
This approach reduces the complexity of the manufacturing process by eliminating photographic steps and minimizing the use of environmentally harmful chemicals, while maintaining the reliability and efficiency of semiconductor device production.
Smart Images
Figure 2026099194000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. [Background technology]
[0002] Figure 8 is a cross-sectional view illustrating a conventional method for manufacturing a mesa diode. This manufacturing method involves applying solder 101 and 102 to both sides of a wafer 110 while it is still in wafer form. A photographic process using photolithography is performed to leave an oxide film 111 on the back surface so that Ni plating is not formed on the entire back surface of the wafer. Ni plating is then performed on the back surface of the wafer 110, excluding the oxide film 111, while simultaneously Ni plating is performed on the front surface of the wafer 110. After that, solder 101 and 102 are applied to the Ni-plated electrodes 121 and 122, and the oxide film 111 on the back surface is irradiated with a chip-dividing laser 131 to perform a breaking process and form a chip. Related technology for wafer 110 is disclosed in Patent Document 1.
[0003] The above mesa-type diode is N - P in contact on the semiconductor layer 110a + It has a type semiconductor layer 112, P + A first Ni plated electrode 121 is formed on the type semiconductor layer 112. + Semiconductor layer 112 and N - A groove is formed in the N-type semiconductor layer 110a, and a passivation layer 125 is formed within this groove. - N in contact beneath the semiconductor layer 110a + A semiconductor layer 113 of type N is formed, + A second Ni-plated electrode 122 is formed beneath the type semiconductor layer 113. A first solder 101 is formed on the first Ni-plated electrode 121, and a second solder 102 is formed beneath the second Ni-plated electrode 122.
[0004] However, the above manufacturing method requires a photographic step to leave an oxide film 111 on the back surface, which complicates the manufacturing process and increases manufacturing costs. [Prior art documents] [Patent Documents]
[0005] [Patent Document 1] Japanese Patent Publication No. 2014-192500 (Figures 4 and 5) [Overview of the project] [Problems that the invention aims to solve]
[0006] Various aspects of the present invention aim to provide semiconductor devices and methods for manufacturing the same that can reduce the complexity of the manufacturing process by reducing the number of photographic steps. [Means for solving the problem]
[0007] Various aspects of the present invention will be described below.
[0008] [1] Silicon layer and A first metal silicide layer formed on the surface of the silicon layer, A first electrode layer formed on the first metal silicide layer, The first solder formed on the first electrode layer, A second metal silicide layer formed on the back surface of the silicon layer, A second electrode layer formed beneath the second metal silicide layer, The second solder formed beneath the second electrode layer, It has, A semiconductor device characterized in that the second metal silicide layer located around the second electrode layer in a plan view is separated from the second solder so that the second solder does not adhere to it.
[0009] According to the semiconductor device of [1] according to one aspect of the present invention, since the second metal silicide layer on which the second solder does not mount is disposed around the second electrode layer in a plan view, it is possible to form the second solder on the second electrode layer without using a photo process in the manufacturing process of the semiconductor device. Therefore, it is possible to realize a semiconductor device that can reduce the complexity of the manufacturing process by reducing the photo process.
[0010] [2] A silicon layer, A first metal silicide layer formed on the surface of the silicon layer, A first electrode layer formed on the first metal silicide layer, A first Au plating formed on the first electrode layer, A second metal silicide layer formed on the back surface of the silicon layer, A second electrode layer formed under the second metal silicide layer, A second Au plating formed under the second electrode layer, having In a plan view, a resist is disposed around the second electrode layer, The resist is characterized in that it separates the second Au platings from each other so that the second Au plating does not mount.
[0011] According to the semiconductor device of [2] according to one aspect of the present invention, since the resist is disposed around the second metal silicide layer in a plan view so that the second Au plating does not mount, it is possible to form the second Au plating on the second electrode layer without using a photo process in the manufacturing process of the semiconductor device. Therefore, it is possible to realize a semiconductor device that can reduce the complexity of the manufacturing process by reducing the photo process. Note that the above resist is formed without using an exposure process.
[0012] [3] In [1] or [2] above, An inclined surface of a mesa structure formed on a side surface on the surface side of the silicon layer, The passivation layer formed on the inclined surface and the side surface of the first metal silicide layer, A semiconductor device characterized by having the following features.
[0013] According to the semiconductor device described in [3] above in one aspect of the present invention, the reliability of the semiconductor device can be increased because the passivation layer is formed on the inclined surface in a highly clean environment.
[0014] [4] In any one of the above items [1] to [3], A semiconductor device characterized in that the first and second metal silicide layers are made of Ni silicide.
[0015] [5] In any one of the above items [1] to [4], A semiconductor device characterized by having a mold resin disposed on the side surface of the semiconductor layer.
[0016] [6] A step (A1) of forming a PN junction on a silicon wafer by introducing impurities from the front or back side of the silicon wafer, The process (A2) involves forming mesa-structured grooves on the surface of the silicon wafer, A3 is a step of forming a passivation layer on the inner surface of the groove, A4 is a step of forming a first metal layer on the front and back surfaces of the silicon wafer by plating, Step (B) involves annealing the silicon wafer and the first metal layer to react the silicon with the metal, thereby forming first and second metal silicide layers on the front and back surfaces of the silicon wafer. Step (C) to remove the unreacted first metal layer remaining on the first and second metal silicide layers, The process (D) involves forming a plating resist on the scribe lines of the second metal silicide layer on the back surface of the silicon wafer, Step (E) of forming a plurality of first electrode layers made of the second metal layer on the front side of the silicon wafer and a plurality of second electrode layers made of the second metal layer on the back side of the silicon wafer by plating the front and back surfaces of the silicon wafer with the passivation layer and the plating resist as masks, respectively. The process of removing the aforementioned plating resist (F), Step (G) of placing first and second solder on each of the plurality of first electrode layers and each of the plurality of second electrode layers, It has, A method for manufacturing a semiconductor device, characterized in that, in a plan view, the plating resist on the back surface of the silicon wafer is positioned to overlap with the grooves of the mesa structure.
[0017] According to the semiconductor device manufacturing method described in [6] above in one aspect of the present invention, the method comprises the steps of: (B) forming first and second metal silicide layers on the front and back surfaces of a silicon wafer by annealing a silicon wafer and a first metal layer and reacting silicon with metal; and (E) forming a plurality of second electrode layers consisting of the second metal layer on the back surface of the silicon wafer by plating a second metal layer on the first and second metal silicide layers, using the front and back surfaces of the silicon wafer as a mask with a passivation layer and a plating resist. As a result, the second metal silicide layer on which the second solder does not adhere is arranged around the second electrode layer in a plan view, so that the second solder can be placed on each of the plurality of second electrode layers. For this reason, a photographic process as in the prior art is unnecessary, and the complexity of the manufacturing process can be reduced.
[0018] [7] In the above [6], A method for manufacturing a semiconductor device, characterized by having, after step (G), step (H) of dividing the silicon wafer into a plurality of chips by irradiating the second metal silicide layer exposed on the scribe line on the back surface of the silicon wafer with a chip-dividing laser or making grooves with a dicer, and then performing a breaking process.
[0019] [8] A step (A1) of forming a PN junction on a silicon wafer by introducing impurities from the front or back side of the silicon wafer, The process (A2) involves forming mesa-structured grooves on the surface of the silicon wafer, A3 is a step of forming a passivation layer on the inner surface of the groove, A4 is a step of forming a first metal layer on the front and back surfaces of the silicon wafer by plating, Step (B) involves annealing the silicon wafer and the first metal layer to react the silicon with the metal, thereby forming first and second metal silicide layers on the front and back surfaces of the silicon wafer. Step (C) to remove the unreacted first metal layer remaining on the first and second metal silicide layers, (D) A step of forming a plating resist on the scribe lines of the second metal silicide layer on the back surface of the silicon wafer, Step (E) of forming a second metal layer on the first metal silicide layer and below the second metal silicide layer, respectively, using the passivation layer and the plating resist as masks on the front and back surfaces of the silicon wafer, Step (G) of forming first and second Au plating layers on the second metal layer using the passivation layer and the plating resist as masks on the front and back surfaces of the silicon wafer, thereby forming a plurality of first electrode layers consisting of the first Au plating layer on the front surface of the silicon wafer and a plurality of second electrode layers consisting of the second Au plating layer on the back surface of the silicon wafer, It has, A method for manufacturing a semiconductor device, characterized in that, in a plan view, the plating resist on the back surface of the silicon wafer is positioned to overlap with the grooves of the mesa structure.
[0020] According to the semiconductor device manufacturing method described in [8] above in one aspect of the present invention, the method comprises the steps of: (B) annealing a silicon wafer and a first metal layer to react silicon with metal and form first and second metal silicide layers on the front and back surfaces of the silicon wafer; and forming a second metal layer on the first and second metal silicide layers by plating, using a passivation layer and a plating resist as masks on the front and back surfaces of the silicon wafer, and further forming first and second Au plating layers on the second metal layer. This makes it possible to form a plurality of first electrode layers consisting of the first Au plating layer on the front surface of the silicon wafer and a plurality of second electrode layers consisting of the second Au plating layer on the back surface of the silicon wafer. As a result, a photographic process as in the prior art is unnecessary, and the complexity of the manufacturing process can be reduced.
[0021] [9] In the above [8], A method for manufacturing a semiconductor device, characterized by having, after step (G) above, step (H) of removing the plating resist, irradiating the second metal silicide layer exposed on the scribe line on the back surface of the silicon wafer with a chip-dividing laser or making grooves with a dicer, and then performing a breaking process to divide the silicon wafer into a plurality of chips.
[0022] Figure 1(D)
[10] In the above [8] or [9], The method for forming the plating resist in step (D) is characterized by applying it by spraying, printing, or inkjet, and then curing the resist by heat or ultraviolet irradiation.
[0023] Figure 1(A)
[11] In any one of the above paragraphs [6] to
[10] , A method for manufacturing a semiconductor device, characterized in that the groove in step (A2) is formed by cutting with a dicing blade.
[0024] According to the semiconductor device manufacturing method described in
[11] above, which is one aspect of the present invention, the manufacturing process can be simplified because the steps of oxide film growth by photolithography, photography, and etching are eliminated compared to forming grooves by wet etching. Furthermore, while wet etching groove formation may require the use of large amounts of chemicals, the semiconductor device manufacturing method described in
[11] above only involves the step of removing the slight strain layer created by the dicing blade by etching, thus significantly reducing the amount of environmentally harmful chemicals used. [Effects of the Invention]
[0025] According to various aspects of the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can reduce the complexity of the manufacturing process by reducing the number of photographic steps. [Brief explanation of the drawing]
[0026] [Figure 1] (A) to (E) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 2] (F) to (H) are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 3] Figure 2(F) is a plan view of the silicon wafer as seen from the back side. [Figure 4] Figure 2(G) is a plan view of the silicon wafer as seen from the back side. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 7] This is a cross-sectional view showing a semiconductor device according to one aspect of the present invention. [Figure 8]It is a cross-sectional view for explaining a method of manufacturing a conventional mesa-type diode.
Embodiments for Carrying Out the Invention
[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.
[0028] (First Embodiment) FIGS. 1(A) to (E) and FIGS. 2(F) and (G) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an aspect of the present invention. FIG. 3 is a plan view seen from the back side of the silicon wafer shown in FIG. 2(F). FIG. 4 is a plan view seen from the back side of the silicon wafer shown in FIG. 2(G).
[0029] The method of manufacturing the semiconductor device according to the above [6] aspect of the present invention forms a PN junction 12 in the silicon wafer 10 by introducing impurities from the front side or the back side of the silicon wafer 10 as shown in FIG. 1(A) (Step (A1)). Note that in each cross-section of FIGS. 1 and 2, the front surface is drawn on the lower side and the back surface is drawn on the upper side.
[0030] Specifically, boron and phosphorus are simultaneously diffused over the entire surface from both sides of the N - -type silicon wafer as the silicon wafer 10. That is, boron is diffused from the entire front surface of the N - -type silicon wafer 10, and at the same time, phosphorus is diffused from the entire back surface of the N - -type silicon wafer 10. As a result, a P - -type silicon layer is formed on the front side with respect to the PN junction 12 of the N + -type silicon wafer 10, and an N - -type silicon layer and an N - -type silicon layer are formed on the back side with respect to the PN junction 12 of the N + -type silicon wafer 10.
[0031] N - On the back side of the type silicon wafer 10, N - N has a higher impurity concentration than the molded silicon layer. + A molded silicon layer is formed. + The molded silicon layer is N - It is in contact with the molded silicon layer. - On the surface side of the type silicon wafer 10 is N - P bonded to the molded silicon layer + A type semiconductor layer is formed. + Molded silicon layer and N - A PN bond 12 is formed on the surface where it joins with the mold silicon.
[0032] Next, mesa-structured grooves 10a are formed on the surface of the silicon wafer 10 (step (A2)). In detail, P is added to the silicon wafer 10. + From the surface of the silicon wafer 10, which is the side of the molded silicon layer, N - A groove 10a, with a depth up to the middle of the molded silicon layer, is formed by cutting with a dicing blade (not shown).
[0033] Next, to remove the strain on the inner surface of the groove 10a, the silicon wafer 10 including the inner surface of the groove 10a may be wet-etched.
[0034] Next, a passivation layer 40 is formed on the inner surface of the groove 10a (step (A3)). In detail, a glass paste is applied to the inner surface of the groove 10a by a printing method, and the glass paste is fired to form a passivation layer 40 made of glass.
[0035] Next, the oxide film on the electrode formation surface of the silicon wafer 10 is removed by wet etching or sandblasting the front and back surfaces of the silicon wafer 10 with BHF (buffered hydrofluoric acid).
[0036] Next, a first metal layer 21 is formed on the front and back surfaces of the silicon wafer 10 by plating (step (A4)). For example, a Ni layer 21 is formed on the front and back surfaces of the silicon wafer 10 by plating.
[0037] Next, as shown in Figure 1(B), the silicon wafer 10 and the first metal layer 21 are annealed to react the silicon with the metal, thereby forming the first and second metal silicide layers 21a and 21b on the front and back surfaces of the silicon wafer 10 (step (B)). If the first metal layer 21 is a Ni layer, then the first and second metal silicide layers 21a and 21b will be Ni silicide layers.
[0038] Next, as shown in Figure 1(C), the unreacted first metal layer 21 remaining on the first and second metal silicide layers 21a and 21b is removed (step (C)). Specifically, the unreacted first metal layer 21 is removed by immersing the silicon wafer 10 in a chemical solution and boiling it, leaving the first and second metal silicide layers 21a and 21b. For example, if the first and second metal silicide layers 21a and 21b are Ni silicide layers, nitric acid may be used as the chemical solution.
[0039] Next, as shown in Figure 1(D), a plating resist 22 is formed on the scribe lines of the second metal silicide layer 21b on the back surface of the silicon wafer 10 (step (D)). Here, the plating resist 22 is formed by applying it by spraying, printing, or inkjet, and then curing the resist by heat or ultraviolet irradiation.
[0040] Subsequently, as shown in Figure 1(E), a second metal layer is formed on the first and second metal silicide layers 21a and 21b of the silicon wafer 10 by plating, using the passivation layer 40 and the plating resist 22 as masks. This forms a plurality of first electrode layers 23 made of the second metal layer on the front side of the silicon wafer 10, and a plurality of second electrode layers 24 made of the second metal layer on the back side of the silicon wafer 10 (step (E)). If the second metal layer is, for example, a Ni layer, the first electrode layer 23 is a first Ni plating layer, and the second electrode layer 24 is a second Ni plating layer. Also, in a plan view, the plating resist 22 on the back side of the silicon wafer 10 is positioned to overlap with the groove 10a of the mesa structure (see Figure 1(E)).
[0041] Next, as shown in Figures 2(F) and 3, the plating resist 22 is removed (step (F)). Specifically, the plating resist 22 is removed using an alkaline chemical solution or an organic solvent. As alkaline chemical solutions, for example, sodium hydroxide, potassium hydroxide, and tetramethylammonium hydroxide (TMAH) can be used, and as organic solvents, hydrocarbon-based solvents (for example, Solfine, etc.) can be used.
[0042] Subsequently, as shown in Figures 2(G) and 4, the first and second solders 31 and 32 are placed on each of the multiple first electrode layers 23 and each of the multiple second electrode layers 24 (step (G)). The second metal silicide layer 21b on the scribe line on the back surface of the silicon wafer 10 is not wetted by the second solder, so the second solder 32 is formed on the second electrode layer 24, and the second solder is not formed on the second metal silicide layer 21b. It is preferable that the first and second metal silicide layers 21a and 21b are Ni silicide layers.
[0043] Next, as shown in Figure 2(H), the silicon wafer 10 is divided into multiple chips by irradiating the second metal silicide layer 21b exposed on the scribe line on the back surface of the silicon wafer 10 with a chip-dividing laser or by making grooves with a dicer, followed by a breaking process (step (H)). In other words, since the second metal silicide layer 21b is exposed on the scribe line on the back surface of the silicon wafer 10, it is possible to make grooves 51 from the back surface of the silicon wafer 10 with a chip-dividing laser or by making grooves with a dicer. The chip-dividing laser is a narrow and deep laser.
[0044] According to this embodiment, the silicon wafer 10 and the first metal layer 21 are annealed to react silicon with metal, thereby forming first and second metal silicide layers 21a and 21b on the front and back surfaces of the silicon wafer 10 (step (B)). The front and back surfaces of the silicon wafer 10 are masked by a passivation layer 40 and a plating resist 22, and a second metal layer is formed by plating on the first metal silicide layer 21a and under the second metal silicide layer 21b, respectively, thereby forming a plurality of second electrode layers 24 made of the second metal layer on the back surface of the silicon wafer 10 (step (E)). As a result, the second metal silicide layer 21b, on which the second solder 32 does not adhere, is arranged around the second electrode layer 24 in a plan view, so that the second solder 32 can be placed on each of the plurality of second electrode layers 24. Therefore, a photographic process like in the conventional technology is unnecessary, and the complexity of the manufacturing process can be reduced.
[0045] Furthermore, in this embodiment, since the grooves 10a of the mesa structure in step (A2) above are formed by cutting the surface of the silicon wafer 10 with a dicing blade, the processes of oxide film growth using photolithography, photography, and etching are eliminated compared to forming grooves by wet etching, thus simplifying the manufacturing process. In addition, while groove formation by wet etching uses a large amount of chemical solution, the above manufacturing method only involves a step of removing the slight strain layer created by the dicing blade by etching, thus significantly reducing the amount of environmentally harmful chemical solution used.
[0046] In this embodiment, the first and second solders 31 and 32 are placed on each of the multiple first electrode layers 23 and each of the multiple second electrode layers 24, but it is also possible to carry out the implementation with the following modifications. After step (E), in which a second metal layer 23, 24 is formed by plating on the first metal silicide layer 21a and under the second metal silicide layer 21b, respectively, using the passivation layer 40 and plating resist 22 as masks on the front and back surfaces of the silicon wafer 10, as shown in Figure 5, the first and second Au plating layers 41, 42 are formed on the second metal layers 23, 24, using the passivation layer 40 and plating resist 22 as masks on the front and back surfaces of the silicon wafer 10. This forms a plurality of first electrode layers consisting of the first Au plating layer 41 on the front side of the silicon wafer 10, and a plurality of second electrode layers consisting of the second Au plating layer 42 on the back side of the silicon wafer 10 (step (G)). Therefore, a photographic process like in the conventional technology is unnecessary, and the complexity of the manufacturing process can be reduced. Note that in Figures 5 and 6, the front surface is depicted on the bottom and the back surface is depicted on the top.
[0047] Then, after forming a plurality of first electrode layers consisting of the first Au plating layer 41 described above, and a plurality of second electrode layers consisting of the second Au plating layer 42 on the back side of the silicon wafer 10, as shown in Figure 6, the plating resist 22 is removed, and grooves are made in the second metal silicide layer 21b exposed on the scribe line on the back side of the silicon wafer 10 using a chip-dividing laser or a dicer, and then the silicon wafer 10 is divided into a plurality of chips by a breaking process (step (H)).
[0048] (Second embodiment) Figure 7 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention. In this semiconductor device, a first lead frame 61 is electrically connected to a first solder 31 of a semiconductor chip manufactured by the manufacturing method according to the first embodiment, and a second lead frame 62 is electrically connected to a second solder 32 of the semiconductor chip. The semiconductor chip and parts of the first and second lead frames are then sealed with a molding resin 50. In other words, parts of the first and second lead frames are formed to be exposed from the molding resin 50 (see Figure 7).
[0049] As shown in Figures 2(G), 4, and 7, the semiconductor device described in [1] above according to one aspect of the present invention has a silicon layer 11 having a PN junction 12, and a first metal silicide layer 21a is formed on the surface of the silicon layer 11. A first electrode layer 23 is formed on the first metal silicide layer 21a, and a first solder 31 is formed on the first electrode layer 23.
[0050] A second metal silicide layer 21b is formed on the back surface of the silicon layer 11, and a second electrode layer 24 is formed beneath the second metal silicide layer 21b. A second solder 32 is formed beneath the second electrode layer 24. In a plan view, the second metal silicide layer 21b, located around the second electrode layer 24, separates it from the second solder 32 so that the second solder 32 does not adhere to it. Resin 50 is placed on the sides of the second metal silicide layer 21b, the sides of the semiconductor layer 11, and the sides of the first and second solders 31 and 32, and this resin is a molding resin (see Figure 7).
[0051] The first and second metal silicide layers 21a and 21b described above may be made of Ni silicide.
[0052] The silicon layer 11 is formed on the back side from the PN junction 12. - It has a molded silicon layer 11c. On the back side of the silicon layer 11, N - N has a higher impurity concentration than the mold silicon layer 11c. + A molded silicon layer 11a is formed, N +The molded silicon layer 11a is N - It is in contact with the molded silicon layer 11c. From the PN junction 12 of silicon 11, P is present on the surface side. + A molded silicon layer 11b is formed, and the PN junction 12 is P + The molded silicon layer 11b is N - It is located on the surface that bonds with the mold silicon layer 11c (see Figure 7).
[0053] A mesa-structured inclined surface 11d is formed on the surface side of the silicon layer 11, and a passivation layer 40 is formed on this inclined surface 11d and on the side of the first metal silicide layer 21a. This passivation layer 40 is formed in a process before the semiconductor wafer 10 is divided, as described in the first embodiment. Therefore, the passivation layer 40 can be formed on the mesa-structured inclined surface 11d in a highly clean environment, and as a result, the reliability of the semiconductor device can be increased.
[0054] According to this embodiment, since the second metal silicide layer 21b, on which the second solder 32 is not placed, is arranged around the second electrode layer 24 in a plan view, it is possible to form the second solder 32 on the second electrode layer 24 without using a photographic process in the semiconductor device manufacturing process. Therefore, it is possible to realize a semiconductor device that reduces the complexity of the manufacturing process by reducing the photographic process.
[0055] (Third embodiment) In this embodiment, the semiconductor device shown in Figure 7 can also be modified as follows. Similar to the example of the modification of the manufacturing method in the first embodiment, in this embodiment as well, the first solder 31 can be changed to a first electrode layer 31 consisting of a first Au plating layer 41, and the second solder 32 can be changed to a second electrode layer 32 consisting of a second Au plating layer 42. In other words, the first lead frame 61 is electrically connected to the first electrode layer 31 consisting of the first Au plating layer 41 of the semiconductor chip, and the second lead frame 62 is electrically connected to the second electrode layer 32 consisting of the second Au plating layer 42 of the semiconductor chip. Then, the semiconductor chip and parts of the first and second lead frames are sealed with molding resin 50.
[0056] As shown in Figure 5, the semiconductor device described in [2] above according to one aspect of the present invention has a silicon layer 11 having a PN junction 12, and a first metal silicide layer 21a is formed on the surface of the silicon layer 11. A first electrode layer 23 is formed on the first metal silicide layer 21a, and a first Au plating layer 41 is formed on the first electrode layer 23.
[0057] A second metal silicide layer 21b is formed on the back surface of the silicon layer 11, and a second electrode layer 24 is formed beneath the second metal silicide layer 21b. A second Au plating layer 42 is formed beneath the second electrode layer 24. In a plan view, a resist 22 is arranged around the second electrode layer 24, and the resist 22 separates the second Au plating 42 from each other so that the second Au plating 42 does not adhere to it. A resin is placed on the side surface of the second metal silicide layer 21b, the side surface of the semiconductor layer 11, and the side surface of the first and second Au platings 41 and 42, and this resin is preferably a molding resin.
[0058] The first and second metal silicide layers 21a and 21b described above may be made of Ni silicide, similar to the third embodiment.
[0059] In this embodiment, as in the second embodiment, a passivation layer 40 is formed on the inclined surface 11d of the mesa structure and on the side surface of the first metal silicide layer 21a. Therefore, it provides the same effects as in the second embodiment.
[0060] According to this embodiment, since the resist 22 is arranged around the second metal silicide layer 21b in a plan view so that the second Au plating 42 does not adhere to it, it is possible to form the second Au plating 42 on the second electrode layer 24 without using a photographic process in the semiconductor device manufacturing process. Therefore, it is possible to realize a semiconductor device that reduces the complexity of the manufacturing process by reducing the photographic process. Note that the resist 22 is formed without using an exposure process.
[0061] Furthermore, it is also possible to combine the second and third embodiments as appropriate. [Explanation of Symbols]
[0062] 10 silicon wafers 10a Mesa structure groove 11 Silicon layer 11d Mesa structure inclined surface 12 PN junction 21 First metal layer 21a First metal silicide layer 21b Second metal silicide layer 22 Plating resist (resist) 23 First electrode layer 24 Second electrode layer 31 First solder 32. Second solder 40 Passivation Layer 41. First Au plating 42 Second Au plating 50 mold resin
Claims
1. Silicon layer and A first metal silicide layer formed on the surface of the silicon layer, A first electrode layer formed on the first metal silicide layer, The first solder formed on the first electrode layer, A second metal silicide layer formed on the back surface of the silicon layer, A second electrode layer formed beneath the second metal silicide layer, The second solder formed beneath the second electrode layer, It has, A semiconductor device characterized in that the second metal silicide layer located around the second electrode layer in a plan view is separated from the second solder so that the second solder does not adhere to it.
2. Silicon layer and A first metal silicide layer formed on the surface of the silicon layer, A first electrode layer formed on the first metal silicide layer, The first Au plating formed on the first electrode layer, A second metal silicide layer formed on the back surface of the silicon layer, A second electrode layer formed beneath the second metal silicide layer, The second Au plating formed beneath the second electrode layer, It has, In a plan view, a resist is arranged around the second electrode layer. The semiconductor device is characterized in that the resist separates the second Au plating from each other so that the second Au plating does not adhere to it.
3. In claim 1 or 2, The inclined surface of the mesa structure formed on the surface side of the silicon layer, The passivation layer formed on the inclined surface and the side surface of the first metal silicide layer, A semiconductor device characterized by having the following features.
4. In claim 1 or 2, A semiconductor device characterized in that the first and second metal silicide layers are made of Ni silicide.
5. In claim 1 or 2, A semiconductor device characterized by having a mold resin disposed on the side surface of the silicon layer.
6. A1 is a step of forming a PN junction on a silicon wafer by introducing impurities from the front or back side of the silicon wafer, A2 is a step of forming mesa structure grooves on the surface of the silicon wafer, A3 is a step of forming a passivation layer on the inner surface of the groove, A4 is a step of forming a first metal layer on the front and back surfaces of the silicon wafer by plating, Step (B) involves annealing the silicon wafer and the first metal layer to react the silicon with the metal, thereby forming first and second metal silicide layers on the front and back surfaces of the silicon wafer. Step (C) of removing the unreacted first metal layer remaining on the first and second metal silicide layers, Step (D) of forming a plating resist on the scribe line of the second metal silicide layer on the back surface of the silicon wafer, Step (E) of forming a plurality of first electrode layers made of the second metal layer on the front side of the silicon wafer and a plurality of second electrode layers made of the second metal layer on the back side of the silicon wafer by plating the front and back surfaces of the silicon wafer with the passivation layer and the plating resist as masks, respectively. The process of removing the aforementioned plating resist (F), Step (G) of placing first and second solder on each of the plurality of first electrode layers and each of the plurality of second electrode layers, It has, A method for manufacturing a semiconductor device, characterized in that, in a plan view, the plating resist on the back surface of the silicon wafer is positioned to overlap with the grooves of the mesa structure.
7. In claim 6, A method for manufacturing a semiconductor device, characterized by having, after step (G), step (H) of dividing the silicon wafer into a plurality of chips by irradiating the second metal silicide layer exposed on the scribe line on the back surface of the silicon wafer with a chip-dividing laser or making grooves with a dicer, and then performing a breaking process.
8. A1 is a step of forming a PN junction on a silicon wafer by introducing impurities from the front or back side of the silicon wafer, A2 is a step of forming mesa structure grooves on the surface of the silicon wafer, A3 is a step of forming a passivation layer on the inner surface of the groove, A4 is a step of forming a first metal layer on the front and back surfaces of the silicon wafer by plating, Step (B) involves annealing the silicon wafer and the first metal layer to react the silicon with the metal, thereby forming first and second metal silicide layers on the front and back surfaces of the silicon wafer. Step (C) of removing the unreacted first metal layer remaining on the first and second metal silicide layers, Step (D) of forming a plating resist on the scribe line of the second metal silicide layer on the back surface of the silicon wafer, Step (E) of forming a second metal layer on the first metal silicide layer and below the second metal silicide layer, respectively, using the passivation layer and the plating resist as masks on the front and back surfaces of the silicon wafer, Step (G) of forming first and second Au plating layers on the second metal layer using the passivation layer and the plating resist as masks on the front and back surfaces of the silicon wafer, thereby forming a plurality of first electrode layers made of the first Au plating layer on the front surface of the silicon wafer and a plurality of second electrode layers made of the second Au plating layer on the back surface of the silicon wafer, It has, A method for manufacturing a semiconductor device, characterized in that, in a plan view, the plating resist on the back surface of the silicon wafer is positioned to overlap with the grooves of the mesa structure.
9. In claim 8, A method for manufacturing a semiconductor device, characterized by having, after step (G) above, step (H) of removing the plating resist, irradiating the second metal silicide layer exposed on the scribe line on the back surface of the silicon wafer with a chip-dividing laser or making grooves with a dicer, and then performing a breaking process to divide the silicon wafer into a plurality of chips.
10. In claim 8, A method for forming the plating resist in step (D) is characterized by applying it by spraying, printing, or inkjet, and then curing the resist by heat or ultraviolet irradiation.
11. In any one of claims 6 to 10, A method for manufacturing a semiconductor device, characterized in that the groove in step (A2) is formed by cutting with a dicing blade.