Vertical transistor-based multilayer capacitor-less DRAM cell
The vertical transistor-based stacked capacitor-less DRAM cell addresses integration and leakage current issues by minimizing overlap areas and reducing cell collisions, improving electrical performance and integration.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- IND ACADEMIC COOP FOUND YONSEI UNIV
- Filing Date
- 2025-06-24
- Publication Date
- 2026-06-18
AI Technical Summary
Conventional 1-transistor-1-capacitor DRAMs face limitations in integration due to cell-to-cell collisions and leakage current, and vertical transistors have issues with large overlap areas that affect electrical performance.
A vertical transistor-based stacked capacitor-less DRAM cell design featuring first and second vertical transistors with specific configurations, including spacers, sources, drains, channels, and gate electrodes, arranged to minimize overlap areas and reduce leakage current.
The design reduces cell-to-cell collisions, minimizes leakage current, and enhances integration and electrical performance by eliminating overlap areas, allowing for adjustable oxide capacitance and increased retention time.
Smart Images
Figure 2026099719000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a stacked capacitorless DRAM cell based on a vertical transistor base.
[0002] This invention was derived from research conducted as part of the National Semiconductor Laboratory (NSL) core technology development of the Ministry of Science and Technology Information and Communication (Project specific number: 1711197801, Project number: 00256917, Research project name: Development of IGZO V-Tr based high-integration / high-performance capacitorless DRAM technology for next-generation neuromorphic computing systems, Project management agency: Korea Research Foundation, Project implementation agency: Industry-Academia Cooperation Group of Yonsei University, Research period: May 1, 2023 to January 31, 2024). On the other hand, there is no property interest of the Korean government in all aspects of this invention.
Background Art
[0003] 3D DRAM means DRAM having a structure in which planar DRAM cells are stacked in the z-axis direction. Therefore, it is essential to form a channel material as a thin film for each stacked layer on a single crystal silicon substrate that is currently used in the existing 1-transistor-1-capacitor structure. However, in conventional 1-transistor-1-capacitor DRAMs, there are limitations in improving the integration due to cell-to-cell collisions and the generation of leakage current.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The present invention provides a stacked capacitorless DRAM cell based on a vertical transistor base that can reduce cell-to-cell collisions and the generation of leakage current to improve the integration.
[0005] Also, the present invention provides a stacked capacitorless DRAM cell based on a vertical transistor base that can improve the electrical performance of the transistor by minimizing the overlap area that was inevitable in a vertical structure transistor. [Means for solving the problem]
[0006] A vertical transistor-based stacked capacitor-less DRAM cell according to one embodiment of the present invention includes a first vertical transistor and a second vertical transistor, each of which may include a spacer, a source located on the upper surface of the spacer, a drain located adjacent to the lower side of the spacer, a channel located along the upper surface of the drain, the upper side of the spacer and the upper surface of the source, a gate insulator located along the side and top of the channel, and a gate electrode located along the side and top of the gate insulator.
[0007] According to one embodiment, the first vertical transistor and the second vertical transistor can be arranged to face each other.
[0008] According to one embodiment, a write word line can be connected to the gate electrode of the first vertical transistor, a write bit line can be connected to the source of the first vertical transistor, a read word line can be connected to the source of the second vertical transistor, and a read bit line can be connected to the drain of the second vertical transistor.
[0009] According to one embodiment, a storage node can be placed between the drain of the first vertical transistor and the gate electrode of the second vertical transistor.
[0010] According to one embodiment, the spacers of the first vertical transistor and the spacers of the second vertical transistor can each be deposited by ALD or PVD.
[0011] According to one embodiment, each of the channels of the first vertical transistor and the second vertical transistor may include an oxide semiconductor.
[0012] According to one embodiment, the first source, which is the source of the first vertical transistor, and the second source, which is the source of the second vertical transistor, can be positioned on the upper surfaces of the spacers of the first vertical transistor and the second vertical transistor, respectively, such that their lower surfaces do not face the upper surfaces of the first drain, which is the drain of the first vertical transistor, and the second drain, which is the drain of the second vertical transistor.
[0013] According to one embodiment, the first vertical transistor includes a first spacer, a first source located on the upper surface of the first spacer, a first drain located adjacent to the lower side of the first spacer, and a first channel located along the upper surface of the first drain, the upper side of the first spacer, and the upper surface of the first source. The second vertical transistor may include a second spacer, a second source located on the upper surface of the second spacer, a second drain located adjacent to the lower side of the second spacer, and a second channel located along the upper surface of the second drain, the upper side of the second spacer, and the upper surface of the second source.
[0014] According to one embodiment, the first drain and the second drain are positioned at the same height with respect to the ground, the second spacer is configured such that its upper surface is higher than the upper surface of the first spacer with respect to the ground, and the second source can be positioned higher than the first source with respect to the ground.
[0015] According to one embodiment, the first vertical transistor further includes a first gate insulator arranged along the side and top surfaces of the first channel, and a first gate electrode arranged along the side and top surfaces of the first gate insulator, and the second vertical transistor may further include a second gate insulator arranged along the side and top surfaces of the second channel, and a second gate electrode arranged along the side and top surfaces of the second gate insulator.
[0016] A manufacturing method for manufacturing the vertical transistor-based stacked capacitor-less DRAM cell according to one embodiment of the present invention may include the steps of: generating the first spacer by dry etching; generating the second spacer by dry etching; depositing the first drain on the lower side surface of the first spacer; depositing the second drain on the lower side surface of the second spacer; depositing the first source on the upper surface of the first spacer; depositing the second source on the upper surface of the second spacer; depositing the first channel along the upper side surface of the first spacer and the upper surface of the first source; and depositing the second channel along the upper side surface of the second spacer and the upper surface of the second source.
[0017] According to one embodiment, the step of depositing the first drain on the lower side surface of the first spacer includes the step of depositing the first drain on the lower side surface of the first spacer opposite to the side surface of the second spacer, and the step of depositing the second drain on the lower side surface of the second spacer includes the step of depositing the second drain on the lower side surface of the second spacer opposite to the side surface of the first spacer.
[0018] According to one embodiment, the step of generating the second spacer through dry etching includes generating the second spacer such that the upper surface of the second spacer is positioned higher than the upper surface of the first spacer with respect to the ground, and the step of depositing the second source onto the upper surface of the second spacer may include depositing the second source such that the second source is positioned higher than the first source with respect to the ground.
[0019] According to one embodiment, the step of depositing the first channel includes depositing the first channel along the upper part of the side surface of the first spacer facing the side surface of the second spacer and the upper surface of the first source, and the step of depositing the second channel can include depositing the second channel along the upper part of the side surface of the second spacer facing the side surface of the first spacer and the upper surface of the second source.
Advantages of the Invention
[0020] According to some embodiments of the present invention, when the transistor is a read transistor, it can be easy to adjust the oxide capacitance value.
[0021] According to some embodiments of the present invention, it can be easy to reduce the leakage current value of the write transistor in order to prevent charge leakage at the storage node.
[0022] According to some embodiments of the present invention, an effect of increasing the retention time can be expected.
[0023] According to some embodiments of the present invention, since two transistors share a partial region without a capacitor, a high integration degree can be expected.
[0024] According to some embodiments of the present invention, the electrical performance of the transistor can be improved by minimizing the overlap area that was inevitable in the vertical structure transistor.
Brief Description of the Drawings
[0025] [Figure 1] It is a perspective view of a vertical transistor-based stacked capacitorless DRAM cell according to an embodiment of the present invention. [Figure 2] It is a schematic diagram showing the manufacturing process of a vertical transistor-based stacked capacitorless DRAM cell according to an embodiment of the present invention. [Figure 3]FIG. 0 is a side view showing an example in which DRAM cells based on vertical transistors according to an embodiment of the present invention are stacked in two layers. [Figure 4] FIG. 3 is a circuit diagram showing a DRAM cell based on a vertical transistor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION
[0026] Hereinafter, specific contents for implementing the present invention will be described in detail with reference to the accompanying drawings. However, in the following description, when there is a risk of unnecessarily obscuring the gist of the present invention, specific descriptions of widely known functions and configurations will be omitted.
[0027] In the accompanying drawings, the same or corresponding components are given the same reference numerals. Also, in the following description of the embodiments, the description of the same or corresponding components can be omitted from being repeated. However, even if the technology related to the components is omitted, it is not intended that such components are not included in a given embodiment.
[0028] The advantages and features of the disclosed embodiments, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. The mere present embodiments are provided to complete the present disclosure and to fully inform those of ordinary skill in the art of the scope of the invention.
[0029] This specification provides a brief explanation of the terms used herein and a more detailed explanation of the disclosed embodiments. The terms used herein are selected from currently widely used general terms, taking into account the function described herein, but these may change in accordance with the intent of the articulates in the relevant field, case law, the emergence of new technologies, etc. In some cases, the applicant has arbitrarily selected terms, in which case their meaning will be described in detail in the description of the relevant invention. Therefore, the terms used in this disclosure are not simply nouns, but must be defined based on the meaning of the term and the overall content of the invention.
[0030] In this specification, singular expressions include plural expressions unless explicitly identified as singular in context. Similarly, plural expressions include singular expressions unless explicitly identified as plural in context. When a given part of the specification “includes” a given component, this means, unless otherwise explicitly stated, that it may include other components, rather than excluding them.
[0031] Figure 1 is a perspective view of a vertical transistor-based stacked capacitorless DRAM cell 100 according to one embodiment of the present invention.
[0032] Referring to Figure 1, the DRAM cell 100 can include a first vertical transistor 110 and a second vertical transistor 130.
[0033] The first vertical transistor 110 may include a first spacer 112, a first drain 114, a first source 116, a first channel 118, a first gate insulator 122, and a first gate electrode 124.
[0034] The second vertical transistor 130 may include a second spacer 132, a second drain 134, a second source 136, a second channel 138, a second gate insulator 142, and a second gate electrode 144.
[0035] The first channel 118 and the second channel 138 may each contain an oxide semiconductor.
[0036] In this case, the oxide semiconductor may contain, but is not limited to, at least one of InO, SnO, ZnO, InZnO, SnZnO, InSnO, SnMgO, InMgO, AlZnO, ZnMgO, InSnZnO, SnGaZnO, AlGaZnO, SnAlZnO, InAlZnO, InGaZnO, and InSnGaZnO.
[0037] On the other hand, in Figures 1 and 2, for simplification, the structure of a vertical transistor is disclosed based on the first vertical transistor 110. That is, the description of the first vertical transistor 110 in Figures 1 and 2 can be interpreted as being replaced with that of the second vertical transistor 130 and its structure.
[0038] The first vertical transistor 110 may include a first spacer 112 provided on the substrate. Additionally, the first vertical transistor 110 may include a first source 116 positioned on the upper surface of the first spacer 112. Furthermore, the first vertical transistor 110 may include a first drain 114 positioned adjacent to the lower side surface of the first spacer 112. Such a configuration can be designed so that when the first vertical transistor 110 is observed from above, there is no region where the first drain 114 and the first source 116 overlap.
[0039] The first vertical transistor 110 may include a first channel 118 arranged in a z-shape along the top surface of the first drain 114, the upper side surface of the first spacer 112, and the top surface of the first source 116. Additionally, the first vertical transistor 110 may include a first gate insulator 122 arranged in a z-shape along the side and top surfaces of the first channel 118. Similarly, the first vertical transistor 110 may include a first gate electrode 124 arranged in a z-shape along the side and top surfaces of the first gate insulator 122.
[0040] On the other hand, the first vertical transistor 110 and the second vertical transistor 130, having the structure described above, can be arranged to face each other.
[0041] On the other hand, due to the characteristics of the DRAM cell, it is desirable that the channel of the second vertical transistor 130 be even wider than that of the first vertical transistor 110.
[0042] The first drain 114 and the second drain 134 can be positioned at the same height relative to the ground.
[0043] The second spacer 132 can be configured such that its upper surface is positioned higher than the upper surface of the first spacer 112 with respect to the ground.
[0044] The second source 136 can be positioned higher than the first source 116 relative to the ground.
[0045] Figure 2 is a schematic diagram showing the manufacturing process of a vertical transistor-based stacked capacitorless DRAM cell (e.g., DRAM cell 100) according to one embodiment of the present invention.
[0046] In Figure 2, the spacer 210, drain 220, source 230, channel 240, gate insulator 250, and gate electrode 260 can correspond to the first spacer 112, first drain 114, first source 116, first channel 118, first gate insulator 122, and first gate electrode 124 in Figure 1, respectively.
[0047] Additionally, in Figure 2, the spacer 210, drain 220, source 230, channel 240, gate insulator 250, and gate electrode 260 can correspond to the second spacer 132, second drain 134, second source 136, second channel 138, second gate insulator 142, and second gate electrode 144, respectively.
[0048] Referring to Figures 2(a) to (c), a spacer 210 for the DRAM cell can be generated by dry etching, and a drain 220 and a source 230 can be deposited on the lower and upper sides of the spacer 210, respectively.
[0049] Referring to (d) through (f), a z-shaped channel 240 can be deposited along the upper surface of the drain 220, the upper side of the spacer 210, and the upper surface of the source 230, and similarly, a z-shaped gate insulator 250 and gate electrode 260 can be deposited.
[0050] A manufacturing method for producing a vertical transistor-based stacked capacitor-less DRAM cell 100 may include the steps of: generating a first spacer 112 by dry etching; generating a second spacer 132 by dry etching; depositing a first drain 114 on the lower side surface of the first spacer 112; depositing a second drain 134 on the lower side surface of the second spacer 132; depositing a first source 116 on the upper surface of the first spacer 112; depositing a second source on the upper surface of the second spacer 132; depositing a first channel 118 along the upper side surface of the first spacer 112 and the upper surface of the first source 116; and depositing a second channel 138 along the upper side surface of the second spacer 132 and the upper surface of the second source.
[0051] Depositing the first drain 114 onto the lower side surface of the first spacer 112 may mean depositing the first drain 114 onto the lower side surface of the first spacer 112 that faces the side surface of the second spacer 132.
[0052] Furthermore, depositing the second drain 134 on the lower side surface of the second spacer 132 may mean depositing the second drain 134 on the lower side surface of the second spacer 132 that faces the side surface of the first spacer 112.
[0053] On the other hand, generating the second spacer 132 through dry etching may involve generating the second spacer 132 such that its upper surface is higher than the upper surface of the first spacer 112 relative to the ground.
[0054] Depositing the second source onto the upper surface of the second spacer 132 may involve depositing the second source such that it is positioned higher than the first source 116 with respect to the ground.
[0055] Depositing the first channel 118 may involve depositing the first channel 118 along the upper side surface of the first spacer 112 facing the side surface of the second spacer 132 and along the upper surface of the first source 116.
[0056] Furthermore, depositing the second channel 138 may involve depositing the second channel 138 along the upper side surface of the second spacer 132 facing the side surface of the first spacer 112 and along the upper surface of the second source 136.
[0057] On the other hand, in a vertical transistor, the width (i.e., horizontal length) and height (i.e., vertical length) of the side of the spacer 210 can be freely deformed. Furthermore, when observing the vertical transistor from above, it can be designed so that there is no region where the drain 220 and source 230 overlap. Therefore, if the transistor in question is a read transistor, the oxidation capacitance value can be easily adjusted. In addition, in a storage node (described later in Figure 3), it is easy to lower the leakage current value of the write transistor to prevent charge leakage. This can also lead to the effect of increasing the retention time.
[0058] Specifically, the first source 116 can be positioned on the upper surface of the first spacer 112 such that its lower surface is not facing the upper surface of the first drain 114.
[0059] The second source 136 can be positioned on the upper surface of the second spacer 132 such that its lower surface is not facing the upper surface of the second drain 134.
[0060] In other words, when observing the vertical transistor from above, there is no region where the drain 220 and source 230 overlap. Therefore, a vertical transistor-based DRAM cell 100 according to one embodiment can improve the electrical performance of the transistor by minimizing the overlap area that inevitably occurs in vertically structured transistors.
[0061] Conventional vertical-structured elements inevitably suffer from the problem of a large overlap area (OA), which increases the electric field in the z-axis direction applied to the channel. In other words, conventional vertical-structured elements have the problem of not being able to form a normal accumulation layer in the channel. However, the vertical transistor-based DRAM cell 100 manufactured through the manufacturing process according to one embodiment eliminates the overlap area (OA) due to its structure, and phenomena such as the increase in subthreshold swing (SS) caused by the overlap area (OA) can be avoided.
[0062] Figure 3 is a side view illustrating an example of a vertical transistor-based DRAM cell (e.g., DRAM cell 100) according to one embodiment of the present invention, stacked in two layers. As shown, a write bit line 310 can be connected to the first source 116, and a write word line 320 can be connected to the first gate electrode 124. Similarly, a read word line 350 can be connected to the second source 136, and a read bit line 340 can be connected to the second drain 134. Additionally, a storage node 330 can be placed between the first drain 114 and the second gate electrode.
[0063] Figure 4 is a circuit diagram showing a vertical transistor-based DRAM cell (e.g., DRAM cell 100) according to one embodiment of the present invention. Here, “Writing CVV-Tr” and “Reading CVV-Tr” can correspond to either a first vertical transistor (e.g., first vertical transistor 110) or a second vertical transistor (e.g., second vertical transistor 130), respectively. That is, if the first vertical transistor 110 is “Writing CVV-Tr”, then the second vertical transistor 130 is “Reading CVV-Tr”, and if the first vertical transistor 110 is “Reading CVV-Tr”, then the second vertical transistor 130 may be “Writing CVV-Tr”. Referring to Figure 4, the source of the Writing CVV-Tr is connected to the gate of the Reading CVV-Tr, and the two transistors share a portion of the region without a capacitor, which has the advantage of being able to achieve a high degree of integration.
[0064] The prior description of the present invention is provided to enable a person of ordinary skill to practice or utilize the present invention. Various modifications of the present invention are readily apparent to a person of ordinary skill, and the general principles defined herein may be applied to various modifications without departing from the spirit or scope of the present invention. Accordingly, the present invention is not intended to be limited to the examples described herein, but is intended to be given the broadest possible scope consistent with the principles and novel features disclosed herein.
[0065] While exemplary embodiments may be noted as utilizing aspects of the subject now introduced in the context of one or more standalone computer systems, the subject is not thus limited and can rather be embodied in any computing environment that is identical to a network or distributed computing environment. Furthermore, aspects of the subject now disclosed can be embodied across multiple processing chips, devices, or therein, and storage can similarly be affected across multiple devices. Such devices may include PCs, network servers, and handheld devices.
[0066] While this disclosure has been described in relation to some embodiments, it should be noted that various modifications and alterations can be made without departing from the scope of the invention as understandable to an ordinary person skilled in the art. Such modifications and alterations should be construed as falling within the scope of the claims appended herein. [Explanation of symbols]
[0067] 100 DRAM cells 110 First Vertical Transistor 112 First Spacer 114 Drain 1 116 First Source 118 Channel 1 122 First gate insulator 124 First Gate 130 Second Vertical Transistor 132 Second Spacer 134 Drain No. 2 136 Second Source 138 Channel 2 142 Second gate insulator 144 Second Gate
Claims
1. First vertical transistor and, Includes a second vertical transistor, Each of the first vertical transistor and the second vertical transistor is, Spacer and, A source positioned on the upper surface of the spacer, A drain positioned adjacent to the lower side of the spacer, A channel arranged along the upper surface of the drain, the upper side of the spacer, and the upper surface of the source, A gate insulator is arranged along the side and top surfaces of the channel, A gate electrode arranged along the side surface and the top surface of the gate insulator, A vertical transistor-based, multilayer capacitor-less DRAM cell, including [specific component].
2. The vertical transistor-based stacked capacitor-less DRAM cell according to claim 1, wherein the first vertical transistor and the second vertical transistor are arranged to face each other.
3. A write word line is connected to the gate electrode of the first vertical transistor. A write bit line is connected to the source of the first vertical transistor. The read word line is connected to the source of the second vertical transistor. A vertical transistor-based stacked capacitor-less DRAM cell according to claim 1, wherein a read bit line is connected to the drain of the second vertical transistor.
4. A vertical transistor-based stacked capacitor-less DRAM cell according to claim 3, wherein a storage node is arranged between the drain of the first vertical transistor and the gate electrode of the second vertical transistor.
5. The vertical transistor-based stacked capacitor-less DRAM cell according to claim 1, wherein each of the spacers of the first vertical transistor and the second vertical transistor is deposited by ALD or PVD.
6. The vertical transistor-based stacked capacitor-less DRAM cell according to claim 1, wherein each of the channels of the first vertical transistor and the second vertical transistor comprises an oxide semiconductor.
7. The aforementioned oxide semiconductor is A vertical transistor-based stacked capacitor-less DRAM cell according to claim 6, comprising at least one of InO, SnO, ZnO, InZnO, SnZnO, InSnO, SnMgO, InMgO, AlZnO, ZnMgO, InSnZnO, SnGaZnO, AlGaZnO, SnAlZnO, InAlZnO, InGaZnO, and InSnGaZnO.
8. The first source, which is the source of the first vertical transistor, and the second source, which is the source of the second vertical transistor, A stacked capacitor-less DRAM cell with a vertical transistor base according to claim 1, wherein the spacers of the first vertical transistor and the second vertical transistor are positioned such that their lower surfaces do not face the upper surfaces of the first drain, which is the drain of the first vertical transistor, and the second drain, which is the drain of the second vertical transistor.
9. The first vertical transistor is, First spacer and, A first source is positioned on the upper surface of the first spacer, A first drain is positioned adjacent to the lower side surface of the first spacer, The first channel includes, which is positioned along the upper surface of the first drain, the upper side of the first spacer, and the upper surface of the first source, The second vertical transistor is, The second spacer, A second source positioned on the upper surface of the second spacer, A second drain is positioned adjacent to the lower side surface of the second spacer, A vertical transistor-based stacked capacitor-less DRAM cell according to claim 1, comprising a second channel positioned along the upper surface of the second drain, the upper side of the second spacer, and the upper surface of the second source.
10. The first drain and the second drain are They are arranged at the same height relative to the ground, The aforementioned second spacer is The upper surface is configured to be higher than the upper surface of the first spacer with respect to the ground, The aforementioned second source is, A vertical transistor-based stacked capacitor-less DRAM cell according to claim 9, positioned higher than the first source with respect to the ground.
11. The first vertical transistor is, A first gate insulator is arranged along the side and top surfaces of the first channel, The present invention further includes a first gate electrode disposed along the side and top surfaces of the first gate insulator, The second vertical transistor is, A second gate insulator is arranged along the side and top surfaces of the second channel, The vertical transistor-based stacked capacitor-less DRAM cell according to claim 9, further comprising a second gate electrode disposed along the side and top surfaces of the second gate insulator.
12. A manufacturing method for producing a vertical transistor-based stacked capacitor-less DRAM cell according to claim 9, A step of generating the first spacer by dry etching, A step of generating the second spacer by dry etching, The steps include depositing the first drain onto the lower side surface of the first spacer, The steps include depositing the second drain onto the lower side surface of the second spacer, The steps include depositing the first source onto the upper surface of the first spacer, The steps include depositing the second source onto the upper surface of the second spacer, A step of depositing the first channel along the upper side surface of the first spacer and the upper surface of the first source, A method for manufacturing a vertical transistor-based stacked capacitor-less DRAM cell, comprising the step of depositing the second channel along the upper side surface of the second spacer and the upper surface of the second source.
13. The step of depositing the first drain onto the lower side surface of the first spacer is as follows: The process includes the step of depositing the first drain onto the lower part of the side surface of the first spacer that is opposite to the side surface of the second spacer, The step of depositing the second drain onto the lower side surface of the second spacer is as follows: A method for manufacturing a vertical transistor-based stacked capacitor-less DRAM cell according to claim 12, further comprising the step of depositing the second drain on the lower part of the side surface of the second spacer that faces the side surface of the first spacer.
14. The step of generating the second spacer through the dry etching is as follows: The step includes generating the second spacer such that the upper surface of the second spacer is positioned higher than the upper surface of the first spacer with respect to the ground, The step of depositing the second source onto the upper surface of the second spacer is: A method for manufacturing a vertical transistor-based stacked capacitor-less DRAM cell according to claim 13, comprising the step of depositing the second source such that the second source is positioned higher than the first source with respect to the ground.
15. The step of depositing the first channel is: The process includes the step of depositing the first channel along the upper side of the first spacer that is opposite to the side of the second spacer and along the upper surface of the first source, The step of depositing the second channel is as follows: A method for manufacturing a vertical transistor-based stacked capacitor-less DRAM cell according to claim 14, comprising the step of depositing the second channel along the upper side of the second spacer facing the side of the first spacer and along the upper surface of the second source.