Vertical gallium nitride transistor

Abstract

In relation to vertical power semiconductor devices, we provide, in particular, gallium nitride (GaN) power semiconductor devices. [Solution] The vertical GaNFET includes cylindrical trench gates 105b, 106b, 106c arranged in a hexagonal configuration to form a vertical FET channel 114. The surface of the vertical GaNFET has a source layer 204 formed within a GaN epitaxial layer 113 and above the GaN substrate. The channel is formed between the cylindrical gates in the form of a "GaN pillar," and the FET characteristics, including the threshold voltage, are at least partially determined by the trench nearest neighbor distance. Thus, the trench nearest neighbor distance is selected so that the vertical GaNFET operates as an enhancement or depletion transistor.

Description

Technical Field

[0001] Cross - reference to related applications

[0001] This application claims priority from U.S. Provisional Patent Application No. 63 / 728,947, filed on December 6, 2024, the entire content of which is incorporated herein by reference.

[0002]

[0002] The present invention relates to vertical power semiconductor devices, and more particularly to gallium nitride (GaN) power semiconductor devices.

Background Art

[0003]

[0003] Gallium nitride (GaN) and other wide - bandgap group - III nitride - based direct - bandgap semiconductor materials exhibit high breakdown electric fields and can utilize high current densities. In this regard, GaN - based semiconductor devices are actively being studied as alternatives to silicon - based semiconductor devices in power and high - frequency applications. For example, GaN power devices can provide lower specific on - resistance while having a higher breakdown voltage than silicon power field - effect transistors of the same area.

[0004]

[0004] A field - effect transistor (FET) including a power FET can be either an enhancement - type or a depletion - type. An enhancement - type device can represent a transistor (e.g., a field - effect transistor) that blocks current (i.e., is off) when no gate bias is applied (i.e., when the gate - to - source bias is zero). In contrast, a depletion - type device can represent a transistor that conducts current (i.e., is on) when the gate - to - source bias is zero.

[0005]

[0005] A field effect transistor (FET) can be formed such that current is conducted laterally between a drain and a source separated on the device surface. Examples of lateral GaN FETs include high electron mobility transistors (HEMTs) that can utilize high conductivity due to a two-dimensional electron gas (2DEG) formed between a GaN layer and an aluminum gallium nitride (AlGaN) layer.

[0006]

[0006] Alternatively, an FET can be further formed such that current is conducted vertically between a drain at the bottom of the device and a source on the device surface. Examples of vertical GaN FETs include current aperture vertical electron transistors (CAVETs), trench metal-oxide field effect transistors (MOSFETs), and fin field effect transistors (FinFETs).

Summary of the Invention

Problems to be Solved by the Invention

[0007]

[0007] State-of-the-art GaN HEMTs have a low specific on-resistance defined by the product of resistance and device area (e.g., milliohm square centimeters) and achieve a high breakdown voltage (e.g., kilovolts). However, a drawback of GaN HEMTs is the phenomenon of "current collapse" that causes an undesirable dynamic increase in on-resistance. Further, in applications that require a higher breakdown voltage (e.g., 2 kilovolts), vertical GaN FETs are an attractive alternative to lateral GaN HEMTs because vertical GaN transistors can provide a lower specific on-resistance, a higher breakdown voltage, and better device reliability.

[0008]

[0008] As described above, development of vertical GaN power FETs, including CAVETs, trench MOSFETs, and FinFETs, has progressed. Unfortunately, CAVETs, trench MOSFETs, and FinFETs involve complex processing steps. For example, CAVETs and trench MOSFETs require the formation of a p-type GaN layer, which can be difficult to process reliably. Furthermore, while FinFETs can be manufactured without p-type GaN, the resulting narrow fins, typically between 0.18 micrometers (0.18um) and 0.4 micrometers (0.4um), can be difficult to manufacture reliably and require costly manufacturing techniques (e.g., electron beam lithography).

[0009]

[0009] Therefore, there is a need to develop a vertical GaN transistor suitable as a power FET that is not limited by the current state-of-the-art technologies of CAVET, trench MOSFET, and FinFET. [Means for solving the problem]

[0010]

[0010] This disclosure describes a novel vertical GaN transistor (i.e., vertical GaN FET) that is different from CAVET, trench MOSFET, and FinFET. As taught herein, a vertical GaN FET includes a cylindrical trench gate composed of a hexagonal arrangement for forming a vertical FET channel. On the surface of the vertical GaN FET is a source layer formed above the GaN substrate within a GaN epitaxial layer. The channel may be formed between the cylindrical gates in the form of a "GaN pillar," and the FET characteristics, including the threshold voltage, may be determined at least in part by the trench nearest neighbor distance. Thus, the trench nearest neighbor distance may be selected so that the vertical GaN FET operates as an enhancement or depletion transistor.

[0011]

[0011] Non-limiting and non-exclusive embodiments of the vertical gallium nitride transistor are described below with reference to the figures, and similar reference numerals indicate the same parts throughout the various drawings unless otherwise specified. [Brief explanation of the drawing]

[0012] [Figure 1A]

[0012] Figure 1A shows a cross-sectional perspective view of a vertical GaN transistor according to an embodiment. [Figure 1B]

[0013] Figure 1B shows a two-dimensional (2D) plan view of the vertical GaN transistor shown in Figure 1A. [Figure 1C]

[0014] Figure 1C shows another two-dimensional (2D) plan view of the vertical GaN transistor shown in Figure 1A. [Figure 2]

[0015] Figure 2 shows a three-dimensional (3D) side perspective view of a vertical GaN transistor. [Figure 3A]

[0016] Figure 3A shows a two-dimensional (2D) cross-sectional view of a portion of the vertical GaN transistor shown in Figure 2. [Figure 3B]

[0017] Figure 3B shows a plot of doping concentrations according to the embodiment shown in Figure 3A. [Figure 4]

[0018] Figure 4 shows another three-dimensional (3D) side perspective view of a vertical GaN transistor. [Figure 5A]

[0019] Figure 5A shows a two-dimensional (2D) cross-sectional view of a vertical GaN transistor. [Figure 5B]

[0020] Figure 5B shows another two-dimensional (2D) cross-sectional view of a vertical GaN transistor. [Figure 6]

[0021] Figure 6 shows the drain current transfer curve obtained from the simulation. [Figure 7A]

[0022] Figure 7A shows a cross-section corresponding to the first transfer curve in Figure 6. [Figure 7B]

[0023] Figure 7B shows a cross-section corresponding to the second transfer curve in Figure 6. [Figure 7C]

[0024] Figure 7C shows a cross-section corresponding to the third transfer curve in Figure 6. [Figure 7D]

[0025] Figure 7D shows a cross-section corresponding to the fourth transfer curve in Figure 6. [Figure 7E]

[0026] Figure 7E shows a cross-section corresponding to the fifth transfer curve in Figure 6. [Figure 8]

[0027] Figure 8 shows another three-dimensional (3D) side perspective view of a vertical GaN transistor. [Figure 9]

[0028] Figure 9 shows a plot of the electric field according to the embodiment shown in Figure 8. [Figure 10]

[0029] Figure 10 shows the drain current transfer curve obtained from the simulation. [Figure 11]

[0030] Figure 11 shows a cross-section corresponding to the transfer curve in Figure 10. [Figure 12A]

[0031] Figure 12A shows a two-dimensional (2D) cross-sectional view according to the embodiment shown in Figure 10. [Figure 12B]

[0032] Figure 12B shows the transition curve of electron density according to the embodiment of Figure 10. [Figure 13A]

[0033] Figure 13A shows a cross-section of a vertical GaN transistor. [Figure 13B]

[0034] Figure 13B shows the transfer curve according to the embodiment shown in Figure 13A. [Figure 13C]

[0035] Figure 13C shows a further transfer curve according to the embodiment shown in Figure 13A. [Figure 14]

[0036] Figure 14 shows a cross-sectional perspective view of a vertical GaN transistor according to another embodiment. [Figure 15A]

[0037] Figure 15A shows a two-dimensional (2D) cross-sectional view of the vertical GaN transistor shown in Figure 14. [Figure 15B]

[0038] Figure 15B shows an enlarged view corresponding to Figure 15A. [Figure 15C]

[0039] Figure 15C shows a plot of electron density corresponding to the cross-section in Figure 15A. [Figure 16]

[0040] Figure 16 shows the transfer curve according to the embodiment shown in Figure 14. [Figure 17]

[0041] Figure 17 shows the transition curve of electron density according to the embodiment shown in Figure 16. [Figure 18A]

[0042] Figure 18A shows another two-dimensional (2D) cross-sectional view of the vertical GaN transistor shown in Figure 14. [Figure 18B]

[0043] Figure 18B shows a plot of the electric field according to the embodiment shown in Figure 18A. [Modes for carrying out the invention]

[0013]

[0044] In the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will understand that the elements in the drawings are drawn to be concise and clear, and not necessarily to a constant scale. For example, the dimensions of some elements and layers in the drawings may be exaggerated compared to others to help understand the various embodiments of the teachings herein. Furthermore, common but well-understood elements, layers, and / or process steps that are useful or necessary in commercially viable embodiments are often omitted to avoid obscuring the drawings of these various embodiments of vertical gallium nitride transistors.

[0014]

[0045] The following description includes many specific details to provide a thorough understanding of vertical gallium nitride transistors. However, it will be apparent to those skilled in the art that not all specific details will necessarily be used to carry out the teachings herein. In other examples, well-known materials or methods are not described in detail so as not to obscure this disclosure.

[0015]

[0046] Figure 1A shows a cross-sectional perspective view of a vertical GaN transistor 100 according to an embodiment. The vertical GaN transistor 100 includes cylindrical trench gates 105a-c and 106a-c formed on its surface. The cylindrical trench gates 105a-c and 106a-c may be covered with a gate dielectric 112 (e.g., oxide) and filled with a gate electrode 111 (e.g., polycrystalline silicon and / or metal).

[0016]

[0047] According to the teachings herein, the cylindrical trench gates 105a-c, 106a-c can be patterned (i.e., arranged) in a hexagonal arrangement when viewed from above the surface. According to solid-state physics, the two-dimensional hexagonal arrangement can also be characterized by triangular unit cells, and as a result, the cylindrical trench gates 105b, 106b, 106c form triangular unit cells 117.

[0017]

[0048] Figure 1B shows a two-dimensional (2D) plan view of the vertical GaN transistor 100 of Figure 1A. The 2D plan view shows the arrangement of the cylindrical trench gates 105b, 106b, and 106c. Based on their proximity, the cylindrical trench gates 105b, 106b, and 106c can be called the "nearest neighbors." As already described in relation to Figure 1A, the cylindrical trench gates 105b, 106b, and 106c form a triangular unit cell 117 and can be further characterized as part of the hexagonal arrangement shown in Figure 1C.

[0018]

[0049] Figure 1C further shows a two-dimensional (2D) plan view of the vertical GaN transistor 100 of Figure 1A. The 2D plan view of Figure 1C shows the arrangement of the cylindrical trench gates 105a-e, 106a-f, and 107a-e, and as already described in relation to Figures 1A-B, the cylindrical trench gates 105b, 106b, and 106c form a triangular unit cell 117. Furthermore, according to the teachings herein, due to their proximity, the cylindrical trench gates 105b, 106b, and 106c of the triangular unit cell 117 may also be called the "closest adjacent ones".

[0019]

[0050] Alternatively and additionally, the cylindrical trench gates 105d~e, 106d~f, and 107d~e further form a hexagonal unit cell 118, with the cylindrical trench gate 106e located at its center. Therefore, based on their proximity, the cylindrical trench gates 105d~e, 106d, 106f, and 107d~e may be the closest to and adjacent to the cylindrical trench gate 106e.

[0020]

[0051] Figure 2 shows a three-dimensional (3D) side perspective view of the vertical GaN transistor 100. The 3D side perspective view shows a portion of the vertical GaN transistor 100, including the cylindrical trench gates 105b, 106b, and 106c. As described above, the cylindrical trench gates 105b, 106b, and 106c may be the closest adjacent ones that form a triangular unit cell 117. Doping concentrations may be drawn according to the legend for doping concentrations 202, and the coordinates are defined with respect to the Cartesian coordinate axes 201.

[0021]

[0052] As taught herein, cylindrical trench gates 105b, 106b, and 106c may be formed extending from the surface into the channel epitaxy layer 114 and above the drift epitaxy layer 113. For example, the cylindrical trench gates 105b, 106b, and 106c may extend over 2 micrometers (2 μm) into the channel epitaxial layer 114. The channel epitaxy (epi) layer 114 and the drift epitaxial layer 113 may be GaN epitaxial layers with different n-type doping concentrations. The source layer 204 may be a highly doped n-type layer formed on the surface. Furthermore, the channel epitaxial layer 114, including the source layer 204, may form "GaN pillars" between the cylindrical trench gates 105b, 106b, and 106c.

[0022]

[0053] Figure 3A shows a two-dimensional (2D) cross-sectional view of a portion of the vertical GaN transistor 100 shown in Figure 2. The 2D cross-sectional view shows a cross-section of the vertical GaN transistor 100 in the XZ plane defined by the Cartesian coordinate axes 201. Coordinate values ​​in micrometers are shown for both the X and Z axes. The source layer depth 309 may be the depth to which the source layer 204 extends from the surface of the vertical GaN transistor 100 into the channel epitaxial layer 114. As shown, the source layer depth 309 may be shown to 12 micrometers (12 μm) from the surface of the vertical GaN transistor 100.

[0023]

[0054] Distance D1 may be the distance that the channel epitaxial layer 114 extends beyond the bottoms of the cylindrical trench gates 105b and 106b to the junction 307 (i.e., the drift-to-trench-bottom distance). Distance D1 may be 0.5 micrometers (0.5 μm), and the junction 307 may be the location where epitaxial doping transitions. For example, the junction 307 may be located at a steep junction where the doping concentration transitions from a lower concentration in the channel epitaxial layer 114 to a higher concentration in the drift epitaxial layer 113.

[0024]

[0055] The trench nearest neighbor distance D4 is the GaN mesa width (shortest distance) between adjacent cylindrical trench gates (for example, between cylindrical trench gate 105b and cylindrical trench gate 106b). The trench nearest neighbor distance D4 can be 0.2 micrometers (0.2 μm).

[0025]

[0056] The sidewall thickness 305 can be the length of the sidewall where the gate dielectric 112 extends beyond the gate electrode 111. The sidewall thickness 305 can be between 0.02 micrometers (0.02 μm) and 0.1 micrometers (0.1 μm).

[0026]

[0057] The dielectric thickness of 306 could be the thickness of the bottom oxide.

[0027]

[0058] According to semiconductor device physics, the threshold voltage of a vertical GaN transistor 100 may depend at least partially on the sidewall thickness 305, the doping concentration of the channel epitaxial layer 114, and / or the work function of the gate electrode 111. In a vertical GaN transistor 100 rated at 1200 volts, the channel epitaxial layer 114 has a doping concentration of 2 × 10⁻¹⁶. 15 cm -3 (2e15cm -3 The doping concentration may be . The gate electrode 111 may be a highly doped p-type polycrystalline silicon (P+poly) with a work function of 5.1 electron volts (5.1 eV). Furthermore, the dielectric thickness 306 may be 0.5 micrometers (0.5 μm).

[0028]

[0059] As taught herein, using a triangular unit cell 117 layout of cylindrical trench gates 105b, 106b, and 106c can be beneficially achieved in realizing a vertical GaN transistor 100 with superior complexity. For example, the cylindrical trench gates can be processed without the need for electron beam lithography.

[0029]

[0060] FIG. 3B shows a plot 303 of doping concentration according to the embodiment of FIG. 3A. Referring to FIG. 3A, the plot 303 can be at (corresponding to) an X-axis coordinate value of 1 micrometer (1 um). The Z-axis value can span from a negative coordinate value to a positive coordinate value and pass through the source layer 204. The doping concentration can be n-type and, in equilibrium, can further correspond to the equilibrium carrier concentration.

[0030]

[0061] As shown, zero (0) of the Z-axis coordinate can define the position of the GaN substrate surface. As can be understood by those skilled in the art, the epitaxy and the epitaxial layer (e.g., the drift epitaxial layer 113) can be grown on a GaN substrate having a doping concentration higher than that of the drift epitaxial layer 113. The channel length D2 can be the thickness of the channel epitaxial layer 114 between the source layer and the junction 307 (at z = 12 um). The channel length D2 can be 2.5 micrometers (2.5 um). Z-axis coordinates less than zero can correspond to the GaN substrate and be located within the GaN substrate.

[0031]

[0062] The GaN substrate can function as the drain of the vertical GaN transistor 100. The doping concentration of the GaN substrate can be higher than 1×10 19 cm -3 (1e19 cm -3 ). For example, the GaN substrate can have a doping concentration of 3×10 19 cm -3 (3e19 cm -3 ). The doping concentration (carrier concentration) of the channel epitaxial layer 114 can be between 1×10 15 cm -3 (1e15 cm -3 ) and 5×10 15 cm -3 (5e15 cm -3 ). The doping concentration (carrier concentration) of the source layer 204 can be between 9×10 17 cm -3 (9e17 cm -3 ) and 2×10 18 cm -3 (2e18 cm -3) between approximately 1 × 10 18 cm -3 (1e18cm -3 ) could be the order.

[0032]

[0063] The thickness D3 of the drift epitaxial layer may be the thickness of the drift epitaxial layer 113 extending between the junction 307 and the Z-axis coordinate of zero (z=0). The thickness D3 of the drift epitaxial layer may be 9.5 micrometers (9.5 μm). The doping concentration (carrier concentration) of the drift epitaxial layer 113 is 9 × 10⁻¹⁰ 15 cm -3 (9e15cm -3 ) from 2 × 10 16 cm -3 (2e16cm -3 ) between approximately 1 × 10 16 cm -3 (1e16cm -3 The order of magnitude may be . The carrier concentration (doping concentration) plot 303 shows a steep transition in the distribution (profile) at coordinates z=0, 12 and at the junction 307, but other distributions are also possible. For example, instead of a steep transition, the doping concentration (carrier concentration) may be sloped, with a more gradual and relatively less steep slope at coordinates z=0, 12 and at the junction 307.

[0033]

[0064] Figure 4 shows another three-dimensional (3D) side perspective view of the vertical GaN transistor 100. Unlike that of Figure 2, the 3D side perspective view further includes cross-sections 401 and 402. Cross-section 401 includes (through) the drift epitaxial layer 113. Cross-section 402 may be parallel to cross-section 401 and includes (through) the cylindrical trench gates 105b, 106b, and 106c.

[0034]

[0065] Figure 5A shows a two-dimensional (2D) cross-sectional view of the vertical GaN transistor 100 along the cross-section 401. The cross-section 401 may include the XY plane (i.e., the X and Y axis coordinates) at a fixed Z-axis coordinate and show the doping concentration of the drift epitaxial layer 113 corresponding to that fixed Z-axis coordinate. For example, the doping concentration is a uniform value of 1 × 10⁻⁶ 16 cm -3 (1e16cm -3 ) is possible.

[0035]

[0066] Figure 5B shows another two-dimensional (2D) cross-sectional view of the vertical GaN transistor 100 along the cross-section 402. The cross-section 402 may correspond to the Z-axis coordinate of the channel epitaxial layer 114, which further includes cylindrical trench gates 105b, 106b, and 106c. Along the cross-section 402, the doping in the cylindrical trench gates 105b, 106b, and 106c may differ from the doping in the channel epitaxial layer 114.

[0036]

[0067] As described above, the trench nearest neighbor distance D4 can be the (shortest) distance between adjacent cylindrical trench gates (e.g., between adjacent cylindrical trench gates 105b and 106b) and can be 0.2 micrometers (0.2 μm). Furthermore, as illustrated, distance D5 can be the widest distance on the cross-section 402 of the channel epitaxial layer 114 confined between cylindrical trench gates 105b, 106b, and 106c. For example, distance D5 can be 0.9 micrometers (0.9 μm), while nearest neighbor distance D4 is 0.2 micrometers (0.2 μm).

[0037]

[0068] Therefore, as can be seen from the 2D cross-sectional view on the cross-section 402, the channel epitaxial layer 114 forms a wedge with a width varying between 0.2 μm (nearest neighbor distance D4) and 0.9 μm (distance D5). As taught herein, the formation of the wedge between the cylindrical trench gates 105b, 106b, and 106c may enable the realization of a vertical GaN transistor 100 with excellent and low complexity.

[0038]

[0069] Figure 6 shows the simulated drain current transfer curves 601-605 in amperes (amps), and Figures 7A-7E show the corresponding cross-sections 701-705 for transfer curves 601-605, respectively. The drain current is plotted as a function of the gate-source voltage VGS in volts against the value of the nearest neighbor distance D4, which decreases monotonically as shown by the cross-sections 701-705. For example, cross-section 701 may correspond to a nearest neighbor distance D4 equal to 1 micrometer (1 μm). Cross-section 702 may correspond to a nearest neighbor distance D4 equal to 0.8 micrometers (0.8 μm). Cross-section 703 may correspond to a nearest neighbor distance D4 equal to 0.6 micrometers (0.6 μm). The cross section 704 may correspond to a nearest neighbor distance D4 equal to 0.6 micrometers (0.4 μm), and the cross section 705 may correspond to a nearest neighbor distance D4 equal to 0.2 micrometers (0.2 μm). The drain-to-source voltage VDS may be 1 volt (1 V). The relative on-resistance Rsp is approximately 1 milliohm-square centimeter (mΩ·cm). 2 ) can be such. For example, the relative on-resistivity Rsp is 1.06 milliohms per square centimeter (1.06 mΩ·cm). 2 ) is possible.

[0039]

[0070] According to semiconductor device practices, the threshold voltage of a field-effect transistor can be quantified by measuring the gate-source voltage VGS with a specified fixed drain current. For example, the threshold voltage Vth is 1 × 10⁻⁶. -11 It can be defined based on a current of (1e-11) amperes. Therefore, as the nearest neighbor distance D4 decreases, the threshold voltage Vth can increase. Thus, as shown in transfer curves 601-605, the threshold voltage Vth increases from negative to positive values ​​in the range from -1 volt (-1V) to positive 1 volt (1V), as defined above.

[0040]

[0071] Furthermore, according to semiconductor device practices, a negative threshold voltage Vth may correspond to depletion-type operation, while a positive threshold voltage Vth may correspond to enhancement-type operation. Therefore, as the spacing between the cylindrical trench gates 105b, 106b, and 106c decreases (i.e., as the nearest neighbor distance D4 decreases), the threshold voltage increases from a negative value to a positive value.

[0041]

[0072] Therefore, the threshold voltage and operating mode (depletion type, enhancement type) can be determined at least partially by the nearest neighbor distance D4. As taught herein, the vertical GaN transistor 100 can be enhancement type (i.e., have a threshold voltage greater than zero) or depletion type (i.e., have a threshold voltage less than zero) at least partially based on the nearest neighbor distance D4. Furthermore, the subthreshold slope, which is a quantity corresponding to the slope of the transfer curves 601-605, can be determined at least partially by the sidewall thickness 305.

[0042]

[0073] Figure 8 shows another three-dimensional (3D) side perspective view of the vertical GaN transistor 100. The 3D side perspective view is similar to that of Figure 2, except that it shows the electric field profile instead of the doping concentration. The electric field may be due to the applied drain-to-source voltage VDS. For example, the applied drain-to-source voltage VDS may be 1500 volts (1500 V). The electric field may be defined in relation to the legend of electric fields 802 and has units of volts per centimeter (V / cm).

[0043]

[0074] Figure 9 shows a plot of the electric field 901 according to the embodiment of Figure 8. The applied drain-to-source voltage VDS can be 1500V. The electric field increases monotonically from the substrate surface at the Z-axis coordinate (z=0), which is equal to zero, and is maximum within the gate dielectric 112 (around z=10um).

[0044]

[0075] Figure 10 shows the simulated drain current transfer curve 1001 in amperes as a function of the gate-to-source voltage VGS in volts. The applied drain-to-source voltage VDS can be 1 volt (1 V). The dielectric 112 can be an oxide. The sidewall thickness 305 can be 0.1 micrometers (0.1 μm). The doping concentration in the channel epitaxial layer 114 is the n-type concentration of 2 × 10⁻¹⁶. 15 cm -3 (2e15cm -3 The threshold voltage Vth, calculated using a simulation based on the slope of the subthreshold region, may be greater than 1 volt. For example, the threshold voltage Vth, calculated using a simulation based on the slope of the subthreshold region, may be equal to 1.3 volts (1.3 V). Furthermore, the calculated relative on-resistance Rsp is 1.06 milliohms per square centimeter (1.06 mΩ·cm). 2 It can be equivalent to ).

[0045]

[0076] Figure 11 shows a cross-section 1101 corresponding to the transfer curve 1001. Cross-section 1101 may be in the XY plane of the vertical GaN transistor 100. Similar to cross-sections 701-705, cross-section 1101 includes the cylindrical trench gates 105b, 106b, 106c and the channel epitaxial layer 114. The drain-to-source voltage VDS may be 1 volt (1V). The gate-to-source voltage VGS may be equal to 1.5 volts (1.5V). Under these conditions (i.e., drain-to-source voltage VDS = 1V, gate-to-source voltage VGS = 1.5V), the carrier concentration is approximately 1 × 10⁻¹⁶. 12 cm -3 (1e12cm -3 ) is possible.

[0046]

[0077] As the gate-to-source voltage VGS changes from 0 volts (0V) to 5 volts (5V), the (electron) carrier concentration in the channel epitaxial layer 114 increases by approximately 1 × 10⁻¹⁶. -9 cm -3 (1e-9cm -3 ) from approximately 1 x 10 19 cm-3 (1e19cm -3 ) can change up to . When the gate-to-source voltage VGS is 0 volts, the carriers (i.e., electrons) are depleted, and the simulated carrier concentration is approximately 1 × 10⁻⁶. -9 cm -3 (1e-9cm -3 ) may be. If the gate-to-source voltage VGS is 0.5 volts (0.5V), the carrier concentration is approximately 1 × 10⁻¹⁶. 3 cm -3 (1e3cm -3 It increases up to ). When the gate-to-source voltage VGS is 5 volts (5V), the carrier concentration is approximately 1 × 10⁻¹⁶. 19 cm -3 (1e19cm -3 It increases up to ).

[0047]

[0078] Figure 12A shows a two-dimensional (2D) cross-sectional view according to the embodiment of Figure 10. The 2D cross-sectional view is similar to that of Figure 3A, except that it shows electron density instead of doping concentration. The unit is the number of electrons (carriers) per cubic centimeter (cm³). -3 ) may be such that the cutting line 1210 remains within the channel epitaxial layer 114 near the cylindrical trench gate 105b, and the cutting line 1210 may correspond to an X-axis coordinate value of approximately 1.5 micrometers. The drain-to-source voltage VDS may be 1 volt (1V). The gate-to-source voltage VGS may be equal to 1.5 volts (1.5V).

[0048]

[0079] Figure 12B shows the electron density transfer curves 1201–1206 along the Z-axis of the cutting line 1210 and according to the embodiment of Figure 10. For reference, Figure 12B further shows the 1D plots 1220 of doping concentrations along the cutting line 1210. The drain-to-source voltage VDS can be 1 volt (1 V). Transfer curve 1201 corresponds to the gate-to-source voltage VGS at 0 volts (0 V). Transfer curve 1202 corresponds to the gate-to-source voltage VGS at 0.5 volts (0.5 V). Transfer curve 1203 corresponds to the gate-to-source voltage VGS at 1 volt (1.0 V). Transfer curve 1204 corresponds to the gate-to-source voltage VGS at 1.5 volts (1.5 V). Transition curve 1205 corresponds to a gate-to-source voltage VGS of 2 volts (2.0V), and transition curve 1206 corresponds to a gate-to-source voltage VGS of 5 volts (5.0V).

[0049]

[0080] Figure 13A shows a cross-section 1300 in the XY plane for simulating the transfer curve of a vertical GaN transistor 100 with a variable nearest neighbor distance D4.

[0050]

[0081] Figure 13B shows the transfer curves 1301–1305 of the total drain current in amperes against the gate-to-source voltage VGS in volts, and Figure 13C shows further transfer curves 1311–1315 of the total drain current against the gate-to-source voltage VGS. Transfer curves 1301–1305 and 1311–1315 are obtained based on simulations using the cross-section 1300 of Figure 13A. In Figure 13B, the total drain current in amperes is plotted on a linear scale, and in Figure 13C, the total drain current in amperes is plotted on a logarithmic scale. The drain-to-source voltage VDS can be 1 volt (1 V).

[0051]

[0082] Plotting amperes on a logarithmic scale can provide graphical insights into the behavior of the slope in the subthreshold region. The slope in the subthreshold region is related to the behavior of current (e.g., total drain current) as a function of the gate-source voltage VGS, and during operation in the subthreshold region (under subthreshold conditions), the drain current can be exponential, suggesting a barrier-dominant current flow.

[0052]

[0083] Transfer curves 1301 and 1311 may correspond to a nearest neighbor distance D4 of 1 micrometer (1 μm). Transfer curves 1302 and 1312 may correspond to a nearest neighbor distance D4 of 0.8 micrometers (0.8 μm). Transfer curves 1303 and 1313 may correspond to a nearest neighbor distance D4 of 0.6 micrometers (0.6 μm). Transfer curves 1304 and 1314 may correspond to a nearest neighbor distance D4 of 0.4 micrometers (0.4 μm), and transfer curves 1305 and 1315 may correspond to a nearest neighbor distance D4 of 0.2 micrometers (0.2 μm).

[0053]

[0084] Figure 14 shows a cross-sectional perspective view of a vertical GaN transistor 100 according to another embodiment. The vertical GaN transistor 100 in Figure 14 is similar to that in Figure 1, except that the source layer comprises a two-dimensional electron gas (2DEG). The surface of the GaN transistor 100 in Figure 14 may comprise an aluminum gallium nitride (AlGaN) layer 1401, and, similar to that of a lateral GaN HEMT, the AlGaN layer 1401 may form an AlGaN-to-GaN interface that generates 2DEG. 2DEG can beneficially provide a very high-density source of n-type carriers (i.e., electrons).

[0054]

[0085] Furthermore, instead of including a channel epitaxial layer 114 and a drift epitaxial layer 113, the vertical GaN transistor 1400 in Figure 14 includes an N-GaN epitaxial layer 1414. The N-GaN epitaxial layer 1414 can be n-type and uniformly doped, and Figure 14 shows a GaN transistor 100 that includes only a uniformly doped N-GaN epitaxial layer 1414, although other doping distributions are also possible. The N-GaN epitaxial layer 1414 includes 2DEG, and AlGaN can form "GaN pillars" between the cylindrical trench gates 105b, 106b, and 106c.

[0055]

[0086] Figure 15A shows a two-dimensional (2D) cross-sectional view corresponding to the embodiment in Figure 14, and Figure 15B shows an enlarged view of 2DEG1530 corresponding to Figure 15A. The 2D cross-sectional view shows a cross-section of the vertical GaN transistor 100 in the XZ plane defined by the Cartesian coordinate axes 201. Coordinate values ​​in micrometers are shown for both the X and Z axes. As shown in Figure 15B, 2DEG1530 can be formed between the AlGaN layer 1401 and the N-GaN epitaxial layer 1414.

[0056]

[0087] The sidewall thickness 305 can be the length of the sidewall where the gate dielectric 112 extends beyond the gate electrode 111. The gate dielectric 112 can be an oxide. The sidewall thickness 305 can be between 0.1 (0.1 μm) and 0.5 micrometers (0.5 μm). The pinch-off characteristics of the device can be determined at least partially by the sidewall thickness 305 and the doping concentration of the N-GaN epitaxial layer 1414. The nearest neighbor distance D4 can be between 1 micrometer (1 μm) and 2 micrometers (2 μm).

[0057]

[0088] The rated dielectric breakdown voltage (e.g., rated maximum drain-to-source voltage) may depend at least partially on the dielectric thickness 306. For example, a vertical GaN transistor 1400 with a dielectric thickness 306 of 0.5 micrometers (0.5 μm) may have a dielectric breakdown voltage greater than 1200 volts (1200 V).

[0058]

[0089] The N-GaN epitaxial layer 1414 has a diameter of 1 × 10 16 cm -3 (1e16cm -3 It may have a doping concentration of ). The cutting line 1501 may correspond to an X-axis coordinate value of approximately 1.5 micrometers (1.5 μm).

[0059]

[0090] Figure 15C shows the distance along the Z-axis on the cutting line 1501, every cubic centimeter (cm) -3 The electron density plot 1520 is shown in units of ). Referring to Figure 15A, plot 1520 may be at an X-axis coordinate value of 1.5 micrometers (1.5 μm). The Z-axis coordinate value can be obtained between negative and positive coordinate values, passing through 2DEG1530. A Z-axis coordinate of zero (0) may define the position on the GaN substrate surface. For Z-axis coordinate values ​​less than zero (z<0), the electron density may be substantially equal to the n-type doping concentration of the GaN substrate. The doping concentration in the GaN substrate is 1 × 10⁻¹⁶. 19 cm -3 (1e19cm -3 ) may be greater than 2DEG1530 between AlGaN layer 1401 and N-GaN epitaxial layer 1414, and the electron density may be substantially equal to the n-type doping concentration of N-GaN epitaxial layer 1414, and the n-type doping concentration of N-GaN epitaxial layer 1414 is 1 × 10⁻¹⁶. 16 cm -3 (1e16cm -3 ) is possible. The distance D15, which is the thickness of the N-GaN epitaxial layer, can be 12 micrometers (12 μm).

[0060]

[0091] Figure 16 shows the simulated drain current transfer curve 1601 in amperes (amps) as a function of the gate-to-source voltage VGS in volts. The applied drain-to-source voltage VDS can be 1 volt (1 V). The dielectric 112 can be an oxide. The sidewall thickness 305 can be 0.1 micrometers (0.1 μm). The doping concentration in the channel epitaxial layer 1414 is 1 e16 cm -3It can be and can be n-type. The calculated relative on-resistance Rsp is 0.72 milliohms per square centimeter (0.72 mΩ·cm). 2 The pinch-off voltage can be equal to ) and can be negative 6 volts (-6V). Therefore, the vertical GaN transistor 1400 can be a depletion-type vertical GaN HEMT.

[0061]

[0092] Figure 17 shows the electron density transfer curves 1701 to 1705 along the Z-axis of the cutting line 1501 according to the embodiment of Figure 16. The drain-to-source voltage VDS can be 1 volt (1 V). Transfer curve 1701 corresponds to a gate-to-source voltage VGS of -30 volts (-30 V). Transfer curve 1702 corresponds to a gate-to-source voltage VGS of -22 volts (-22 V). Transfer curve 1703 corresponds to a gate-to-source voltage VGS of -13 volts (-13 V). Transfer curve 1704 corresponds to a gate-to-source voltage VGS of -5 volts (-5 V), and transfer curve 1705 corresponds to a gate-to-source voltage VGS of 0 volts (0.0 V).

[0062]

[0093] Figure 18A shows another two-dimensional (2D) cross-sectional view according to the embodiment of Figure 14. The 2D cross-sectional view is similar to that of Figure 15A, except that it shows the electric field distribution for an applied drain-to-source voltage of 1000 volts (1000 V). The gate-to-source voltage VGS can be negative 30 volts (-30 V). The units can be volts per centimeter (V / cm) and follow the legend for electric fields 802. The cutting line 1801 may correspond to an X-axis coordinate value of about 2 micrometers, and the dielectric 112 may be an oxide, so that the cutting line 1801 passes through the dielectric 112.

[0063]

[0094] Figure 18B shows a plot 1820 of the electric field in volts per centimeter (V / cm) along the Z-axis according to the cutting line 1801. The applied drain-to-source voltage VDS can be 1,000 volts (1000 V). The electric field increases monotonically from the substrate surface at the Z-axis coordinate (z=0), which is equal to zero, and is maximum within the gate dielectric 112.

[0064]

[0095] The above description of the examples shown in this disclosure, including matters described in the abstract, is not intended to be exhaustive or to be a limitation to the disclosed forms themselves. For example, the applications of vertical gallium nitride transistors may be further extended to radio frequency (RF) and / or higher frequency applications, and while specific embodiments of vertical gallium nitride transistors are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of this disclosure. Indeed, it will be understood that specific exemplary device cross-sections are presented for illustrative purposes and that other embodiments may also be used in accordance with the teachings herein. Furthermore, specific and exemplary voltages, currents, frequencies, output range values, times, etc., are presented for illustrative purposes, and other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0065]

[0096] In this specification, any reference to “one embodiment,” “an embodiment,” “an example,” or “an example” means that any particular feature, structure, or characteristic described in relation to an embodiment or example is included in at least one embodiment of this disclosure. Therefore, the use of expressions such as “one embodiment,” “an embodiment,” “an example,” or “an example” in various places in this specification does not necessarily relate to the same embodiment or example. Furthermore, any particular feature, structure, or characteristic may be combined in any suitable combination and / or partial combination in one or more embodiments or examples. In addition, it should be understood that the drawings provided with this specification are intended for those skilled in the art and that the drawings are not necessarily drawn to a fixed scale.

[0066]

[0097] The preceding descriptions may refer to elements or features together as “connected,” “electrically connected,” and / or “joined.” As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically connected. Similarly, unless otherwise expressly stated, “joined” means that one element / feature is directly or indirectly joined to another element / feature, and not necessarily mechanically connected.

[0067]

[0098] Furthermore, conditional expressions used herein, such as "may," "can," "may," "may," "for example," "as an example," etc., are generally intended to convey that a particular embodiment includes a particular feature, element, and / or state, while other embodiments do not, unless explicitly stated otherwise or understood differently in the context in which they are used. Thus, such conditional expressions are generally not intended to suggest that the feature, element, and / or state is required in any way in one or more embodiments, nor are they intended to suggest that one or more embodiments necessarily include logic for determining whether these features, elements, and / or states are included in or implemented in any particular embodiment.

[0068]

[0099] While specific embodiments have been described, these embodiments are presented for illustrative purposes only and are not intended to limit the scope of this disclosure. In fact, the novel apparatus, methods, and systems described herein may be embodied in various other forms, and various omissions, substitutions, and modifications to the forms of methods and systems described herein may be made without departing from the spirit of this disclosure.

[0069]

[0100] For example, while the disclosed embodiments are shown by a given configuration, alternative embodiments may perform similar functions using different components, materials, and / or semiconductor device layers, and some elements may be removed, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented by various different methods. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the invention is defined solely by reference to the appended claims.

[0070]

[0101] The claims presented in this application are in a form that is one dependent for filing with the USPTO, but it is understood that any claim may be dependent on any one of the prior claims of the same kind, unless it is clearly not technically feasible.

Claims

1. A vertical gallium nitride (GaN) field-effect transistor (FET), GaN substrate and A GaN epitaxial (epi) layer grown on the GaN substrate, A source layer formed on the surface of the GaN epitaxial layer, Multiple cylindrical trench gates arranged in a hexagonal configuration to form multiple vertical FET channels, Equipped with, Vertical GaN FET.

2. Each of the plurality of cylindrical trench gates comprises a gate electrode surrounded by a gate dielectric. The vertical GaN FET according to claim 1.

3. The gate electrode includes polycrystalline silicon, The vertical GaN FET according to claim 2.

4. The gate dielectric comprises silicon dioxide, The vertical GaN FET according to claim 2.

5. The threshold voltage of the vertical GaN FET is at least partially determined by the trench nearest neighbor distance. The vertical GaN FET according to claim 1.

6. The nearest adjacent trench distance is between 2 micrometers (2 μm) and 0.1 micrometers (0.1 μm). The vertical GaN FET according to claim 5.

7. The aforementioned vertical GaN FET is an enhancement-type vertical GaN FET. The vertical GaN FET according to claim 6.

8. The aforementioned vertical GaN FET is a depletion-type vertical GaN FET. The vertical GaN FET according to claim 6.

9. The GaN epitaxial layer is Drift region and A low-concentration doped epiregion extending from the source layer to the drift region, Equipped with, The vertical GaN FET according to claim 1.

10. The plurality of cylindrical trench gates extend into the low-doped epitaxial region and extend above the drift region at a distance equal to the distance between the bottoms of the drift trenches. The vertical GaN FET according to claim 9.

11. The GaN substrate is 1 × 10 １８ cm －３ (1 e 18 cm) －３ ) from 1 x 10 ２０ cm －３ (1 e 20 cm) －３ It is an n-type GaN substrate with doping concentrations between the following: The vertical GaN FET according to claim 9.

12. The drift region has a thickness between 8 micrometers (8 μm) and 10 micrometers (10 μm), and has an n-type doping concentration between 9×10 １５ cm －３ (9e15 cm －３ ) and 2×10 １６ cm －３ (2e16 cm －３ ). The vertical GaN FET according to claim 9.

13. The low-concentration doped epitaxial region has a thickness between 1 micrometer (1 μm) and 3 micrometers (3 μm), and 1 × 10⁻⁶ １５ cm －３ (1 e 15 cm) －３ ) from 3 x 10 １５ cm －３ (3e15cm) －３ ) with n-type doping concentrations between The vertical GaN FET according to claim 9.

14. The source layer is 9 × 10 １７ cm －３ (9 e 17 cm) －３ ) from 2 x 10 １８ cm －３ (2 e 18 cm) －３ ) are being doped with type n, The vertical GaN FET according to claim 9.

15. The source layer includes a two-dimensional electron gas (2DEG) formed between the surface aluminum gallium nitride (AlGaN) layer and the GaN epitaxial layer. The vertical GaN FET according to claim 1.

16. The aforementioned vertical GaN FET is a depletion-type vertical GaN FET. The vertical GaN FET according to claim 15.

17. The aforementioned vertical GaN FET is an enhancement-type vertical GaN FET. The vertical GaN FET according to claim 15.

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