Method for forming a three-dimensional memory device with back-side source contacts

Abstract

This invention provides a three-dimensional (3D) memory device and a method for manufacturing the same. [Solution] Embodiments of a 3D memory device and methods for forming the same are disclosed. In one example, a method for forming a 3D memory device is disclosed. A sacrificial layer and a dielectric stack on the sacrificial layer are formed on a first side of the substrate above a second semiconductor layer. A channel structure is formed that penetrates perpendicularly through the dielectric stack and the sacrificial layer and into the second semiconductor layer. The sacrificial layer is replaced by the first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced by a memory stack, thereby the channel structure penetrates perpendicularly through the memory stack and the first semiconductor layer and into the second semiconductor layer. A source contact is formed on the second side of the substrate opposite to the first side so as to contact the second semiconductor layer.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to three-dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to a smaller size by improving process technology, circuit design, programming algorithms, and fabrication processes. However, as the feature size of the memory cells approaches the lower limit, the planar process and fabrication technology become difficult and the cost increases. As such, the memory density of planar memory cells is approaching the upper limit.

[0003] 3D memory architectures can address this density limitation of planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0004] Embodiments of a 3D memory device and a method for forming the same are disclosed herein.

[0005] In one example, a method for forming a 3D memory device is disclosed. A sacrificial layer above a second semiconductor layer on a first side of a substrate, and a dielectric stack on the sacrificial layer are subsequently formed. A channel structure is formed that vertically penetrates the dielectric stack and the sacrificial layer and penetrates into the second semiconductor layer. The sacrificial layer is replaced with a first semiconductor layer that contacts the second semiconductor layer. The dielectric stack is replaced with a memory stack, whereby the channel structure vertically penetrates the memory stack and the first semiconductor layer and penetrates into the second semiconductor layer. A source contact is formed on a second side of the substrate opposite the first side to contact the second semiconductor layer.

[0006] In another example, a method for forming a 3D memory device is disclosed. A channel structure is formed on a first side of the substrate, penetrating perpendicularly through the memory stack and into an N-type doped semiconductor layer. The memory stack includes alternating stack conductor layers and stack dielectric layers. An insulating structure is formed within an opening that penetrates perpendicularly through the memory stack. Source contacts are formed on a second side of the substrate opposite to the first side, so as to contact the N-type doped semiconductor layer and align with the insulating structure.

[0007] In yet another example, a method for forming a 3D memory device is disclosed. Peripheral circuits are formed on a first substrate. A channel structure is formed that penetrates perpendicularly through the memory stack and the first semiconductor layer and into the second semiconductor layer on the second substrate. The first and second substrates are joined facing each other so that the memory stack is above the peripheral circuits. The second substrate is thinned to expose the second semiconductor layer. Source contacts are formed above the memory stack and in contact with the second semiconductor layer.

[0008] The accompanying drawings, incorporated herein and forming part thereof, illustrate embodiments of the present disclosure and, together with the description, further assist in explaining the principles of the present disclosure and enabling those skilled in the art to fabricate and use the present disclosure. [Brief explanation of the drawing]

[0009] [Figure 1] This is a side view illustrating a cross-section of an exemplary 3D memory device having a backside source contact according to some embodiments of the present disclosure. [Figure 2A] This is a plan view illustrating a cross-section of an exemplary 3D memory device having a backside source contact according to some embodiments of the present disclosure. [Figure 2B] Another plan view illustrating a cross-section of an exemplary 3D memory device having a backside source contact according to some embodiments of the present disclosure. [Figure 3A] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3B] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3C] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3D] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3E] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3F] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3G] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3H] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3I] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3J] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3K]This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3L] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 3M] This figure illustrates a fabrication process for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 4A] This is a flowchart of a method for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Figure 4B] This is a flowchart of a method for forming an exemplary 3D memory device having backside source contacts, according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0010] Embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0011] While specific configurations and arrangements are described, it will be understood that these are described for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will also be apparent to those skilled in the art that this disclosure may be adopted in a variety of other applications.

[0012] References in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc., should be noted to indicate that the described embodiments may have certain features, structures, or characteristics, but not all embodiments necessarily include the certain features, structures, or characteristics. Further, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in relation to one embodiment, it will be within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments whether explicitly described or not.

[0013] Generally, terms can be understood, at least in part, from their usage in context. For example, at least in part depending on the context, the phrase "one or more" as used herein can be used to describe a feature, structure, or characteristic in the singular sense or to describe a combination of features, structures, or characteristics in the plural sense. Similarly, here too, articles such as "a", "an", or "the" in the English text can be understood, at least in part, depending on the context, to convey either the use of the singular form or the use of the plural form. In addition, the phrase "based on" can be understood not to necessarily intend to convey an exclusive set of elements, but rather, here too, at least in part depending on the context, to allow for the presence of additional elements not necessarily explicitly described.

[0014] It should be immediately understood that the meanings of "above", "higher than", and "directly above" in the present disclosure should be interpreted in the broadest sense such that "above" means not only "directly above" something, but also "above" something with intermediate features or layers in between, and "higher than" or "directly above" means not only "higher than" or "directly above" something, but also can include the meaning of being "higher than" or "directly above" something without intermediate features or layers in between (i.e., directly above something).

[0015] Spatial relative terms such as "lower", "below", "downside", "upper", "upside", and similar words may be used herein to facilitate description when describing the relationship between one element or feature and another element or feature, as illustrated in the figures. The spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in some other way (rotated 90 degrees or other orientation), and the spatial relative descriptors used herein may likewise be construed accordingly.

[0016] As used herein, the term "substrate" refers to the material to which subsequent material layers are added. Patterns can be formed on the substrate itself. The materials added on the substrate can be patterned or left unpatterned. Further, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0017] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer may extend across an entire structure below or above it, or it may have a smaller extent than the extent of the structure below or above it. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuum having a thickness smaller than the thickness of the continuum. For example, a layer may be located between the top and bottom surfaces of a continuum, or between a pair of horizontal planes at the top and bottom surfaces. A layer may extend along horizontal, vertical, and / or tapered surfaces. A substrate may be a layer, may contain one or more layers within it, and / or have one or more layers above, above, and / or below it. A layer may also contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (on which interconnection lines and / or vertical interconnection access (via) contacts are formed) and one or more dielectric layers.

[0018] As used herein, the phrase “nominal” refers to a desired or target value of a characteristic or parameter for a component or process operation, set at the design stage of the product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or manufacturing tolerances. As used herein, the word “approximately” indicates a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device of the subject. Based on a particular technology node, the word “approximately” may indicate a value of a given quantity that varies, for example, within 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0019] As used herein, the term “3D memory device” refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as “memory strings,” such as NAND memory strings) on a transversely oriented substrate such that the memory strings extend perpendicularly with respect to the substrate. As used herein, the phrase “perpendicular” means nominally perpendicular to the outer surface of the substrate.

[0020] In some 3D memory devices, such as 3D NAND memory devices, a slit structure (e.g., a gate line slit (GLS)) is used from the front of the device to electrically connect to the memory array source, such as an array common source (ACS). However, the front side source contact can affect the electrical performance of the 3D memory device by introducing both leakage current and parasitic capacitance between the word line and the source contact, even if a spacer is present in between. The formation of the spacer also complicates the manufacturing process. In addition to affecting electrical performance, the slit structure typically contains polysilicon and / or buildup in the wall shape, which can introduce localized stress, causing wafer bending or warping, thereby reducing production yield.

[0021] Furthermore, some 3D NAND memory devices include semiconductor plugs selectively grown at the bottom of the channel structure. However, as the number of levels in 3D NAND memory devices increases, especially in multi-deck architectures, various issues arise in fabricating the bottom semiconductor plugs, including overlay control, epitaxial layer formation, and etching of the memory film and semiconductor channels at the bottom of the channel holes (also known as "SONO" punching), which can further complicate the fabrication process and reduce yield.

[0022] Various embodiments of this disclosure provide 3D memory devices having backside source contacts. By moving the source contacts from the front side to the back side, the effective memory cell array area is increased and the cost per memory cell can be reduced because the spacer formation process can be skipped. Furthermore, device performance can be improved by avoiding leakage current and parasitic capacitance between the word line and the source contacts, and by reducing local stress caused by the frontside slit structure (as the source contact). In some embodiments, the 3D memory device does not include a semiconductor plug selectively grown on the bottom surface of the channel structure, but is replaced by a semiconductor layer (e.g., N-wells) surrounding the sidewalls of the channel structure, enabling gate-inductive drain leak (GIDL) assisted body biasing for erase operations. As a result, various problems associated with bottom semiconductor plugs, such as overlay control, epitaxial layer formation, and SONO punching, can be avoided, thereby improving production yield.

[0023] Figure 1 is a side view illustrating a cross-section of an exemplary 3D memory device 100 having a backside source contact according to some embodiments of the present disclosure. In some embodiments, the 3D memory device 100 is a bonded chip comprising a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 are connected by a junction interface 106 between them, according to some embodiments. As shown in Figure 1, the first semiconductor structure 102 may include a substrate 101 which can include silicon (e.g., single-crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0024] The first semiconductor structure 102 of the 3D memory device 100 may include peripheral circuits 108 on the substrate 101. Note that the x, y, and z axes are included in Figure 1 to illustrate the spatial relationships of the components within the 3D memory device 100. The substrate 101 includes two transverse surfaces extending laterally in the xy plane, namely the surface on the front side of the wafer and the back surface on the back side opposite the front side of the wafer. The x and y directions are two orthogonal directions in the wafer plane, namely the x direction is the word line direction and the y direction is the bit line direction. The z axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or device) is "above," "above," or "below" another component (e.g., a layer or device) of a semiconductor device (e.g., a 3D memory device 100) is determined with respect to the substrate of the semiconductor device (e.g., substrate 101) in the z-direction (perpendicular to the xy-plane) when the substrate is positioned in the z-direction at the lowest plane of the semiconductor device. The same concepts for describing spatial relationships apply throughout this disclosure.

[0025] In some embodiments, the peripheral circuit 108 is configured to control and sense the 3D memory device 100. The peripheral circuit 108 may be any suitable digital, analog, and / or mixed-signal control and sensing circuit used to smooth the operation of the 3D memory device 100, including, but not limited to, a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 108 may include transistors formed "on" the substrate 101, with all or part of the transistors formed within the substrate 101 (e.g., below the top surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of the transistors) may also be formed within the substrate 101. Transistors are high-speed by using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.) in some embodiments. It is understood that in some embodiments, peripheral circuits 108 may further include any other circuits compatible with advanced logic processes, including logic circuits such as processors and programmable logic devices (PLDs), or memory circuits such as static random access memory (SRAM).

[0026] In some embodiments, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnection layer (not shown) above the peripheral circuit 108 for exchanging electrical signals with the peripheral circuit 108. The interconnection layer may include a plurality of interconnections (also referred to herein as “contacts”), including lateral interconnection lines and vertical interconnection access (VIA) contacts. As used herein, the term “interconnection” in a broad sense may include any preferred type of interconnection, such as middle end-of-line (MEOL) interconnections and back-end-of-line (BEOL) interconnections. The interconnection layer may further include one or more interlayer insulating film (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”) on which interconnection lines and VIA contacts can be formed. That is, the interconnection layer may include interconnection lines and VIA contacts within a plurality of ILD layers. The interconnecting wires and via contacts within the interconnecting layer may include, but are not limited to, conductive materials including tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer within the interconnecting layer may include, but are not limited to, dielectric materials including silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0027] As shown in Figure 1, the first semiconductor structure 102 of the 3D memory device 100 may further comprise a junction layer 110 at the junction interface 106 and above the interconnection layer and peripheral circuitry 108. The junction layer 110 may include a plurality of junction contacts 111 and a dielectric that electrically insulates the junction contacts 111. The junction contacts 111 may include conductive materials, but are not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining region of the junction layer 110 may be formed of a dielectric, but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The junction contacts 111 within the junction layer 110 and the surrounding dielectric may be used for a hybrid junction.

[0028] Similarly, as shown in Figure 1, the second semiconductor structure 104 of the 3D memory device 100 may also include a junction layer 112 at the junction interface 106 and above the junction layer 110 of the first semiconductor structure 102. The junction layer 112 may include a plurality of junction contacts 113 and a dielectric that electrically insulates the junction contacts 113. The junction contacts 113 may include conductive materials, but are not limited to W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of ​​the junction layer 112 may be formed of a dielectric, but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The junction contacts 113 within the junction layer 112 and the surrounding dielectric may be used for a hybrid junction. In some embodiments, the junction contacts 113 are in contact with the junction contacts 111 at the junction interface 106.

[0029] As described in detail below, the second semiconductor structure 104 may be bonded to the first semiconductor structure 102 facing each other at the junction interface 106. In some embodiments, the junction interface 106 is located between junction layers 110 and 112 as a result of a hybrid junction (also called a “metal / dielectric hybrid junction”), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer such as solder or adhesive) and can simultaneously obtain a metal-to-metal junction and a dielectric-to-dielectric junction. In some embodiments, the junction interface 106 is the location where the junction layers 112 and 110 come into contact and are bonded. In practice, the junction interface 106 may be a layer of a specific thickness that includes the top surface of the junction layer 110 of the first semiconductor structure 102 and the bottom surface of the junction layer 112 of the second semiconductor structure 104.

[0030] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnection layer (not shown) above the junction layer 112 for transferring electrical signals. The interconnection layer may include multiple interconnections, such as MEOL interconnections and BEOL interconnections. The interconnection layer may further include one or more ILD layers on which interconnection lines and via contacts can be formed. The interconnection lines and via contacts within the interconnection layer may include conductive materials, but are not limited to W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers within the interconnection layer may include dielectric materials, but are not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0031] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings. As shown in Figure 1, the second semiconductor structure 104 of the 3D memory device 100 may include an array of channel structures 124 that function as an array of NAND memory strings. As shown in Figure 1, each channel structure 124 may vertically penetrate multiple pairs, each containing a conductive layer 116 and a dielectric layer 118. The alternating conductive layers 116 and dielectric layers 118 constitute a memory stack 114. The number of pairs of conductive layers 116 and dielectric layers 118 in the memory stack 114 (e.g., 32, 64, 96, 128, 160, 192, 224, 256, or more) determines the number of memory cells in the 3D memory device 100. In some embodiments, it is understood that the memory stack 114 may have a multi-deck architecture (not shown) which includes multiple memory decks stacked on top of each other. The number of pairs of conductive layer 116 and dielectric layer 118 in each memory deck may be the same or different.

[0032] The memory stack 114 may include a plurality of alternating conductive layers 116 and dielectric layers 118. The conductive layers 116 and dielectric layers 118 in the memory stack 114 may be alternating vertically. In other words, except for those at the top or bottom of the memory stack 114, each conductive layer 116 may be adjacent to two dielectric layers 118 on either side, and each dielectric layer 118 may be adjacent to two conductive layers 116 on either side. The conductive layers 116 may include conductive materials, but are not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. Each conductive layer 116 may include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the conductive layer 116 may extend laterally as a word line and terminate in one or more stepped structures of the memory stack 114. The dielectric layer 118 may include, but is not limited to, a dielectric material containing silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0033] As shown in Figure 1, the second semiconductor structure 104 of the 3D memory device 100 may also include a first semiconductor layer 120 located above the memory stack 114, and a second semiconductor layer 122 located above the first semiconductor layer 120 and in contact with it. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer, such as a silicon layer doped with an N-type dopant such as phosphorus (P) or arsenic (As). In those cases, the first semiconductor layer 120 and the second semiconductor layer 122 may be considered together as an N-type doped semiconductor layer 120 / 122 located above the memory stack 114. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 includes N wells. That is, each of the first semiconductor layer 120 and the second semiconductor layer 122 may be a region within a P-type substrate doped with an N-type dopant, such as P or As. It is understood that the doping concentrations in the first semiconductor layer 120 and the second semiconductor layer 122 may be the same or different. In some embodiments, the first semiconductor layer 120 comprises polysilicon, e.g., N-type doped polysilicon. As described in detail below, the first semiconductor layer 120 may be formed on top of the P-type silicon substrate by thin-film deposition and / or epitaxial growth. In contrast, in some embodiments, the second semiconductor layer 122 comprises single-crystal silicon, e.g., N-type doped single-crystal silicon. As described in detail below, the second semiconductor layer 122 may be formed by injecting an N-type dopant into a P-type silicon substrate having single-crystal silicon. In some embodiments, the lateral dimension of the second semiconductor layer 122 in the x-direction (e.g., the word line direction) is greater than the lateral dimension of the first semiconductor layer 120 in the x-direction.

[0034] In some embodiments, each channel structure 124 includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel 128) and a composite dielectric layer (e.g., as a memory film 126). In some embodiments, the semiconductor channel 128 includes silicon such as amorphous silicon, polysilicon, or single-crystal silicon. In some embodiments, the memory film 126 is a composite layer including a tunnel layer, a storage layer (also called a “charge trap layer”), and a blocking layer. The remaining space of the channel structure 124 may be partially or completely filled with a capping layer containing a dielectric material such as silicon oxide, and / or voids. The channel structure 124 may have a cylindrical shape (e.g., a columnar shape). In some embodiments, the capping layer, semiconductor channel 128, tunnel layer, storage layer, and blocking layer of the memory film 126 are arranged radially in this order from the center toward the outer surface of the column. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory film 126 may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0035] In some embodiments, the channel structure 124 further includes a channel plug 129 at the bottom (e.g., the lower end) of the channel structure 124. As used herein, the “upper end” of the component (e.g., the channel structure 124) is the end furthest from the substrate 101 in the z direction, and the “lower end” of the component (e.g., the channel structure 124) is the end closest to the substrate 101 in the z direction when the substrate 101 is positioned within the lowest plane of the 3D memory device 100. The channel plug 129 may include a semiconductor material (e.g., polysilicon). In some embodiments, the channel plug 129 functions as a drain for the NAND memory string.

[0036] As shown in Figure 1, each channel structure 124 can penetrate vertically through the memory stack 114 and the first semiconductor layer 120, for example, alternating conductive layers 116 and dielectric layers 118 of N-type doped polysilicon layers. In some embodiments, the first semiconductor layer 120 surrounds a portion of the channel structure 124 and is in contact with the semiconductor channel 128 containing polysilicon. That is, in some embodiments, the memory film 126 is interrupted at a portion of the channel structure 124 that abuts the first semiconductor layer 120, exposing the semiconductor channel 128 that should be in contact with the surrounding first semiconductor layer 120. As a result, the first semiconductor layer 120 surrounding and in contact with the semiconductor channel 128 can act as a "sidewall semiconductor plug" of the channel structure 124, replacing the "bottom semiconductor plug" as described above, which can mitigate issues such as overlay control, epitaxial layer formation, and SONO punching.

[0037] In some embodiments, each channel structure 124 can further penetrate vertically into a second semiconductor layer 122, for example, an N-type doped single-crystal silicon layer. That is, each channel structure 124 can, in some embodiments, penetrate vertically through the memory stack 114 into the N-type doped semiconductor layer (including the first semiconductor layer 120 and the second semiconductor layer 122). As shown in Figure 1, the top (e.g., upper end) of the channel structure 124 is, in some embodiments, located within the second semiconductor layer 122. In some embodiments, each of the first semiconductor layer 120 and the second semiconductor layer 122 is an N-type doped semiconductor layer, for example, an N-well, which enables GIDL-assisted body biasing for erase operations, as opposed to P-well bulk erase operations. GIDL around the source select gate of the NAND memory string can generate hole currents within the NAND memory string, raising the body potential for erase operations.

[0038] As shown in Figure 1, the second semiconductor structure 104 of the 3D memory device 100 may further include insulating structures 130 that penetrate vertically through the alternating conductive layers 116 and dielectric layers 118 of the memory stack 114, respectively. Unlike the channel structures 124 that further penetrate the first semiconductor layer 120, the insulating structures 130, in some embodiments, terminate at the first semiconductor layer 120, i.e., do not extend vertically into the N-type doped semiconductor layer. That is, the top surface of the insulating structure 130 may be coplanar with the bottom surface of the first semiconductor layer 120. Each insulating structure 130 may extend laterally, separating the channel structures 124 into multiple blocks. That is, the memory stack 114 may be divided into multiple memory blocks by the insulating structures 130, thereby separating the array of channel structures 124 into individual memory blocks. Unlike the slit structures of existing 3D NAND memory devices described above, which include front-side ACS contacts, the insulating structure 130 does not contain any contacts (i.e., does not function as source contacts) and therefore, in some embodiments, does not introduce parasitic capacitance and leakage current by the conductive layer 116 (including word lines). In some embodiments, each insulating structure 130 comprises an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 may be filled with silicon oxide.

[0039] Instead of a front-side source contact, the 3D memory device 100 may include a back-side source contact 132 located above the memory stack 114 and in contact with a second semiconductor layer 122, such as an N-type doped semiconductor layer, as shown in Figure 1. The source contact 132 and the memory stack 114 (and the insulating structure 130 through it) may be located on the opposite side of the semiconductor layer 122 (thinned substrate) and thus may be considered a “back-side” source contact. In some embodiments, the source contact 132 penetrates further into the second semiconductor layer 122 and is electrically connected through the second semiconductor layer 122 to the first semiconductor layer 120 and the semiconductor channels 128 of the channel structure 124. It is understood that the depth to which the source contact 132 penetrates into the second semiconductor layer 122 may differ in different examples. In some embodiments where the second semiconductor layer 122 contains N wells, the source contact 132 is also referred to herein as an “N-well pickup.” In some embodiments, the source contact 132 is aligned with the insulating structure 130. The source contact 132 may be aligned laterally with the insulating structure 130, i.e., aligned in at least one lateral direction. In one example, the source contact 132 and the insulating structure 130 may be aligned in the y-direction (e.g., the bit line direction). In another example, the source contact 132 and the insulating structure 130 may be aligned in the x-direction (e.g., the word line direction). The source contact 132 may include any preferred type of contact. In some embodiments, the source contact 132 includes a VIA contact. In some embodiments, the source contact 132 includes a wall-shaped contact that extends laterally. The source contact 132 may include one or more conductive layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., titanium nitride (TiN)).

[0040] As shown in Figure 1, the 3D memory device 100 may further include a BEOL interconnect layer 133 that is on and in contact with the source contact 132 for pad-out, for example, for transferring electrical signals between the 3D memory device 100 and an external circuit. In some embodiments, the interconnect layer 133 includes one or more ILD layers 134 on the second semiconductor layer 122 and a redistribution layer 136 on the ILD layer 134. In some embodiments, the upper end of the source contact 132 is coplanar with the top surface of the ILD layer 134 and the bottom surface of the redistribution layer 136, and the source contact 132 penetrates vertically through the ILD layer 134 into the second semiconductor layer 122. The ILD layer 134 in the interconnect layer 133 may include dielectric materials including, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The redistribution layer 136 within the interconnection layer 133 may include, but is not limited to, conductive materials including W, Co, Cu, Al, silicide, or any combination thereof. In one example, the redistribution layer 136 includes Al. In some embodiments, the interconnection layer 133 further includes a passivation layer 138 as the outermost layer for passivation and protection of the 3D memory device 100. A portion of the redistribution layer 136 may be exposed from the passivation layer 138 as a contact pad 140. That is, the interconnection layer 133 of the 3D memory device 100 may also include a contact pad 140 for wire bonding and / or bonding with an interposer.

[0041] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 passing through the second semiconductor layer 122. Since the second semiconductor layer 122 may be a thinned substrate, for example, an N-well of a P-type silicon substrate, in some embodiments, the contacts 142 and 144 are through-silicon contacts (TSCs). In some embodiments, the contact 142 penetrates the second semiconductor layer 122 and the ILD layer 134 to contact the redistribution layer 136, thereby electrically connecting the first semiconductor layer 120 to the contact 142 through the second semiconductor layer 122, the source contact 132, and the redistribution layer 136 of the interconnection layer 133. In some embodiments, the contact 144 penetrates the second semiconductor layer 122 and the ILD layer 134 to contact the contact pad 140. Each of the contacts 142 and 144 may include one or more conductive layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN). In some embodiments, at least contact 144 further includes a spacer (e.g., a dielectric layer) for electrically insulating contact 144 from the second semiconductor layer 122.

[0042] In some embodiments, the 3D memory device 100 further comprises peripheral contacts 146 and 148, each extending perpendicularly to a second semiconductor layer 122 (e.g., an N-well in a P-type silicon substrate) outside the memory stack 114. Each peripheral contact 146 or 148 may have a depth greater than the depth of the memory stack 114 so as to extend perpendicularly from the junction layer 112 to the second semiconductor layer 122 in a peripheral region outside the memory stack 114. In some embodiments, the peripheral contact 146 is below and in contact with the contact 142, thereby electrically connecting the first semiconductor layer 120 to peripheral circuits 108 in the first semiconductor structure 102 through at least the second semiconductor layer 122, source contact 132, interconnection layer 133, contact 142, and peripheral contact 146. In some embodiments, the peripheral contact 148 is located below and in contact with the contact 144, thereby electrically connecting the peripheral circuit 108 within the first semiconductor structure 102 to the contact pad 140 for pad-out through at least the contact 144 and the peripheral contact 148. The peripheral contacts 146 and 148 may each include one or more conductive layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0043] As shown in Figure 1, the 3D memory device 100 also includes various local contacts (also called "C1") as part of its interconnection structure, which are in direct contact with structures within the memory stack 114. In some embodiments, the local contacts include channel local contacts 150, each located below and in contact with the lower end of each channel structure 124. Each channel local contact 150 may be electrically connected to a bit line contact (not shown) for bit line fan-out. In some embodiments, the local contacts further include word line local contacts 152, each located below and in contact with each conductive layer 116 (containing word lines) in the stepped structure of the memory stack 114 for word line fan-out. Local contacts such as the channel local contacts 150 and word line local contacts 152 may be electrically connected to peripheral circuits 108 of the first semiconductor structure 102 through at least the junction layers 112 and 110. Local contacts, such as the channel local contact 150 and the word line local contact 152, may each include one or more conductive layers, such as a silicide layer surrounded by a metal layer (e.g., W, Co, Cu, or Al) or an adhesive layer (e.g., TiN).

[0044] Figure 2A is a plan view illustrating a cross-section of an exemplary 3D memory device 200 having a backside source contact according to some embodiments of the present disclosure. The 3D memory device 200 may be an example of the 3D memory device 100 of Figure 1, and Figure 2A may illustrate a plan view of a cross-section in the AA plane of the 3D memory device 100 of Figure 1 according to some embodiments. That is, Figure 2A shows an example of a plan view of the front side of the second semiconductor structure 104 of the 3D memory device 100.

[0045] As shown in Figure 2A, the 3D memory device 200, in some embodiments, includes a central staircase region 204 that laterally separates the memory stack in the x-direction (e.g., the word line direction) into two parts, namely a first core array region 206A and a second core array region 206B, each of which includes an array of channel structures 210 (corresponding to channel structure 124 in Figure 1). It is understood that the layout of the staircase region and core array region is not limited to the example in Figure 2A and may include any other preferred layout, such as having side staircase regions at the edges of the memory stack. The 3D memory device 200 also, in some embodiments, includes parallel insulating structures 208 (corresponding to insulating structure 130 in Figure 1) in the y-direction (e.g., the bit line direction), each extending laterally in the x-direction to separate the core array regions 206A and 206 and the array of channel structures 210 within them into block 202. The 3D memory device 200 further includes a drain select gate cut 212 parallel to the y-direction in block 202, allowing block 202 to be further separated into fingers. Unlike existing 3D memory devices that have a front-side source contact (e.g., a front-side ACS contact) located opposite an insulating structure 208, which interrupts the front-side bit line fan-out of a particular channel structure 210 (e.g., within region 214), all channel structures 210 in the 3D memory device 200 without a front-side source contact, including those in region 214, can have corresponding bit line fan-out from the front side. As a result, the effective area of ​​core array regions 206A and 206B can be increased by moving the source contact to the back side of the 3D memory device 200.

[0046] Figure 2B is another plan view illustrating a cross-section of an exemplary 3D memory device having a backside source contact according to some embodiments of the present disclosure. The 3D memory device 200 may be an example of the 3D memory device 100 of Figure 1, and Figure 2B illustrates a plan view of a cross-section in the BB plane of the 3D memory device 100 of Figure 1 according to some embodiments. That is, Figure 2B shows an example of a plan view of the backside of the second semiconductor structure 104 of the 3D memory device 100.

[0047] As shown in Figure 2B, the 3D memory device 200 includes a central staircase region 204 that laterally separates the memory stack into two parts in the x-direction (e.g., the word line direction), namely a first core array region 206A and a second core array region 206B. It is understood that the layout of the staircase region and core array regions is not limited to the example in Figure 2B and may include any other preferred layout, such as having side staircase regions at the edges of the memory stack. In some embodiments, the 3D memory device 200 includes backside source contacts 215 (e.g., in the form of VIA contacts, corresponding to source contact 132 in Figure 1) within the core array regions 206A and 206B. For example, the source contacts 215 may be evenly distributed in the core array regions 206A or 206B. The 3D memory device 200 may include backside source lines 209 (e.g., in the form of a source line mesh, corresponding to the redistribution layer 136 in Figure 1) that electrically connect multiple source contacts 215. In some examples, it is understood that multiple source VIA contacts may be replaced by one or more source wall-shaped contacts, i.e., interconnection lines. In some embodiments, the 3D memory device 200 further includes pad-out contacts 213 (e.g., corresponding to contact pad 140, contact 144, and peripheral contact 148 in Figure 1) within a stepped region 204 for pad-out, and includes N-well pickup contacts 211 (e.g., corresponding to contact 142 and peripheral contact 146 in Figure 1) within the stepped region 204 and core array regions 206A and 206B. It is further understood that the layout of the pad-out contacts 213 and N-well pickup contacts 211 is not limited to the example in Figure 2B and may include any preferred layout depending on the design of the 3D memory device, such as electrical performance specifications (e.g., voltage and resistance). In one example, additional pad-out contacts 213 may be added outside the memory stack.

[0048] Figures 3A–3M illustrate a fabrication process for forming an exemplary 3D memory device with backside source contacts according to several embodiments of the present disclosure. Figures 4A and 4B illustrate a flowchart of Method 400 for forming an exemplary 3D memory device with backside source contacts according to several embodiments of the present disclosure. The examples of 3D memory devices shown in Figures 3A–3M, Figure 4A, and Figure 4B include the 3D memory device 100 shown in Figure 1. Figures 3A–3M, Figure 4A, and Figure 4B will be described together. The operations shown in Method 400 are not exhaustive, and it will be understood that other operations may be performed before, after, or between any of the exemplary operations. Furthermore, some of these operations may be performed simultaneously or in a different order than those shown in Figures 4A and 4B.

[0049] Referring to Figure 4A, Method 400 begins with Operation 402, in which peripheral circuits are formed on a first substrate. The first substrate may be a silicon substrate. Multiple transistors are formed on the silicon substrate 350 using a number of processes, including, but not limited to, photolithography, etching, thin-film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable processes, as illustrated in Figure 3I. In some embodiments, doped regions (not shown) are formed within the silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some embodiments, isolated regions (e.g., STI) are also formed within the silicon substrate 350 by wet etching and / or dry etching and thin-film deposition. The transistors can have peripheral circuits 352 formed on the silicon substrate 350.

[0050] As illustrated in Figure 3I, the junction layer 348 is formed above the peripheral circuit 352. The junction layer 348 includes junction contacts that are electrically connected to the peripheral circuit 352. To form the junction layer 348, the ILD layer is deposited using one or more thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and the junction contacts are formed through the ILD layer using wet etching and / or dry etching, e.g., RIE, and then one or more thin film deposition processes such as ALD, CVD, PVD, or any other suitable process, or any combination thereof.

[0051] Method 400 proceeds to operation 404, as illustrated in Figure 4A, in which a portion of the second substrate is doped with an N-type dopant to form a second semiconductor layer. The second substrate may be a P-type silicon substrate. In some embodiments, a first side of the second substrate (e.g., the front side on which the semiconductor device is formed) is doped to form N-wells. As illustrated in Figure 3A, the N-type doped semiconductor layer 304 is formed on the silicon substrate 302. The N-type doped semiconductor layer 304 contains N-wells of the P-type silicon substrate 302 and may contain single-crystal silicon. The N-type doped semiconductor layer 304 may be formed by doping the P-type silicon substrate 302 with an N-type dopant, such as P or As, using ion implantation and / or thermal diffusion.

[0052] Method 400 proceeds to operation 406, as illustrated in Figure 4A, where a sacrificial layer above the second semiconductor layer and a dielectric stack on the sacrificial layer are subsequently formed. The dielectric stack may include alternating stack sacrificial layers and stack dielectric layers. In some embodiments, to subsequently form the sacrificial layer and dielectric stack, polysilicon is deposited on the second semiconductor layer to form the sacrificial layer, and stack dielectric layers and stack sacrificial layers are alternately deposited on the sacrificial layer to form the dielectric stack.

[0053] As shown in Figure 3A, the sacrificial layer 306 is formed on the N-type doped semiconductor layer 304. The sacrificial layer 306 may be formed by depositing polysilicon or any other suitable sacrificial material (e.g., carbon) that can be selectively removed later using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some embodiments, a pad oxide layer 305 is formed between the sacrificial layer 306 and the N-type doped semiconductor layer 304 by depositing or thermally oxidizing a dielectric material such as silicon oxide on the silicon substrate 302 prior to the formation of the N-type doped semiconductor layer 304.

[0054] As illustrated in Figure 3A, a dielectric stack 308, comprising multiple pairs of first dielectric layers (referred herein to as “stack sacrificial layers” 312) and second dielectric layers (referred herein to as “stack dielectric layers” 310, collectively referred herein to as “dielectric layer pairs”), is formed on a sacrificial layer 306. In some embodiments, the dielectric stack 308 includes alternately arranged stack sacrificial layers 312 and stack dielectric layers 310. The stack dielectric layers 310 and stack sacrificial layers 312 can be alternately deposited on the sacrificial layer 306 above the silicon substrate 302 to form the dielectric stack 308. In some embodiments, each stack dielectric layer 310 comprises a layer of silicon oxide, and each stack sacrificial layer 312 comprises a layer of silicon nitride. The dielectric stack 308 may be formed by one or more thin-film deposition processes, including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in Figure 3A, a stepped structure may be formed on the edge of the dielectric stack 308. The stepped structure can be formed by performing multiple so-called "trim etch" cycles on the dielectric layer pairs of the dielectric stack 308 toward the silicon substrate 302. By repeatedly applying trim etch cycles to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more inclined edges and top dielectric layer pairs that are shorter than the bottom dielectric layer pairs, as shown in Figure 3A.

[0055] Method 400 proceeds to operation 408, as illustrated in Figure 4A, to form a channel structure that penetrates vertically through the dielectric stack and sacrificial layer into the second semiconductor layer. In some embodiments, to form the channel structure, a channel hole is formed that penetrates vertically through the dielectric stack and sacrificial layer into the second semiconductor layer, and then a memory film and a semiconductor channel are formed on the sidewalls of the channel hole, with a channel plug formed above and in contact with the semiconductor channel.

[0056] As illustrated in Figure 3A, channel holes are openings that penetrate vertically through the dielectric stack 308 and sacrificial layer 306 into the N-type doped semiconductor layer 304. In some embodiments, multiple openings are formed, each opening becoming a location for growing a separate channel structure 314 in a later process. In some embodiments, the fabrication process for forming the channel holes of the channel structure 314 includes wet etching and / or dry etching such as deep reactive ion etching (DRIE). In some embodiments, the channel holes of the channel structure 314 penetrate further into the top of the N-type doped semiconductor layer 304. The etching process through the dielectric stack 308 and sacrificial layer 306 may continue to etch a portion of the N-type doped semiconductor layer 304. In some embodiments, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 304 after etching through the dielectric stack 308 and sacrificial layer 306.

[0057] As illustrated in Figure 3A, the memory film 316 (including a blocking layer, a storage layer, and a tunnel layer), and the semiconductor channel 318 are subsequently formed in this order along the sidewalls and bottom of the channel hole. In some embodiments, the memory film 316 is first deposited along the sidewalls and bottom of the channel hole, and then the semiconductor channel 318 is deposited on top of the memory film 316. The blocking layer, storage layer, and tunnel layer can then be deposited in this order using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof, to form the memory film 316. The semiconductor channel 318 can then be formed by depositing a semiconductor material, such as polysilicon, on top of the tunnel layer of the memory film 316 using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof. In some embodiments, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer ("SONO" structure) are subsequently deposited to form a memory film 316 and a semiconductor channel 318.

[0058] As illustrated in Figure 3A, a capping layer is formed within the channel hole and on top of the semiconductor channel 318 to completely or partially fill the channel hole (e.g., with or without voids). The capping layer may be formed by depositing a dielectric material such as silicon oxide using one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof. A channel plug may then be formed at the top of the channel hole. In some embodiments, the memory film 316, semiconductor channel 318, and a portion of the capping layer on the top surface of the dielectric stack 308 are removed and planarized by CMP, wet etching, and / or dry etching. A recess may then be formed at the top of the channel hole by wet etching and / or dry etching the semiconductor channel 318 and a portion of the capping layer at the top of the channel hole. A channel plug may then be formed by depositing a semiconductor material such as polysilicon within the recess using one or more thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof. As a result, the channel structure 314 is formed within the N-type doped semiconductor layer 304, passing through the dielectric stack 308 and the sacrificial layer 306.

[0059] Method 400 proceeds to operation 410, as illustrated in Figure 4A, where the sacrificial layer is replaced with an N-type doped semiconductor layer to form a first semiconductor layer. In some embodiments, to replace the sacrificial layer with a first semiconductor layer, an opening is formed perpendicularly through the dielectric stack to expose a portion of the sacrificial layer, the sacrificial layer is etched through the opening to form a cavity, and N-type doped polysilicon is deposited in the cavity through the opening to form a first semiconductor layer.

[0060] As illustrated in Figure 3A, the slit 320 is an opening that penetrates the dielectric stack 308 vertically, exposing a portion of the sacrificial layer 306. In some embodiments, the fabrication process for forming the slit 320 includes wet etching and / or dry etching, such as DRIE. In some embodiments, the slit 320 penetrates further into the top of the sacrificial layer 306. The etching process through the dielectric stack 308 may not stop at the top surface of the sacrificial layer 306 and may continue to etch a portion of the sacrificial layer 306.

[0061] As illustrated in Figure 3B, the sacrificial layer 306 (shown in Figure 3A) is removed by wet etching and / or dry etching to form the cavity 322. In some embodiments, the sacrificial layer 306 contains polysilicon, which is etched by applying tetramethylammonium hydroxide (TMAH) etchant through the slit 320, and this etching can be stopped by a pad oxide layer 305 between the sacrificial layer 306 and the N-type doped semiconductor layer 304. That is, the removal of the sacrificial layer 306 does not affect the N-type doped semiconductor layer 304 in some embodiments. In some embodiments, a spacer 324 is formed along the sidewall of the slit 320 before the removal of the sacrificial layer 306. The spacer 324 may be formed by depositing a dielectric material, such as silicon nitride, silicon oxide, and silicon nitride, into the slit 320 using one or more thin-film deposition processes, such as CVD, PVD, ALD, or any combination thereof.

[0062] As illustrated in Figure 3C, a portion of the memory film 316 of the channel structure 314 exposed within the cavity 322 is removed to expose a portion of the semiconductor channel 318 of the channel structure 314 that abuts against the cavity 322. In some embodiments, portions of the blocking layer (e.g., containing silicon oxide), the storage layer (e.g., containing silicon nitride), and the tunnel layer (e.g., containing silicon oxide) are etched by applying an etchant, such as phosphoric acid for etching silicon nitride and hydrofluoric acid for etching silicon oxide, through the slit 320 and cavity 322. Etching can be stopped by the semiconductor channel 318 of the channel structure 314. A spacer 324 containing dielectric material (shown in Figure 3B) can also protect the dielectric stack 308 from etching of the memory film 316 and can be removed by an etchant in the same step as removing a portion of the memory film 316. Similarly, the pad oxide layer 305 on the N-type doped semiconductor layer 304 (shown in Figure 3B) can be removed in the same steps as removing a portion of the memory film 316.

[0063] As illustrated in Figure 3D, the N-type doped semiconductor layer 326 is formed above and in contact with the N-type doped semiconductor layer 304. In some embodiments, the N-type doped semiconductor layer 326 is formed by depositing polysilicon into the cavity 322 (shown in Figure 3C) through the slit 320 using one or more thin-film deposition processes, such as CVD, PVD, ALD, or any combination thereof. In some embodiments, the N-type doped semiconductor layer 326 is formed by selectively filling the cavity 322 with polysilicon epitaxially grown from the exposed portion (containing polysilicon) of the semiconductor channel 318. The fabrication process for epitaxially growing the N-type doped semiconductor layer 326 may include pre-cleaning the cavity 322 and then performing, for example, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. In some embodiments, in-situ doping with an N-type dopant, such as P or As, is performed when depositing or epitaxially growing polysilicon to form an N-type doped polysilicon layer as an N-type doped semiconductor layer 326. The N-type doped semiconductor layer 326 can fill a cavity 322 so as to contact the exposed portion of the semiconductor channel 318 of the channel structure 314.

[0064] Method 400 proceeds to operation 412, as illustrated in Figure 4A, where the dielectric stack is replaced with the memory stack, for example, using a so-called "gate replacement" process, thereby penetrating the channel structure perpendicularly through the memory stack and the first semiconductor layer into the second semiconductor layer. In some embodiments, to replace the dielectric stack with the memory stack, the stack sacrificial layer is replaced with a stack conductor layer through an opening. In some embodiments, the memory stack includes alternately arranged stack conductor layers and stack dielectric layers.

[0065] As illustrated in Figure 3E, the stack sacrificial layer 312 (shown in Figure 3A) is replaced by a stack conductor layer 328, and a memory stack 330, including alternating stack conductor layers 328 and stack dielectric layers 310, is formed thereby, replacing the dielectric stack 308 (shown in Figure 3A). In some embodiments, outer recesses (not shown) are first formed by removing the stack sacrificial layer 312 through a slit 320. In some embodiments, the stack sacrificial layer 312 is removed by etching through the slit 320, forming alternating outer recesses between the stack dielectric layers 310. The etchant may include any suitable etchant that selectively etches the stack sacrificial layer 312 with respect to the stack dielectric layers 310. As illustrated in Figure 3E, the stack conductor layer 328 (including the gate electrode and adhesive layer) is deposited in the outer recesses through the slit 320. In some embodiments, the gate dielectric layer 332 is deposited in the outer recess in front of the stacked conductor layer 328, and the stacked conductor layer 328 is deposited on top of the gate dielectric layer. The stacked conductor layer 328, such as a metal layer, can be deposited using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. In some embodiments, the gate dielectric layer 332, such as a high-k dielectric layer, is also formed along the sidewall and at the bottom of the slit 320.

[0066] Method 400 proceeds to operation 414, as illustrated in Figure 4B, to form an insulating structure that penetrates the memory stack vertically. In some embodiments, to form the insulating structure, one or more dielectric materials are deposited in the openings after the memory stack has been formed to fill the openings. As illustrated in Figure 3F, an insulating structure 336 is formed that penetrates the memory stack 330 vertically and stops on the top surface of the N-type doped semiconductor layer 326. The insulating structure 336 may be formed by depositing one or more dielectric materials, such as silicon oxide, into the slit 320 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof, to completely or partially fill the slit 320 (with or without voids). In some embodiments, the insulating structure 336 includes a gate dielectric layer 332 (e.g., containing a high-k dielectric) and a dielectric capping layer 334 (e.g., containing silicon oxide).

[0067] As illustrated in Figure 3G, after the formation of the insulating structure 336, local contacts, including channel local contacts 344 and word line local contacts 342, as well as peripheral contacts 338 and 340, are formed. The local dielectric layer may be formed on the memory stack 330 by depositing a dielectric material, such as silicon oxide or silicon nitride, onto the memory stack 330 using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. The channel local contacts 344, word line local contacts 342, and peripheral contacts 338 and 340 may be formed by etching the contact openings through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching, e.g., RIE, and then filling the contact openings with conductive material using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0068] As illustrated in Figure 3H, the bonding layer 346 is formed above the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. The bonding layer 346 includes bonding contacts electrically connected to the channel local contact 344, the word line local contact 342, and the peripheral contacts 338 and 340. To form the bonding layer 346, the ILD layer is deposited using one or more thin film deposition processes such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and / or dry etching, e.g., RIE, and then one or more thin film deposition processes, or any combination thereof, such as ALD, CVD, PVD, or any other preferred process.

[0069] Method 400 proceeds to operation 416, as illustrated in Figure 4B, where the first and second substrates are bonded facing each other, and the memory stack is above the peripheral circuitry. The bonding can be a hybrid bonding. As illustrated in Figure 3I, the silicon substrate 302 and the components formed thereon (e.g., the memory stack 330 and the channel structure 314 formed through it) are inverted. The downward bonding layer 346 is bonded to the upward bonding layer 348, i.e., bonded facing each other, thereby forming a bonding interface 354 between the silicon substrates 302 and 350, in some embodiments. In some embodiments, processing steps, such as plasma treatment, wet treatment, and / or heat treatment, are applied to the bonding surface before bonding. After bonding, the bonding contacts in bonding layer 346 and bonding contacts in bonding layer 348 are aligned and in contact with each other, thereby electrically connecting the memory stack 330 and the channel structure 314 formed through it to the peripheral circuit 352, which is located above the peripheral circuit 352.

[0070] Method 400 proceeds to operation 418, as illustrated in Figure 4B, in which the second substrate is thinned to expose the second semiconductor layer. Thinning is performed from the second side (e.g., the back side) opposite the first side of the second substrate. As illustrated in Figure 3J, the silicon substrate 302 (shown in Figure 3I) is thinned from the back side to expose the N-type doped semiconductor layer 304. The silicon substrate 302 may be thinned using CMP, grinding, dry etching, and / or wet etching. In some embodiments, the CMP process is performed to thin the silicon substrate 302 until the top surface of the N-type doped semiconductor layer 304 is reached.

[0071] Method 400 proceeds to operation 420, as illustrated in Figure 4B, in which a source contact is formed above the memory stack and in contact with the second semiconductor layer. In some embodiments, the source contact is formed on the second side of the second substrate opposite to the first side (e.g., the back side) (e.g., the second semiconductor layer after thinning). In some embodiments, the source contact is aligned with an insulating structure.

[0072] As illustrated in Figure 3K, one or more ILD layers 356 are formed on the N-type doped semiconductor layer 304. The ILD layers 356 may be formed by depositing dielectric material on the top surface of the N-type doped semiconductor layer 304 using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof. As illustrated in Figure 3K, a source contact opening 358 is formed in the N-type doped semiconductor layer 304 through the ILD layer 356. In some embodiments, the source contact opening 358 is formed using wet etching and / or dry etching, such as RIE. In some embodiments, the source contact opening 358 penetrates further into the top of the N-type doped semiconductor layer 304. The etching process through the ILD layer 356 may continue to etch a portion of the N-type doped semiconductor layer 304. In some embodiments, a separate etching process is used to etch a portion of the N-type doped semiconductor layer 304 after etching through the ILD layer 356. In some embodiments, the source contact opening 358 is patterned using lithography to align with the insulating structure 336 on the opposite side of the N-type doped semiconductor layer 304.

[0073] As illustrated in Figure 3L, the source contact 364 is formed within a source contact opening 358 (shown in Figure 3K) on the back side of the N-type doped semiconductor layer 304. In some embodiments, the source contact 364 is located above the memory stack 330 and in contact with the N-type doped semiconductor layer 304. In some embodiments, one or more conductive materials are deposited within the source contact opening 358 using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof, to fill the source contact opening 358 with an adhesive layer (e.g., TiN) and a conductive layer (e.g., W). A planarization process, such as CMP, is then performed to remove excess conductive material and ensure that the top surface of the source contact 364 is coplanar with the top surface of the ILD layer 356. In some embodiments, when the source contact opening 358 is aligned with the insulating structure 336, the back-side source contact 364 is also aligned with the insulating structure 336.

[0074] Method 400 proceeds to operation 422, as illustrated in Figure 4B, where an interconnection layer is formed above the source contact and in contact with the source contact. As illustrated in Figure 3M, a redistribution layer 370 is formed above the source contact 364 and in contact with the source contact 364. In some embodiments, the redistribution layer 370 is formed by depositing a conductive material such as Al on the top surface of the N-type doped semiconductor layer 304 and the source contact 364 using one or more thin film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof. As illustrated in Figure 3M, a passivation layer 372 is formed on the redistribution layer 370. In some embodiments, the passivation layer 372 is formed by depositing a dielectric material such as silicon nitride using one or more thin film deposition processes, such as ALD, CVD, PVD, any other preferred process, or any combination thereof. In some embodiments, the interconnection layer 376, which includes the ILD layer 356, the redistribution layer 370, and the passivation layer 372, is formed accordingly.

[0075] Method 400 proceeds to operation 424, as illustrated in Figure 4B, where the contacts are formed through the second semiconductor layer and in contact with the interconnect layer, thereby electrically connecting the first semiconductor layer to the contacts through the second semiconductor layer, the source contacts, and the interconnect layer. Contact openings 360 and 361 are formed, penetrating the ILD layer 356 and the N-type doped semiconductor layer 304, respectively, as illustrated in Figure 3K. The contact openings 360 and 361 and the source contact opening 358 are formed using the same etching process, thereby reducing the number of etching processes. In some embodiments, the contact openings 360 and 361 are formed through the ILD layer 356 and the N-type doped semiconductor layer 304 using wet etching and / or dry etching such as RIE. In some embodiments, the contact openings 360 and 361 are patterned using lithography so as to be aligned with the peripheral contacts 338 and 340, respectively. Etching of the contact openings 360 and 361 can be stopped at the upper edges of the peripheral contacts 338 and 340, exposing the peripheral contacts 338 and 340. As illustrated in Figure 3K, spacers 362 are formed along the sidewalls of the contact openings 360 and 361 to electrically isolate the N-type doped semiconductor layer 304 using one or more thin film deposition processes such as ALD, CVD, PVD, any other preferred process, or any combination thereof.

[0076] As illustrated in Figure 3L, contacts 366 and 368 are formed in contact openings 360 and 361 (shown in Figure 3K) on the backside of the N-type doped semiconductor layer 304, respectively. In some embodiments, contacts 366 and 368 penetrate vertically through the ILD layer 356 and the N-type doped semiconductor layer 304. Contacts 366 and 368, as well as the source contact 364, are formed using the same deposition process, thereby reducing the number of deposition processes. In some embodiments, one or more conductive materials are deposited in the contact openings 360 and 361 using one or more thin-film deposition processes, such as ALD, CVD, PVD, any other suitable process, or any combination thereof, to fill the contact openings 360 and 361 with an adhesive layer (e.g., TiN) and a conductive layer (e.g., W). A planarization process, such as CMP, is then performed to remove excess conductive material and ensure that the top surfaces of contacts 366 and 368 are coplanar with the top surface of the ILD layer 356. In some embodiments, the contact openings 360 and 361 are aligned with the peripheral contacts 338 and 340, respectively, so that the contacts 366 and 368 are similarly above and in contact with the peripheral contacts 338 and 340, respectively.

[0077] As illustrated in Figure 3M, the redistribution layer 370 is also formed above the contact 366 and in contact with the contact 366. As a result, the N-type doped semiconductor layer 326 can be electrically connected to the peripheral contact 338 through the N-type doped semiconductor layer 304, the source contact 364, the redistribution layer 370 of the interconnection layer 376, and the contact 366. In some embodiments, the N-type doped semiconductor layers 326 and 304 are electrically connected to the peripheral circuit 352 through the source contact 364, the interconnection layer 376, the contact 366, the peripheral contact 338, and the junction layers 346 and 348.

[0078] As illustrated in Figure 3M, the contact pad 374 is formed above the contact 368 and in contact with the contact 368. In some embodiments, a portion of the passivation layer 372 covering the contact 368 is removed by wet etching and dry etching, thereby exposing a portion of the underlying redistribution layer 370 to form the contact pad 374. As a result, the contact pad 374 for pad-out can be electrically connected to the peripheral circuit 352 through the contact 368, the peripheral contact 340, and the bonding layers 346 and 348.

[0079] One aspect of this disclosure discloses a method for forming a 3D memory device. A sacrificial layer and a dielectric stack on the sacrificial layer are subsequently formed on a first side of the substrate above a second semiconductor layer. A channel structure is formed that penetrates perpendicularly through the dielectric stack and the sacrificial layer and into the second semiconductor layer. The sacrificial layer is replaced by the first semiconductor layer in contact with the second semiconductor layer. The dielectric stack is replaced by a memory stack, thereby the channel structure penetrates perpendicularly through the memory stack and the first semiconductor layer and into the second semiconductor layer. A source contact is formed on the second side of the substrate opposite to the first side so as to be in contact with the second semiconductor layer.

[0080] In some embodiments, before forming the sacrificial layer, a portion of the substrate is doped with an N-type dopant on the first side to form a second semiconductor layer.

[0081] In some embodiments, to replace the sacrificial layer with a first semiconductor layer, an opening is formed perpendicular to the dielectric stack to expose a portion of the sacrificial layer, the sacrificial layer is etched through the opening to form a cavity, and N-type doped polysilicon is deposited in the cavity through the opening to form the first semiconductor layer.

[0082] In some embodiments, polysilicon is deposited on a second semiconductor layer to form a sacrificial layer, and stack dielectric layers and stack sacrificial layers are alternately deposited on the sacrificial layer to form a dielectric stack.

[0083] In some embodiments, to replace the dielectric stack with a memory stack, the stack sacrificial layer is replaced with a stack conductive layer through an opening.

[0084] In some embodiments, after the memory stack is formed, one or more dielectric materials are deposited in the opening to form an insulating structure that penetrates the memory stack vertically.

[0085] In some embodiments, the source contacts are aligned with an insulating structure.

[0086] In some embodiments, before forming the source contact, the substrate is thinned from the second side to expose the second semiconductor layer.

[0087] In some embodiments, the interconnection layer is formed above the source contacts and is electrically connected to the source contacts.

[0088] In some embodiments, a contact is formed through a second semiconductor layer that is in contact with an interconnection layer, thereby electrically connecting the first semiconductor layer to the contact through the second semiconductor layer, the source contact, and the interconnection layer.

[0089] Another aspect of this disclosure discloses a method for forming a 3D memory device. A channel structure is formed on a first side of the substrate, penetrating perpendicularly through the memory stack and into an N-type doped semiconductor layer. The memory stack includes alternating stack conductor layers and stack dielectric layers. An insulating structure is formed within an opening that penetrates perpendicularly through the memory stack. Source contacts are formed on a second side of the substrate opposite to the first side, so as to contact the N-type doped semiconductor layer and align with the insulating structure.

[0090] In some embodiments, to form a channel structure, a portion of the substrate is doped with an N-type dopant on a first side to form a second N-type doped semiconductor layer, a sacrificial layer above the second N-type doped semiconductor layer, and a dielectric stack on the sacrificial layer are subsequently formed, the dielectric layer including alternating stacked sacrificial layers and stacked dielectric layers, forming a channel structure that penetrates perpendicularly through the dielectric stack and sacrificial layers and into the second N-type doped semiconductor layer, the sacrificial layer being replaced by the first N-type doped semiconductor layer through an opening.

[0091] In some embodiments, the stack sacrificial layer is replaced with a stack conductive layer to form a channel structure, thereby forming a memory stack.

[0092] In some embodiments, after replacing the stack sacrificial layer with a stack conductive layer to form an insulating structure, the openings are filled with one or more dielectric materials.

[0093] In some embodiments, before forming the source contact, the substrate is thinned from the second side to expose a second N-type doped semiconductor layer.

[0094] A method for forming a 3D memory device is disclosed in yet another aspect of this disclosure. Peripheral circuits are formed on a first substrate. A channel structure is formed that penetrates perpendicularly through the memory stack and the first semiconductor layer and into a second semiconductor layer on a second substrate. The first and second substrates are bonded facing each other so that the memory stack is above the peripheral circuits. The second substrate is thinned to expose the second semiconductor layer. Source contacts are formed above the memory stack and in contact with the second semiconductor layer.

[0095] In some embodiments, to form a channel structure, a portion of a second substrate is doped with an N-type dopant to form a second semiconductor layer, a sacrificial layer above the second semiconductor layer and a dielectric stack on the sacrificial layer are subsequently formed, and a channel structure is formed that penetrates perpendicularly through the dielectric stack and the sacrificial layer and into the second semiconductor layer, and the sacrificial layer is replaced by an N-type doped semiconductor layer through an opening to form a first semiconductor layer.

[0096] In some embodiments, the dielectric stack is replaced with a memory stack to further form a channel structure.

[0097] In some embodiments, an insulating structure is formed that penetrates the memory stack vertically before the first and second substrates are joined. Source contacts are aligned with the insulating structure according to some embodiments.

[0098] In some embodiments, the interconnection layer is formed above the source contact and in contact with the source contact.

[0099] In some embodiments, a contact is formed through a second semiconductor layer that is in contact with an interconnection layer, thereby electrically connecting the first semiconductor layer to the contact through the second semiconductor layer, the source contact, and the interconnection layer.

[0100] The above descriptions of specific embodiments will reveal the general nature of this disclosure so that, by applying knowledge within the scope of the art, such specific embodiments can be easily modified and / or adapted to various uses without departing from the general concepts of this disclosure and without conducting unnecessary experiments. Accordingly, such adaptations and modifications are intended to fall within the meaning and scope of the equivalent embodiments disclosed, based on the teachings and guidance presented herein. It will be understood that the language or terminology used herein is for illustrative purposes only and should therefore be interpreted by those skilled in the art in light of the teachings and guidance.

[0101] Embodiments of the present disclosure have been described above with the help of functional configuration blocks illustrating implementations of specified functions and their relationships. The boundaries of these functional configuration blocks are arbitrarily defined herein for the sake of clarity. Alternative boundaries may be defined insofar as the specified functions and their relationships are adequately performed.

[0102] The sections describing the invention and abstract may specify one or more, but not all, exemplary embodiments of the present disclosure as contemplated by the inventors, and are therefore not intended to limit the present disclosure and the accompanying claims in any way.

[0103] The extent and scope of this disclosure should be defined solely by the claims and their equivalents, and not by the exemplary embodiments described above. [Explanation of symbols]

[0104] 100 3D memory devices 101 circuit board 102 First Semiconductor Structure 104 Second Semiconductor Structure 106 Joint interface 108 Peripheral Circuits 110 Bonding layer 111 Bonding Contact 112 Bonding layer 113 Bonding Contact 114 Memory Stack 116 Conductive layer 118 Dielectric layer 120 First semiconductor layer 122 Second semiconductor layer 124-channel structure 126 memory film 128 semiconductor channels 129 Channel Plug 130 Insulation structure 132 Source contact, backside source contact 133 Interconnection Layer 134 ILD layer 136 Redistribution layer 138 Passivation Layer 140 Contact Pads 142, 144 Contact 146, 148 Peripheral contact 150 Channel Local Contacts 152 Word Line Local Contact 200 3D memory devices 202 blocks 204 Stairs area 206 Core Array Area 206A First core array region 206B Second core array region 208 Insulation structure 209 Backside source line 210-channel structure 211 N-well pickup contact 212 Drain Select Gate Cut 213 Pad-out contact 214 areas 215 Source Contact 302 Silicon substrate 304 N-type doped semiconductor layer 305 Pad oxide layer 306 layers of victims 308 Dielectric Stack 310 Stacked dielectric layer 312 stack sacrifice layer 314 channel structure 316 Memory film 318 Semiconductor Channels 320 slits 322 Cavity 324 Spacer 326 N-type doped semiconductor layer 328 Stacked conductive layer 330 memory stack 332 Gate dielectric layer 334 Dielectric capping layer 336 Insulation structure 338, 340 Peripheral Contact 342 Word Line Local Contact 344 Channel Local Contacts 346 Bonding layer 348 Bonding layer 350 silicon substrates 352 Peripheral Circuits 354 Joint interface 356 ILD layer 358 Source Contact Opening 360, 361 Contact openings 362 Spacers 364 Source Contact, Backside Source Contact 366, 368 Contacts 370 Redistribution layer 372 Passivation Layer 374 Contact Pads 376 Interconnection Layer 400 ways

Claims

1. A first stack structure comprising a first dielectric layer and a first conductive layer arranged alternately along a first direction, A second dielectric layer located to the side of the first stack structure in a second direction perpendicular to the first direction, In the first direction, the semiconductor layer is located on the first stack structure and the second dielectric layer, A channel structure extending along the first direction through the first stack structure and coupled to the semiconductor layer, comprising a memory film and a semiconductor channel surrounded by the memory film, A first contact structure extending within the second dielectric layer along the first direction, wherein the length of the first contact structure in the first direction is greater than the dimension of the first stack structure in the first direction, A second contact structure extends through a portion of the semiconductor layer in the second dielectric layer and is coupled to the first contact structure, A semiconductor device equipped with the following features.

2. One or more third dielectric layers on the semiconductor layer, wherein the semiconductor layer is located between one or more of the third dielectric layers and the first stack structure in the first direction, A third contact structure extending through one or more of the aforementioned third dielectric layers and bonded to the semiconductor layer, The semiconductor device according to claim 1, further comprising:

3. The present invention further comprises a second conductive layer bonded to the semiconductor layer through the third contact structure, The semiconductor device according to claim 2, wherein one or more of the third dielectric layers are located between the second conductive layer and the semiconductor layer in the first direction.

4. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The semiconductor device according to claim 2, wherein the channel structure extends through the first semiconductor layer into the second semiconductor layer.

5. The semiconductor device according to claim 4, wherein the third contact structure extends further into the second semiconductor layer but does not extend into the first semiconductor layer.

6. The semiconductor device according to claim 3, wherein a plurality of the third contact structures are arranged along the second direction and are in contact with the second conductive layer.

7. The second stack structure further comprises a fourth dielectric layer and a third conductive layer arranged alternately along the first direction, The semiconductor device according to claim 1, wherein the second dielectric layer and the first contact structure are located between the first stack structure and the second stack structure in the second direction.

8. The semiconductor layer further comprises a concave structure aligned with the first contact structure, The semiconductor device further comprises an insulating layer located within the concave structure, The semiconductor device according to claim 1, wherein the insulating layer is located between the second contact structure and the semiconductor layer.

9. The semiconductor device according to claim 1, wherein the first contact structure extends into the second contact structure and is in contact with the second contact structure.

10. The structure further comprises a slit structure extending along the second direction through the first stack structure, The semiconductor device according to claim 2, wherein the slit structure overlaps with the third contact structure.

11. The semiconductor device according to claim 3, wherein the top surface of the second contact structure is aligned with the top surface of the second conductive layer.

12. A first interconnection layer, wherein the first stack structure is located between the first interconnection layer and the semiconductor layer in the first direction, circuit board and The peripheral circuits on the aforementioned substrate, A second interconnection layer joined to the first interconnection layer, Furthermore, The semiconductor device according to claim 1, wherein the peripheral circuit is located between the substrate and the second interconnection layer in the first direction.

13. The semiconductor device according to claim 12, wherein the first contact structure extends from the semiconductor layer to the first interconnection layer.

14. The semiconductor device according to claim 4, wherein the first semiconductor layer extends through the memory film and contacts the semiconductor channel.

15. A stack structure comprising a first dielectric layer and a first conductive layer arranged alternately along a first direction, A second dielectric layer located laterally to the stack structure in a second direction perpendicular to the first direction, A semiconductor layer on the stack structure in the first direction, A channel structure extending through the stack structure along the first direction and coupled to the semiconductor layer, comprising a memory film and a semiconductor channel surrounded by the memory film, A first contact structure extending within the second dielectric layer along the first direction, wherein the length of the first contact structure in the first direction is greater than the dimensions of the stack structure in the first direction, A plurality of third contact structures arranged along a third direction perpendicular to the first and second directions, Equipped with, A semiconductor device in which the semiconductor layer is located between the stack structure and a plurality of third contact structures in the first direction, and the first contact structure is located between two adjacent third contact structures in the third direction.

16. The semiconductor layer is further located on the second dielectric layer. The semiconductor layer further comprises a concave structure aligned with the first contact structure, The aforementioned semiconductor device A second contact structure extends through a portion of the semiconductor layer in the second dielectric layer and is coupled to the first contact structure, The aforementioned recessed structure further comprises an insulating layer, The semiconductor device according to claim 15, wherein the insulating layer is located between the second contact structure and the semiconductor layer.

17. A first interconnection layer, wherein the stack structure is located between the first interconnection layer and the semiconductor layer in the first direction, circuit board and The peripheral circuits on the aforementioned substrate, A second interconnection layer joined to the first interconnection layer, Furthermore, The semiconductor device according to claim 15, wherein the peripheral circuit is located between the substrate and the second interconnection layer in the first direction.

18. One or more third dielectric layers on the semiconductor layer, wherein the semiconductor layer further comprises a third dielectric layer located between the one or more third dielectric layers and the stack structure in the first direction. The semiconductor device according to claim 15, wherein a plurality of the third contact structures extend through one or more third dielectric layers and are bonded to the semiconductor layer.

19. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer. The channel structure extends through the first semiconductor layer and into the second semiconductor layer. The semiconductor device according to claim 15, wherein the plurality of third contact structures extend further into the second semiconductor layer but do not extend into the first semiconductor layer.

20. A stack structure comprising a first dielectric layer and a first conductive layer arranged alternately along a first direction, A second dielectric layer located laterally to the stack structure in a second direction perpendicular to the first direction, Semiconductor layer, A channel structure extending through the stack structure along the first direction and coupled to the semiconductor layer, comprising a memory film and a semiconductor channel surrounded by the memory film, A slit structure extending through the stack structure along the second direction, One or more third dielectric layers, wherein the semiconductor layer is located between the one or more third dielectric layers and the stack structure in the first direction, A plurality of source contact structures arranged along the second direction, wherein the semiconductor layer is located between the stack structure and the plurality of source contact structures in the first direction, and the plurality of source contact structures extend through one or more third dielectric layers and are coupled to the semiconductor layer, A second conductive layer coupled to a plurality of the source contact structures, wherein one or more of the third dielectric layers are located between the second conductive layer and the semiconductor layer in the first direction, A semiconductor device equipped with the following features.

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