Semiconductor memory

Abstract

To provide a highly integrated semiconductor memory device, or in situations where power is not supplied. However, the objective is to provide a semiconductor memory device that can retain its contents, or a writable memory device. To provide a large number of semiconductor memory devices. [Solution] The memory cell is composed of two transistors and one capacitor, and these By arranging transistors and capacitors in a three-dimensional manner, the integration density of the memory cell array is increased. The transistor that controls the amount of charge in the capacitor provided in the memory cell is made of silicon. By forming it with a wide-bandgap semiconductor with a wide bandgap, the off-current is reduced, thus increasing capacitance. This prevents the charge accumulated in the lower part from leaking out. This ensures that even in situations where power is not supplied... To provide a semiconductor memory device capable of retaining its contents.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device.

Background Art

[0002] With the integration of semiconductor memory devices, reduction in the occupied area of semiconductor elements has been demanded. For example , in order to increase the integration degree of a transistor, which is one of semiconductor elements, a so-called vertical transistor in which a channel is formed perpendicular to a substrate is known. When adopting this structure, a source electrode or a drain electrode and an active layer where a channel is formed overlap, and the occupied area of the transistor can be reduced (see, for example, Patent Document 1). As a result, a semiconductor memory device using a plurality of such transistors can be integrated.

[0003] By the way, semiconductor memory devices include a volatile semiconductor memory device in which stored contents are lost when power supply is stopped, and a non-volatile semiconductor memory device in which stored contents are retained even when power supply is stopped.

[0004] Typical examples of volatile semiconductor memory devices include DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). These volatile semiconductor memory devices lose stored contents when power supply is stopped, but consume relatively low power because they do not require a large voltage like non-volatile memory.

[0005]

[0006]

[0007]

[0008]

[0009]

[0010]

[0011] <0000It has a floating gate, and memory is stored by holding an electric charge in the floating gate. To achieve this, the data retention period is extremely long (semi-permanent), and the refrigerant required for volatile memory is... It has the advantage of not requiring a reshuffling operation (see, for example, Patent Document 2).

[0006] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Due to degradation, a problem arises where the memory element ceases to function after a predetermined number of write cycles. To mitigate the effects of this problem, for example, the number of write cycles for each memory element can be made uniform. A method is employed. However, achieving this requires complex peripheral circuits. Furthermore, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. In other words, floating-gate memory is unsuitable for applications where information is frequently rewritten. be.

[0007] To improve the problems of such floating-gate memory, two transistors and A semiconductor memory device equipped with a memory cell using a single capacitive element has been proposed (Patent Document). 3) The semiconductor memory device according to the disclosed invention has a capacitor on the gate electrode of the first transistor. A lower section is provided, and a second transistor is provided for injecting and removing charge from the capacitor. The second transistor is made of a material that can sufficiently reduce the transistor's off-current. For example, it is composed of oxide semiconductor material, which is a wide-bandgap semiconductor. Because the off-current of the zista is sufficiently small, the charge of the capacitor does not disappear over a long period of time. Therefore, this semiconductor memory device can retain information for a long period of time.

[0008] The semiconductor memory device has no problem with the function of retaining information. However, as a semiconductor memory device, further integration is desired.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, one of the objectives is to provide a semiconductor memory device with a high degree of integration Or, one of the objectives is to provide a semiconductor memory device capable of retaining stored content even when no power is supplied Or, one of the objectives is to provide a semiconductor memory device with a large number of writeable cycles Or, one of the objectives is to provide a semiconductor memory device with a large number of writeable cycles.

Means for Solving the Problems

[0011] A semiconductor memory device according to one aspect of the present invention comprises a memory cell composed of two transistors and one capacitor, and arranges these transistors and the capacitor three-dimensionally. By arranging the transistors and the capacitor that constitute the memory cell three-dimensionally, the cell density per unit area of the memory cell array is increased. One of the transistors provided in the memory cell is a transistor that controls the charge amount of the capacitor. In one aspect of the present invention, this The memory cell is composed of two transistors and one capacitor, and these transistors and the capacitor are arranged three-dimensionally. By arranging the transistors and the capacitor that constitute the memory cell three-dimensionally, the cell density per unit area of the memory cell array is increased. One of the transistors provided in the memory cell is a transistor that controls the charge amount of the capacitor. In one aspect of the present invention, this memory cell is composed of two transistors and one capacitor, and these transistors and the capacitor are arranged three-dimensionally. By arranging the transistors and the capacitor that constitute the memory cell three-dimensionally, the cell density per unit area of the memory cell array is increased. One of the transistors provided in the memory cell is a transistor that controls the charge amount of the capacitor. In one aspect of the present invention, this memory cell is composed of two transistors and one capacitor, and these transistors and the capacitor are arranged three-dimensionally. By arranging the transistors and the capacitor that constitute the memory cell three-dimensionally, the cell density per unit area of the memory cell array is increased. One of the transistors provided in the memory cell is a transistor that controls the charge amount of the capacitor. In one aspect of the present invention, this memory cell is composed of two transistors and one capacitor, and these transistors and the capacitor are arranged three-dimensionally. By arranging the transistors and the capacitor that constitute the memory cell three-dimensionally, the cell density per unit area of the memory cell array is increased. One of the transistors provided in the memory cell is a transistor that controls the charge amount of the capacitor. In one aspect of the present invention, this Reduce the leakage current of the transistor. In order to reduce the leakage current of the transistor use a semiconductor material having a wider bandgap than silicon in the channel region. As a result a semiconductor memory device capable of retaining stored content for a certain period even when power is not supplied is provided .

[0012] That is, one aspect of the present invention has a memory cell including a first transistor, a second transistor, and a capacitor The first transistor has a first semiconductor layer, a first gate insulating layer contacting the first semiconductor layer above, a first gate electrode contacting the first gate insulating layer and overlapping the first semiconductor layer, and a source region and a drain region provided to sandwich a region overlapping the first gate electrode of the first semiconductor layer The second transistor is disposed to overlap the first gate electrode and has a second semiconductor layer electrically connected to the first gate electrode, a second gate insulating layer contacting a side surface of the second semiconductor layer, and a second gate electrode formed to cover at least a part of the side surface of the second semiconductor layer by contacting the second gate insulating layer The capacitor has a capacitive layer contacting a side surface of the first gate electrode and a first capacitive electrode formed to cover at least a part of the side surface of the first gate electrode by contacting the capacitive layer This is a semiconductor memory device The first gate electrode functions as a source electrode or a drain electrode of the second transistor, and the second semiconductor layer is formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor The first capacitive electrode is formed so as to cover at least a part of the side surface of the first gate electrode by contacting the capacitive layer This is a semiconductor memory device

[0013] The first gate electrode functions as a source electrode or a drain electrode of the second transistor, and the second semiconductor layer is formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor formed to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor sandwich the second semiconductor layer and are disposed substantially perpendicular to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupation area than, for example, a planar transistor

[0014] Furthermore, the first gate electrode of the first transistor is used as one of the capacitive electrodes of the capacitor. Therefore, the area occupied by the capacitor can be reduced.

[0015] When the second transistor of the semiconductor memory is turned on, one electrode of the capacitor, that is, Therefore, a potential difference is generated between the first gate electrode of the first transistor and the first capacitive electrode of the other transistor. According to that potential difference, charge is retained in the capacitor. Then, the first transistor... By turning it off, the written data can be retained.

[0016] Furthermore, the second semiconductor layer is composed of a semiconductor material with a wider bandgap than silicon. It is preferable that the semiconductor memory device is one of the following.

[0017] Applying a semiconductor made of a material with a wider bandgap than silicon to the second semiconductor layer. This reduces the off-current of the second transistor. Therefore, when power is supplied... Even in situations where it cannot be used, the second transistor retains the memory content for a longer period than a configuration where silicon is used. This allows us to provide a semiconductor memory device that can maintain its capacity.

[0018] Furthermore, the semiconductor memory device is a floating-gate (FG) type non-volatile memory. Therefore, during data writing and erasing, the carrier does not damage the gate insulation layer. It does not degrade even after repeated writing and erasing. In other words, this semiconductor memory device is FG type non It can improve the reliability of data retention compared to volatile memory. Therefore, writable We can provide semiconductor memory devices with a high number of cycles (for example, more than 1 million cycles).

[0019] Furthermore, it is preferable that the second semiconductor layer is a semiconductor memory device composed of an oxide semiconductor. It seems so.

[0020] By applying an oxide semiconductor to the second semiconductor layer, the off-current of the second transistor is reduced. Therefore, it provides a semiconductor memory device that can retain its contents even when power is not supplied. It is possible to do so. In addition, oxide semiconductor films are used in semiconductor fabrication processes using silicon wafers. Since it can be formed at temperatures lower than those commonly used in Seth, for example, 1000°C, the said semi-semi Conductive memory devices can be easily fabricated. In addition, the second semiconductor layer can be subjected to a heat treatment after film formation. Even when using an oxide semiconductor that has not undergone any special treatment, the second transistor can, for example, operate at 100 cm². 2 It is also possible to achieve field effect mobility exceeding / V·sec. By using a second transistor with high mobility, it is possible to obtain a semiconductor memory device with a high writing speed. It is possible.

[0021] Furthermore, one aspect of the present invention includes a first transistor, a second transistor, and a capacitor. The first transistor has a memory cell and a first semiconductor layer and a first semiconductor layer in contact with the first semiconductor layer. A gate insulating layer and a first gate electrode that is in contact with the first gate insulating layer and overlaps with the first semiconductor layer. , a source region and a dotted region are provided so as to sandwich the region that overlaps with the first gate electrode of the first semiconductor layer. The second transistor has a rain region and is positioned to overlap the first gate electrode. A second semiconductor layer electrically connected to the first gate electrode, and a second gate electrode in contact with the side surface of the second semiconductor layer. A gate insulating layer and a second gate insulating layer that are in contact with and cover at least a portion of the side surface of the second semiconductor layer. The capacitor has a second gate electrode formed in such a way, and the capacitor has a first gate electrode and a second semiconductor A second capacitive electrode electrically connects to the body layer, a capacitive layer in contact with the second capacitive electrode, and a capacitive layer in contact with the body layer. and a first capacitive electrode formed to cover at least a portion of the side surface of the second capacitive electrode, It is a semiconductor memory device.

[0022] The first gate electrode functions as the source or drain electrode of the second transistor, The two semiconductor layers are formed so as to overlap with the first gate electrode. Therefore, the second transistor The source and drain electrodes of the transistor are perpendicular to the substrate forming the transistor, and the second half The conductor layer is sandwiched between the transistors. Therefore, the second transistor is, for example, a planar type transistor. Compared to Zista, it can occupy a smaller area.

[0023] Furthermore, the capacitor uses the second and first capacitance electrodes as capacitance electrodes. The first transistor and the second transistor overlap. Therefore, When the first transistor, capacitor, and second transistor are formed so that they do not overlap, This allows for a reduction in the area occupied by the capacitor.

[0024] Furthermore, by providing a second capacitive electrode, the electrical connection between the first gate electrode and the second semiconductor layer is established. It can be made easy.

[0025] When the second transistor of the semiconductor memory is turned on, one electrode of the capacitor, that is, A potential difference is generated between the second capacitive electrode and the first capacitive electrode. According to that potential difference, Charge is retained in the capacitor. Then, by turning off the first transistor... It can retain the data that has been written to it.

[0026] Furthermore, the second semiconductor layer is composed of a semiconductor material with a wider bandgap than silicon. It is preferable that the semiconductor memory device is one of the following.

[0027] Applying a semiconductor made of a material with a wider bandgap than silicon to the second semiconductor layer. This reduces the off-current of the second transistor. Therefore, when power is supplied... This provides a semiconductor memory device that can retain its contents even in situations where it cannot be stored.

[0028] Furthermore, the semiconductor memory device is a floating-gate (FG) type non-volatile memory. Therefore, during data writing and erasing, the carrier does not damage the gate insulation layer. It does not degrade even after repeated writing and erasing. In other words, this semiconductor memory device is FG type non It can improve the reliability of data retention compared to volatile memory. Therefore, writable We can provide semiconductor memory devices with a high number of cycles (for example, more than 1 million cycles).

[0029] Furthermore, it is preferable that the second semiconductor layer is a semiconductor memory device composed of an oxide semiconductor. It seems so.

[0030] By applying an oxide semiconductor to the second semiconductor layer, the off-current of the second transistor is reduced. Therefore, it provides a semiconductor memory device that can retain its contents even when power is not supplied. It is possible to do so. In addition, oxide semiconductor films are used in semiconductor fabrication processes using silicon wafers. Since it can be formed at temperatures lower than those commonly used in Seth, for example, 1000°C, the said semi-semi Conductive memory devices can be easily fabricated. In addition, the second semiconductor layer can be subjected to a heat treatment after film formation. Even when using an oxide semiconductor that has not undergone any special treatment, the second transistor can, for example, operate at 100 cm². 2 It is also possible to achieve field effect mobility exceeding / V·sec. By using a second transistor with high mobility, it is possible to obtain a semiconductor memory device with a high writing speed. It is possible. [Effects of the Invention]

[0031] According to one aspect of the present invention, a highly integrated semiconductor memory device can be provided. We can provide a semiconductor memory device that can retain its contents even when power is not supplied. It is possible to provide a semiconductor memory device that can be written to a large number of times.

[0032] According to one aspect of the present invention, the second semiconductor layer of the second transistor overlaps with the first gate electrode. By arranging them in this way, the integration density of the memory cell array can be improved. The transistor that controls the amount of charge in the capacitor provided in the memory cell is made of silicon rather than silicon. By forming it with a semiconductor material with a wide bandgap, memory can be retained even when power is not supplied. A semiconductor memory device capable of retaining capacity can be provided. A transistor with low leakage current is used to control the amount of charge in the capacitor. This provides a semiconductor memory device that is non-volatile yet has no limit on the number of write cycles. It is possible. [Brief explanation of the drawing]

[0033] [Figure 1] A cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device according to one embodiment of the present invention. [Figure 2] A cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device according to one embodiment of the present invention. [Figure 3] A cross-sectional view, a top view, and a circuit diagram of a semiconductor memory device according to one embodiment of the present invention. [Figure 4]A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 5] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 6] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 7] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 8] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 9] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 10] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 11] A cross-sectional view of each step in the manufacturing process of a semiconductor memory device according to one embodiment of the present invention. [Figure 12] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 13] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 14] A diagram illustrating the structure of an oxide material according to one aspect of the present invention. [Figure 15] A diagram illustrating the crystal structure of an oxide material according to one aspect of the present invention. [Figure 16] A circuit diagram of the main part of a semiconductor memory device according to one aspect of the present invention. [Figure 17] A diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] A diagram illustrating an electronic device according to one embodiment of the present invention. [Figure 19] A diagram illustrating an electronic device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0034] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... The present invention may be implemented in any form without departing from the spirit and scope of the invention, but is not limited to the following description. It will be easily understood by those skilled in the art that the details can be changed in various ways. The invention shall not be construed as being limited to the embodiments described below.

[0035] (Embodiment 1) In this embodiment, an example of the configuration of a semiconductor memory device, which is one aspect of the present invention, is shown using Figure 1. I will explain.

[0036] Figure 1(B) is a schematic top view of the semiconductor memory device 1, and Figure 1(A) is a part of Figure 1(B). This is a schematic cross-sectional view along the dashed line A1-B1. Figure 1(C) is a circuit diagram of semiconductor memory device 1. That is the case.

[0037] The semiconductor memory device 1 illustrated in this embodiment has a plurality of parallel bit lines 500 and bit It has multiple first word lines 105 and second word lines 106 that are perpendicular to the bit line 500, and bit line 500, in the overlapping region of the first word line 105 and the second word line 106, the first transit A transistor 100, a second transistor 200, and a capacitor 300a are formed. Cell 10 consists of the first transistor 100, the second transistor 200, and the capacitor 30. Includes 0a. Note that the first word line 105 is the first capacitive electrode 310a and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0038] ((First transistor)) The first transistor 100 will be described. The first transistor 100 is located in the first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and the first gate insulating layer The first gate electrode 120 is in contact with 110 and overlaps with the first semiconductor layer 101, and the first semiconductor layer 1 Source region and Dray It has a region 130 and a first interlayer film 150. The first gate electrode 120 is connected to the second transistor It is electrically connected to the second semiconductor layer 201 of TA 200. Also, the first gate electrode 120 It functions as one of the electrodes of capacitor 300a.

[0039] Either the source region or the drain region 130 is connected to the bit line 500 via the conductive layer 600. They are electrically connected. The other of the source region or drain region 130 is used as wiring. And, electrically, the source region or drain region 130 of the adjacent first transistor 100 is connected. Connect to the source region and drain region 130 to reduce the electrical resistance of the source region and The drain region 130 is doped with a high concentration of impurities. Also, the source region Alternatively, the drain region 130 is separated from the source region or drain region of an adjacent element by the insulating layer 7 It is electrically isolated at 00.

[0040] (First semiconductor layer) The first semiconductor layer 101 is, for example, single crystal silicon, polysilicon, microcrystal silicon Recon and oxide semiconductors can be used. The first transistor 100 is as described later. Since it is a transistor that reads out information, it is a transistor with a high switching speed. It is preferable to apply this. Therefore, the first semiconductor layer 101 uses single crystal silicon. This is preferable.

[0041] (First gate insulating layer) An insulating material can be used for the first gate insulating layer 110. For example, an insulating material can be used. Hafnium oxide, yttrium oxide, hafnium silicate, aluminum hafnium Hafnium silicate, nitrogen-added hafnium aluminate Materials such as lanthanum oxide can be used. The material used for the first gate insulating layer 110 is The optimal material is used for the first semiconductor layer 101 used in the first transistor 100. That is fine. Also, the thickness of the first gate insulating layer 110 is the channel length of the first transistor 100. You should set the appropriate film thickness accordingly.

[0042] (First gate electrode) The material of the first gate electrode 120 has electrical conductivity and adhesion to the first gate insulating layer 110, All that is needed is low-resistance polysilicon (with impurities such as phosphorus added to impart conductivity). Polysilicon), or, for example, molybdenum, titanium, tantalum, copper, tungsten, Metal materials such as aluminum, chromium, neodymium, scandium, or materials with these as the main components It can be formed using an alloy material. Furthermore, the first gate electrode 120 has a single-layer structure. Alternatively, it may be a laminated structure.

[0043] (Source area or drain area) The source region or drain region 130 has good ohms with the source electrode or drain electrode. It is preferable that a contact is obtained and that the resistance in the direction perpendicular to the film thickness direction is low. The goal is to be able to connect to the region where the channel of the semiconductor layer 101 is formed without creating resistance. When silicon is used for the first semiconductor layer 101, a shallow pn junction is formed, and the first gate electrode It is preferable that 120 and the source area or drain area 130 do not overlap.

[0044] (First interlayer membrane) The first interlayer film 150 can be an insulator. For example, silicon oxide, silicon oxynitride Inorganic materials such as carbon dioxide, silicon nitride, and aluminum oxide can be used. Organic resins such as acrylic resin and polyimide resin can be used.

[0045] (Conductive layer) The conductive layer 600 only needs to be electrically connected to the first semiconductor layer 101 and the bit line 500, for example. For example, it can be formed by embedding metal and flattening it using methods such as CMP.

[0046] (Insulating layer) The insulating layer 700 can be formed from silicon oxide, silicon nitride, etc. For example, LOCOS (Local Oxidation of Silicon) method or shallow trench Using the separation method (STI method: Shallow Trench Isolation), Multiple device formation regions, separated by an oxide film, can be formed on a crystalline semiconductor substrate.

[0047] ((capacitor)) Next, capacitor 300a will be described. Capacitor 300a has a first capacitance electrode 31 It has 0a and a capacitance layer 410 in contact with the first gate electrode 120, and the first gate electrode is It functions as one electrode of the capacitor. The first gate electrode of the first transistor 100. 120 is used as one of the capacitance electrodes of capacitor 300a, therefore capacitor 300 The occupied area of ​​a can be reduced. As a result, the occupied area of ​​the semiconductor memory can be reduced. It is possible.

[0048] (1st capacitor electrode) For the first capacitance electrode 310a, for example, low-resistance polysilicon or molybdenum Titanium, tantalum, copper, tungsten, aluminum, chromium, neodymium, Scandinavian It can be formed using metallic materials such as um, or alloy materials that mainly consist of these materials. The first capacitance electrode 310a is electrically connected to the first word line 105.

[0049] (capacitance layer) An insulating material can be used as the capacitance layer 410. For example, silicon oxide, silicon oxynitride Inorganic materials such as silicon nitride can be used. Also, the first gate electrode 120 When using low-resistance polysilicon, an oxide film is formed on its surface by thermal oxidation, etc. It can also be used as layer 410.

[0050] Capacitor 300a controls the first gate electrode 120 of the first transistor 100. It is used as one of the electrodes. Therefore, the occupied area of ​​capacitor 300a is reduced. It is possible.

[0051] ((Second transistor)) Next, we will explain the second transistor 200. The second transistor 200 is the first gate The second half is positioned so as to overlap the first electrode 120 and is electrically connected to the first gate electrode 120. Conductor layer 201, second gate insulating layer 210 in contact with the side surface of second semiconductor layer 201, and second gate It is shaped to be in contact with the insulating layer 210 and to cover at least a portion of the side surface of the second semiconductor layer 201. It has a second gate electrode 220 and a bit line 500, and the second semiconductor layer 2 It is electrically connected to 01.

[0052] (Second semiconductor layer) The shape of the second semiconductor layer 201 will now be described. The side surface of the second semiconductor layer 201 is the second gate insulating The second gate electrode 220 is covered via the marginal layer 210. Therefore, the second transistor In the 200, the second gate electrode 220, which covers the side surface of the second semiconductor layer 201, functions as the gate. Furthermore, the first gate electrode 120, which is in contact with the bottom surface of the second semiconductor layer 201, is the source electrode, and on the top surface This is a vertical transistor in which the contacting bit line 500 functions as the drain electrode. Therefore, the area occupied by the second transistor 200 can be reduced.

[0053] Furthermore, the second transistor 200 is a transistor with an extremely small off-current. This allows for the creation of a semiconductor memory device that can retain its contents even when power is not supplied. Furthermore, it becomes possible to retain data in capacitor 300a for a long period of time. Therefore, in semiconductor memory devices, periodic data rewriting operations (hereinafter referred to as refresh) (Also called an operation.) This eliminates the need for this operation, or makes the frequency of refresh operations extremely low. This makes it possible to effectively function as a non-volatile semiconductor memory device.

[0054] Furthermore, since the second transistor 200 is a transistor with an extremely small off-current, the charge The size of the capacitor 300a that holds the capacitor can be reduced. Reducing the size of 0a shortens the time required for writing and reading, enabling high-speed operation. It can be used as a semiconductor memory device.

[0055] The channel length of the second transistor 200 also depends on the thickness of the second gate insulating layer 210, for example. For example, 10 times or more, preferably 20 times, the diagonal length or diameter of the second semiconductor layer 201 This approach is preferable because it suppresses short-channel effects.

[0056] Furthermore, although the second semiconductor layer 201 is shown as cylindrical in Figure 1(B), it can also be a rectangular prism shape. This may also be done. For example, if the second semiconductor layer 201 is prismatic in shape, it may be formed near its side surface. Because the effective width of the channel can be increased, the on current of the second transistor 200 can be increased. It is possible to do so. Also, if it is cylindrical in shape, there are no protruding parts on its sides, and on its sides Because the gate electric field is applied uniformly, a highly reliable second transistor 200 can be created. Yes, it is possible. For example, if you want to increase the on-current even further, you can change the shape of the bottom surface of the second semiconductor layer 201. A polygon with a shape like a star polygon, where at least one interior angle exceeds 180° (concave) It may also be a polygon.

[0057] As the second semiconductor layer 201, a semiconductor having a wider band gap than silicon is used. This is preferable. Specifically, in order to obtain a very high off-resistance, silicon (bandgear) A band gap of 1.1 electron volts is insufficient; a band gap of 2.5 electron volts or more is required. Wide bandgap half-volts of 0.5 or less, preferably 3 to 3.8 electron volts. It is necessary to use a conductor. For example, oxide semiconductors such as indium oxide and zinc oxide. For this purpose, nitride semiconductors such as gallium nitride, sulfide semiconductors such as zinc sulfide, etc., can be used. When such a semiconductor is used in the region where the channel is formed, the off-current of that transistor is extremely low. It can be made smaller.

[0058] Furthermore, oxide semiconductors are quaternary metal oxides, specifically In-Sn-Ga-Zn oxide semiconductors. In-Ga-Zn oxide semiconductors and In-Sn-Zn oxide semiconductors are ternary metal oxides. Monocrystalline semiconductors, In-Al-Zn oxide semiconductors, Sn-Ga-Zn oxide semiconductors, Al- Ga-Zn oxide semiconductors, Sn-Al-Zn oxide semiconductors, and binary metal oxides In-Zn oxide semiconductors, Sn-Zn oxide semiconductors, Al-Zn oxide semiconductors, Zn-Mg oxide semiconductors, Sn-Mg oxide semiconductors, In-Mg oxide semiconductors, I n-Ga-based oxide semiconductors, as well as indium oxide, tin oxide, zinc oxide, etc., can be used. In this specification, for example, In-Sn-Ga-Zn oxide semiconductors are defined as follows: Metal oxides containing indium (In), tin (Sn), gallium (Ga), and zinc (Zn) This means that the stoichiometric composition is not particularly important.

[0059] The oxide semiconductor film may, for example, have a non-single crystal structure. The non-single crystal is, for example, CAAC( (C Axis Aligned Crystal), polycrystalline, microcrystalline, having amorphous parts The amorphous region has a higher defect level density than the microcrystalline and CAAC regions. Also, the microcrystalline region is CAAC. It has a higher defect level density than [another material]. Note that an oxide semiconductor containing CAAC is called CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor This is referred to as uctor, and further details can be found in Embodiment 6.

[0060] The oxide semiconductor film may have, for example, CAAC-OS. CAAC-OS is, for example, The c-axis is oriented, and the a-axis and / or the b-axis are not aligned macroscopically.

[0061] The oxide semiconductor film may, for example, have microcrystals. These are called microcrystalline oxide semiconductors. Microcrystalline oxide semiconductor films are, for example, 1 nm to 10 nm in thickness. The film contains microcrystals (also called nanocrystals) of full size.

[0062] The oxide semiconductor film may have, for example, an amorphous region. This material is called an amorphous oxide semiconductor. An amorphous oxide semiconductor film, for example, has a disordered atomic arrangement. It does not have crystalline components. Alternatively, an amorphous oxide semiconductor film is, for example, completely amorphous. It does not have a crystalline portion.

[0063] Furthermore, the oxide semiconductor film is CAAC-OS, microcrystalline oxide semiconductor, amorphous oxide semiconductor. A mixed film may also be used. The mixed film may consist of, for example, regions of amorphous oxide semiconductor and microcrystalline oxide. It has a semiconductor region and a CAAC-OS region. Furthermore, the mixed film is, for example, amorphous. Layers of oxide semiconductor regions, microcrystalline oxide semiconductor regions, and CAAC-OS regions. It may have a structure.

[0064] The oxide semiconductor film may, for example, have a single crystal structure.

[0065] The oxide semiconductor film has multiple crystalline regions, and the c-axis of the crystalline region is aligned with the normal vector of the surface on which it is formed. Alternatively, it is preferable that they are aligned in a direction parallel to the surface normal vector. The orientations of the a-axis and b-axis may be different in between. Such an oxide semiconductor film One example of this is the CAAC-OS membrane.

[0066] (Second gate insulating layer) An insulating material can be used for the second gate insulating layer 210. For example, an insulating material can be used. Silicon oxynitride, hafnium oxide, yttrium oxide, hafnium silicate, Hafnium aluminate, nitrogen-added hafnium silicate, nitrogen-added ha Phnium aluminate, lanthanum oxide, etc., can be used. Acids that satisfy stoichiometric ratios. Silicon oxide containing more oxygen than silicon is preferable.

[0067] The second gate insulating layer 210 can be formed using CVD or sputtering methods, etc. Yes, it is possible. As the second gate insulating layer 210, a silicon oxide film or a silicon oxynitride film can be used. When forming using the D method, the generation of glow discharge plasma is typically between 3 MHz and 30 MHz. High-frequency power in the HF bands of 13.56MHz and 27.12MHz, or greater than 30MHz High-frequency power in the VHF band up to approximately 300MHz, typically 60MHz, is applied. It is preferable to do so. Also, apply high-frequency microwave power of 1 GHz or higher. It can also be done in this way. Furthermore, pulse oscillation, where high-frequency power is applied in a pulsed manner, or continuously The applied continuous oscillation can be used. Acid formed using microwaves of 1 GHz or higher The silicon oxide film or silicon oxynitride film provides fixation within the film and at the interface with the second semiconductor layer 201. The charge is greater than that of silicon oxide or silicon oxynitride films deposited by conventional plasma CVD methods. The number is small. Therefore, the reliability of electrical characteristics such as threshold voltage in the second transistor 200 is It can be made higher.

[0068] Furthermore, the thickness of the second gate insulating layer 210 corresponds to the channel length of the second transistor 200. Then, you just need to set the appropriate film thickness.

[0069] (Second gate electrode) The material of the second gate electrode 220 has electrical conductivity and adhesion to the second gate insulating layer 210, All that's needed is low-resistance polysilicon, or, for example, molybdenum, titanium, tan. Metal materials such as tul, copper, tungsten, aluminum, chromium, neodymium, and scandium , or can be formed using alloy materials that mainly consist of these. Also, the second g The gate electrode 220 may have a single-layer structure or a multi-layer structure. Pole 220 is electrically connected to the second word line 106.

[0070] (Second interlayer membrane) The second interlayer film 250 can be an insulator. For example, silicon oxide, silicon oxynitride Inorganic materials such as carbon dioxide, silicon nitride, and aluminum oxide can be used. Organic resins such as acrylic resin and polyimide resin can be used.

[0071] (Insulating film) The insulating film 251 can be an insulator. For example, silicon oxide, silicon oxynitride. Inorganic materials such as silicon nitride and aluminum oxide can be used. Bit wire 500 and The second gate electrode 220 should be electrically insulated.

[0072] In Figure 1, the second gate electrode 220 is connected to the second semiconductor layer 2 via the second gate insulating layer 210. The configuration is designed to cover the sides of 01, but it is sufficient if it covers at least a portion of the sides. For example, on only one side of the second semiconductor layer 201 along the second gate electrode 220, By providing the bit electrode 220, the integration density in the bit line 500 direction can be increased. On the other hand, if the configuration is such that the side surface of the second semiconductor layer 201 is covered as shown in Figure 1, the second transient Because the effective channel width of the STA200 can be increased, the on-current can be increased.

[0073] (Bit line) It is preferable to use a material with low electrical resistance for the bit wire 500. For example, aluminum Single-layer films of aluminum, titanium, tungsten, and copper, or multilayer films of titanium and aluminum, etc. It is preferable to use it.

[0074] Next, we will explain how to write and read data from the semiconductor memory device.

[0075] <Write data> When writing data, the second transistor 200 is turned ON. When it is turned ON, One electrode of capacitor 300a, i.e., the first gate electrode 1 of the first transistor 100 A potential difference is generated between 20 and the other electrode, the capacitive layer 410. According to that potential difference... Then, charge is retained in capacitor 300a. After that, the first transistor 100 is turned off. By doing so, the written data can be retained.

[0076] <Data Retrieval> By determining whether the first transistor 100 is in the ON state or the OFF state, the data can be read. Perform the discharge. If a high level potential is maintained in capacitor 300a, the first transient Since transistor 100 is in the ON state, the bit line 500 is transmitted through the first transistor 100. The high-level potential applied to the bit line is output. The change in the potential of that bit line 500 is, By detecting this with a readout circuit such as a sense amplifier connected to the bit line 500, It is possible to read the data.

[0077] As described above, the semiconductor memory device 1 illustrated in this embodiment is the first transistor 100 1. The gate electrode 120 is used as one electrode of the capacitor 300a. This allows for a reduction in the area occupied by the capacitor 300a. Furthermore, relative to the surface area of ​​the substrate, The second transistor 200, which occupies an extremely small area, is placed on top of the first transistor 100. This allows for a reduction in the footprint of the semiconductor memory device.

[0078] Furthermore, the second transistor 200, which uses an oxide semiconductor in the second semiconductor layer, has an extremely low off-current. It is a very small transistor. Therefore, it can retain its memory contents even when power is not supplied. This makes it possible to create a semiconductor memory device that can perform floating-point operation. Like a finite gate (FG) type non-volatile memory, during data writing and erasing, Because the rear does not damage the gate insulation layer, it does not degrade even after repeated writing and erasing. In other words, the semiconductor memory device has higher data retention reliability than FG-type non-volatile memory. This can increase the number of write cycles (for example, more than 1 million). This makes it possible to use semiconductor memory devices.

[0079] (Embodiment 2) In this embodiment, an example of the configuration of a semiconductor memory device, which is one aspect of the present invention, is shown using Figure 2. I will explain.

[0080] Figure 2(B) is a schematic top view of the semiconductor memory device 2, and Figure 2(A) is a part of Figure 2(B). This is a schematic cross-sectional view along the dashed line A2-B2. Figure 2(C) is the circuit diagram of the semiconductor memory device 2. That is the case.

[0081] The semiconductor memory device 2 illustrated in this embodiment has a plurality of parallel bit lines 500 and bit It has multiple first word lines 105 and second word lines 106 that are perpendicular to the bit line 500, and bit line 500, in the overlapping region of the first word line 105 and the second word line 106, the first transit The transistor 100, the second transistor 200, and the capacitor 300b are formed. Cell 20 consists of the first transistor 100, the second transistor 200, and the capacitor 30. Includes 0b. Note that the first word line 105 is the first capacitive electrode 310b and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0082] ((First transistor)) The first transistor 100 will be described. The first transistor 100 is located in the first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and the first gate insulating layer The first gate electrode 120 is in contact with 110 and overlaps with the first semiconductor layer 101, and the first gate electrode The sidewall layer 140 in contact with 120 and the first gate electrode 120 of the first semiconductor layer 101 A source region and a drain region 130 are provided so as to sandwich the overlapping region, and the first interlayer membrane It has 150. The first gate electrode 120 is the second semiconductor layer 20 of the second transistor 200. It is electrically connected to 1. Also, the first gate electrode 120 is connected to one side of capacitor 300b. It functions as an electrode.

[0083] The first gate electrode 120 is electrically connected to the second capacitive electrode 320 of the capacitor 300b, which will be described later. Connecting.

[0084] Either the source region or the drain region 130 consists of a conductive layer 600a and a first capacitive electrode 310b At the same time, through the buffer layer 310d and conductive layer 600b that are formed, the bit line 500 and electrical It is connected to the source region or drain region 130 of the adjacent element. The drain region or other similar region is electrically isolated by the insulating layer 700.

[0085] First semiconductor layer 101, first gate insulating layer 110, first gate electrode 120, source region and Details of the drain region 130, the first interlayer film 150, and the insulating layer 700 are as follows in each embodiment. Reference to 1 can be taken into consideration. Furthermore, details of conductive layers 600a and 600b can be found in the conductive layer 60 of Embodiment 1. The entry for 0 can be taken into consideration.

[0086] (Sidewall layer) The sidewall layer 140 can be formed from silicon oxide, silicon nitride, etc. The idwall layer 140 forms a channel with the source region or drain region 130. The region where the channel is formed and the drain region (or A low-concentration drain (LDD: Lightly D) has an LDD region between it and the source region. It is preferable to have an oped drain structure.

[0087] ((capacitor)) Next, we will explain capacitor 300b. Capacitor 300b is the first gate electrode 1 A second capacitive electrode 320 electrically connects 20 and the second semiconductor layer 201, and the second capacitive electrode 3 It has a capacitance layer 410 in contact with 20 and a first capacitance electrode 310b in contact with the capacitance layer 410, The second capacitance electrode 320 functions as one of the electrodes of the capacitor.

[0088] Details of the first capacitive electrode 310b can be found in the description of the first capacitive electrode 310a in Embodiment 1. Furthermore, details of the capacitance layer 410 can be found in the first embodiment.

[0089] (Second capacitor electrode) The second capacitance electrode 320 can be, for example, low-resistance polysilicon or molybdenum. Titanium, tantalum, copper, tungsten, aluminum, chromium, neodymium, scandium It can be formed using metallic materials such as lum, or alloy materials that mainly consist of these materials. By providing the second capacitive electrode 320, the first gate electrode 120 and the second semiconductor layer 201 Electrical connections can be made easier.

[0090] The width of the second capacitance electrode 320 (width in the channel formation direction of the first transistor 100), and the second capacitance Regarding the relationship between the film thickness of the capacitance electrode 320, it is preferable that the film thickness ratio is high. If the film thickness is increased, the second capacitance electrode 320 can be used as one of the electrodes of the capacitor. This is because it allows for a reduction in the area occupied by the capacitor.

[0091] Capacitor 300b uses the second capacitive electrode 320 and the first capacitive electrode 310b as capacitive electrodes. Therefore, the footprint of capacitor 300b can be reduced.

[0092] ((Second transistor)) Next, we will explain the second transistor 200. The second transistor 200 is the second semiconductor It has a body layer 201, a second gate insulating layer 210, and a second gate electrode 220. Ta200 is positioned to overlap the first gate electrode 120. Also, the second semiconductor layer 201 is electrically connected to the first gate electrode 120. Also, the second gate insulating layer 21 0 is in contact with the side surface of the second semiconductor layer 201. Also, the second gate electrode 220 is in contact with the second gate It is shaped to be in contact with the insulating layer 210 and to cover at least a portion of the side surface of the second semiconductor layer 201. This has been done. Furthermore, bit line 500 is electrically connected to the second semiconductor layer 201.

[0093] Details of the second transistor can be found in Embodiment 1. Also, the second semiconductor layer 201, 2 gate insulating layer 210, second gate electrode 220, second interlayer film 250, insulating film 251, and Details of bit line 500 can also be found in Embodiment 1. Furthermore, semiconductor memory The first embodiment can also be used to describe the writing and reading of data.

[0094] As described above, in the semiconductor memory device 2 illustrated in this embodiment, the second capacitance electrode 320 is the It functions as the source or drain electrode of the 2 transistor 200. Therefore, the second In transistor 200, the source electrode and the drain electrode are the base that forms the transistor. It is positioned perpendicular to the board. Therefore, the second transistor 200 is, for example, a planar type transistor. Compared to DISTRA, it can occupy a smaller area. Therefore, it can be used in semiconductor memory with a high degree of integration. We can provide a memory device.

[0095] Furthermore, the second transistor 200, which occupies an extremely small area relative to the surface area of ​​the substrate, is connected to the first transistor. It is placed on top of the Rangista 100. This reduces the footprint of the semiconductor memory device. It can be cut.

[0096] Furthermore, by providing the second capacitive electrode 320, the first gate electrode 120 and the second semiconductor layer 2 This makes the electrical connection of 01 easier.

[0097] Furthermore, the second transistor 200, which uses an oxide semiconductor in the second semiconductor layer 201, has an off-current It is an extremely small transistor. Therefore, even when power is not supplied, the stored contents can be stored. It becomes possible to create a semiconductor memory device that can retain data. Furthermore, this semiconductor memory device is F Like G-type non-volatile memory, during data writing and erasing, the carriers are separated by the gate insulating layer. Because it does not damage the data, it does not degrade even after repeated writing and erasing. In other words, Semiconductor memory devices can offer higher data retention reliability than FG-type non-volatile memory. Therefore, a semiconductor memory device with a large number of writable cycles (for example, more than 1 million) is used. This becomes possible.

[0098] (Embodiment 3) In this embodiment, an example of the configuration of a semiconductor memory device, which is one aspect of the present invention, is shown using Figure 3. I will explain.

[0099] Figure 3(B) is a schematic top view of the semiconductor memory device 3, and Figure 3(A) is a part of Figure 3(B). This is a schematic cross-sectional view along the dashed line A3-B3. Figure 3(C) is the circuit diagram of the semiconductor memory device 3. That is the case.

[0100] The semiconductor memory device 3 illustrated in this embodiment has a plurality of parallel bit lines 500 and bit It has multiple first word lines 105 and second word lines 106 that are perpendicular to the bit line 500, and bit line 500, in the overlapping region of the first word line 105 and the second word line 106, the first transit A transistor 100, a second transistor 200, and a capacitor 300c are formed. Cell 30 consists of the first transistor 100, the second transistor 200, and the capacitor 30. Includes 0c. Note that the first word line 105 is the first capacitive electrode 310c and the second word line 10 6 is electrically connected to the second gate electrode 220.

[0101] ((First transistor)) The first transistor 100 will be described. The first transistor 100 is located in the first semiconductor layer 1 01, a first gate insulating layer 110 in contact with the first semiconductor layer 101, and the first gate insulating layer The first gate electrode 120 is in contact with 110 and overlaps with the first semiconductor layer 101, and the first gate electrode The sidewall layer 140 in contact with 120 and the first gate electrode 120 of the first semiconductor layer 101 A source region and a drain region 130 are provided so as to sandwich the overlapping region, and the first interlayer membrane It has 150. The first gate electrode 120 is the second semiconductor layer 20 of the second transistor 200. It is electrically connected to 1. Also, the first gate electrode 120 is connected to one side of the capacitor 300c. It functions as an electrode.

[0102] The first gate electrode 120 is electrically connected to the second capacitive electrode 320 of the capacitor 300c, which will be described later. Connecting.

[0103] Either the source region or the drain region 130 is connected via conductive layer 600a and conductive layer 600b It is electrically connected to bit line 500. Also, source area or drain area 13 0 is electrically isolated from the source or drain region of an adjacent element by the insulating layer 700. It is being done.

[0104] First semiconductor layer 101, first gate insulating layer 110, first gate electrode 120, source region and The details of the drain region 130, sidewall layer 140, first interlayer film 150, and insulating layer 700 are as follows: Details can be found in each embodiment 1. Furthermore, details of the conductive layers 600a and 600b can be found in the following: The description of the conductive layer 600 in Embodiment 1 can be given further consideration.

[0105] ((capacitor)) Next, we will explain capacitor 300c. Capacitor 300c is the first gate electrode 1 A second capacitive electrode 320 electrically connects 20 and the second semiconductor layer 201, and the second capacitive electrode 3 It has a capacitance layer 410 in contact with 20 and a first capacitance electrode 310c in contact with the capacitance layer 410, The second capacitance electrode 320 functions as one of the electrodes of the capacitor.

[0106] Details of the first capacitive electrode 310c can be found in the description of the first capacitive electrode 310a in Embodiment 1. Furthermore, details of the capacitance layer 410 can be found in the first embodiment.

[0107] Details of the second capacitance electrode 320 can be found in Embodiment 2. The width (the width of the channel formation direction of the first transistor 100) is determined by the capacitance of the capacitor. It is fine to set it, but extend it to the edge of the sidewall layer 140 of the first transistor 100. This is possible. The width of the second capacitance electrode 320 (the width of the first transistor 100 in the channel formation direction) By widening this, the margin for alignment between the second capacitance electrode 320 and the second semiconductor layer 201 is increased. It can be done.

[0108] Capacitor 300c uses the second capacitive electrode 320 and the first capacitive electrode 310c as capacitive electrodes. Therefore, the footprint of the 300c capacitor can be reduced.

[0109] ((Second transistor)) Next, we will explain the second transistor 200. The second transistor 200 is the second semiconductor It has a body layer 201, a second gate insulating layer 210, and a second gate electrode 220. Ta200 is positioned to overlap the first gate electrode 120. Also, the second semiconductor layer 201 is electrically connected to the first gate electrode 120. Also, the second gate insulating layer 21 0 is in contact with the side surface of the second semiconductor layer 201. Also, the second gate electrode 220 is in contact with the second gate It is shaped to be in contact with the insulating layer 210 and to cover at least a portion of the side surface of the second semiconductor layer 201. This has been done. Furthermore, bit line 500 is electrically connected to the second semiconductor layer 201.

[0110] Details of the second transistor can be found in Embodiment 1. Also, the second semiconductor layer 201, 2 gate insulating layer 210, second gate electrode 220, second interlayer film 250, insulating film 251, and Details of bit line 500 can also be found in Embodiment 1. Furthermore, semiconductor memory The first embodiment can also be used to describe the writing and reading of data.

[0111] As described above, the semiconductor memory device 3 illustrated in this embodiment has a second capacitance electrode 320, and It functions as the source or drain electrode of transistor 200. Therefore, the second In transistor 200, the source electrode and drain electrode are located on the substrate that forms the transistor. It is arranged perpendicularly to the . Therefore, the second transistor 200 is, for example, a planar type transistor Compared to a standard, it can occupy a smaller area. Therefore, it is a semiconductor memory with a high degree of integration. We can provide the device.

[0112] Furthermore, the second transistor 200, which occupies an extremely small area relative to the surface area of ​​the substrate, is connected to the first transistor. It is placed on top of the Rangista 100. This reduces the footprint of the semiconductor memory device. It can be cut.

[0113] Furthermore, by providing the second capacitive electrode 320, the first gate electrode 120 and the second semiconductor layer 2 This makes the electrical connection of 01 easier.

[0114] Furthermore, the second transistor 200, which uses an oxide semiconductor in the second semiconductor layer 201, has an off-current It is an extremely small transistor. Therefore, even when power is not supplied, the stored contents can be stored. It becomes possible to create a semiconductor memory device that can retain data. Furthermore, this semiconductor memory device is F Like G-type non-volatile memory, during data writing and erasing, the carriers are separated by the gate insulating layer. Because it does not damage the data, it does not degrade even after repeated writing and erasing. In other words, Semiconductor memory devices can offer higher data retention reliability than FG-type non-volatile memory. Therefore, a semiconductor memory device with a large number of writable cycles (for example, more than 1 million) is used. This becomes possible.

[0115] (Embodiment 4) This embodiment describes a method for manufacturing a semiconductor memory device according to one aspect of the present invention.

[0116] The manufacturing process of the semiconductor memory device 1 shown in Figure 1 will be explained below with reference to Figures 4 to 7. The cross-sectional view of the area corresponds to the cross-section along the dashed line A1-B1 in the top view of the semiconductor memory device 1. This shows the state of the area after each process has been carried out. The top view showing the later state is omitted. In this embodiment, single-crystal silicon is used for the substrate. Let's explain the case where this is the case. Note that the materials that can be used for the constituent elements shown below are actually Forms 1 to 3 of the implementation can be considered.

[0117] Figure 4 shows the semiconductor process from the formation of the insulating layer 700 to the formation of the capacitive layer 410. This shows a cross-section of memory device 1.

[0118] The insulating layer 700 forms an electrically isolated region on the single-crystal semiconductor substrate. The goal is to isolate transistor 100 (Figure 4(A)).

[0119] Next, a first gate insulating layer 110 is formed. For example, it may be formed of a thermal oxide film (Fig. 4( B)).

[0120] Next, a first gate electrode 120 is formed. The first gate electrode 120 may be formed using low-resistance polysilicon or a metal such as tungsten (Fig. 4(B)).

[0121] Next, the first gate electrode 120 is processed to a desired gate length by photolithography (Fig. 4(C)).

[0122] Next, impurities are doped into the regions where the source and drain are to be formed to form the source region and the drain region 130. Impurities capable of forming a transistor of a desired conductivity type may be implanted into the silicon in the region where the source or drain is to be formed. The implantation method may be, for example, an ion implantation method or the like (Fig. 4(D)).

[0123] Next, a capacitor layer 410 is formed. The capacitor layer 410 functions as an insulating layer of the capacitor (Fig. 4(E)).

[0124] Fig. 5 shows a cross section of the semiconductor memory device 1 from the step of forming the first interlayer dielectric 150 to the step of forming the second gate insulating layer 210.

[0125] Next, a first interlayer dielectric 150 is formed. As the material of the first interlayer dielectric 150, an insulator can be used. For example, silicon oxide, silicon oxynitride, silicon nitride, etc. may be formed by CVD method. Or aluminum oxide or the like may be formed by sputtering method.

[0126] Next, using a photolithography process and an etching process, a first capacitor electrode 310a is ​​​​​​​​​The area to be formed is processed. To form a fine pattern, the etching process is performed dry An etching method is preferred (Figure 5(A)).

[0127] As the first capacitive electrode 310a, a semiconductor or metal with low electrical resistance can be used. For example, low-resistance polysilicon can be formed by the CVD method. Alternatively, molybdenum, cyanoacrylate Tan, tantalum, copper, tungsten, aluminum, chromium, neodymium, scandium, etc. Metal materials, or alloy materials mainly composed of these materials, are formed using the sputtering method. It is also possible to do so.

[0128] Next, the first capacitive electrode 310a is polished until the surface of the first gate electrode 120 is exposed. Polishing can be performed, for example, using the CMP method. This polishing will improve the first gate electrode 120. Since the surface is exposed, the second semiconductor layer 201 and the first gate electrode 120 to be formed in the next step are Electrical connection becomes possible (Figure 5(B)).

[0129] Next, a second semiconductor layer 201 is formed on the surface of the exposed first gate electrode 120. It is preferable to use an oxide semiconductor for the conductive layer 201. The oxide semiconductor film is, for example, spa It can be formed by the taring method (Figure 5(C)).

[0130] In this embodiment, the second semiconductor layer 201 and the first gate electrode 120 are formed to overlap. However, the second semiconductor layer 201 only needs to be electrically connected to the first gate electrode 120. The width of the second semiconductor layer 201 does not need to be the same as that of the first gate electrode 120.

[0131] Next, a second gate insulating layer 210 is formed to cover the second semiconductor layer 201 (Figure 5(D ))

[0132] Figure 6 shows the process from the formation of the region for forming the second gate electrode 220 to the formation of the second gate electrode 220. This shows a cross-section of the semiconductor memory device 1 after the formation process has been completed.

[0133] Next, the second interlayer film 250 is formed, and the region where the second gate electrode 220 is to be formed is photolithographed. It is formed by a roughing process and an etching process. The etching process creates a fine pattern. For formation, a dry etching method is preferred (Figure 6(A)).

[0134] A conductive layer 601 is deposited so as to be embedded in the pattern formed above (Figure 6(B)). The material for the conductive layer 601 only needs to have electrical conductivity and good adhesion to the second gate insulating layer 210. Low-resistance polysilicon, or, for example, molybdenum, titanium, tantalum, copper, tan Metal materials such as gusten, aluminum, chromium, neodymium, scandium, or these It can be formed using an alloy material that has as its main component. In addition, the conductive layer 601 is a single layer structure It may be constructed as a single unit or as a laminated structure.

[0135] Next, the conductive layer 601 is polished until at least the surface of the second gate insulating layer 210 is exposed. This forms the second gate electrode 220 (Figure 6(C)). Polishing is performed using, for example, the CMP method. It is sufficient if this polishing is performed until the surface of the second semiconductor layer 201 is exposed. Damage to the second semiconductor layer 201 causes deterioration of the electrical characteristics of the second transistor. Therefore, it is preferable to polish the conductive layer 601 so that the second gate insulating layer 210 remains. It seems so.

[0136] The steps from exposing the second semiconductor layer 201 to forming the bit line 500 are carried out as shown in Fig. 7. A cross-section of the semiconductor memory device 1 is shown.

[0137] The second gate insulating layer 210 is removed by a dry etching method to expose the second semiconductor layer 201 (Fig. 7(A)). Expose it (Fig. 7(A)).

[0138] Next, an insulating film 251 is formed. Next, a through-hole for electrically connecting the source region or the drain region 130 of the first transistor 100 and the bit line 500 is formed, and the hole is filled with a conductive layer 600. For example, it may be filled with aluminum, tungsten, copper, polysilicon, etc. to fill the hole. Expose it (Fig. 7(A)).

[0139] Next, the bit line 500 is formed (Fig. 7(B)).

[0140] Through the above steps, the semiconductor memory device 1 can be manufactured.

[0141] In the semiconductor memory device, the first gate electrode functions as the source electrode or the drain electrode of the second transistor, and the second semiconductor layer is formed so as to overlap the first gate electrode. Therefore, the source electrode and the drain electrode of the second transistor are arranged sandwiching the second semiconductor layer perpendicularly to the substrate on which the transistor is formed. Thus, the second transistor can have a smaller occupied area compared to, for example, a planar-type transistor. Therefore, a semiconductor memory device with a high integration degree can be provided. For example, compared with a planar transistor, the occupied area can be reduced. Therefore, a semiconductor memory device with a high integration degree can be provided.

[0142] In addition, since the first gate electrode of the first transistor is used as one capacitive electrode of the capacitor, the occupied area of the capacitor can be reduced. As a result, a semiconductor memory device with a high integration degree can be obtained. It can provide a body memory device.

[0143] (Embodiment 5) This embodiment describes a method for manufacturing a semiconductor memory device according to one aspect of the present invention.

[0144] The manufacturing process of the semiconductor memory device 2 shown in Figure 2 will be explained below using Figures 8 to 11. The cross-sectional view of the process corresponds to the cross-section along the dashed line A2-B2 in the top view of the semiconductor memory device 2. This shows the state of the area after each step has been completed. The top view showing the state after the procedure is omitted. In this embodiment, single-crystal silicon is used on the substrate. The following explains how to use it. The materials that can be used for the constituent elements shown below are: Embodiments 1 to 4 can be considered.

[0145] Figure 8 shows the process of forming the first gate electrode 120, and impurities in the source region and drain region. During the process of doping and forming the conductive layer 600b, the semiconductor memory device 2 was subjected to the following steps. A cross-section is shown.

[0146] Up to the step of forming the first gate electrode 120 (Figure 8(A)), refer to Embodiment 4. can.

[0147] After forming the first gate electrode 120, the channel region is formed in the region where the sidewall layer 140 is formed. The electrical resistance is lower than that of the source region and higher than that of the source and drain regions. The transistor 100 is doped with impurities. The type of impurity to be doped is the desired type of impurity for the first transistor 100. The choice should be based on the type of conduction (Figure 8(B)).

[0148] Next, the sidewall layer 140 is formed. The method for forming the sidewall layer 140 is as follows: For example, a silicon oxide film and a silicon nitride film are formed to cover the first gate electrode 120. Then, the surface can be formed by anisotropic etching, also known as etch-back (Figure 8). (C)

[0149] Next, impurities are doped into the region that forms the source or drain, and the source region Alternatively, a drain region 130 is formed. Then, an impurity capable of forming a transistor of the desired conductivity type can be injected. The injection method is, for example, This can be done using methods such as ion implantation (Figure 8(D)).

[0150] Next, the first interlayer membrane 150 is formed (Figure 8(E)).

[0151] Next, the source region or drain region 130 of the first transistor 100 and the shape in a later process A conductive hole is formed to electrically connect to the bit wire 500, and the hole is covered with a conductive layer 6 Fill with 00b. For example, using aluminum, tungsten, copper, polysilicon, etc. Then, simply fill the hole (Figure 8(E)).

[0152] Figure 9 shows the process from the formation of the second capacitance electrode 320 to the formation of the insulating layer 152.

[0153] The second capacitive electrode 320 is formed to be electrically connected to the first gate electrode 120. The conductive layer 321 is formed to be electrically connected to the conductive layer 600b. The conductive layer 321 is It is preferable to form it from the same material as the second capacitance electrode 320.

[0154] Next, the capacitance layer 410 is formed so as to be in contact with the second capacitance electrode 320 (Figure 9(A)).

[0155] Next, the first capacitance electrode 310b is formed so as to be in contact with the capacitance layer 410. Capacitor 300 Based on the required capacity at b, the width and film thickness of the first capacitance electrode 310b should be determined (Figure 9(B)).

[0156] Next, insulating layer 151 and insulating layer 152 are formed. Insulating layer 151 and insulating layer 152 are insulating material That would be fine. For example, silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide Materials such as M can be used. At this stage of the process, insulating layer 151 or insulating layer 152 It is preferable to flatten the surface (Figure 9(C)).

[0157] Figure 10 shows the process from the formation of the second interlayer film 250 to the formation of the second gate insulating layer 210. A cross-sectional view is shown below.

[0158] First, a second interlayer film 250 is formed, and an opening is created in the region where the second gate electrode 220 will be formed. (Figure 10(A)). It is preferable to form the opening by dry etching.

[0159] Next, the second gate electrode 220 is formed (Figure 10(B)).

[0160] Next, an opening is formed in the region where the second semiconductor layer 201 is to be formed. This creates the second capacitive electrode 3 The surface of transistor 20 is exposed. The sidewall of the opening becomes the gate insulating layer of the second transistor 200. Therefore, after forming the opening, the second gate insulating layer 210 is formed on the side surface of the opening. This is preferable (Figure 10(C)). The second gate insulating layer 210 is made by CVD or sputtering. It can be formed using methods such as the shaping method.

[0161] Figure 11 shows the cross-section after the process from the formation of the second semiconductor layer 201 to the formation of the bit line 500. A view drawing is shown.

[0162] The second semiconductor layer 201 is formed to be electrically connected to the second capacitive electrode 320. It is preferable to use an oxide semiconductor for the second semiconductor layer 201. The oxide semiconductor film is, for example It can be formed by sputtering (Figure 11(A)).

[0163] Next, after forming the insulating film 251, the region overlapping with the second semiconductor layer 201 is removed by etching. Remove the insulating film 251, the second interlayer film 250, the insulating layer 151 and the insulating layer 152. It is preferable to form an opening in the region that overlaps with the conductive layer 321 (Figure 11(B)).

[0164] Next, a conductive layer 600a is formed to electrically connect with the conductive layer 321. The wire 500 is formed to electrically connect with the second semiconductor layer 201.

[0165] By following the above steps, the semiconductor memory device 2 can be manufactured.

[0166] In this semiconductor memory device, the first gate electrode is the source electrode or drain electrode of the second transistor. The second semiconductor layer functions as an electrode, and is formed to overlap with its first gate electrode. Therefore, the source and drain electrodes of the second transistor form the transistor. The second semiconductor layer is positioned perpendicular to the substrate, sandwiching it between the two semiconductor layers. Therefore, the second transistor is, for example For example, it can occupy a smaller area compared to a planar transistor. Therefore This enables the provision of highly integrated semiconductor memory devices.

[0167] Furthermore, capacitor 300b has a second capacitance electrode 320 and a first capacitance electrode 310b as capacitance electrodes. Because it is used in this way, the occupied area of ​​capacitor 300b can be reduced. As a result, it is possible to provide semiconductor memory devices with a high degree of integration.

[0168] (Embodiment 6) In this embodiment, it can be used in the oxide semiconductor films exemplified in Embodiments 1 to 5. Next, we will explain the CAAC-OS membrane.

[0169] The crystalline portion contained within the CAAC-OS film is small enough to fit within a cube with sides less than 100 nm in size. This is often the case. Also, transmission electron microscope (TEM) Observation images using an ectron microscope show that the CAAC-OS film contains The boundaries between crystalline regions are not clear. Furthermore, TEM revealed that the CAAC-OS film is not clear. Definite grain boundaries (also called grain boundaries) cannot be confirmed. Therefore, CAAC-O The S film suppresses the decrease in electron mobility caused by grain boundaries.

[0170] The crystalline portion contained in the CAAC-OS film is, for example, located along the c-axis of the surface on which the CAAC-OS film is formed. Aligned so as to be parallel to the line vector or the surface normal vector, and perpendicular to the ab-plane. When viewed from a certain direction, the metal atoms are arranged in a triangular or hexagonal shape, and when viewed from a direction perpendicular to the c-axis... Metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. The orientations of the a-axis and b-axis may differ between them. In this specification, simply vertical When referring to a straight line, the range of 80° to 100°, preferably 85° to 95°, is also included. It shall be included. Also, when simply stating "parallel," -10° or more and 10° or less is preferred. This includes the range of -5° to 5°.

[0171] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystal structure in the impurity-added region is altered. Sexual function may also decline.

[0172] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. The shape of the CAAC-OS film is aligned so as to be parallel to the normal vector of the film or surface. Depending on the shape (cross-sectional shape of the surface to be formed or the surface itself), they may face in different directions. Furthermore, the crystalline portion undergoes crystallization treatment such as heat treatment when the film is formed or after film formation. It is formed when the CAAC-OS film is formed. Therefore, the c-axis of the crystalline portion is the same as when the CAAC-OS film is formed. They are aligned so as to be parallel to the normal vector of the surface being formed or the normal vector of the surface itself.

[0173] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0174] An example of the crystal structure contained in a CAAC-OS film is explained in detail using Figures 12 to 15. To clarify. Unless otherwise specified, Figures 12 to 15 use the upward direction as the c-axis direction. Let the plane perpendicular to the direction be called plane ab. Note that when simply referring to the upper half and the lower half, the plane ab is used as the boundary. This refers to the upper and lower halves in that case. Also, in Figure 12, the circled O indicates 4-coordinate O. Furthermore, the O enclosed in a double circle indicates a 3-coordinate O.

[0175] Figure 12(A) shows one 6-coordinate In atom and six 4-coordinate oxygen atoms adjacent to the In atom (hereinafter referred to as 4 The structure shows a coordinated O) and a nearby oxygen atom. Here, for each metal atom, A structure showing only the children is called a small group. The structure in Figure 12(A) takes the form of an octahedron, but For simplicity, it is shown as a planar structure. Note that the upper and lower halves of Figure 12(A) are respectively There are 4-coordinate oxygen atoms, 3 in each group. The small group shown in Figure 12(A) has a charge of 0.

[0176] Figure 12(B) shows one 5-coordinate Ga atom and three 3-coordinate oxygen atoms adjacent to the Ga atom (hereinafter referred to as 3 The structure shows a coordinated oxygen atom and two 4-coordinate oxygen atoms adjacent to Ga. The 3-coordinate oxygen atom is All of them are located on the ab plane. There is one in the upper half and one in the lower half of Figure 12(B), for a total of four. There is a coordinate oxygen atom. Also, since In can take on a 5-coordinate state, it can take on the structure shown in Figure 12(B). The small group shown in Figure 12(B) has a charge of 0.

[0177] Figure 12(C) shows a structure having one 4-coordinate Zn and four 4-coordinate O adjacent to the Zn. The structure is shown. In the upper half of Figure 12(C), there are three 4-coordinate oxygen atoms, and in the lower half, there is one 4-coordinate oxygen atom. It may be present. The small group shown in Figure 12(C) has a charge of 0.

[0178] Figure 12(D) shows a structure having one 6-coordinate Sn and six 4-coordinate O adjacent to the Sn. The structure is shown. The upper half of Figure 12(D) has 3 four-coordinate oxygen atoms, and the lower half has 3 four-coordinate oxygen atoms. There is an O. The small group shown in Figure 12(D) has a charge of +1.

[0179] Figure 12(E) shows a small group containing two Zn molecules. The upper half of Figure 12(E) shows one There is a 4-coordinate oxygen atom, and the lower half has one 4-coordinate oxygen atom. The small group shown in Figure 12(E) The charge becomes -1.

[0180] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is We call it a large group.

[0181] Here, we will explain the rules by which these subgroups combine. The upper half of In in 6 coordination The three O's in the lower half each have three adjacent In's in the downward direction, and the three O's in the lower half have upward direction Each has 3 adjacent In atoms. One O atom in the upper half of the 5-coordinate Ga has one downward direction It has adjacent Ga atoms, and one O atom in the lower half has one adjacent Ga atom above it. 4-coordinate Zn The single O in the upper half has one adjacent Zn in the downward direction, and the three O in the lower half have an upward direction Each has three adjacent Zn atoms. In this way, the number of 4-coordinate O atoms in the upward direction of the metal atom and its The number of adjacent metal atoms below the O atom is equal, and similarly, the number of 4-coordinate O atoms below the metal atom is equal. The number of nearby metal atoms above the oxygen is equal. Since oxygen is 4-coordinate, the number of atoms below it is equal. The sum of the number of nearby metal atoms and the number of nearby metal atoms above is 4. Therefore, metal atoms The sum of the number of 4-coordinate oxygen atoms above and the number of 4-coordinate oxygen atoms below another metal atom is When there are four atoms, two small groups containing metal atoms can bond together. For example, When a 6-coordinate metal atom (In or Sn) is bonded via a 4-coordinate oxygen atom in the lower half, Because there are 3 oxygen atoms in the position, it is a 5-coordinate metal atom (Ga or In), and a 4-coordinate metal atom (Z It will be combined with one of n).

[0182] Metal atoms with these coordination numbers are bonded in the c-axis direction via 4-coordinate oxygen atoms. In addition, multiple small groups combine such that the total charge of the layered structure becomes 0. It forms a middle group.

[0183] Figure 13(A) shows a model diagram of the intermediate groups that constitute the layered structure of the In-Sn-Zn-O system. Figure 13(B) shows the large group, which is composed of three subgroups. C) shows the atomic arrangement when the layer structure of Figure 13(B) is observed from the c-axis direction.

[0184] In Figure 13(A), for simplicity, three-coordinate oxygen atoms are omitted, and only the number of four-coordinate oxygen atoms is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate oxygen atoms (indicated by the circle). This is shown as 3. Similarly, in Figure 13(A), the upper half and lower half of In are Each of these has one 4-coordinate oxygen atoms, which are shown as 1 in the circle. Similarly, Figure 13 In (A), the lower half has one 4-coordinate oxygen atom, and the upper half has three 4-coordinate oxygen atoms. Zn has one 4-coordinate oxygen atom in the upper half and three 4-coordinate oxygen atoms in the lower half. This indicates that.

[0185] In Figure 13(A), the middle group constituting the layered structure of the In-Sn-Zn-O system is from the top In order, Sn has three 4-coordinate oxygen atoms in the upper half and three in the lower half, and one 4-coordinate oxygen atom in the upper half. It bonds with In in the half and lower half, and that In has three 4-coordinate O in the upper half. It bonds with n, and through one 4-coordinate oxygen atom in the lower half of the Zn, three 4-coordinate oxygen atoms are bonded to the upper half. And bonded to In in the lower half, that In has one 4-coordinate O in the upper half of Zn2 It combines with a small group consisting of , and through one 4-coordinate O in the lower half of this small group, 4 The coordination is structured so that three oxygen atoms are bonded to the Sn atoms in the upper half and three in the lower half. Multiple loops combine to form a larger group.

[0186] Here, in the case of 3-coordinate oxygen and 4-coordinate oxygen, the charge per bond is -0.6, respectively. 67, -0.5 can be considered. For example, In (6-coordinate or 5-coordinate), Zn (4 The charges of (5-coordinate) and Sn (5-coordinate or 6-coordinate) are +3, +2, and +4, respectively. Therefore Therefore, the small group containing Sn has a charge of +1. As a result, it forms a layered structure containing Sn. For this to work, a charge of -1 is needed to cancel out the charge of +1. Figure 1 shows a structure that takes on a charge of -1. As shown in 2(E), a small group containing two Zn elements is an example. If there is one small group and one small group containing two Zn atoms, the charges cancel each other out. Therefore, the total charge of the layered structure can be set to 0.

[0187] Specifically, the large groups shown in Figure 13(B) are repeated, resulting in In-Sn-Zn -O-based crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be represented by the following compositional formula. Note that in In-Sn-Zn-O crystals, the number of m is large. This is preferable because it improves crystallinity.

[0188] In addition, there are other oxides of quaternary metals, such as In-Sn-Ga-Zn oxides, and ternary metals. In-Ga-Zn oxides (also written as IGZO), which are oxides of the original metal, Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-C e-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm -Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb- Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Z n-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides, In-Lu-Zn-based oxides In-Zn oxides, Sn-Zn oxides, and Al oxides are examples of oxides of binary metals. -Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, and I The same applies when using n-Ga-based materials.

[0189] For example, Figure 14(A) shows a model diagram of the intermediate group that constitutes the layered structure of the In-Ga-Zn system. This indicates.

[0190] In Figure 14(A), the intermediate groups constituting the In-Ga-Zn layer structure are, from top to bottom: In a molecule with three 4-coordinate oxygen atoms in the upper half and three in the lower half, and with one 4-coordinate oxygen atom in the upper half... It bonds with Zn, and through the three 4-coordinate oxygen atoms in the lower half of the Zn, one 4-coordinate oxygen atom is bonded to each of them. It bonds with Ga in the upper and lower halves, and via one 4-coordinate O in the lower half of that Ga. This configuration consists of 4-coordinate oxygen atoms bonded to inions in the upper and lower halves, with three oxygen atoms bonded to each other. Multiple medium-sized groups combine to form a large group.

[0191] Figure 14(B) shows the large group, which is composed of three medium groups. Figure 14(C) is Figure 14(B) shows the atomic arrangement when the layered structure is observed from the c-axis direction.

[0192] Here, the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are as follows: Since they are +3, +2, and +3 respectively, small groups containing any of In, Zn, and Ga Therefore, the charge becomes 0. The charge of the sum is always 0.

[0193] Furthermore, the intermediate groups that constitute the layered structure of the In-Ga-Zn system are shown in Figure 14(A). Not limited to loops, large groups are formed by combining medium groups with different sequences of In, Ga, and Zn. A loop is also possible.

[0194] Specifically, the large groups shown in Figure 14(B) are repeated, resulting in In-Ga-Zn A crystal of the In-Ga-Zn system can be obtained. The resulting In-Ga-Zn layer structure is InGa O3(ZnO) n It can be expressed by the empirical formula (where n is a natural number).

[0195] For n=1 (InGaZnO4), the crystal structure can take the form shown in Figure 15(A), for example. Furthermore, in the crystal structure shown in Figure 15(A), as explained in Figure 12(B), Ga and Since in takes a 5-coordinate state, it can also take a structure in which Ga is replaced by in.

[0196] Furthermore, in the case of n=2(InGaZn2O5), for example, the crystal structure shown in Figure 15(B) is It is possible. Furthermore, in the crystal structure shown in Figure 15(B), as explained in Figure 12(B) Since Ga and In can form a 5-coordinate structure, a structure in which Ga is replaced by In is also possible.

[0197] (Embodiment 7) In this embodiment, an example of the configuration of a semiconductor memory device according to one aspect of the present invention will be shown with reference to Figure 16. I will explain.

[0198] Figure 16 is a circuit diagram of the main part of a semiconductor memory device according to one embodiment of the present invention. The device comprises a first transistor 1101, a second transistor 1102, and a capacitor 1103. It is equipped with.

[0199] The semiconductor memory device has a gate for the first transistor 1101 and a second transistor 1102. The first electrode and one electrode of the capacitor 1103 are electrically connected to each other at the node. It includes (holding node R).

[0200] Furthermore, wiring S2 and the second are used to electrically connect the first electrode of the first transistor 1101. Let wire D be the wire that is electrically connected to the electrode of the second transistor 1102. Let the wiring connected to the first electrode be wiring W1, and the wiring electrically connected to the second electrode be wiring S1. Furthermore, the wiring that electrically connects to the other electrode of capacitor 1103 is denoted as wiring W2.

[0201] When writing data to the semiconductor memory, the second transistor 1102 is turned ON on wiring W1. A potential is input to cause a certain voltage, and a predetermined voltage is supplied from wiring S1 to the second electrode of the second transistor 1102. By inputting a position, a predetermined potential can be written to the holding node R. After that, When a potential that turns off the second transistor 1102 is input to wiring W1, the holding node R The potential is maintained.

[0202] Furthermore, depending on the potential held by the holding node R, a gate is connected to the holding node R. The first transistor 1101 is either ON or OFF. Therefore, the wiring S2 and By inputting a potential for reading to one side of line D and detecting the potential on the other side, the reading can be performed. It is possible to do so.

[0203] Thus, when writing or erasing data to a semiconductor memory device according to one aspect of the present invention Therefore, only a voltage sufficient to turn on the second transistor 1102 is needed. Furthermore, holding The voltage required to write to node R is the ON state of the first transistor 1101 or Only a voltage sufficient to control the off state is needed. Therefore, according to one aspect of the present invention, semiconductor memory Because it does not require high voltage like flash memory to operate, it is extremely energy-efficient. This enables the realization of semiconductor memory devices with reduced power consumption.

[0204] Here, as the second transistor 1102, silicon is used as the semiconductor in which the channel is formed. Compared to conventional transistors, this transistor exhibits reduced leakage current (off-current) in the off state. It is preferable to use a zista. Specifically, as the semiconductor in which the channel is formed, silica Transistors using semiconductors with a wider band gap than silicon are used. Compound semiconductors are semiconductors with a wide band gap, such as oxide semiconductors. Examples include nitride semiconductors.

[0205] In particular, an oxide semiconductor is used as the semiconductor constituting the channel of the second transistor 1102. It is preferable that they be present.

[0206] Thus, a transistor with reduced off-current is applied to the second transistor 1102. This will result in a semiconductor memory device that can retain its contents even when power is not supplied. It is possible.

[0207] (Embodiment 8) In this embodiment, at least a portion of the semiconductor memory device disclosed in the above embodiment is used. One example of a semiconductor device is a CPU (Central Processing Unit). I will explain about that.

[0208] Figure 17(A) is a block diagram showing the specific configuration of the CPU. The PU is located on circuit board 1190, with ALU1191 (ALU: Arithmetic Logi c unit (arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189 (R It has an OM I / F. The substrate 1190 is a semiconductor substrate, SOI substrate, glass substrate, etc. The ROM 1199 and ROM interface 1189 are provided on separate chips. That is also fine. Of course, the CPU shown in Figure 17(A) is just one example of a simplified configuration. In fact, actual CPUs have a wide variety of configurations depending on their intended use.

[0209] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0210] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal for that purpose. Also, the interrupt controller 1194 is the CPU programmer. During execution, interrupt requests from external input / output devices and peripheral circuits are prioritized and masked. The state is judged and processed. The register controller 1197 adds register 1196 It generates a response and reads or writes to register 1196 depending on the CPU state.

[0211] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates a signal that controls the timing of the operation of the zista controller 1197. For example, The ming controller 1195 uses the reference clock signal CLK1 to generate the internal clock signal C It is equipped with an internal clock generation unit that generates LK2, and the internal clock signal CLK2 is used by the above-mentioned It supplies power to the seed circuit.

[0212] In the CPU shown in Figure 17(A), a memory cell is provided in register 1196. The memory cell of ZISTA 1196 contains a logic element that inverts logic (value) and, in the above embodiment, It includes both of the disclosed semiconductor memory devices.

[0213] In the CPU shown in Figure 17(A), the register controller 1197 is ALU1191 Following the instructions, select a hold operation in register 1196. That is, register In the memory cell of the Ta1196, data is inverted by a logic element that reverses logic (value). Choose whether to retain the data or retain it using semiconductor memory. (Logical value) If data retention by a logic element that inverts is selected, in register 1196 Power voltage is supplied to the memory cell. Data retention in semiconductor memory devices is selected. If selected, data is rewritten to the semiconductor memory, and in register 1196 The power supply voltage to the memory cell can be stopped.

[0214] Regarding power shutdown, as shown in Figure 17(B) or Figure 17(C), the memory cell group and A switching element is placed between nodes where the power supply potential VDD or power supply potential VSS is given. This can be done by providing the following circuit. The circuits in Figures 17(B) and 17(C) are described below. To do so.

[0215] In Figures 17(B) and 17(C), register 1196 supplies the power potential to the memory cell. It is equipped with a switching element to control the supply.

[0216] The register 1196 shown in Figure 17(B) consists of a switching element 1141 and a memory cell 11 It has a memory cell group 1143 having multiple 42s. Specifically, each memory cell 114 2 is equipped with both a logic element that inverts logic (values) and the above-mentioned semiconductor memory device. Each memory cell 1142 in the Morissel group 1143 is connected via a switching element 1141. And a high power potential VDD is supplied. Furthermore, the memory cell group 1143 Each memory cell 1142 has a signal IN potential and a low-level power supply potential VSS. A rank has been assigned.

[0217] In Figure 17(B), a transistor is used as the switching element 1141, and The switching of a transistor is controlled by the signal SigA applied to its gate electrode. ru.

[0218] Note that in Figure 17(B), the switching element 1141 has only one transistor. The expression indicates a configuration, but is not particularly limited and may have multiple transistors. When element 1141 has multiple transistors that function as switching elements The above-mentioned transistors may be connected in parallel or in series. Furthermore, a combination of series and parallel connections is also acceptable.

[0219] Furthermore, Figure 17(C) shows that each memory cell 1142 of the memory cell group 1143 has a sw A low-level power supply potential VSS is supplied via the switching element 1141, An example of T1196 is shown. The memory cell group 1143 is controlled by the switching element 1141. It is possible to control the supply of a low-level power potential VSS to each memory cell 1142. Cut.

[0220] Between the memory cell group and the node to which the power supply potential VDD or power supply potential VSS is provided, When a switching element is installed, temporarily stopping the CPU's operation and cutting off the power supply voltage, It is possible to retain data even in this state, and power consumption can be reduced. Physically, for example, when a personal computer user interacts with an input device such as a keyboard... Even while inputting information is stopped, the CPU operation can be stopped, thereby eliminating It can reduce power consumption.

[0221] Furthermore, electronic devices using such CPUs have reduced power consumption, so even if The relatively small amount of power obtained by solar cells or contactless power transfer (also called wireless power transfer) But it can be made to work perfectly well. For example, a solar cell module or wireless connection to an electronic device. A contact power supply module and a secondary battery that stores the power obtained by such a module. The configuration will include a lithium-ion battery, etc.

[0222] Here, we used the CPU as an example, but DSP (Digital Signal Processor) Processor), custom LSI, FPGA (Field Programmable) It can also be applied to LSIs such as e Gate Arrays.

[0223] (Embodiment 9) The semiconductor memory devices disclosed herein are applicable to a variety of electronic devices (including gaming machines). It is possible. Examples of electronic devices include televisions, monitors and other display devices, lighting devices, and desktop computers. Printed or notebook-type personal computers, word processors, DVDs (digital) Still images or videos stored on recording media such as a Versatile Disc Playback devices, portable CD players, radios, tape recorders, headphones. Stereo, cordless phone handset, transceiver, portable radio, mobile phone, automatic Car phones, portable game consoles, calculators, personal digital assistants, electronic organizers, e-books, electronic translators, voice High-frequency devices such as input devices, video cameras, digital still cameras, electric shavers, and microwave ovens. Heating devices, electric rice cookers, electric washing machines, electric vacuum cleaners, air conditioning equipment such as air conditioners Dishwasher, dish dryer, clothes dryer, futon dryer, electric refrigerator, electric freezer, electric refrigerator Freezers, freezers for DNA storage, smoke detectors, radiation detectors, dialysis machines and other medical equipment, etc. These include guide lights, traffic lights, conveyor belts, elevators, escalators, Industrial equipment such as industrial robots and power storage systems can also be mentioned. Furthermore, engines using petroleum... Mobile devices that use electricity from din-type or non-aqueous secondary batteries to propel themselves with electric motors are also electric. It shall be included in the category of a "vessel." Examples of the above-mentioned mobile devices include electric vehicles (EVs) and internal combustion engines. Hybrid electric vehicles (HEVs) and plug-in hybrid vehicles (PHEVs) combine an engine and an electric motor. EVs, tracked vehicles that replace these tires and wheels with tracks, and electric assist bicycles are all types of vehicles. Motorized bicycles, motorcycles, electric wheelchairs, golf carts, small or large vessels, submarines Examples include helicopters, aircraft, rockets, satellites, space probes and planetary probes, and spacecraft. These electronic devices are shown in Figures 18 and 19.

[0224] Figure 18(A) shows a portable music player, which has a display unit 3023 on the main unit 3021 and is worn on the ear. Fixing part 3022, speaker, operation button 3024, external memory slot 302 5 etc. are provided. The semiconductor memory device and semiconductor device exemplified in the above embodiment are the main body By applying this to the memory and CPU built into the 3021, power consumption will be further reduced. It can be used as a portable music player.

[0225] Furthermore, the portable music player shown in Figure 18(A) has an antenna, microphone function, and wireless function. By linking it with your mobile phone, you can wirelessly use hands-free while driving a car or other vehicle. Conversation is also possible.

[0226] Figure 18(B) shows a computer, consisting of a main unit 9201 including the CPU, a casing 9202, and a display unit. 9203, Keyboard 9204, External connection port 9205, Pointing device 92 Including 06, etc. Using semiconductor devices such as semiconductor memory devices and CPUs as shown in the above embodiment. This would make it possible to create a more power-efficient computer.

[0227] In Figure 19(A), the television device 8000 has a display unit 8002 in the housing 8001. It is integrated, with the display unit 8002 displaying video and the speaker unit 8003 outputting audio. It is possible to output. The semiconductor memory device or semiconductor device exemplified in the above embodiment. This can be used in the drive circuit for operating the display unit 8002 which is incorporated into the housing 8001. It is possible.

[0228] The display unit 8002 is a light-emitting device equipped with light-emitting elements such as liquid crystal display devices and organic EL elements in each pixel. Electrophoresis display device, DMD (Digital Micromirror Display) e) Semiconductor display devices such as PDPs (Plasma Display Panels) It can be used.

[0229] The television equipment 8000 may include a receiver, modem, etc. The Oki 8000 can receive general television broadcasts using a receiver, and also has a modem. By connecting to a wired or wireless communication network via this, one-way communication (sender or Information communication between (sender and receiver) or two-way (sender and receiver, or between receivers, etc.) It is possible to do so.

[0230] Furthermore, the television equipment 8000 is equipped with a CPU and memory for information communication. It may also be the case that the television device 8000 includes the semiconductor memory device exemplified in the above embodiment, It is possible to use semiconductor devices such as CPUs.

[0231] In Figure 19(A), an air conditioner having an indoor unit 8200 and an outdoor unit 8204. - is an example of an electrical device using a semiconductor device such as a CPU as exemplified in the above embodiment. Specifically, the indoor unit 8200 includes the casing 8201, the air outlet 8202, the CPU 8203, etc. In Figure 19(A), when the CPU 8203 is located in the indoor unit 8200... Although this is shown as an example, the CPU 8203 may also be located in the outdoor unit 8204. Alternatively, A CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By using the CPU exemplified in the above embodiment, an air conditioner with excellent power saving capabilities can be produced. —can be achieved.

[0232] In Figure 19(A), the electric refrigerator 8300 is a CPU as illustrated in the above embodiment. This is an example of an electrical device equipped with semiconductor equipment. Specifically, the electric refrigerator-freezer 8300 is: It includes a casing 8301, a door for the refrigerator compartment 8302, a door for the freezer compartment 8303, a CPU 8304, and the like. In Figure 19(A), the CPU 8304 is located inside the chassis 8301. The semiconductor device such as the CPU, as exemplified in this form, is used in the CPU 8304 of the electric refrigerator 8300. By using it, power consumption can be reduced.

[0233] Figures 19(B) and 19(C) show an example of an electric vehicle, which is an example of an electrical device. The electric vehicle 9700 is equipped with a secondary battery 9701. The force is supplied to the drive unit 9703 after its output is adjusted by the control circuit 9702. Circuit 9702 is controlled by a processing unit 9704 having a ROM, RAM, CPU, etc. (not shown). It is controlled by the semiconductor device such as the semiconductor memory device and CPU exemplified in the above embodiment. By using it in the processing unit 9704 of the 9700 electric vehicle, power consumption can be reduced.

[0234] The drive unit 9703 consists of a DC motor or an AC motor alone, or a motor and an internal combustion engine. It is composed of a combination of these. The processing unit 9704 processes the driver's operation information of the electric vehicle 9700. Information (acceleration, deceleration, stopping, etc.) and driving information (information such as uphill and downhill slopes, and the driving force applied to the drive wheels) Based on input information (such as load information), the control circuit outputs a control signal to the control circuit 9702. 9702 receives power from the secondary battery 9701 via a control signal from the processing unit 9704. The energy is adjusted to control the output of the drive unit 9703. Although not shown in the diagram, the unit also incorporates an inverter that converts direct current to alternating current.

[0235] This embodiment may be implemented in appropriate combination with other embodiments described herein. It is possible. [Explanation of symbols]

[0236] 1. Semiconductor memory 2. Semiconductor memory devices 3. Semiconductor memory devices 10 memory cells 20 memory cells 30 cell cells 100 First Transistor 101 First Semiconductor Layer 105 First Word Line 106 Second Word Line 110 First gate insulating layer 120 First Gate 130 Source area or drain area 150 First interlayer membrane 151 Insulating layer 152 Insulating layer 200 Second Transistor 201 Second Semiconductor Layer 210 Second gate insulating layer 220 Second Gate 250 Second interlayer membrane 251 Insulating film 300A capacitor 300b capacitor 300C Capacitor 310a 1st capacitor electrode 310b 1st capacitor electrode 310c 1st capacitor electrode 320 2nd capacitor electrode 321 Conductive layer 410 capacitive layer 500 bit line 700 Insulating layer 600 conductive layer 600a conductive layer 600b conductive layer 601 Conductive layer 1101 First Transistor 1102 Second Transistor 1103 Capacitor 1141 Switching element 1142 memory cells 1143 memory cell group 1189 ROM Interface 1190 circuit board 1191 ALU 1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM 3021 Main Unit 3022 Fixed part 3023 Display section 3024 Operation Buttons 3025 External memory slot 8000 Television equipment 8001 enclosure 8002 Display section 8003 Speaker section 8200 indoor unit 8201 enclosure 8202 Air outlet 8203 CPU 8204 Outdoor unit 8300 Electric Refrigerator / Freezer 8301 enclosure 8302 Refrigerator door 8303 Freezer door 8304 CPU 9201 Main Unit 9202 enclosure 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing device 9700 Electric Vehicles 9701 Secondary battery 9702 control circuit 9703 Drive unit 9704 Processing Unit

Claims

[Claim 1] It has a memory cell including a first transistor, a second transistor, and a capacitor, The first transistor includes a first semiconductor layer, a first gate insulating layer in contact with the first semiconductor layer, a first gate electrode in contact with the first gate insulating layer and overlapping with the first semiconductor layer, and a source region and a drain region provided so as to sandwich the region of the first semiconductor layer that overlaps with the first gate electrode. The second transistor includes a second semiconductor layer arranged to overlap the first gate electrode and electrically connected to the first gate electrode, a second gate insulating layer in contact with the side surface of the second semiconductor layer, and a second gate electrode formed in contact with the second gate insulating layer and covering at least a portion of the side surface of the second semiconductor layer. The capacitor is a semiconductor memory device having a capacitance layer in contact with the side surface of the first gate electrode and a first capacitance electrode formed in contact with the capacitance layer and covering at least a portion of the side surface of the first gate electrode.

Images