Semiconductor equipment
The semiconductor device addresses the challenge of chip arrangement by using a wiring board with face-up and face-down chips connected via wires, ensuring efficient electrical connections and alignment, thereby improving device performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- KIOXIA CORP
- Filing Date
- 2026-04-10
- Publication Date
- 2026-06-18
AI Technical Summary
Existing semiconductor devices face challenges in appropriately arranging multiple stacked chips, particularly in ensuring efficient electrical connections and alignment of terminals.
A semiconductor device design featuring a wiring board with stacked semiconductor chips, where some chips are face-up and others face-down, connected via connection wires, and covered by a molded resin layer, allowing for efficient electrical connections and alignment.
The solution enables effective arrangement and electrical connectivity of multiple chips, enhancing the semiconductor device's performance and functionality.
Smart Images
Figure 2026100012000001_ABST
Abstract
Description
Technical Field
[0001] This embodiment relates to a semiconductor device.
Background Art
[0002] In a semiconductor device, a plurality of chips may be stacked, and terminals may extend from each chip in the stacking direction. In a semiconductor device, it is desirable to appropriately arrange a plurality of chips.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] According to this embodiment, a semiconductor device capable of appropriately arranging a plurality of chips is provided.
Means for Solving the Problems
[0005] This embodiment is a semiconductor device including a wiring board provided with a wiring layer inside, and a stacked body including a plurality of first semiconductor chips stacked with a shift on the wiring board. The first semiconductor chips include semiconductor chips arranged face-up with respect to the wiring board and semiconductor chips arranged face-down with respect to the wiring board.
Brief Description of the Drawings
[0006] [Figure 1] It is a cross-sectional view showing a semiconductor device in the first embodiment. [Figure 2] It is a cross-sectional view for explaining a manufacturing method of the semiconductor device in the first embodiment. [Figure 3] It is a cross-sectional view for explaining a manufacturing method of the semiconductor device in the first embodiment. [Figure 4] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 5] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 6] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 7] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 8] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 9] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device in a first embodiment. [Figure 10] This is a cross-sectional view showing a semiconductor device in a second embodiment. [Figure 11] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 12] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 13] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 14] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 15] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 17] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 18] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Modes for carrying out the invention]
[0007] Hereinafter, this embodiment will be described with reference to the accompanying drawings. For ease of understanding of the description, the same reference numerals are given to the same components in each drawing as much as possible, and duplicate descriptions are omitted.
[0008] (First Embodiment) The semiconductor device 2 in the first embodiment will be described with reference to FIG. 1. FIG. 1 is a cross-sectional view of the semiconductor device 2. As shown in FIG. 1, the semiconductor device 2 includes a wiring substrate 21, first semiconductor chips 23a, 231, 232, 233, 23b, connection wires 241, 242, 243, 244, 251, 252, 253, 254, a second semiconductor chip 28, metal balls 29, and a mold resin layer 30.
[0009] The first semiconductor chip 23a is provided on the wiring substrate 21. The first semiconductor chip 23a is, for example, a memory chip of a NAND-type flash memory. The first semiconductor chip 231 is provided on the first semiconductor chip 23a. The first semiconductor chip 232 is provided on the first semiconductor chip 231. The semiconductor chip 233 is provided on the semiconductor chip 232. The first semiconductor chip 23b is provided on the first semiconductor chip 233.
[0010] The first semiconductor chips 231, 232, 233 are each a semiconductor chip formed by bonding two semiconductor chips together. The first semiconductor chips 23a, 23b are each a single semiconductor chip and have substantially the same thickness as the first semiconductor chips 231, 232, 233. Therefore, although the first semiconductor chips 23a, 231, 232, 233, 23b are stacked five layers, since the first semiconductor chips 231, 232, 233 are each formed by bonding two semiconductor chips, it is substantially equivalent to stacking eight chips.
[0011] The first semiconductor chip 231 is formed by bonding, on the back surface, a semiconductor chip facing down with respect to the wiring board 21 and a semiconductor chip facing up with respect to the wiring board 21 to form a single semiconductor chip. The same applies to the first semiconductor chips 232 and 233.
[0012] The first semiconductor chip 23a is mounted facing up with respect to the wiring board 21. The first semiconductor chip 23a is fixed to the wiring board 21 with an adhesive 27. The first semiconductor chip 23a is electrically connected to the wiring board 21 by a connection wire 251. In the first semiconductor chip 231, the semiconductor chip facing down with respect to the wiring board 21 is electrically connected to the wiring board 21 by a connection wire 241. In the first semiconductor chip 231, the semiconductor chip facing up with respect to the wiring board 21 is electrically connected to the first semiconductor chip 23a by a connection wire 252.
[0013] In the first semiconductor chip 232, the semiconductor chip facing down with respect to the wiring board 21 is electrically connected to the semiconductor chip facing down with respect to the wiring board 21 in the first semiconductor chip 231 by a connection wire 242. In the first semiconductor chip 232, the semiconductor chip facing up with respect to the wiring board 21 is electrically connected to the semiconductor chip facing up with respect to the wiring board 21 in the first semiconductor chip 231 by a connection wire 253.
[0014] In the first semiconductor chip 233, the semiconductor chip facing down with respect to the wiring board 21 is electrically connected to the semiconductor chip facing down with respect to the wiring board 21 in the first semiconductor chip 232 by a connection wire 243. In the first semiconductor chip 233, the semiconductor chip facing up with respect to the wiring board 21 is electrically connected to the semiconductor chip facing up with respect to the wiring board 21 in the first semiconductor chip 232 by a connection wire 254.
[0015] The first semiconductor chip 23a is mounted on the first semiconductor chip 233 so as to be face-down relative to the wiring board 21. The first semiconductor chip 23a is electrically connected to the semiconductor chip on the first semiconductor chip 233, which is also face-down relative to the wiring board 21, by connecting wires 244.
[0016] A second semiconductor chip 28 is flip-chip mounted on the wiring board 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring board 21 via metal bumps.
[0017] The first semiconductor chips 23a, 231, 232, 233, and 23b are stacked with an offset so that at least a portion of each faces the wiring substrate 21. A die attach film (DAF) is provided between the stacked first semiconductor chips 23a, 231, 232, 233, and 23b. The mounted first semiconductor chips 23a, 231, 232, 233, and 23b are arranged with an offset so that the one mounted on top is closer to the second semiconductor chip 28. The first semiconductor chip 23a, which is located closest to the wiring substrate 21, is located furthest from the second semiconductor chip 28. The first semiconductor chip 231 is placed on top of the first semiconductor chip 23a, which is located closest to the wiring substrate 21, with an offset so that it is closer to the second semiconductor chip 28. The first semiconductor chip 23b, which is located furthest from the wiring substrate 21, is located closest to the second semiconductor chip 28.
[0018] A molded resin layer 30 is provided on the wiring board 21. The molded resin layer 30 covers the first semiconductor chips 23a, 231, 232, 233, 23b, connecting wires 241, 242, 243, 244, 251, 252, 253, 254, and the second semiconductor chip 28.
[0019] A metal ball 29 is provided on the side of the wiring board 21 opposite to the side on which the first semiconductor chip 23a is mounted.
[0020] Next, the manufacturing method of the semiconductor device 2 will be described with reference to Figures 2 to 9. As shown in Figure 2, semiconductor chips 233a and 233b are prepared. The back surfaces of semiconductor chips 233a and 233b are joined together via a die attach film (DAF) to form the first semiconductor chip 233.
[0021] Next, as shown in Figure 3, the first semiconductor chip 233 is laminated onto the first semiconductor chip 23b using an adhesive. The semiconductor chip 233 is laminated onto the side of the first semiconductor chip 23b that faces the wiring board 21 during mounting.
[0022] Next, as shown in Figure 4, the first semiconductor chip 232 is laminated onto the first semiconductor chip 233 using an adhesive. The first semiconductor chip 232 is laminated onto the side of the first semiconductor chip 233 that faces the wiring board 21 when mounted. The first semiconductor chip 231 is laminated onto the first semiconductor chip 232 using an adhesive. The first semiconductor chip 231 is laminated onto the side of the first semiconductor chip 232 that faces the wiring board 21 when mounted. The first semiconductor chip 23a is laminated onto the first semiconductor chip 231 using an adhesive. The first semiconductor chip 23a is laminated onto the side of the first semiconductor chip 231 that faces the wiring board 21 when mounted.
[0023] Next, as shown in Figure 5, the semiconductor chips are electrically connected to each other. The first semiconductor chip 23b and the first semiconductor chip 233 are electrically connected with a connecting wire 244. The first semiconductor chip 233 and the first semiconductor chip 232 are electrically connected with a connecting wire 243. The first semiconductor chip 232 and the first semiconductor chip 231 are electrically connected with a connecting wire 242. The connecting wire 241 is provided as a vertical wire for the first semiconductor chip 231.
[0024] Next, prepare the wiring board 21 and the second semiconductor chip 28 as shown in Figure 6. Flip-chip mount the second semiconductor chip 28 onto the wiring board 21. Apply adhesive 27 to the wiring board 21.
[0025] Next, as shown in Figure 7, the laminate prepared in Figure 5 is mounted on the wiring board 21. The laminate prepared in Figure 5 is placed upside down so that the first semiconductor chip 23a is in contact with the wiring board 21. The connecting wires 241 are joined to the wiring board 21.
[0026] Next, as shown in Figure 8, the semiconductor chips are electrically connected to each other. The first semiconductor chip 233 and the first semiconductor chip 232 are electrically connected with a connecting wire 254. The first semiconductor chip 232 and the first semiconductor chip 231 are electrically connected with a connecting wire 253. The first semiconductor chip 231 and the first semiconductor chip 23a are electrically connected with a connecting wire 252. The first semiconductor chip 23a and the wiring board 21 are electrically connected with a connecting wire 251.
[0027] Next, as shown in Figure 9, a molded resin layer 30 is formed to cover the first semiconductor chips 23a, 231, 232, 233, 23b, connecting wires 241, 242, 243, 244, 251, 252, 253, 254, and the second semiconductor chip 28.
[0028] A metal ball 29 is provided on the side of the wiring board 21 opposite to the side on which the first semiconductor chip 23a is mounted, thereby forming a semiconductor device 2 as shown in Figure 1. (Second Embodiment) A spacer 22 is provided between the first semiconductor chip 23, which is located closest to the wiring board 21, and the wiring board 21. A die attach film (DAF) is provided between the spacer 22 and the first semiconductor chip 23. An adhesive layer (not shown) is provided between the wiring board 21 and the spacer 22.
[0029] The semiconductor device 2A in the second embodiment will be described with reference to Figure 10. Figure 10 is a cross-sectional view of the semiconductor device 2A. As shown in Figure 10, the semiconductor device 2A comprises a wiring board 21, first semiconductor chips 231, 232, 233, 234, connecting wires 241, 242, 243, 244, 251, 252, 253, 254, spacers 26, second semiconductor chip 28, metal balls 29, and a molded resin layer 30.
[0030] A spacer 26 is provided on the wiring board 21. A die attach film (DAF) is provided between the wiring board 21 and the spacer 26. A first semiconductor chip 231 is provided on the spacer 26. The first semiconductor chip 231 is, for example, a memory chip of a NAND flash memory. A first semiconductor chip 232 is provided on the first semiconductor chip 231. A first semiconductor chip 233 is provided on the first semiconductor chip 232. A semiconductor chip 234 is provided on the semiconductor chip 233.
[0031] The first semiconductor chips 231, 232, 233, and 234 are each semiconductor chips formed by bonding two semiconductor chips together. Therefore, although the first semiconductor chips 231, 232, 233, and 234 are stacked in a total of four chips, since each of the first semiconductor chips 231, 232, 233, and 234 is formed by bonding two semiconductor chips together, it is effectively a stack of eight chips.
[0032] The first semiconductor chip 231 is formed by bonding a semiconductor chip with its face down relative to the wiring board 21 and a semiconductor chip with its face up relative to the wiring board 21 on their back surfaces to form a single semiconductor chip. The first semiconductor chips 232, 233, and 234 are constructed similarly.
[0033] In the first semiconductor chip 231, the semiconductor chip facing down relative to the wiring board 21 is electrically connected to the wiring board 21 by connecting wires 241. In the first semiconductor chip 231, the semiconductor chip facing up relative to the wiring board 21 is electrically connected to the wiring board 21 by connecting wires 251.
[0034] In the first semiconductor chip 232, the semiconductor chip facing down relative to the wiring board 21 is electrically connected to the semiconductor chip facing down relative to the wiring board 21 in the first semiconductor chip 231 by a connecting wire 242. In the first semiconductor chip 232, the semiconductor chip facing up relative to the wiring board 21 is electrically connected to the semiconductor chip facing up relative to the wiring board 21 in the first semiconductor chip 231 by a connecting wire 252.
[0035] In the first semiconductor chip 233, the semiconductor chip facing down relative to the wiring board 21 is electrically connected to the semiconductor chip facing down relative to the wiring board 21 in the first semiconductor chip 232 by a connecting wire 243. In the first semiconductor chip 233, the semiconductor chip facing up relative to the wiring board 21 is electrically connected to the semiconductor chip facing up relative to the wiring board 21 in the first semiconductor chip 232 by a connecting wire 253.
[0036] In the first semiconductor chip 234, the semiconductor chip facing down relative to the wiring board 21 is electrically connected to the semiconductor chip facing down relative to the wiring board 21 in the first semiconductor chip 233 by a connecting wire 244. In the first semiconductor chip 234, the semiconductor chip facing up relative to the wiring board 21 is electrically connected to the semiconductor chip facing up relative to the wiring board 21 in the first semiconductor chip 233 by a connecting wire 254.
[0037] A second semiconductor chip 28 is flip-chip mounted on the wiring board 21. The second semiconductor chip 28 is, for example, a semiconductor chip equipped with an arbitrary LSI. The second semiconductor chip 28 is mounted on the wiring board 21 via metal bumps.
[0038] The first semiconductor chips 231, 232, 233, and 234 are stacked with an offset so that at least a portion of each faces the wiring board 21. A die attach film (DAF) is provided between the stacked first semiconductor chips 231, 232, 233, and 234. The mounted first semiconductor chips 231, 232, 233, and 234 are arranged with an offset so that the one mounted on top is closer to the second semiconductor chip 28. The first semiconductor chip 231, which is located closest to the wiring board 21, is located furthest from the second semiconductor chip 28. The first semiconductor chip 232 is placed on top of the first semiconductor chip 231, which is located closest to the wiring board 21, with an offset so that it is closer to the second semiconductor chip 28. The first semiconductor chip 234, which is located furthest from the wiring board 21, is located closest to the second semiconductor chip 28.
[0039] A molded resin layer 30 is provided on the wiring board 21. The molded resin layer 30 covers the first semiconductor chips 231, 232, 233, 234, connecting wires 241, 242, 243, 244, 251, 252, 253, 254, spacers 26, and the second semiconductor chip 28.
[0040] A metal ball 29 is provided on the side of the wiring board 21 opposite to the side on which the first semiconductor chip 231 is mounted.
[0041] Next, the manufacturing method of the semiconductor device 2A will be described with reference to Figures 11 to 19. As shown in Figure 11, semiconductor chips 234a and 234b are prepared. The back surfaces of semiconductor chips 234a and 234b are joined together via a die attach film (DAF) to form the first semiconductor chip 234.
[0042] Next, as shown in Figure 12, the first semiconductor chip 233 is laminated onto the first semiconductor chip 234 using an adhesive. The semiconductor chip 233 is laminated onto the side of the first semiconductor chip 234 that faces the wiring board 21 during mounting.
[0043] Next, as shown in Figure 13, the first semiconductor chip 232 is laminated onto the first semiconductor chip 233 using an adhesive. The first semiconductor chip 232 is laminated onto the side of the first semiconductor chip 233 that faces the wiring board 21 during mounting. The first semiconductor chip 231 is laminated onto the first semiconductor chip 232 using an adhesive. The first semiconductor chip 231 is laminated onto the side of the first semiconductor chip 232 that faces the wiring board 21 during mounting.
[0044] Next, as shown in Figure 14, the semiconductor chips are electrically connected to each other. The first semiconductor chip 234 and the first semiconductor chip 233 are electrically connected by a connecting wire 244. The first semiconductor chip 233 and the first semiconductor chip 232 are electrically connected by a connecting wire 243. The first semiconductor chip 232 and the first semiconductor chip 231 are electrically connected by a connecting wire 242. The connecting wire 241 is provided as a vertical wire for the first semiconductor chip 231.
[0045] Next, prepare the wiring board 21 and spacer 26 as shown in Figure 15. Attach the spacer 26 to the wiring board 21 using DAF.
[0046] Next, as shown in Figure 16, the second semiconductor chip 28 is flip-chip mounted on the wiring board 21. Adhesive 27A is applied to the spacer 26.
[0047] Next, as shown in Figure 17, the laminate prepared in Figure 14 is mounted on the wiring board 21. The laminate prepared in Figure 14 is placed upside down so that the first semiconductor chip 231 is in contact with the spacer 26. The connecting wires 241 are joined to the wiring board 21.
[0048] Next, as shown in Figure 18, the semiconductor chips are electrically connected to each other. The first semiconductor chip 234 and the first semiconductor chip 233 are electrically connected with a connecting wire 254. The first semiconductor chip 233 and the first semiconductor chip 232 are electrically connected with a connecting wire 253. The first semiconductor chip 232 and the first semiconductor chip 231 are electrically connected with a connecting wire 252. The first semiconductor chip 231 and the wiring board 21 are electrically connected with a connecting wire 251.
[0049] Next, as shown in Figure 19, a molded resin layer 30 is formed to cover the first semiconductor chips 231, 232, 233, 234, connecting wires 241, 242, 243, 244, 251, 252, 253, 254, spacer 26, and the second semiconductor chip 28.
[0050] A metal ball 29 is provided on the side of the wiring board 21 opposite to the side on which the first semiconductor chip 231 is mounted, thereby forming a semiconductor device 2A as shown in Figure 10.
[0051] The embodiments have been described above with reference to specific examples. However, this disclosure is not limited to these specific examples. Modifications made to these specific examples by those skilled in the art are also included within the scope of this disclosure, as long as they retain the features of this disclosure. The elements, their arrangement, conditions, shapes, etc., of each of the aforementioned specific examples are not limited to those illustrated and can be modified as appropriate. The elements of each of the aforementioned specific examples can be combined in different ways as appropriate, as long as no technical inconsistencies arise. [Explanation of symbols]
[0052] 2,2A: Semiconductor equipment 21: Wiring board 231, 232, 233, 234, 23a, 23b: First semiconductor chip 241, 242, 243, 244, 251, 252, 253, 254: Connecting wires 26: Spacer 27,27A: Adhesive 28: Second semiconductor chip 29: Metal ball 30: Mold resin layer
Claims
1. A semiconductor device, A wiring board with a wiring layer inside, The laminate includes a plurality of first semiconductor chips stacked in a staggered manner on the aforementioned wiring board, The first semiconductor chip includes a semiconductor chip that is positioned face-up relative to the wiring substrate and a semiconductor chip that is positioned face-down relative to the wiring substrate, in a semiconductor device.
2. A semiconductor device according to claim 1, The first semiconductor chip is a semiconductor device in which the back surfaces of a semiconductor chip positioned face-up on the wiring substrate and a semiconductor chip positioned face-down on the wiring substrate are bonded together.
3. A semiconductor device according to claim 1, A semiconductor device in which the first semiconductor chip located in the uppermost or lowermost layer of the laminate is thicker than the other first semiconductor chips.
4. A semiconductor device according to claim 1, A semiconductor device in which the first semiconductor chip, located at the bottom of the laminate, is connected to the wiring substrate via a vertical wire.
5. A semiconductor device according to claim 1, A semiconductor device in which the aforementioned laminate is mounted on the wiring board via spacers.
6. A semiconductor device according to claim 1, The system includes a second semiconductor chip with a different function from the first semiconductor chip, A semiconductor device comprising a second semiconductor chip arranged on the wiring substrate such that it overlaps with at least a portion of the laminate.