Semiconductor device and its manufacturing method

Abstract

This invention provides a technique for suppressing the increase in switching loss in a reverse-conducting IGBT having a boundary region between the IGBT region and the diode region. [Solution] The semiconductor substrate 10 of the reverse-conducting IGBTs 1, 2, and 3 has a first conductivity type boundary layer 18 of a first conductivity type provided in the boundary region 106, positioned below the drift layer 13 and in contact with the lower electrode 22, and a second conductivity type boundary layer 19 of a second conductivity type provided in the boundary region 106 and positioned between the first conductivity type boundary layer 18 and the drift layer 13.

Description

[Technical Field]

[0001] The technologies disclosed herein relate to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Development is underway on a type of semiconductor device called a reverse-conducting insulated gate bipolar transistor (IGBT). The semiconductor substrate of this type of device has an IGBT region where an IGBT structure is provided, and a diode region where a diode structure is provided. The diode structure is connected in antiparallel to the IGBT structure and can operate as a freewheeling diode during recovery.

[0003] In this type of semiconductor device, during recovery operation, holes are injected obliquely from the p-type base layer of the IGBT region towards the n-type cathode layer of the diode region. When the amount of holes injected obliquely from the p-type base layer towards the n-type cathode layer increases, the recovery current increases, and the recovery loss increases. For this reason, as disclosed in Patent Document 1, a boundary region may be provided between the IGBT region and the diode region in this type of semiconductor device. In the boundary region, the p-type collector layer is formed extending from the IGBT region. As a result, the diode structure is not configured in the boundary region, and the amount of holes injected obliquely from the p-type base layer towards the n-type cathode layer during recovery operation is suppressed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-15194 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] When a p-type collector layer is provided in the boundary region, holes are injected from the p-type collector layer in the boundary region toward the n-type drift layer in the boundary region when the IGBT structure is turned on. When the IGBT structure turns off, the holes injected into the boundary region drift layer move obliquely toward the p-type base layer in the IGBT region and are discharged through the p-type base layer. As a result, the time it takes for the holes to be discharged becomes longer, and there is a concern that switching losses will increase due to an increase in tail current.

[0006] This specification provides a technique for suppressing the increase in switching loss in a reverse-conducting IGBT having a boundary region between the IGBT region and the diode region. [Means for solving the problem]

[0007] The semiconductor devices (1, 2, 3) disclosed herein are of a type called a reverse-conducting IGBT, and may comprise a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, a lower electrode (22) provided on the lower surface of the semiconductor substrate, and an upper electrode (24) provided on the upper surface of the semiconductor substrate. The semiconductor substrate comprises a first-conductivity drift layer (13) provided across the IGBT region, the diode region, and the boundary region, a second-conductivity base layer (14) provided across the IGBT region, the diode region, and the boundary region and located above the drift layer, a first-conductivity emitter layer (15) provided in the IGBT region and located above the base layer and in contact with the upper electrode, and a layer provided in the IGBT region and located below the drift layer. The semiconductor substrate may include a collector layer (11) of a second conductivity type in contact with the lower electrode, a cathode layer (17) of a first conductivity type provided in the diode region, positioned below the drift layer, and in contact with the lower electrode, a first conductivity type boundary layer (18) of a first conductivity type provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode, and a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and positioned between the first conductivity type boundary layer and the drift layer. Here, "positioned above" and "positioned below" only specify the positional relationship between the two semiconductor layers in the vertical direction of the semiconductor substrate, and for example, the two semiconductor layers may be positioned in contact with each other, or other semiconductor layers may be interposed between the two semiconductor layers.

[0008] In the reverse-conducting IGBT described above, the first conductivity type boundary layer and the second conductivity type boundary layer are provided in the lower layer of the boundary region of the semiconductor substrate. Because the second conductivity type boundary layer is provided in the boundary region, the amount of carriers injected diagonally from the base layer of the IGBT region toward the cathode layer of the diode region is suppressed during recovery operation. Furthermore, because the first conductivity type boundary layer is provided in the boundary region, the amount of carriers injected into the drift layer of the boundary region is suppressed when the IGBT structure of the IGBT region is turned on. As a result, the increase in switching loss is suppressed in the reverse-conducting IGBT described above.

[0009] This specification discloses a method for manufacturing reverse-conducting IGBTs (1,2,3) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region. This manufacturing method may comprise a first ion implantation step of ion implanting a second conductivity type impurity into the lower layer of the semiconductor substrate corresponding to the IGBT region and the boundary region, and a second ion implantation step of ion implanting a first conductivity type impurity into the lower layer of the semiconductor substrate corresponding to the diode region and the boundary region. The second conductivity type impurity ion-implanted in the first ion implantation step and the first conductivity type impurity ion-implanted in the second ion implantation step may be adjusted such that the concentration of the first conductivity type impurity is higher than the concentration of the second conductivity type impurity on the side closer to the bottom surface of the semiconductor substrate, and the concentration of the second conductivity type impurity is higher than the concentration of the first conductivity type impurity on the side farther from the bottom surface of the semiconductor substrate.

[0010] According to the above manufacturing method, using two masks, namely the first mask and the second mask, a collector layer containing impurities of the second conductivity type is formed in the IGBT region of the semiconductor substrate, a collector layer containing impurities of the first conductivity type is formed in the diode region of the semiconductor substrate, a first conductivity type boundary layer is formed on the side closer to the lower surface in the boundary region of the semiconductor substrate, and a second conductivity type boundary layer can be formed on the side farther from the lower surface in the boundary region of the semiconductor substrate. The above manufacturing method can form a plurality of layers more than the number of masks.

Brief Description of the Drawings

[0011] [Figure 1] It is a plan view of the semiconductor device of the present embodiment, schematically showing a plan view for explaining the layout of the IGBT region, the diode region, and the boundary region. [Figure 2] It is a cross-sectional view of a main part including the IGBT region, the diode region, and the boundary region partitioned in the element region of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the line II-II in FIG. 1. [Figure 3] It shows the flow of the process of forming the collector layer, the cathode layer, the n-type boundary layer, and the p-type boundary layer in the manufacturing method of the semiconductor device of the present embodiment. [Figure 4] It is a cross-sectional view of a main part including the IGBT region, the diode region, and the boundary region partitioned in the element region of a modified example of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the line II-II in FIG. 1. [Figure 5] It is a cross-sectional view of a main part including the IGBT region, the diode region, and the boundary region partitioned in the element region of a modified example of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the line II-II in FIG. 1.

Embodiments for Carrying Out the Invention

[0012] Hereinafter, the semiconductor device of the present embodiment will be described with reference to the drawings. For the purpose of clarity in illustration, only one of the repeatedly arranged components is labeled with a reference numeral, and the labeling of the other components is omitted.

[0013] Figure 1 schematically shows a plan view of the semiconductor device 1 according to this embodiment. The semiconductor device 1 is a type of semiconductor device called a reverse-conducting IGBT and is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 has an element region 10A and a termination region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is divided into an IGBT region 102 where an IGBT structure is provided, a diode region 104 where a diode structure is provided, and a boundary region 106 located between the IGBT region 102 and the diode region 104. When viewed from a direction perpendicular to the upper surface of the semiconductor substrate 10 (hereinafter referred to as "when the semiconductor substrate 10 is viewed from above"), the IGBT region 102 and the diode region 104 are arranged alternately and repeatedly along the y direction within the element region 10A. A termination breakdown structure such as a guard ring is formed in the area of ​​the semiconductor substrate 10 corresponding to the termination region 10B. Furthermore, a plurality of small signal pads 26 are provided in the area of ​​the upper surface of the semiconductor substrate 10 corresponding to the termination region 10B. The small signal pad 26 may be, for example, a gate pad for inputting a gate signal, a temperature sense pad for outputting a temperature sense signal, or a current sense pad for outputting a current sense signal.

[0014] Figure 2 schematically shows a cross-sectional view of the main part corresponding to line II-II in Figure 1. As shown in Figure 2, the semiconductor device 1 comprises a semiconductor substrate 10 which is a silicon substrate, a collector electrode 22 (an example of a lower electrode) provided to cover the lower surface of the semiconductor substrate 10, an emitter electrode 24 (an example of an upper electrode) provided to cover the upper surface of the semiconductor substrate 10, a plurality of trench gates 30 provided in the upper part of the semiconductor substrate 10, and a plurality of dummy trench gates 40 provided in the upper part of the semiconductor substrate 10.

[0015] The semiconductor substrate 10 has a p-type collector layer 11, an n-type buffer layer 12, and n - A drift layer 13 of type p, a base layer 14 of type p, and multiple n + A type emitter layer 15 and multiple p+ A contact layer 16 of type n + It has a cathode layer 17 of type n, an n-type boundary layer 18 of type n, and a p-type boundary layer 19 of type p.

[0016] The collector layer 11 is provided in the lower part of the semiconductor substrate 10, in the area corresponding to the IGBT region 102, and is positioned to be exposed on the lower surface of the semiconductor substrate 10. The collector layer 11 is in ohmic contact with the collector electrode 22 that covers the lower surface of the semiconductor substrate 10. The collector layer 11 is formed by ion implantation of p-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The collector layer 11 is formed by multi-stage ion implantation and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurities contained in the collector layer 11 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 16 cm -3 ~1 × 10 18 cm -3 That's fine.

[0017] The buffer layer 12 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The buffer layer 12 is provided between the collector layer 11 and the drift layer 13 in the IGBT region 102, separates the collector layer 11 and the drift layer 13, has its lower surface in contact with the collector layer 11, and its upper surface in contact with the drift layer 13. The buffer layer 12 is provided between the p-type boundary layer 19 and the drift layer 13 in the boundary region 106, separates the p-type boundary layer 19 and the drift layer 13, has its lower surface in contact with the p-type boundary layer 19, and its upper surface in contact with the drift layer 13. The buffer layer 12 is provided between the cathode layer 17 and the drift layer 13 in the diode region 104, separates the cathode layer 17 and the drift layer 13, has its lower surface in contact with the cathode layer 17, and its upper surface in contact with the drift layer 13. The buffer layer 12 is a layer with a higher concentration of n-type impurities than the drift layer 13. The buffer layer 12 is formed by ion-implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, and for example, they may be phosphorus. The peak concentration of the n-type impurities contained in the buffer layer 12 is not particularly limited, and for example, it may be 1×10 15 cm -3 ~1×10 18 cm -3 or the like.

[0018] The drift layer 13 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The drift layer 13 is provided between the buffer layer 12 and the base layer 14, separates the buffer layer 12 and the base layer 14, has its lower surface in contact with the buffer layer 12, and its upper surface in contact with the base layer 14. The drift layer 13 is the remainder of the semiconductor substrate 10 where other semiconductor layers are formed. The peak concentration of the n-type impurities contained in the drift layer 13 is not particularly limited, and for example, it may be 1×10 13 cm -3 ~1×10 15 cm -3 or the like.

[0019] The base layer 14 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. In the IGBT region 102, the base layer 14 is provided between the drift layer 13, the emitter layer 15, and the contact layer 16, separating the drift layer 13 from the emitter layer 15 and the contact layer 16, with its lower surface in contact with the drift layer 13 and its upper surface in contact with the emitter layer 15 and the contact layer 16. In the boundary region 106 and the diode region 104, the base layer 14 is provided between the drift layer 13 and the contact layer 16, separating the drift layer 13 from the contact layer 16, with its lower surface in contact with the drift layer 13 and its upper surface in contact with the contact layer 16. The base layer 14 is formed by ion implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of p-type impurities in the base layer 14 is not particularly limited, but for example, 1 × 10⁻⁶ 15 cm -3 ~1 × 10 17 cm -3 That's fine.

[0020] In this example, the base layer 14 further comprises a first base layer 14a and a second base layer 14b. The first base layer 14a is the portion of the base layer 14 that corresponds to the IGBT region 102 of the semiconductor substrate 10. The second base layer 14b is the portion of the base layer 14 that corresponds to the diode region 104 and the boundary region 106 of the semiconductor substrate 10. The concentration of p-type impurities in the first base layer 14a is adjusted so that the gate threshold voltage of the trench gate 30 is a desired value. The concentration of p-type impurities in the second base layer 14b is adjusted to control the amount of holes injected during recovery operation. For this reason, the concentration of p-type impurities in the second base layer 14b is smaller than the concentration of p-type impurities in the first base layer 14a.

[0021] Each of the multiple emitter layers 15 is partially provided in the upper part of the semiconductor substrate 10 in a region corresponding to the IGBT region 102, and is positioned to be exposed on the upper surface of the semiconductor substrate 10. Each of the multiple emitter layers 15 is in contact with the side surface of the corresponding trench gate 30 and is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple emitter layers 15 is selectively formed in the IGBT region 102 of the semiconductor substrate 10, and is not formed in the diode region 104 and boundary region 106 of the semiconductor substrate 10. In other words, the region of the semiconductor substrate 10 in which the multiple emitter layers 15 are provided is the IGBT region 102. Each of the multiple emitter layers 15 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may be phosphorus, for example. The peak concentration of the n-type impurities contained in each of the multiple emitter layers 15 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 18 cm -3 ~1 × 10 20 cm -3 This may also be the case. In addition, in the technology disclosed herein, the layout of the plurality of emitter layers 15 formed on the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0022] Each of the multiple contact layers 16 is partially provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10, and is positioned to be exposed on the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is formed by ion implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurities contained in each of the multiple contact layers 16 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 17 cm -3 ~1 × 10 20 cm-3 This may also be the case. Furthermore, in the technology disclosed herein, the layout of the multiple contact layers 16 formed on the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0023] The cathode layer 17 is provided in the lower part of the semiconductor substrate 10 in the area corresponding to the diode region 104, and is positioned to be exposed on the lower surface of the semiconductor substrate 10. The cathode layer 17 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. The cathode layer 17 is selectively formed in the diode region 104 of the semiconductor substrate 10, and is not formed in the IGBT region 102 and the boundary region 106 of the semiconductor substrate 10. In other words, the area of ​​the semiconductor substrate 10 in which the cathode layer 17 is provided is the diode region 104. The cathode layer 17 is formed by ion implantation of n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The cathode layer 17 is formed by multi-stage ion implantation and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The n-type impurities are not particularly limited, but may be phosphorus, for example. The peak concentration of the n-type impurities contained in the cathode layer 17 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 18 cm -3 ~1 × 10 20 cm -3 That's fine.

[0024] The n-type boundary layer 18 is provided in the lower part of the semiconductor substrate 10, in the area corresponding to the boundary region 106, and is positioned to be exposed on the lower surface of the semiconductor substrate 10. The n-type boundary layer 18 has an end on the IGBT region 102 side that is in contact with the collector layer 11, and an end on the diode region 104 side that is in contact with the cathode layer 17. The n-type boundary layer 18 is provided between the collector electrode 22 and the p-type boundary layer 19, separating the collector electrode 22 and the p-type boundary layer 19, with its lower surface in contact with the collector electrode 22 and its upper surface in contact with the p-type boundary layer 19. The n-type boundary layer 18 is in ohmic contact with the collector electrode 22 that covers the lower surface of the semiconductor substrate 10. The n-type boundary layer 18 is formed by ion implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may be phosphorus, for example. The peak concentration of n-type impurities contained in the n-type boundary layer 18 is not particularly limited, but for example, 1 × 10⁻⁶ 18 cm -3 ~1 × 10 20 cm -3 That's fine.

[0025] The p-type boundary layer 19 is provided in the lower part of the semiconductor substrate 10, in the area corresponding to the boundary region 106. The p-type boundary layer 19 has its end on the IGBT region 102 side in contact with the collector layer 11, and its end on the diode region 104 side in contact with the cathode layer 17. The p-type boundary layer 19 is provided between the n-type boundary layer 18 and the buffer layer 12, separating the n-type boundary layer 18 and the buffer layer 12, with its lower surface in contact with the n-type boundary layer 18 and its upper surface in contact with the buffer layer 12. The p-type boundary layer 19 is formed by ion implanting p-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be boron, for example. The peak concentration of p-type impurities contained in the p-type boundary layer 19 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 16 cm -3 ~1 × 10 18 cm -3 That's fine.

[0026] Each of the multiple trench gates 30 is provided within a trench formed in the upper layer of the semiconductor substrate 10 in a region corresponding to the IGBT region 102, and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34 and insulated from the emitter electrode 24 by the interlayer insulating film. Each of the multiple trench gates 30 penetrates the base layer 14 from the upper surface of the semiconductor substrate 10 to reach the drift layer 13. In this example, each of the multiple trench gates 30 extends along the x-direction when the semiconductor substrate 10 is viewed from above, and is spaced apart from each other in the y-direction. That is, when the semiconductor substrate 10 is viewed from above, the multiple trench gates 30 are spaced apart from each other along the direction in which the IGBT region 102 and diode region 104 are repeatedly arranged, and have a striped layout. Instead of this example, the multiple trench gates 30 may have other types of layouts.

[0027] Each of the multiple dummy trench gates 40 is provided within a trench formed in the upper layer of the semiconductor substrate 10, in the area corresponding to the diode region 104 and the boundary region 106. The multiple dummy trench gates 40 are manufactured using the same process as the multiple trench gates 30, and differ from the trench gates 30 in that the interlayer insulating film that insulates the gate electrode 32 and the emitter electrode 24 has been removed. The multiple dummy trench gates 40 have the same layout as the multiple trench gates 30. The provision of such dummy trench gates 40 can mitigate electric field concentration in the diode region 104 and the boundary region 106.

[0028] The semiconductor device 1 can control the on / off state of the current flowing from the collector electrode 22 to the emitter electrode 24 in the IGBT region 102 based on the gate voltage applied to the gate electrode 32 of the trench gate 30. Furthermore, the semiconductor device 1 allows the diode structure formed in the diode region 104 to operate as a freewheeling diode during recovery operation.

[0029] During the recovery operation in which the diode structure is operating, if the amount of holes injected obliquely from the p-type base layer 14 of the IGBT region 102 to the n-type cathode layer 17 of the diode region 104 increases, the recovery current increases, and the recovery loss increases. In semiconductor device 1, a p-type boundary layer 19 is provided in the boundary region 106, so the distance between the p-type base layer 14 of the IGBT region 102 and the n-type cathode layer 17 of the diode region 104 becomes longer. Therefore, the amount of holes injected obliquely during the recovery operation is suppressed, and the recovery current is suppressed. Thus, semiconductor device 1 can have characteristics of low recovery loss.

[0030] The width of the boundary region 106, measured along the direction connecting the IGBT region 102 and the diode region 104, is adjusted to a size necessary to suppress the amount of holes injected in the oblique direction. The width of the boundary region 106 is not particularly limited, but may be, for example, 0.5 μm or more, preferably 1.0 μm or more. The width of the boundary region 106 may also be greater than the width between adjacent dummy trench gates 40 (i.e., the pitch width of the dummy trench gates 40). Alternatively, the width of the boundary region 106 may be greater than the substrate thickness of the semiconductor substrate 10. In order to reduce area consumption, the width of the boundary region 106 may also be less than twice the substrate thickness of the semiconductor substrate 10.

[0031] Now, consider the case where the boundary region 106 does not have an n-type boundary layer 18, but only a p-type boundary layer 19. In this case, when the IGBT structure is on, holes are injected from the p-type boundary layer 19 of the boundary region 106 towards the n-type drift layer 13 of the boundary region 106. When the IGBT structure turns off, the holes injected into the drift layer 13 move diagonally toward the p-type base layer 14 of the IGBT region 102 and are discharged through the p-type base layer 14. As a result, the time until the holes are discharged becomes longer, and the switching loss increases due to the increase in tail current.

[0032] In semiconductor device 1, an n-type boundary layer 18 is provided in the boundary region 106. The n-type boundary layer 18 is provided between the collector electrode 22 and the p-type boundary layer 19, separating the collector electrode 22 from the p-type boundary layer 19. Therefore, when the IGBT structure is turned on, the amount of holes injected from the p-type boundary layer 19 in the boundary region 106 toward the n-type drift layer 13 is suppressed. Consequently, semiconductor device 1 can have characteristics of low switching loss.

[0033] Next, referring to Figure 3, the steps for forming the collector layer 11, cathode layer 17, n-type boundary layer 18, and p-type boundary layer 19 in the manufacturing method of the semiconductor device 1 will be described. For steps other than those described below in the manufacturing method of the semiconductor device 1, known steps can be used.

[0034] First, a first mask is deposited on the underside of the semiconductor substrate 10 using photolithography technology (see step S1). The first mask covers the diode region 104 on the underside of the semiconductor substrate 10, while having openings that expose the IGBT region 102 and the boundary region 106.

[0035] Next, using ion implantation technology, p-type impurities are ion-implanted into the lower layer of the semiconductor substrate 10, specifically in the area corresponding to the IGBT region 102 and the boundary region 106, passing through the opening of the first mask (see step S2). The p-type impurities are implanted from the bottom surface of the semiconductor substrate 10 to a first depth. The first mask is removed after ion implantation.

[0036] Next, a second mask is deposited on the underside of the semiconductor substrate 10 using photolithography technology (see step S3). The second mask covers the IGBT region 102 on the underside of the semiconductor substrate 10, while having openings that expose the diode region 104 and the boundary region 106.

[0037] Next, using ion implantation technology, n-type impurities are ion-implanted into the lower layer of the semiconductor substrate 10, corresponding to the diode region 104 and the boundary region 106, through the opening of the second mask (see step S4). The n-type impurities are implanted to a second depth from the bottom surface of the semiconductor substrate 10. Comparing the first depth in step S2 with the second depth in step S4, the second depth is shallower than the first depth. The second mask is removed after ion implantation.

[0038] Next, laser annealing is performed by irradiating the lower surface of the semiconductor substrate 10 with a laser (see step S5). This activates the p-type and n-type impurities introduced into the lower layer of the semiconductor substrate 10. Through these steps, the collector layer 11, cathode layer 17, n-type boundary layer 18, and p-type boundary layer 19 can be formed in the lower layer of the semiconductor substrate 10. Note that steps S1 and S2 may be performed after steps S3 and S4.

[0039] According to this manufacturing method, both n-type and p-type impurities are injected into the area corresponding to the boundary region 106 in the lower part of the semiconductor substrate 10. The p-type impurities are injected at a relatively deeper first depth, and the n-type impurities are injected at a relatively shallower second depth. The peak concentration of the p-type impurities at the first depth is greater than the concentration of the n-type impurities at the first depth. The peak concentration of the n-type impurities at the second depth is greater than the concentration of the p-type impurities at the second depth. Laser annealing can activate the injected impurities without causing significant diffusion. Therefore, the concentration distribution of the n-type and p-type impurities after activation can be maintained as described above. As a result, an n-type boundary layer 18 is formed on the side closer to the bottom surface of the semiconductor substrate 10 in the boundary region 106 of the semiconductor substrate 10, and a p-type boundary layer 19 is formed on the side further from the bottom surface of the semiconductor substrate 10.

[0040] According to the above manufacturing method, using two masks, a first mask and a second mask, a collector layer 11 containing p-type impurities can be formed in the IGBT region 102 of the semiconductor substrate 10, a cathode layer 17 containing n-type impurities can be formed in the diode region 104 of the semiconductor substrate 10, and a stack of an n-type boundary layer 18 and a p-type boundary layer 19 can be formed in the boundary region 106 of the semiconductor substrate 10. The above manufacturing method can form more layers than the number of masks.

[0041] In the above manufacturing method, p-type impurities are simultaneously ion-implanted through a first mask into the IGBT region 102 and the boundary region 106 of the lower layer of the semiconductor substrate 10. Therefore, the distribution of p-type impurities in the thickness direction of the semiconductor substrate 10 is the same in the portion where the n-type boundary layer 18 and the p-type boundary layer 19 are stacked and in the collector layer 11. Similarly, in the above manufacturing method, n-type impurities are simultaneously ion-implanted through a second mask into the diode region 104 and the boundary region 106 of the lower layer of the semiconductor substrate 10. Therefore, the distribution of n-type impurities in the thickness direction of the semiconductor substrate 10 is the same in the portion where the n-type boundary layer 18 and the p-type boundary layer 19 are stacked and in the cathode layer 17. Such concentration distributions are one of the characteristics of applying the above manufacturing method.

[0042] Furthermore, in the above manufacturing method, n-type and p-type impurities are injected into the boundary region 106 of the lower layer of the semiconductor substrate 10. The portion with a relatively high concentration of p-type impurities becomes the p-type boundary layer 19, and the portion with a relatively high concentration of n-type impurities becomes the n-type boundary layer 18. Therefore, the effective peak concentration of n-type impurities in the n-type boundary layer 18 is smaller than the effective peak concentration of n-type impurities in the cathode layer 17. Similarly, the effective peak concentration of p-type impurities in the p-type boundary layer 19 is smaller than the effective peak concentration of p-type impurities in the collector layer 11. This relationship between the effective peak concentrations of impurities is one of the characteristics of applying the above manufacturing method. In addition, in the above manufacturing method, the depth of the upper surface of the collector layer 11 coincides with the depth of the upper surface of the p-type boundary layer 19. This positional relationship is also one of the characteristics of applying the above manufacturing method.

[0043] In the above manufacturing method, p-type impurities and n-type impurities were introduced into the lower layer of the semiconductor substrate 10 by a single ion implantation. Alternatively, p-type impurities and n-type impurities may be introduced into the lower layer of the semiconductor substrate 10 by multiple ion implantations, so that the layer into which p-type impurities are introduced and the layer into which n-type impurities are introduced form multi-stage diffusion layers. In this case, in the layer into which p-type impurities are introduced, the concentration of p-type impurities may be adjusted so that it is higher than the concentration of n-type impurities in the stages furthest from the lower surface of the semiconductor substrate 10, and in the layer into which n-type impurities are introduced, the concentration of n-type impurities may be adjusted so that it is higher than the concentration of p-type impurities in the stages closer to the lower surface of the semiconductor substrate 10. With this manufacturing method as well, a stack of an n-type boundary layer 18 and a p-type boundary layer 19 can be formed in the boundary region 106 of the semiconductor substrate 10.

[0044] The semiconductor device 1 described above can be modified as follows. In the semiconductor device 2 shown in Figure 4, the n-type boundary layer 18 and the p-type boundary layer 19 are stacked and extend from the boundary between the IGBT region 102 and the boundary region 106 into the IGBT region 102 side. The length of the stack of the n-type boundary layer 18 and the p-type boundary layer 19 extending from the boundary between the IGBT region 102 and the boundary region 106 into the IGBT region 102 side may be a length that allows for manufacturing variations. Similarly, the stack of the n-type boundary layer 18 and the p-type boundary layer 19 may be formed recessed from the boundary between the IGBT region 102 and the boundary region 106 into the boundary region 106 side. In either case, the semiconductor device 2 can achieve the same effects as the semiconductor device 1.

[0045] The semiconductor device 3 shown in Figure 5 is characterized by having an n-type barrier layer 21 within the semiconductor substrate 10. The barrier layer 21 is provided over the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The barrier layer 21 is embedded in the base layer 14, dividing the base layer 14 into upper and lower sections. The barrier layer 21 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may be phosphorus, for example. The effective peak concentration of n-type impurities in the barrier layer 21 may be smaller than the effective peak concentration of p-type impurities in the second base layer 14b. With such a barrier layer 21 provided, hole injection from the base layer 14 can be suppressed during recovery operation. Therefore, the semiconductor device 3 can have low recovery loss characteristics.

[0046] The following summarizes the features of the technology disclosed in this specification. Note that each of the technical elements described below is an independent technical element, and exhibits technical usefulness either individually or in various combinations.

[0047] (Feature 1) Reverse conduction IGBT(1,2,3), A semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, The lower electrode (22) provided on the lower surface of the semiconductor substrate, The semiconductor substrate is provided with an upper electrode (24) on its upper surface, The aforementioned semiconductor substrate is A first-conductivity drift layer (13) is provided across the IGBT region, the diode region, and the boundary region, A second conductivity type base layer (14) is provided extending across the IGBT region, the diode region, and the boundary region, and is positioned above the drift layer. A first conductivity type emitter layer (15) is provided in the IGBT region, positioned above the base layer, and in contact with the upper electrode, A second conductivity type collector layer (11) is provided in the IGBT region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type cathode layer (17) is provided in the diode region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type boundary layer (18) of a first conductivity type is provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode, A reverse-conducting IGBT comprising a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and positioned between the first conductivity type boundary layer and the drift layer.

[0048] (Feature 2) The distribution of the first conductivity type impurity in the thickness direction of the semiconductor substrate is the same in the laminated portion of the first conductivity type boundary layer and the second conductivity type boundary layer and in the cathode layer. The reverse-conducting IGBT according to Feature 1, wherein the distribution of second conductivity type impurities in the thickness direction of the semiconductor substrate is the same in the laminated portion of the first conductivity type boundary layer and the second conductivity type boundary layer and in the collector layer.

[0049] (Feature 3) The aforementioned base layer is The IGBT region includes a first base layer (14a), It has a second base layer (14b) provided in the diode region and the boundary region, The reverse-conducting IGBT according to feature 1 or 2, wherein the concentration of the second conductivity type impurity in the second base layer is smaller than the concentration of the second conductivity type impurity in the first base layer.

[0050] (Feature 4) The aforementioned semiconductor substrate is A reverse conducting IGBT according to any one of features 1 to 3, further comprising a first-conductivity type barrier layer (21) provided across the IGBT region, the diode region, and the boundary region, and embedded in the base layer.

[0051] (Feature 5) The aforementioned semiconductor substrate is The IGBT region, the diode region, and the boundary region are provided, and the first conductivity type buffer layer (12) is further provided between the collector layer, the cathode layer, the second conductivity type boundary layer, and the drift layer. A reverse-conducting IGBT according to any one of features 1 to 4, wherein the concentration of the first conductivity type impurity in the buffer layer is higher than the concentration of the first conductivity type impurity in the drift layer.

[0052] (Feature 6) The reverse conducting IGBT according to any one of features 1 to 5, further comprising a trench gate (30) provided in the IGBT region and located within a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

[0053] (Feature 7) The reverse conducting IGBT according to any one of features 1 to 6, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, and provided in a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

[0054] (Feature 8) A method for manufacturing reverse-conducting IGBTs (1,2,3) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, A first ion implantation step involves ion implanting a second conductivity type impurity into the lower layer of the semiconductor substrate, specifically in the lower layer corresponding to the IGBT region and the boundary region. The system includes a second ion implantation step of implanting a first conductivity type impurity into the lower layer of the semiconductor substrate that corresponds to the diode region and the boundary region, A method for manufacturing a reverse-conducting IGBT, wherein the second conductivity type impurity implanted in the first ion implantation step and the first conductivity type impurity implanted in the second ion implantation step are adjusted such that the concentration of the first conductivity type impurity is higher than the concentration of the second conductivity type impurity on the side closer to the bottom surface of the semiconductor substrate, and the concentration of the second conductivity type impurity is higher than the concentration of the first conductivity type impurity on the side further from the bottom surface of the semiconductor substrate.

[0055] (Feature 9) In the first ion implantation step, a second conductivity type impurity is ion-implanted from the lower surface of the semiconductor substrate to a first depth. In the second ion implantation step, a first conductivity type impurity is ion-implanted from the lower surface of the semiconductor substrate to a second depth. The method for manufacturing a reverse-conducting IGBT according to feature 8, wherein the second depth is shallower than the first depth.

[0056] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of symbols]

[0057] 10: Semiconductor substrate, 11: Collector layer, 12: Buffer layer, 13: Drift layer, 14: Base layer, 14a: First base layer, 14b: Second base layer, 15: Emitter layer, 16: Contact layer, 17: Cathode layer, 18: n-type boundary layer, 19: p-type boundary layer, 22: Collector electrode, 24: Emitter electrode, 30: Trench gate, 32: Gate electrode, 34: Gate insulating film, 40: Dummy trench gate, 102: IGBT region, 104: Diode region, 106: Boundary region

Claims

1. Reverse conducting IGBTs (1, 2, 3), A semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, The lower electrode (22) provided on the lower surface of the semiconductor substrate, The semiconductor substrate is provided with an upper electrode (24) on its upper surface, The aforementioned semiconductor substrate is A first-conductivity drift layer (13) is provided across the IGBT region, the diode region, and the boundary region, A second conductivity type base layer (14) is provided extending across the IGBT region, the diode region, and the boundary region, and is positioned above the drift layer. A first conductivity type emitter layer (15) is provided in the IGBT region, positioned above the base layer, and in contact with the upper electrode, A second conductivity type collector layer (11) is provided in the IGBT region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type cathode layer (17) is provided in the diode region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type boundary layer (18) of a first conductivity type is provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode, A reverse-conducting IGBT having a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and positioned between the first conductivity type boundary layer and the drift layer.

2. The distribution of the first conductivity type impurity in the thickness direction of the semiconductor substrate is the same in the portion where the first conductivity type boundary layer and the second conductivity type boundary layer are stacked and in the cathode layer. The reverse-conducting IGBT according to claim 1, wherein the distribution of second conductivity type impurities in the thickness direction of the semiconductor substrate is the same in the laminated portion of the first conductivity type boundary layer and the second conductivity type boundary layer and in the collector layer.

3. The aforementioned base layer is The IGBT region includes a first base layer (14a), The diode region and the boundary region are provided with a second base layer (14b), The reverse-conducting IGBT according to claim 1, wherein the concentration of the second conductivity type impurity in the second base layer is smaller than the concentration of the second conductivity type impurity in the first base layer.

4. The aforementioned semiconductor substrate is The reverse conducting IGBT according to claim 1, further comprising a first conductivity type barrier layer (21) provided across the IGBT region, the diode region, and the boundary region, and embedded in the base layer.

5. The aforementioned semiconductor substrate is The device further comprises a first conductivity type buffer layer (12) provided across the IGBT region, the diode region, and the boundary region, and positioned between each of the collector layer, the cathode layer, the second conductivity type boundary layer, and the drift layer. The reverse conducting IGBT according to claim 1, wherein the concentration of the first conductivity type impurity in the buffer layer is higher than the concentration of the first conductivity type impurity in the drift layer.

6. The reverse conducting IGBT according to claim 1, further comprising a trench gate (30) provided in the IGBT region and located within a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

7. The reverse conducting IGBT according to claim 1, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, and located in a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

8. A method for manufacturing reverse-conducting IGBTs (1, 2, 3) comprising a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, A first ion implantation step involves implanting a second conductivity type impurity into the lower layer of the semiconductor substrate, specifically in the lower layer corresponding to the IGBT region and the boundary region. The system includes a second ion implantation step of implanting a first conductivity type impurity into the lower layer of the semiconductor substrate corresponding to the diode region and the boundary region, A method for manufacturing a reverse-conducting IGBT, wherein the second conductivity type impurity implanted in the first ion implantation step and the first conductivity type impurity implanted in the second ion implantation step are adjusted such that the concentration of the first conductivity type impurity is higher than the concentration of the second conductivity type impurity on the side closer to the bottom surface of the semiconductor substrate, and the concentration of the second conductivity type impurity is higher than the concentration of the first conductivity type impurity on the side further from the bottom surface of the semiconductor substrate.

9. In the first ion implantation step, a second conductivity type impurity is ion-implanted from the lower surface of the semiconductor substrate to a first depth. In the second ion implantation step, a first conductivity type impurity is ion-implanted from the lower surface of the semiconductor substrate to a second depth. The method for manufacturing a reverse-conducting IGBT according to claim 8, wherein the second depth is shallower than the first depth.

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