Semiconductor equipment

Abstract

To provide semiconductor devices with improved reliability. [Solution] The semiconductor device 100 includes a semiconductor layer 101 having a main surface 101a, a main surface electrode 102 disposed on the main surface 101a, an insulating film 104 that partially covers the main surface electrode 102 so as to expose a part of the main surface electrode 102, a mold layer 106 that covers the insulating film 104 so as to expose the main surface electrode 102, and a pad electrode 105 disposed on the main surface electrode 102 so as to be electrically connected to the main surface electrode 102.

Description

[Technical Field]

[0001] This application corresponds to Japanese Patent Application No. 2020-082728, filed with the Japan Patent Office on 8 May 2020, and the full disclosure of this application is incorporated herein by reference. The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses technology relating to a vertical semiconductor device using a SiC semiconductor substrate. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2012-79945 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] One embodiment of the present invention provides a semiconductor device with improved reliability. [Means for solving the problem]

[0005] One embodiment of the present invention provides a semiconductor device comprising: a semiconductor layer having a first main surface and a second main surface facing away from the first main surface; a first electrode layer formed on the first main surface; a second electrode layer formed on the second main surface; an insulating film covering the edge of the first electrode layer; a plating layer covering at least a portion of the first electrode layer other than the edge; and a mold layer covering the insulating film.

[0006] One embodiment of the present invention provides a method of manufacturing a semiconductor device, including: forming a first electrode layer on a first main surface of a semiconductor layer; forming a second electrode layer on a second main surface of the semiconductor layer, which faces away from the first main surface; forming an insulating film covering an end portion of the first electrode layer; forming a plating layer covering at least a part of the first electrode layer other than the end portion; and forming a mold layer covering the insulating film.

[0007] One embodiment of the present invention provides a semiconductor device, including: a semiconductor layer having a main surface; a main surface electrode disposed on the main surface; an insulating film partially covering the main surface electrode so as to expose a part of the main surface electrode; a mold layer covering the insulating film so as to expose the main surface electrode; and a pad electrode disposed on the main surface electrode so as to be electrically connected to the main surface electrode.

[0008] One embodiment of the present invention provides a semiconductor device, including: a semiconductor layer having a main surface; a main surface electrode disposed on the main surface; a photosensitive resin layer covering a peripheral portion of the main surface electrode so as to expose an inner portion of the main surface electrode; a thermosetting resin layer covering the peripheral portion of the main surface electrode with the photosensitive resin layer interposed therebetween so as to expose the inner portion of the main surface electrode; and a pad electrode disposed on the inner portion of the main surface electrode.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1. [Figure 3] FIG. 3 is a view showing a detailed configuration of an outer peripheral portion of the semiconductor device shown in FIG. 1. [Figure 4] FIG. 4 is a view showing a detailed configuration of a semiconductor layer of the semiconductor device shown in FIG. 1. [Figure 5A] FIG. 5A is a first cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 1. [Figure 5B] FIG. 5B is a second cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG. 1. [Figure 5C] Figure 5C is a third cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1. [Figure 5D] Figure 5D is a fourth cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1. [Figure 5E] Figure 5E is a fifth cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1. [Figure 5F] Figure 5F is a sixth cross-sectional view showing the method of manufacturing the semiconductor device shown in FIG. 1. [Figure 6] FIG. 6 is a plan view of a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor device shown in FIG. 8. [Figure 8] FIG. 8 is a view showing a detailed configuration of an outer peripheral portion of the semiconductor device shown in FIG. 8. [Figure 9] FIG. 9 is a view showing an example of a semiconductor package according to the third embodiment. [Figure 10] FIG. 10 is a view showing an example of the semiconductor package shown in FIG. 9. [Figure 11] FIG. 11 is a view showing another example of the semiconductor package according to the third embodiment. [Figure 12] FIG. 12 is a cross-sectional view of a semiconductor device having a structure in which a nickel layer is formed on a plating layer. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device including a two-layer plating layer. [Figure 14] FIG. 14 is a plan view of a semiconductor device according to a modified example. [Figure 15A] FIG. 15A is a first cross-sectional view showing a dicing process according to a modified example. [Figure 15B] FIG. 15B is a second cross-sectional view showing a dicing process according to a modified example. [Figure 15C] FIG. 15C is a third cross-sectional view showing a dicing process according to a modified example. [Figure 16A] FIG. 16A is a first cross-sectional view showing a dicing process according to another modified example. [Figure 16B]Figure 16B is a second cross-sectional view showing the dicing process for another modified example. [Figure 16C] Figure 16C is a third cross-sectional view showing the dicing process for another modified example. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be specifically described below with reference to the attached drawings. The embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement positions of components, connection configurations of components, steps, and the order of steps shown in the following embodiments are examples and are not intended to limit the present invention. Components in the following embodiments that are not described in an independent claim will be described as optional components.

[0011] Each attached drawing is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale in the attached drawings may not necessarily match. In the attached drawings, substantially identical components are denoted by the same reference numerals, and redundant explanations are omitted or simplified.

[0012] In this specification, terms indicating relationships between elements such as vertical and horizontal, terms indicating the shape of elements such as rectangles, and numerical ranges are expressions that do not represent only strict meanings but also include substantially equivalent ranges.

[0013] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Specifically, in this specification, the first main surface side of one semiconductor layer is described as the upper side (upper), and the second main surface side of the other is described as the lower side (lower). In actual use of a semiconductor device (vertical transistor), the first main surface side may be the lower side (lower), and the second main surface side may be the upper side (upper). Alternatively, the semiconductor device (vertical transistor) may be used in an orientation where the first and second main surfaces are inclined or perpendicular to the horizontal plane.

[0014] Furthermore, the terms “above” and “below” apply when two components are spaced apart from each other with another component interposed between them, as well as when two components are placed in close proximity to each other.

[0015] The configuration of the semiconductor device according to the first embodiment will be described below. Figure 1 is a plan view of the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view of the semiconductor device shown in Figure 1 (cross-sectional view along line II-II in Figure 1).

[0016] The semiconductor device 100 shown in Figure 1 is a semiconductor chip that functions as a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor). The semiconductor device 100 is a power semiconductor device used, for example, for power supply and control. Specifically, the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, an insulating film 104, a plating layer 105, and a mold layer 106.

[0017] The semiconductor layer 101 is a SiC semiconductor layer containing a SiC (silicon carbide) single crystal as an example of a wide-bandgap semiconductor. The semiconductor layer 101 is formed in a rectangular plate shape in plan view. In this specification, "plan view" means viewing from a direction perpendicular to the first main surface 101a or the second main surface 101b (viewing from the z-axis direction in the figure). The length of one side of the semiconductor layer 101 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0018] The semiconductor layer 101 has a first main surface 101a and a second main surface 101b facing away from the first main surface 101a. The semiconductor layer 101 also includes a semiconductor substrate 101c that constitutes the second main surface 101b, and an epitaxial layer 101d located on the semiconductor substrate 101c. The epitaxial layer 101d is obtained by epitaxial growth of the semiconductor substrate 101c.

[0019] The thickness of the semiconductor substrate 101c is, for example, 100 μm or more and 350 μm or less. The thickness of the epitaxial layer 101d is, for example, 5 μm or more and 20 μm or less. The thickness t1 of the semiconductor layer 101 (i.e., the total thickness of the semiconductor substrate 101c and the epitaxial layer 101d) is preferably 200 μm or less. The semiconductor layer 101 is not limited to a SiC semiconductor layer, but may also be a semiconductor layer made of other wide-bandgap semiconductors such as GaN, or it may be a Si semiconductor layer.

[0020] The first electrode layer 102 is formed on the first main surface 101a. The first electrode layer 102 may also be referred to as the "first main surface electrode". The first electrode layer 102 includes a first electrode layer 102g that functions as a gate electrode and a first electrode layer 102s that functions as a source electrode. The first electrode layer 102 is formed of, for example, aluminum. The first electrode layer 102 may also be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, or tungsten.

[0021] The first electrode layer 102s may have an area of ​​50% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the first electrode layer 102s may have an area of ​​70% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. On the other hand, the first electrode layer 102g may have an area of ​​20% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the first electrode layer 102g may have an area of ​​10% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view.

[0022] The first electrode layer 102s is located in a region that includes the center of the semiconductor substrate 101c in a plan view. The first electrode layer 102g is located in a region that avoids the first electrode layer 102s. However, the first electrode layer 102g may be located in a region that includes the center of the semiconductor substrate 101c in a plan view, and the first electrode layer 102s may be located around the first electrode layer 102g.

[0023] The second electrode layer 103 is formed on the second main surface 101b. The second electrode layer 103 may also be referred to as the "second main surface electrode". The second electrode layer 103 functions as a drain electrode. The second electrode layer 103 is formed, for example, by a laminated film of titanium, nickel, and gold. The second electrode layer 103 may also be formed by other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0024] The insulating film 104 covers the entire periphery of the first electrode layer 102 (i.e., both ends in the x-axis direction and both ends in the y-axis direction). The periphery of the first electrode layer 102 may also be referred to as the peripheral edge of the first electrode layer 102. The insulating film 104 includes a first portion 104a and a second portion 104b. The first portion 104a overlaps the first electrode layer 102. More specifically, the first portion 104a overlaps the peripheral edge of the first electrode layer 102. The second portion 104b is located outside the first portion 104a and covers the area other than the first electrode layer 102. In other words, the second portion 104b does not overlap the first electrode layer 102.

[0025] The first portion 104a further includes an inner end 104a1 and a flat portion 104a2. The inner end 104a1 is the end of the portion of the first portion 104a located on the inner side of the semiconductor layer 101 in a plan view. In a cross-sectional view, the inner end 104a1 slopes downward at an angle toward the inner part of the first electrode layer 102. The flat portion 104a2 is located outside the inner end 104a1 (on the peripheral side of the semiconductor layer 101) and has a substantially uniform thickness.

[0026] The insulating film 104 is, for example, an organic film containing a photosensitive resin. The insulating film 104 is formed from, for example, polyimide, PBO (polybenzoxazole), etc. The insulating film 104 may also be an inorganic film formed from, for example, silicon nitride (SiN), silicon oxide (SiO2), etc. The insulating film 104 may have a single-layer structure or a multilayer structure in which multiple types of materials are stacked. If the insulating film 104 has a multilayer structure, the insulating film 104 may contain both an organic film and an inorganic film. In this case, it is preferable that the insulating film 104 contains an inorganic film and an organic film stacked in this order from the first main surface 101a side. The thickness of the insulating film 104 is at most about 10 μm.

[0027] The plating layer 105 is a metallic layer that covers at least a portion of the first electrode layer 102. The plating layer 105 covers at least a portion of the first electrode layer 102, excluding the edges (i.e., the portion covered by the insulating film 104). As shown in Figure 1, in plan view, the plating layer 105 is surrounded by the mold layer 106. The plating layer 105 includes the plating layer 105 on the first electrode layer 102g side (first plating layer) and the plating layer 105 on the first electrode layer 102s side (second plating layer).

[0028] The plating layer 105 formed on the first electrode layer 102g functions as a gate pad (pad electrode) with a rectangular shape in plan view. The plating layer 105 formed on the first electrode layer 102s functions as a source pad (pad electrode). A pad is the part to which bonding wires are joined when the semiconductor device 100 is packaged. The plating layer 105 also functions as a support member for the mold layer 106.

[0029] The plating layer 105 is formed of a different material than the first electrode layer 102, for example. The plating layer 105 is formed of copper or a copper alloy with copper as the main component. The plating layer 105 may be formed of other metallic materials. The thickness t2 of the plating layer 105 is greater than the thickness of the insulating film 104. More specifically, the thickness t2 of the plating layer 105 is greater than the maximum thickness of the insulating film 104 located on the first electrode layer 102. As a result, the top of the plating layer 105 is higher than the top of the insulating film 104. The thickness t2 of the plating layer 105 is, for example, 30 μm or more and 100 μm or less. The thickness t2 of the plating layer 105 may be 100 μm or more and 200 μm or less.

[0030] The side surface 105a of the plating layer 105 extends vertically or substantially vertically. The side surface 105a does not necessarily have to extend in a straight line in cross-sectional view, but may include curves or irregularities. The side surface 105a is located in the region where both the first electrode layer 102 and the insulating film 104 overlap each other. More specifically, the side surface 105a is located on the flat portion 104a2 of the insulating film 104. In other words, the plating layer 105 covers the inner end portion 104a1 and the flat portion 104a2 of the first portion 104a. By positioning the side surface 105a on the flat portion 104a2, the plating layer 105 can be formed more stably compared to when the side surface 105a is located on the inner end portion 104a1, which has relatively large variations in thickness.

[0031] The mold layer 106 is a resin layer that covers at least a portion of the insulating film 104. In this embodiment, the mold layer 106 also covers a portion of the first main surface 101a. The mold layer 106 is located on the outer periphery of the semiconductor layer 101 on the side of the first main surface 101a. The outer periphery of the semiconductor layer 101 (first main surface 101a) may also be referred to as the peripheral edge of the semiconductor layer 101 (first main surface 101a).

[0032] In a plan view, the mold layer 106 is a rectangular annular shape that follows the outer periphery of the semiconductor layer 101. The mold layer 106 is also located between the gate pad (plating layer 105 on the first electrode layer 102g) and the source pad (plating layer 105 on the first electrode layer 102s). In other words, the mold layer 106 is formed only on the first main surface 101a of the semiconductor layer 101, exposing the second main surface 101b and the side surfaces of the semiconductor layer 101.

[0033] The inner surface of the mold layer 106 is in direct contact with the side surface 105a of the plating layer 105. The inner surface of the mold layer 106 includes the inner surface on the side of the first electrode layer 102g (first inner surface) and the inner surface on the side of the first electrode layer 102s (second inner surface). The mold layer 106 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon and glass fibers, etc. The thickness t3 of the mold layer 106 is, for example, 30 μm or more and 100 μm or less. The thickness t3 of the mold layer 106 may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 106 and the upper surface of the plating layer 105 are flush or substantially flush.

[0034] The source pad may have an area of ​​50% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the source pad may have an area of ​​70% or more of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. On the other hand, the gate pad may have an area of ​​20% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view. Preferably, the gate pad may have an area of ​​10% or less of the area of ​​the semiconductor substrate 101c (first main surface 101a) in a plan view.

[0035] The source pad is located in a region that includes the center of the semiconductor substrate 101c in a plan view. The gate pad is located in a region that avoids the source pad. However, the gate pad may be located in a region that includes the center of the semiconductor substrate 101c in a plan view, and the source pad may be located so as to surround the gate pad.

[0036] Next, the detailed configuration of the outer periphery (in other words, the edge) of the semiconductor device 100 will be described. Figure 3 is a diagram showing the detailed configuration of the outer periphery of the semiconductor device 100 (a cross-sectional view showing the details of region III in Figure 2). In Figure 3, in addition to the first electrode layer 102s, the gate finger 102a and the outer periphery source contact 102b are also shown.

[0037] The edges of the first electrode layer 102s are covered by an insulating film 104. Specifically, the insulating film 104 includes a first insulating film 104c located on the first electrode layer 102s and a second insulating film 104d located on the first insulating film 104c. The first insulating film 104c is an inorganic film formed from silicon nitride, silicon oxide, etc. The second insulating film 104d is an organic film formed from polyimide, PBO, etc.

[0038] Furthermore, the insulating film 104 includes a third insulating film 104e located beneath the outer peripheral source contact 102b. More specifically, the third insulating film 104e is located between the outer peripheral source contact 102b and the semiconductor layer 101. The third insulating film 104e is an inorganic film formed from silicon nitride, silicon oxide, or the like.

[0039] In typical semiconductor devices, such an insulating film 104 is provided to suppress the intrusion of moisture into the edges of the first electrode layer 102s and the occurrence of ion migration. However, when durability tests are conducted in high-temperature and high-humidity environments, or reliability tests such as temperature cycling tests are performed, the insulating film 104 may deteriorate, potentially allowing moisture to intrude through the deteriorated areas or causing ion migration at those areas. In other words, deterioration of the insulating film 104 can cause failure of the semiconductor device.

[0040] Therefore, in the semiconductor device 100, the insulating film 104 is further covered with a mold layer 106. This suppresses the degradation of the insulating film 104 and improves the reliability of the semiconductor device 100.

[0041] The edges of the first electrode layer 102s, the gate finger 102a, and the outer peripheral source contact 102b are basically covered by the first insulating film 104c. However, in the example shown in Figure 3, the outermost edges of the first electrode layer 102s, the gate finger 102a, and the outer peripheral source contact 102b are covered by the second insulating film 104d, and the first insulating film 104c is omitted. This configuration relieves stress.

[0042] Next, the detailed structure of the semiconductor layer 101 will be described. Figure 4 shows the detailed configuration of the semiconductor layer 101. In Figure 4, the semiconductor layer 101 is not shaded to represent a cross-section for the sake of readability. As shown in Figures 3 and 4, the semiconductor layer 101 specifically includes a semiconductor substrate 101c and an epitaxial layer 101d.

[0043] The semiconductor device 100 shown in Figure 4 is an example of a switching device and includes a vertical transistor 2. The vertical transistor 2 is, for example, a vertical MISFET. As shown in Figure 4, the semiconductor device 100 includes a semiconductor layer 101, a gate electrode 20, a source electrode 30, and a drain electrode 40. The drain electrode 40 corresponds to a second electrode layer 103.

[0044] The semiconductor layer 101 includes a semiconductor layer 101 mainly composed of SiC (silicon carbide). Specifically, the semiconductor layer 101 is an n-type SiC semiconductor layer containing a SiC single crystal. The SiC single crystal is, for example, a 4H-SiC single crystal.

[0045] A 4H-SiC single crystal has an off-angle that is tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane. The off-angle may be between 0° and 4°. The off-angle may be greater than 0° and less than 4°. The off-angle may be set to, for example, 2° or 4°, in the range of 2°±0.2° or 4°±0.4°.

[0046] The semiconductor layer 101 is formed in the shape of a rectangular parallelepiped chip. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b. The semiconductor layer 101 has a semiconductor substrate 101c and an epitaxial layer 101d. The semiconductor substrate 101c contains a SiC single crystal. The lower surface of the semiconductor substrate 101c is the second main surface 101b. This second main surface 101b is the carbon surface (000-1) surface where the carbon of the SiC crystal is exposed. The epitaxial layer 101d is laminated on the upper surface of the semiconductor substrate 101c and contains an n - This is a SiC semiconductor layer of type 101d. The upper surface of the epitaxial layer 101d is the first main surface 101a. This first main surface 101a is the silicon surface (0001) where the silicon of the SiC crystal is exposed.

[0047] A drain electrode 40 is connected to the second main surface 101b of the semiconductor layer 101. The semiconductor substrate 101c is n + It is provided as a drain region of type n -It is provided as a drain drift region of the type.

[0048] The n-type impurity concentration of the semiconductor substrate 101c is, for example, 1.0×10 18 cm -3 or more and 1.0×10 21 cm -3 or less. The n-type impurity concentration of the epitaxial layer 101d is lower than the n-type impurity concentration of the semiconductor substrate 101c, for example, 1.0×10 15 cm -3 or more and 1.0×10 17 cm -3 or less. In this specification, "impurity concentration" means the peak value of the impurity concentration.

[0049] As shown in FIG. 4, the epitaxial layer 101d of the semiconductor layer 101 includes a deep well region 15, a body region 16, a source region 17, and a contact region 18.

[0050] The deep well region 15 is formed in a region along the source trench 32 in the semiconductor layer 101. The deep well region 15 is also referred to as a breakdown voltage holding region. The deep well region 15 is a p - -type semiconductor region. The p-type impurity concentration of the deep well region 15 is, for example, 1.0×10 17 cm -3 or more and 1.0×10 19 cm -3 or less. The p-type impurity concentration of the deep well region 15 is, for example, higher than the n-type impurity concentration of the epitaxial layer 101d.

[0051] The deep well region 15 includes a side wall portion 15a along the side wall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32. The thickness (length in the z-axis direction) of the bottom wall portion 15b is, for example, equal to or greater than the thickness (length in the x-axis direction) of the side wall portion 15a. At least a part of the bottom wall portion 15b may be located within the semiconductor substrate 101c.

[0052] The body region 16 is provided on the surface portion of the first main surface 101a of the semiconductor layer 101. - This is a semiconductor region of a certain type. In a plan view, the body region 16 is located between the gate trench 22 and the source trench 32. In a plan view, the body region 16 is located in a strip shape extending along the y-axis. The body region 16 is connected to the deep well region 15.

[0053] The p-type impurity concentration in body region 16 is, for example, 1.0 × 10⁻⁶. 16 cm -3 The above 1.0 × 10 19 cm -3 The following applies: The p-type impurity concentration in the body region 16 may be equal to that of the impurity region in the deep well region 15. The p-type impurity concentration in the body region 16 may be higher than that of the deep well region 15.

[0054] The source region 17 is provided on the surface portion of the first main surface 101a of the semiconductor layer 101. + This is a semiconductor region of type 16. The source region 17 is part of the body region 16. The source region 17 is located in the region along the gate trench 22. The source region 17 is in contact with the gate insulating layer 23.

[0055] The source region 17 is provided in a strip shape extending along the y-axis in a plan view. The width (length in the x-axis direction) of the source region 17 is, for example, 0.2 μm or more and 0.6 μm or less. As an example, the width of the source region 17 may be about 0.4 μm. The n-type impurity concentration in the source region 17 is, for example, 1.0 × 10⁻⁶ 18 cm -3 The above 1.0 × 10 21 cm -3 The following applies:

[0056] The contact region 18 is provided on the surface portion of the first main surface 101a of the semiconductor layer 101. +This is a semiconductor region of the type. The contact region 18 may be considered as part of the body region 16 (high-concentration region). The contact region 18 is located in a region along the source trench 32. The contact region 18 is in contact with the barrier forming layer 33. The contact region 18 is also connected to the source region 17.

[0057] The contact region 18 is provided in a strip shape extending along the y-axis in a plan view. The width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 μm or more and 0.4 μm or less. As an example, the width of the contact region 18 may be about 0.2 μm. The p-type impurity concentration in the contact region 18 is, for example, 1.0 × 10⁻⁶. 18 cm -3 The above 1.0 × 10 21 cm -3 The following applies:

[0058] Multiple trench gate structures 21 and multiple trench source structures 31 are provided on the first main surface 101a of the semiconductor layer 101. The trench gate structures 21 and trench source structures 31 are provided alternately one at a time along the x-axis. In Figure 4, only the area where one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.

[0059] Both the trench gate structure 21 and the trench source structure 31 are provided in a strip shape extending along the y-axis direction. For example, the x-axis direction is the [11-20] direction and the y-axis direction is the [1-100] direction. The x-axis direction may also be the [1-100] direction ([-1100] direction). In this case, the y-axis direction may also be the [11-20] direction.

[0060] The trench gate structures 21 and trench source structures 31 are arranged alternately along the x-axis, forming a stripe structure in plan view. The distance between the trench gate structures 21 and trench source structures 31 is, for example, between 0.3 μm and 1.0 μm.

[0061] The trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20, as shown in Figure 4.

[0062] The gate trench 22 is formed by excavating the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b. The gate trench 22 is an elongated groove-shaped recess with a rectangular cross-sectional shape in the xz cross-section and extending along the y-axis direction. The gate trench 22 has a length on the order of millimeters in the longitudinal direction (y-axis direction). For example, the gate trench 22 has a length of 1 mm to 10 mm. The length of the gate trench 22 may be 2 mm to 5 mm. The total length of one or more gate trenches 22 per unit area may be 0.5 μm / μm² to 0.75 μm / μm².

[0063] The gate insulating layer 23 is provided in a film-like manner along the side walls 22a and bottom wall 22b of the gate trench 22. The gate insulating layer 23 defines a concave space inside the gate trench 22. The gate insulating layer 23 contains, for example, silicon oxide. The gate insulating layer 23 may contain at least one of the following: impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

[0064] The thickness of the gate insulating layer 23 is, for example, 0.01 μm or more and 0.5 μm or less. The thickness of the gate insulating layer 23 may be uniform or may vary depending on the location. For example, the gate insulating layer 23 includes a side wall portion 23a along the side wall 22a of the gate trench 22, and a bottom wall portion 23b along the bottom wall 22b of the gate trench 22. The thickness of the bottom wall portion 23b may be greater than the thickness of the side wall portion 23a. The thickness of the bottom wall portion 23b is, for example, 0.01 μm or more and 0.2 μm or less. The thickness of the side wall portion 23a is, for example, 0.05 μm or more and 0.5 μm or less. The gate insulating layer 23 may also include a top surface portion provided on the upper surface of the source region 17 outside the gate trench 22. The thickness of the top surface portion may be greater than the thickness of the side wall portion 23a.

[0065] The gate electrode 20 is an example of a control electrode for the vertical transistor 2. The gate electrode 20 is embedded in the gate trench 22. A gate insulating layer 23 is provided between the gate electrode 20 and the side walls 22a and bottom wall 22b of the gate trench 22. In other words, the gate electrode 20 is embedded in a concave space partitioned by the gate insulating layer 23. The gate electrode 20 is, for example, a conductive layer containing conductive polysilicon. The gate electrode 20 may contain at least one of the following: a metal such as titanium, nickel, copper, aluminum, silver, gold, or tungsten, or a conductive metal nitride such as titanium nitride.

[0066] The aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21. The aspect ratio of the trench gate structure 21 is, for example, the same as the aspect ratio of the gate trench 22. The aspect ratio of the trench gate structure 21 is, for example, between 0.25 and 15.0. The width of the trench gate structure 21 is, for example, between 0.2 μm and 2.0 μm. As an example, the width of the trench gate structure 21 may be about 0.4 μm. The depth of the trench gate structure 21 is, for example, between 0.5 μm and 3.0 μm. As an example, the depth of the trench gate structure 21 may be about 1.0 μm.

[0067] The trench source structure 31 includes a deep well region 15, a source trench 32, a barrier forming layer 33, and a source electrode 30, as shown in Figure 4.

[0068] The source trench 32 is formed by excavating the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b. The source trench 32 has a rectangular cross-sectional shape in the xz section and is an elongated groove-like recess extending along the y-axis. The source trench 32 is deeper than, for example, the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located toward the second main surface 101b than the bottom wall 22b of the gate trench 22.

[0069] The barrier-forming layer 33 is provided in a film-like manner along the side walls 32a and bottom wall 32b of the source trench 32. The barrier-forming layer 33 partitions a concave space within the source trench 32. The barrier-forming layer 33 is formed using a different material than the source electrode 30. The barrier-forming layer 33 has a higher potential barrier than the potential barrier between the source electrode 30 and the deep well region 15.

[0070] The barrier-forming layer 33 is an insulating barrier-forming layer. In this case, the barrier-forming layer 33 contains at least one of the following: impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The barrier-forming layer 33 may be formed using the same material as the gate insulating layer 23. In this case, the barrier-forming layer 33 may have the same film thickness as the gate insulating layer 23.

[0071] For example, if the barrier forming layer 33 and the gate insulating layer 23 are formed using silicon oxide, they can be formed simultaneously by a thermal oxidation treatment method. The barrier forming layer 33 may be a conductive barrier forming layer. In this case, the barrier forming layer 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt, or molybdenum.

[0072] The source electrode 30 is embedded in the source trench 32. A barrier forming layer 33 is provided between the source electrode 30 and the side wall 32a and bottom wall 32b of the source trench 32. In other words, the source electrode 30 is embedded in a concave space partitioned by the barrier forming layer 33.

[0073] The source electrode 30 is, for example, a conductive layer containing conductive polysilicon. The source electrode 30 may be n-type polysilicon with n-type impurities added, or p-type polysilicon with p-type impurities added. The source electrode 30 may contain at least one of the following: a metal such as titanium, nickel, copper, aluminum, silver, gold, or tungsten, or a conductive metal nitride such as titanium nitride. The source electrode 30 may be formed using the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 can be formed in the same process.

[0074] The aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31. The width of the trench source structure 31 is, for example, the sum of the width of the source trench 32 and the width of the sidewall portions 15a of the deep well regions 15 located on both sides of the source trench 32. The width of the trench source structure 31 is, for example, between 0.6 μm and 2.4 μm.

[0075] For example, the width of the trench source structure 31 may be about 0.8 μm. The depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15. The depth of the trench source structure 31 is, for example, 1.5 μm or more and 11 μm or less. For example, the depth of the trench source structure 31 may be about 2.5 μm.

[0076] The aspect ratio of the trench source structure 31 is greater than the aspect ratio of the trench gate structure 21. For example, the aspect ratio of the trench source structure 31 is between 1.5 and 4.0. By increasing the depth of the trench source structure 31, the pressure-resistant effect of the superjunction (SJ) structure can be enhanced.

[0077] The drain electrode 40 corresponds to the second electrode layer 103. The drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold, or silver. For example, the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer stacked in order from the second main surface 101b of the semiconductor layer 101. The drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer stacked in order from the second main surface 101b of the semiconductor layer 101. The AlCu layer is an alloy layer of aluminum and copper.

[0078] The drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer stacked in order from the second main surface 101b of the semiconductor layer 101. The AlSiCu layer is an alloy layer of aluminum, silicon, and copper. The drain electrode 40 may also include a single-layer structure consisting of a TiN layer instead of a Ti layer, or a stacked structure including a Ti layer and a TiN layer.

[0079] The semiconductor device 100 configured as described above can switch between an ON state, where drain current flows, and an OFF state, where no drain current flows, depending on the gate voltage applied to the gate electrode 20 of the vertical transistor 2. The gate voltage is, for example, a voltage of 10V to 50V. As an example, the gate voltage may be 30V. The source voltage applied to the source electrode 30 is a reference voltage, such as the ground voltage (0V). The drain voltage applied to the drain electrode 40 is a voltage greater than or equal to the source voltage. The drain voltage is, for example, a voltage of 0V to 10000V. The drain voltage may be a voltage of 1000V or greater.

[0080] When a gate voltage is applied to the gate electrode 20, p -A channel is formed in the portion of the body region 16 of the type that is in contact with the gate insulating layer 23. This creates a current path from the source electrode 30 through the contact region 18, source region 17, the channel in the body region 16, the epitaxial layer 101d, and the semiconductor substrate 101c to the drain electrode 40. Since the drain electrode 40 is at a higher potential than the source electrode 30, the drain current flows from the drain electrode 40 through the semiconductor substrate 101c, the epitaxial layer 101d, the channel in the body region 16, the source region 17, and the contact region 18 to the source electrode 30. In this way, the drain current flows along the thickness direction of the semiconductor device 100.

[0081] p - Type deep well regions 15 and n - A pn junction is formed between the epitaxial layers 101d of type A. When the vertical transistor 2 is ON, p - A source voltage is applied to the deep well region 15 of the type via the source electrode 30, n - A drain voltage greater than the source voltage is applied to the epitaxial layer 101d of the type via the drain electrode 40.

[0082] In other words, a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 101d. Since the n-type impurity concentration in the epitaxial layer 101d is lower than the p-type impurity concentration in the deep well region 15, the depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 101d toward the drain electrode 40. This increases the breakdown voltage of the vertical transistor 2.

[0083] The source electrode 30 is electrically connected to the first electrode layer 102s provided on the source electrode 30. The gate electrode 20 is insulated from the first electrode layer 102s by an insulating layer 61 and is electrically connected to the first electrode layer 102g via a gate finger (for example, the gate finger 102a in Figure 3) provided above the outer periphery of the semiconductor layer 101. The insulating layer 61 mainly consists of silicon oxide or silicon nitride, for example.

[0084] Next, a method for manufacturing the semiconductor device 100 will be described. Figures 5A to 5F are cross-sectional views showing the manufacturing method of the semiconductor device 100. First, as shown in Figure 5A, a semiconductor layer 101 is formed, and a first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101. Various existing methods can be used for forming the semiconductor layer 101. The first electrode layer 102 is formed, for example, by sputtering or vapor deposition.

[0085] Next, as shown in Figure 5B, the outer periphery of the first electrode layer 102 is covered with an insulating film 104. The insulating film 104 is formed, for example, through a coating process and an exposure and development process. In the coating process, a liquid photosensitive resin material, which will become the insulating film 104, is applied to the first electrode layer 102 by a spin coating method. In the exposure and development process, after the photosensitive resin material is cured by exposure, any unwanted portions of the photosensitive resin material are removed by methods such as ashing or wet etching. This forms the insulating film 104.

[0086] Next, as shown in Figure 5C, a plating layer 105 is formed on the first electrode layer 102. The plating layer 105 is formed on the first electrode layer 102, for example, by electroplating or electroless plating. The plating layer 105 is selectively formed on at least a portion of the portion of the first electrode layer 102 that is not covered by the insulating film 104.

[0087] Next, as shown in Figure 5D, a liquid resin material 106a (for example, a thermosetting resin) that will form the mold layer 106 is applied or printed over the entire surface of the first main surface 101a of the semiconductor layer 101. As a result, the insulating film 104 and the plating layer 105 are covered with the resin material 106a. The resin material 106a also penetrates between the plating layer 105 on the first electrode layer 102g and the plating layer 105 on the first electrode layer 102s. The applied or printed resin material 106a is cured, for example, by heating.

[0088] Next, as shown in Figure 5E, the upper surface (surface) of the resin material 106a is ground until the plating layer 105 is exposed. As a result, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 become flush. In other words, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 consist of continuous ground surfaces.

[0089] Next, as shown in Figure 5F, a second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101. The second electrode layer 103 is formed, for example, by sputtering or vapor deposition. Finally, the wafer is cut along the scribe line SL by a dicing blade, thereby separating the wafer into individual pieces. The dicing blade cuts the semiconductor layer 101 and the mold layer 106 simultaneously. As a result, the side surfaces of the semiconductor layer 101 and the mold layer 106 become flush. In other words, the side surfaces of the semiconductor layer 101 and the mold layer 106 consist of connected ground surfaces. As a result, a semiconductor device 100 as shown in Figure 2 is obtained.

[0090] The second electrode layer 103 may be formed on the second main surface 101b of the semiconductor layer 101 at the stage shown in Figure 5A. The lower surface of the second electrode layer 103, the upper surface of the plating layer 105, the side surface of the plating layer 105, and the upper surface of the mold layer 106 constitute the outer surface of the semiconductor device 100 (chip).

[0091] Next, the configuration of the semiconductor device according to the second embodiment will be described. Figure 6 is a plan view of the semiconductor device shown in Figure 8. Figure 7 is a cross-sectional view of the semiconductor device shown in Figure 8 (a cross-sectional view along line VII-VII in Figure 6).

[0092] The semiconductor device 200 shown in Figure 8 is a semiconductor chip that functions as a vertical Schottky barrier diode by utilizing the Schottky barrier created by the junction of the semiconductor layer 201 and the first electrode layer 202. The semiconductor device 200 is a power semiconductor device used, for example, for power supply and control. Specifically, the semiconductor device 200 includes a semiconductor layer 201, a first electrode layer 202, a second electrode layer 203, an insulating film 204, a plating layer 205, and a mold layer 206.

[0093] The semiconductor layer 201 is a SiC semiconductor layer containing a SiC (silicon carbide) single crystal as an example of a wide-bandgap semiconductor. In the semiconductor device 200, the entire semiconductor layer 201 corresponds to the semiconductor substrate (for example, semiconductor substrate 101c). The conductivity type of the semiconductor layer 201 is, for example, n-type. The semiconductor layer 201 is formed in the shape of a rectangular plate in plan view. The length of one side of the semiconductor layer 201 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.

[0094] The semiconductor layer 201 has a first main surface 201a and a second main surface 201b facing away from the first main surface 201a. The thickness t4 of the semiconductor layer 201 (semiconductor substrate) is, for example, 100 μm or more and 350 μm or less. Preferably, the thickness t4 of the semiconductor layer 201 is 200 μm or less. The semiconductor layer 201 is not limited to a SiC semiconductor layer, but may be a semiconductor layer made of other wide bandgap semiconductors such as GaN, or it may be a Si semiconductor layer. Of course, the semiconductor layer 201 may have a stacked structure including the aforementioned semiconductor substrate 101c and the aforementioned epitaxial layer 101d.

[0095] The first electrode layer 202 is formed on the first main surface 201a. The first electrode layer 202 functions as the anode of the Schottky barrier diode. The first electrode layer 202 is formed of, for example, aluminum. The first electrode layer 202 may also be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, or tungsten.

[0096] The second electrode layer 203 is formed on the second main surface 201b. The second electrode layer 203 functions as the cathode of the Schottky barrier diode. The second electrode layer 203 is formed by, for example, a multilayer film of titanium, nickel, and gold. The second electrode layer 203 may also be formed by other materials such as aluminum, copper, silver, titanium nitride, and tungsten.

[0097] The insulating film 204 covers the entire periphery of the first electrode layer 202 (i.e., both ends in the X-axis direction and both ends in the Y-axis direction). The insulating film 204 includes a first portion 204a and a second portion 204b. The first portion 204a overlaps the first electrode layer 202. More specifically, the first portion 204a overlaps the periphery of the first electrode layer 202. The second portion 204b is located outside the first portion 204a and covers the area other than the first electrode layer 202. In other words, the second portion 204b does not overlap the first electrode layer 202.

[0098] The first portion 204a further includes an inner end 204a1 and a flat portion 204a2. The inner end 204a1 is the end of the portion of the first portion 204a located on the inner side of the semiconductor layer 201 in a plan view. In a cross-sectional view, the inner end 204a1 slopes downward at an angle toward the inner part of the first electrode layer 202. The flat portion 104a2 is located outside the inner end 204a1 (on the peripheral side of the semiconductor layer 101) and has a substantially uniform thickness.

[0099] The insulating film 204 is, for example, an organic film containing a photosensitive resin. The insulating film 204 is formed from, for example, polyimide, PBO (polybenzoxazole), etc. The insulating film 204 may also be an inorganic film formed from silicon nitride, silicon oxide, etc. The insulating film 204 may have a single-layer structure or a laminated structure in which multiple types of materials are stacked. If the insulating film 204 has a laminated structure, the insulating film 204 may contain both an organic film and an inorganic film. In this case, it is preferable that the insulating film 204 contains an inorganic film and an organic film stacked in this order from the first main surface 201a side. The thickness of the insulating film 204 is at most about 10 μm.

[0100] The plating layer 205 is a metallic layer that covers at least a portion of the first electrode layer 202. The plating layer 205 covers at least a portion of the first electrode layer 202, excluding the edges (i.e., the portion covered by the insulating film 204). As shown in Figure 6, in plan view, the plating layer 205 is surrounded by the mold layer 206. The plating layer 205 formed on the first electrode layer 202 functions as a rectangular pad in plan view. The pad is the portion to which bonding wires are joined when the semiconductor device 200 is packaged. The plating layer 205 also functions as a support member for the mold layer 206.

[0101] The plating layer 205 is formed of a different material than the first electrode layer 202, for example. The plating layer 205 is formed of copper or a copper alloy with copper as the main component. The plating layer 205 may be formed of other metallic materials. The thickness t5 of the plating layer 205 is greater than the thickness of the insulating film 204. More specifically, the thickness t5 of the plating layer 205 is greater than the maximum thickness of the insulating film 204 located on the first electrode layer 202. As a result, the top of the plating layer 205 is higher than the top of the insulating film 204. The thickness t5 of the plating layer 205 is, for example, 30 μm or more and 100 μm or less. The thickness t5 of the plating layer 205 may be 100 μm or more and 200 μm or less.

[0102] The side surface 205a of the plating layer 205 extends vertically or substantially vertically. The side surface 205a does not necessarily have to extend in a straight line in cross-sectional view, but may include curves or irregularities. The side surface 205a is located in the region where both the first electrode layer 202 and the insulating film 204 overlap each other. More specifically, the side surface 205a is located on the flat portion 204a2 of the insulating film 204. In other words, the plating layer 205 covers the inner end portion 204a1 and the flat portion 204a2 of the first portion 204a. By positioning the side surface 205a on the flat portion 204a2, the plating layer 205 can be formed more stably compared to when the side surface 205a is located on the inner end portion 204a1, which has relatively large variations in thickness.

[0103] The mold layer 206 is a resin layer that covers a portion of the insulating film 204. In this configuration, the mold layer 206 also covers a portion of the first main surface 201a. The mold layer 206 is located on the outer periphery of the semiconductor layer 201 on the side of the first main surface 201a. In plan view, the mold layer 206 is a rectangular annular shape along the outer periphery of the semiconductor layer 201. The inner surface of the mold layer 206 is in direct contact with the side surface 205a of the plating layer 205. The mold layer 206 is formed only on the first main surface 201a of the semiconductor layer 201, exposing the second main surface 201b and the side surface of the semiconductor layer 201.

[0104] The mold layer 206 is formed of, for example, a thermosetting resin (epoxy resin). The mold layer 106 may be formed of an epoxy resin containing carbon and glass fibers. The thickness t6 of the mold layer 206 is, for example, 30 μm or more and 100 μm or less, but may be 100 μm or more and 200 μm or less. The upper surface of the mold layer 206 and the upper surface of the plating layer 205 are flush or substantially flush.

[0105] Next, the detailed configuration of the outer periphery (in other words, the edge) of the semiconductor device 200 will be described. Figure 8 is a diagram showing the detailed configuration of the outer periphery of the semiconductor device 200 (a cross-sectional view showing the details of region VIII in Figure 7).

[0106] The edges of the first electrode layer 202 are covered by an insulating film 204. Specifically, the insulating film 204 includes a first insulating film 204c located on the first electrode layer 202, a second insulating film 204d located on the first insulating film 204c, and a third insulating film 204e located below the first electrode layer 202. More specifically, the third insulating film 204e is located between the first electrode layer 202 and the semiconductor layer 201. The first insulating film 204c is an inorganic film formed from silicon nitride, silicon oxide, etc. The second insulating film 204d is an organic film formed from polyimide, PBO, etc. The third insulating film 204e is an inorganic film formed from silicon nitride, silicon oxide, etc.

[0107] In typical semiconductor devices, such an insulating film 204 is provided to suppress the intrusion of moisture into the edges of the first electrode layer 202 and the occurrence of ion migration. However, if durability tests or reliability tests such as temperature cycling tests are performed in high-temperature and high-humidity environments, the insulating film 204 may deteriorate, potentially allowing moisture to intrude through the deteriorated areas or causing ion migration at those areas. In other words, deterioration of the insulating film 204 can cause failure of the semiconductor device.

[0108] Therefore, in the semiconductor device 200, the insulating film 204 is further covered with a mold layer 206. This suppresses the degradation of the insulating film 204 and improves the reliability of the semiconductor device 200. As shown in Figure 8, the outermost edge of the first electrode layer 202 is covered with the second insulating film 204d, and the first insulating film 204c is omitted. This configuration relieves stress. The manufacturing method of the semiconductor device 200 is the same as that of the semiconductor device 100, so a detailed explanation of the manufacturing method of the semiconductor device 200 is omitted.

[0109] In a third embodiment, a semiconductor package having a semiconductor device is described. Figures 9 and 10 show an example of a semiconductor package according to the third embodiment. Figure 10 shows the internal structure of the semiconductor package 300 shown in Figure 9, viewed from the opposite side from Figure 9.

[0110] The semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package. The semiconductor package 300 includes a package body 301, terminals 302d, 302g, 302s, bonding wires 303g, bonding wires 303s, and semiconductor device 100.

[0111] The package body 301 is rectangular in shape, with terminals 302d, 302g, and 302s protruding from its bottom. The package body 301 also contains the semiconductor device 100. In other words, the package body 301 is a encapsulant that seals the semiconductor device 100. The package body 301 is formed of, for example, epoxy resin. The package body 301 may also be formed of epoxy resin containing carbon and glass fibers.

[0112] Each of the terminals 302d, 302g, and 302s protrudes from the bottom of the package body 301 and is arranged in a row. Each of the terminals 302d, 302g, and 302s is formed of, for example, aluminum. Each of the terminals 302d, 302g, and 302s may be formed of another metallic material such as copper.

[0113] Inside the package body 301, the gate pad (plating layer 105 on the first electrode layer 102g) included in the semiconductor device 100 is electrically connected to the terminal 302g by a bonding wire 303g. The source pad (plating layer 105 on the first electrode layer 102s) included in the semiconductor device 100 is electrically connected to the terminal 302s by a bonding wire 303s. The drain electrode (second electrode layer 103) included in the semiconductor device 100 is joined to the wide portion of the terminal 302d located inside the package body 301 by solder or a sintered layer made of silver or copper.

[0114] The semiconductor package 300 may include a semiconductor device 200 instead of the semiconductor device 100. In this case, the semiconductor package 300 includes two terminals, and within the package body 301, the anode (first electrode layer 202) included in the semiconductor device 200 is electrically connected to one of the two terminals by a bonding wire or the like, and the cathode (second electrode layer 203) is joined to the wider portion located within the package body 401 on the other of the two terminals by solder or a sintered layer made of silver or copper.

[0115] The semiconductor package 300 described above, by including the semiconductor device 100 (or semiconductor device 200), has higher reliability than a package that includes a general semiconductor device.

[0116] Next, another example of a semiconductor package according to the third embodiment will be described. Figure 11 shows another example of a semiconductor package according to the third embodiment. The semiconductor package 400 shown in Figure 11 is a so-called DIP (Dual In-line Package) type semiconductor package. The semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 100.

[0117] The package body 401 is rectangular in shape, and multiple terminals 402 protrude from it. The package body 401 also contains the semiconductor device 100. In other words, the package body 401 is a encapsulant that seals the semiconductor device 100. The package body 401 is formed from, for example, an epoxy resin containing carbon and glass fibers.

[0118] Multiple terminals 402 are arranged in a line along the long side of the package body 401. Each of the multiple terminals 402 is formed of, for example, aluminum. Each of the multiple terminals 402 may be formed of another metallic material such as copper.

[0119] Inside the package body 401, the gate pad (plating layer 105 on the first electrode layer 102g), source pad (plating layer 105 on the first electrode layer 102s), and drain electrode (second electrode layer 103) included in the semiconductor device 100 are each electrically connected to the corresponding terminal 402 by bonding wires or the like. The semiconductor package 400 may contain multiple semiconductor devices 100. In other words, the package body 401 may contain multiple semiconductor devices 100.

[0120] Furthermore, the semiconductor package 400 may include a semiconductor device 200 in place of, or in addition to, the semiconductor device 100. In this case, within the package body 401, the anode (first electrode layer 202) and cathode (second electrode layer 203) included in the semiconductor device 200 are electrically connected to the corresponding terminals 402 by bonding wires or the like.

[0121] The semiconductor package 400 described above, by including the semiconductor device 100 (or semiconductor device 200), has higher reliability than a package that includes a general semiconductor device.

[0122] As described above, bonding wires are used for the electrical connection between the terminals included in the semiconductor package 300 or semiconductor package 400 and the semiconductor device 100 (or semiconductor device 200). When the bonding wire is made of aluminum, it is preferable that a nickel layer is formed on the plating layer 105, as shown in Figure 12. Figure 12 is a cross-sectional view of a semiconductor device 100 having a structure in which a nickel layer is formed on the plating layer 105.

[0123] In Figure 12, bonding wires 303g and 303s are also shown as examples of bonding wires. Nickel layer 107 is an example of a metal layer formed from a different metal material than the metal material forming the plating layer 105. Although not shown, a nickel layer may also be formed on the plating layer 205 of the semiconductor device 200 in a similar manner.

[0124] Furthermore, as shown in Figure 13, the plating layer 105 may consist of a first plating layer 1051 made of copper and a second plating layer 1052 made of nickel. Figure 13 is a cross-sectional view of a semiconductor device 100 including a two-layer plating structure. This eliminates the need to form an additional nickel layer as in the example in Figure 12. In the example in Figure 13, the upper surface of the second plating layer 1052 and the upper surface of the mold layer are flush.

[0125] Furthermore, in the examples shown in Figures 12 and 13, a nickel layer is formed on the outermost surface of the plating layer 105, which is the joint portion with the bonding wire made of aluminum. However, other layer configurations may be formed on the outermost surface of the plating layer 105 instead of a nickel layer. For example, the outermost surface of the plating layer 105 may be a two-layer structure (i.e., a NiPd layer) in which a palladium layer is formed on top of a nickel layer.

[0126] Furthermore, the outermost surface of the plating layer 105 may be a three-layer structure (for example, a NiPdAu layer) in which another metal layer is formed on top of the palladium layer. Such NiPd and NiPdAu layers are suitable not only when a bonding wire is joined to the plating layer 105 which functions as a source pad, but also when an external terminal is joined to the plating layer 105 which functions as a source pad by silver sintering.

[0127] The form of the semiconductor package containing the semiconductor device 100 (or semiconductor device 200) is not limited to forms such as semiconductor package 300 and semiconductor package 400. The semiconductor package may be an SOP (Small Outline Package), QFN (Quad Flat Non-Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package). Furthermore, various other semiconductor packages similar to these may be used.

[0128] As described above, the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, a plating layer 105, and a mold layer 106. The semiconductor layer 101 has a first main surface 101a and a second main surface 101b facing away from the first main surface 101a. The first electrode layer 102 is formed on the first main surface 101a. The second electrode layer 103 is formed on the second main surface 101b. The insulating film 104 covers the edge of the first electrode layer 102. The plating layer 105 covers at least a portion of the first electrode layer 102 other than the edge. The mold layer 106 covers the insulating film 104.

[0129] In this semiconductor device 100, the insulating film 104 covering the edge of the first electrode layer 102 is further covered with a mold layer 106, which suppresses the degradation of the insulating film 104. In other words, the semiconductor device 100 is a semiconductor device with improved reliability.

[0130] For example, in a plan view, the mold layer 106 is annular along the outer periphery of the semiconductor layer 101. Such a semiconductor device 100 has improved reliability because the outer periphery of the semiconductor layer 101 is covered with the mold layer 106. For example, the surface of the plating layer 105 and the surface of the mold layer 106 are flush. Such a semiconductor device 100 can be manufactured by applying or printing a resin material 106a to the first main surface 101a side of the semiconductor layer 101, and then grinding until the plating layer 105 is exposed.

[0131] For example, the plating layer 105 and the mold layer 106 are in direct contact. In such a semiconductor device 100, the plating layer 105 can be used as a support for the mold layer 106. For example, the semiconductor layer 101 is formed of SiC. Such a semiconductor device 100 can obtain a relatively high dielectric breakdown field strength.

[0132] For example, the semiconductor device 100 may function as a transistor. In this case, the second electrode layer 103 may be the drain electrode of the transistor. In this case, the first electrode layer 102 may include the source electrode and the gate electrode of the transistor. In the first electrode layer 102, the gate electrode is insulated from the source electrode. Such a semiconductor device 100 can function as a transistor.

[0133] For example, the semiconductor device 200 functions as a Schottky barrier diode with the first electrode layer 202 as the anode and the second electrode layer 203 as the cathode. Such a semiconductor device 100 can function as a Schottky barrier diode. For example, the side surface of the semiconductor layer 101 and the side surface of the molding layer 106 are flush. Such a semiconductor device 100 can be manufactured by simultaneously cutting the semiconductor layer 101 and the molding layer 106.

[0134] For example, a nickel layer 107 made of a different metal material than the metal material forming the plating layer 105 is formed on the surface of the plating layer 105. The nickel layer 107 is an example of a metal layer. In such a semiconductor device 100, bonding wires can be easily joined because a nickel layer 107 suitable for bonding wires is formed on the surface of the plating layer 105.

[0135] The method for manufacturing the semiconductor device 100 includes first to fifth steps. In the first step, a first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101. In the second step, a second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101, which is opposite to the first main surface 101a. In the third step, an insulating film 104 is formed to cover the edges of the first electrode layer 102. In the fourth step, a plating layer 105 is formed to cover at least a portion of the first electrode layer 102 other than the edges. In the fifth step, a mold layer 106 is formed to cover the insulating film 104. According to this manufacturing method, a semiconductor device 100 with improved reliability can be manufactured.

[0136] For example, the fifth step of forming a mold layer 106 that covers the insulating film 104 includes the steps of forming the mold layer 106 so as to cover the plating layer 105, and grinding the surface of the mold layer 106 so as to expose the plating layer 105. According to this manufacturing method, the semiconductor device 100 can be manufactured by grinding the surface of the mold layer 106 until the plating layer 105 is exposed.

[0137] In the above embodiment, an example of a semiconductor device (semiconductor device 100) was described in which a plating layer 105 functioning as a gate pad and a plating layer 105 functioning as a source pad are provided on the upper surface. Here, the semiconductor device may further include a plating layer 105 functioning as a pad for current sensing and a plating layer 105 functioning as a pad for temperature sensing. Figure 14 is a plan view of a semiconductor device according to one modified example having such a structure.

[0138] As shown in Figure 14, the semiconductor device 100a includes a gate pad 105g (a plating layer 105 that functions as a gate pad; the same applies hereafter) and a source pad 105s, as well as a current sensing pad 105c (pad electrode) and a pair of temperature sensing pads 105t (pad electrodes).

[0139] The semiconductor device 100a includes a first electrode layer 102s having a plurality of isolated portions that are separated from each other. The current sensing pad 105c is a plating layer connected to an isolated portion (isolated portion) of the first electrode layer 102s included in the semiconductor device 100a. When current flows between the source pad 105s and the second electrode layer 103 included in the semiconductor device 100a, a current smaller than the above current flows between the current sensing pad 105c and the second electrode layer 103. By monitoring such a current, an increase in current can be detected.

[0140] The semiconductor device 100a includes a diode (temperature-sensitive diode) provided on the first main surface 101a of the semiconductor layer 101. One of a pair of temperature-sensing pads 105t is a plating layer electrically connected to the anode of the diode (temperature-sensing diode) included in the semiconductor device 100a. The other of the pair of temperature-sensing pads 105t is a plating layer electrically connected to the cathode of the diode (temperature-sensing diode). The temperature of the semiconductor device 100a can be detected by the magnitude of the voltage between the pair of temperature-sensing pads 105t.

[0141] As described above, the present invention can also be realized as a semiconductor device 100a including a current-sensing pad 105c and a pair of temperature-sensing pads 105t. The present invention may also be realized as a semiconductor device including at least one of the current-sensing pad 105c and a pair of temperature-sensing pads 105t.

[0142] In the above embodiment, an example was described in which the mold layer 106 and the semiconductor layer 101 are cut simultaneously by a dicing blade, but the present invention is not limited thereto. For example, a two-stage dicing process may be combined. Figures 15A to 15C are cross-sectional views illustrating a dicing process according to one modified example having such a two-stage dicing process.

[0143] First, as shown in Figure 15A, the entire mold layer 106 and a portion of the semiconductor layer 101 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in Figure 15B, the entire semiconductor substrate 101c is cut by a second dicing blade DB2 having the same axis of rotation as the first dicing blade DB1 and a second width w2 smaller than the first width w1. As shown in Figure 15C, in the semiconductor device 100b separated by this method, the side surface of the mold layer 106 is located inward from the side surface of the semiconductor layer 101, and there is a step near the boundary between the mold layer 106 and the semiconductor layer 101.

[0144] Dicing may be performed with the wafer inverted. That is, dicing may be performed with the back surface (carbon side) of the semiconductor substrate 101c facing upwards. It is preferable that the rotation direction of the dicing blade be in the direction of cutting from the carbon side toward the silicon side. Figures 16A to 16C are cross-sectional views illustrating a dicing process according to another modified example having such a two-stage dicing process.

[0145] First, as shown in Figure 16A, the entire semiconductor layer 101 and a portion of the mold layer 106 are cut by a first dicing blade DB1 having a first width w1. Then, as shown in Figure 16B, the entire mold layer 106 is cut by a second dicing blade DB2 having the same axis of rotation as the first dicing blade DB1 and a second width w2 smaller than the first width w1. As shown in Figure 16C, in the semiconductor device 100c separated by this method, the side surface of the semiconductor layer 101 is located inward from the side surface of the mold layer 106c, and there is a step near the boundary between the mold layer 106 and the semiconductor layer 101.

[0146] The two-stage dicing process shown in Figures 15A to 15C, and the two-stage dicing process shown in Figures 16A to 16C, are applicable not only to semiconductor devices that function as transistors, but also to semiconductor devices that function as Schottky barrier diodes.

[0147] Although semiconductor devices according to embodiments have been described above, the present invention is not limited to the above embodiments. For example, the numbers used in the above embodiments are all illustrative to specifically illustrate the present invention, and the present invention is not limited to the illustrated numbers.

[0148] Furthermore, while the above embodiments illustrate the main materials of the components included in the semiconductor device, each layer of the laminated structure included in the semiconductor device may contain other materials to the extent that it can achieve the same functionality as the laminated structure of the above embodiments. Also, although the corners and edges of each component are depicted as straight lines in the drawings, the present invention also includes components with rounded corners and edges for manufacturing reasons or other reasons. In addition, the present invention also includes semiconductor devices having a structure in which the conductivity type described in the above embodiments is reversed.

[0149] Although semiconductor devices according to one or more embodiments have been described above based on these embodiments, the present invention is not limited to these embodiments. Without departing from the spirit of the present invention, various modifications that a person skilled in the art could conceive of are applied to the embodiments, as well as embodiments constructed by combinations of components from different embodiments, are also included within the scope of the present invention.

[0150] Furthermore, each of the above embodiments can be modified, replaced, added, or omitted in various ways within the scope of the claims or their equivalents. For example, although the above embodiments described a power semiconductor device using a SiC substrate, the present invention is also applicable to power semiconductor devices (IGBTs or MOSFETs) using a Si substrate. The present invention has industrial applicability and can be applied to semiconductor devices and semiconductor packages, etc.

[0151] The following are examples of features extracted from this specification and drawings. The alphanumeric characters in parentheses below represent corresponding components in the embodiments described above, but this is not intended to limit the scope of each item to the embodiments. The following describes a semiconductor device with improved reliability.

[0152] [A1] A semiconductor layer (100, 201) having a first main surface (101a, 201a) and a second main surface (101b, 201b) facing away from the first main surface (101a, 201a), a first electrode layer (102, 102g, 102s, 202) formed on the first main surface (101a, 201a), a second electrode layer (103, 203) formed on the second main surface (101b, 201b), and the A semiconductor device (100, 100a, 100b, 100c, 200) comprising: an insulating film (104, 204) covering the edges of a first electrode layer (102, 102g, 102s, 202); a plating layer (105, 205) covering at least a portion of the first electrode layer (102, 102g, 102s, 202) other than the edges; and a mold layer (106, 206) covering the insulating film (104, 204).

[0153] [A2] In a plan view, the mold layer (106, 206) is annular along the outer periphery of the semiconductor layer (100, 201), as described in A1 (100, 100a, 100b, 100c, 200).

[0154] [A3] The semiconductor device (100, 100a, 100b, 100c, 200) according to A1 or A2, wherein the surface of the plating layer (105, 205) and the surface of the mold layer (106, 206) are flush.

[0155] [A4] The plating layer (105, 205) and the molding layer (106, 206) are in direct contact with the semiconductor device (100, 100a, 100b, 100c, 200) described in any one of A1 to A3.

[0156] [A5] The semiconductor layer (100, 201) is formed of SiC, and is a semiconductor device (100, 100a, 100b, 100c, 200) as described in any one of A1 to A4.

[0157] [A6] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A5, wherein the semiconductor device (100, 100a, 100b, 100c, 200) functions as a transistor, the second electrode layer (103, 203) is the drain electrode (40) of the transistor, and the first electrode layer (102, 102g, 102s, 202) includes the source electrode (102s) of the transistor and the gate electrode (102g) of the transistor which is insulated from the source electrode (102s).

[0158] [A7] The semiconductor device (100, 100a, 100b, 100c, 200) is a Schottky barrier diode that has the first electrode layer (102, 102g, 102s, 202) as the anode and the second electrode layer (103, 203) as the cathode, as described in any one of A1 to A6.

[0159] [A8] A semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A7, wherein the side surface of the semiconductor layer (100, 201) and the side surface of the mold layer (106, 206) are flush.

[0160] [A9] A semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A8, wherein a metal layer is formed on the surface of the plating layer (105, 205) using a metal material different from the metal material forming the plating layer (105, 205).

[0161] [A10] A step of forming a first electrode layer (102, 102g, 102s, 202) on the first main surface (101a, 201a) of a semiconductor layer (100, 201), and a step of forming a second electrode layer (103, 203) on the second main surface (101b, 201b) of the semiconductor layer (100, 201) that is facing away from the first main surface (101a, 201a), and the first electrode layer (102, 102g, 102s, 202) A method for manufacturing a semiconductor device (100, 100a, 100b, 100c, 200), comprising the steps of: forming an insulating film (104, 204) covering the edges of; forming a plating layer (105, 205) covering at least a portion of the first electrode layer (102, 102g, 102s, 202) other than the edges; and forming a mold layer (106, 206) covering the insulating film (104, 204).

[0162] [A11] A method for manufacturing a semiconductor device (100, 100a, 100b, 100c, 200) according to A10, wherein the step of forming the mold layer (106, 206) that covers the insulating film (104, 204) includes the steps of forming the mold layer (106, 206) so as to cover the plating layer (105, 205) and grinding the surface of the mold layer (106, 206) so as to expose the plating layer (105, 205).

[0163] [B1] A semiconductor layer (101, 201) having main surfaces (101a, 201a), main surface electrodes (102, 102g, 102s, 202) disposed on the main surfaces (101a, 201a), an insulating film (104, 204) that partially covers the main surface electrodes (102, 102g, 102s, 202) so that a part of the main surface electrodes (102, 102g, 102s, 202) is exposed, and the main surface electrodes (102, 102g, 102s A semiconductor device (100, 100a, 100b, 100c, 200) comprising: a mold layer (106, 206) that covers the insulating film (104, 204) so ​​as to expose the 202; and pad electrodes (105, 105c, 105g, 105s, 105t, 205) positioned on the main surface electrodes (102, 102g, 102s, 202) so as to be electrically connected to the main surface electrodes (102, 102g, 102s, 202).

[0164] [B2] The pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the mold layer (106, 206) of the semiconductor device described in B1 (100, 100a, 100b, 100c, 200).

[0165] [B3] The insulating film (104, 204) covers the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) so as to expose the inner parts of the main surface electrodes (102, 102g, 102s, 202), and the mold layer (106, 206) covers the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) so as to expose the inner parts of the main surface electrodes (102, 102g, 102s, 202), and the insulating film (104, 204) covers the peripheral edges mold layer (106, 206) covers the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) so as to expose the inner parts of the main surface electrodes (102, 102g, 102s, 202), and the mold layer (106, 206) covers the peripheral edges of the main surface electrodes A semiconductor device (100, 100a, 100b, 100c, 200) according to B1 or B2, wherein the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) are covered with (04) in between, and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are arranged on the inner portion of the main surface electrodes (102, 102g, 102s, 202).

[0166] [B4] The semiconductor device (100, 100a, 100b, 100c, 200) described in B3, wherein the mold layer (106, 206) partially exposes the insulating film (104, 204) on the inner side of the main surface electrodes (102, 102g, 102s, 202), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the main surface electrodes (102, 102g, 102s, 202), the insulating film (104, 204), and the mold layer (106, 206) on the inner side of the main surface electrodes (102, 102g, 102s, 202).

[0167] [B5] The semiconductor device (100, 100a, 100b, 100c, 200) described in any one of B1 to B4, wherein the insulating film (104, 204) covers the main surface (101a, 201a) with a gap inward from the periphery of the main surface (101a, 201a), and the mold layer (106, 206) covers the periphery of the main surface (101a, 201a).

[0168] [B6] The mold layer (106, 206) is formed in an annular shape surrounding the inner part of the main surface (101a, 201a) in a plan view, as described in any one of B1 to B5, semiconductor device (100, 100a, 100b, 100c, 200).

[0169] [B7] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B6, wherein the semiconductor layer (101, 201) includes a side surface, and the mold layer (106, 206) has a mold side surface that is connected to the side surface of the semiconductor layer (101, 201).

[0170] [B8] The semiconductor device (100, 100a, 100b, 100c, 200) according to B7, wherein the side surfaces of the semiconductor layers (101, 201) are ground surfaces, and the mold side surfaces of the mold layers (106, 206) are ground surfaces.

[0171] [B9] The mold layer (106, 206) has a mold main surface that extends along the main surface (101a, 201a), the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B8.

[0172] [B10] The semiconductor device (100, 100a, 100b, 100c, 200) according to B9, wherein the pad electrodes (105, 105c, 105g, 105s, 105t, 205) have electrode surfaces that are continuous with the mold main surface of the mold layer (106, 206).

[0173] [B11] The semiconductor device (100, 100a, 100b, 100c, 200) described in B10, wherein the mold main surface of the mold layer (106, 206) is made of a ground surface, and the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a ground surface.

[0174] [B12] A semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B11, wherein the mold layer (106, 206) is thicker than the insulating film (104, 204), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are thicker than the insulating film (104, 204).

[0175] [B13] The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B12, wherein the insulating film (104, 204) contains a photosensitive resin and the mold layer (106, 206) contains a thermosetting resin.

[0176] [B14] The pad electrodes (105, 105c, 105g, 105s, 105t, 205) are semiconductor devices (100, 100a, 100b, 100c, 200) described in any one of B1 to B13, including a plating layer.

[0177] [B15] The semiconductor layer (101, 201) is a semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B14, including a wide bandgap semiconductor.

[0178] [B16] The semiconductor layer (101, 201) is a semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B1 to B15, including SiC.

[0179] [B17] Semiconductor layers (101, 201) having main surfaces (101a, 201a), main surface electrodes (102, 102g, 102s, 202) disposed on the main surfaces (101a, 201a), photosensitive resin layers (104, 204) covering the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) so as to expose the inner parts of the main surface electrodes (102, 102g, 102s, 202), and the main surface electrodes (102, 102g, 102s, 2 A semiconductor device (100, 100a, 100b, 100c, 200) comprising: a thermosetting resin layer (106, 206) that covers the peripheral edges of the main surface electrodes (102, 102g, 102s, 202) with the photosensitive resin layer (104, 204) sandwiched between them so as to expose the inner portion of (02); and pad electrodes (105, 105c, 105g, 105s, 105t, 205) positioned on the inner portion of the main surface electrodes (102, 102g, 102s, 202).

[0180] [B18] The semiconductor device (100, 100a, 100b, 100c, 200) according to B17, wherein the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are arranged on the main surface electrodes (102, 102g, 102s, 202) so as to be in contact with the thermosetting resin layer (106, 206), and have electrode surfaces exposed from the thermosetting resin layer (106, 206).

[0181] [B19] The semiconductor device (100, 100a, 100b, 100c, 200) according to B17 or B18, wherein the thermosetting resin layers (106, 206) partially expose the photosensitive resin layers (104, 204) on the inner side of the main surface electrodes (102, 102g, 102s, 202), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are in contact with the main surface electrodes (102, 102g, 102s, 202), the photosensitive resin layers (104, 204), and the thermosetting resin layers (106, 206) on the inner side of the main surface electrodes (102, 102g, 102s, 202).

[0182] [B20] The semiconductor layer (101, 201) is a semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B17 to B19, including SiC.

[0183] [C1] A semiconductor device comprising: a semiconductor layer having a main surface and a side surface; a main surface electrode disposed on the main surface; an insulating film covering the peripheral edge of the main surface electrode so as to expose a part of the main surface electrode; a mold layer covering the peripheral edge of the main surface electrode with the insulating film in between so as to expose the main surface electrode; and a pad electrode disposed on the main surface electrode so as to be electrically connected to the main surface electrode, wherein, from the inner part of the main surface toward the side surface, the peripheral edge of the main surface electrode, the outer end of the insulating film, and the outer end face of the mold layer are arranged in that order, and the outer end face of the mold layer is flush with the side surface.

[0184] [C2] The semiconductor device according to C1, wherein the pad electrode is in contact with the mold layer.

[0185] [C3] The semiconductor device according to C1 or C2, wherein the insulating film covers the peripheral edge of the main surface electrode so as to expose the inner portion of the main surface electrode, the mold layer covers the peripheral edge of the main surface electrode with the insulating film in between so as to expose the inner portion of the main surface electrode, and the pad electrode is disposed on the inner portion of the main surface electrode.

[0186] [C4] The mold layer partially exposes the insulating film on the inner side of the main surface electrode, The semiconductor device according to C3, wherein the pad electrode is in contact with the main surface electrode, the insulating film, and the mold layer on the inner side of the main surface electrode.

[0187] [C5] The semiconductor device according to any one of C1 to C4, wherein the insulating film covers the main surface with a gap inward from the periphery of the main surface, and the mold layer covers the periphery of the main surface.

[0188] [C6] The semiconductor device according to any one of C1 to C5, wherein the mold layer is formed in an annular shape surrounding the inner part of the main surface in a plan view.

[0189] [C7] The semiconductor device according to any one of C1 to C6, wherein the mold layer has a mold side surface that is connected to the side surface of the semiconductor layer.

[0190] [C8] The semiconductor device according to C7, wherein the side surface of the semiconductor layer is a ground surface, and the mold side surface of the mold layer is a ground surface.

[0191] [C9] The semiconductor device according to any one of C1 to C8, wherein the mold layer has a mold main surface extending along the main surface.

[0192] [C10] The semiconductor device according to C9, wherein the pad electrode has an electrode surface that is continuous with the mold main surface of the mold layer.

[0193] [C11] The semiconductor device according to C10, wherein the mold main surface of the mold layer is made of a ground surface, and the electrode surface of the pad electrode is made of a ground surface.

[0194] [C12] The semiconductor device according to any one of C1 to C11, wherein the mold layer is thicker than the insulating film and the pad electrode is thicker than the insulating film.

[0195] [C13] The semiconductor device according to any one of C1 to C12, wherein the insulating film comprises a photosensitive resin and the mold layer comprises a thermosetting resin.

[0196] [C14] The semiconductor device according to any one of C1 to C13, wherein the pad electrode includes a plating layer.

[0197] [C15] The semiconductor device according to any one of C1 to C14, wherein the semiconductor layer includes a wide bandgap semiconductor. [Explanation of symbols]

[0198] 100: Semiconductor device, 100a: Semiconductor device, 100b: Semiconductor device, 100c: Semiconductor device, 101: Semiconductor layer, 101a: First main surface (main surface), 102: First electrode layer (main surface electrode), 102g: First electrode layer (main surface electrode), 102s: First electrode layer (main surface electrode), 104: Insulating film (photosensitive resin layer), 105: Plating layer (pad electrode), 105c: Current sensing pad (pad electrode), 105g : Gate pad (pad electrode), 105s: Source pad (pad electrode), 105t: Temperature sensing pad (pad electrode), 106: Mold layer (thermosetting resin layer), 200: Semiconductor device, 201: Semiconductor layer, 201a: First main surface (main surface), 202: First electrode layer (main surface electrode), 204: Insulating film (photosensitive resin layer), 205: Plating layer (pad electrode), 206: Mold layer (thermosetting resin layer)

Claims

1. A semiconductor layer having a main surface, A main surface electrode disposed on the main surface, An insulating film that partially covers the main surface electrode so as to expose a part of the main surface electrode, A mold layer covering the insulating film so as to expose the main surface electrode, A semiconductor device comprising: a pad electrode disposed on the main surface electrode so as to be electrically connected to the main surface electrode;

2. The semiconductor device according to claim 1, wherein the pad electrode is in contact with the mold layer.

3. The insulating film covers the peripheral edge of the main surface electrode so as to expose the inner portion of the main surface electrode. The mold layer covers the peripheral edge of the main surface electrode with the insulating film sandwiched between them, exposing the inner portion of the main surface electrode. The semiconductor device according to claim 1 or 2, wherein the pad electrode is arranged on the inner portion of the main surface electrode.

4. The mold layer partially exposes the insulating film on the inner side of the main surface electrode. The semiconductor device according to claim 3, wherein the pad electrode is in contact with the main surface electrode, the insulating film, and the mold layer on the inner side of the main surface electrode.

5. The insulating film covers the main surface with a gap inward from the periphery of the main surface, The semiconductor device according to any one of claims 1 to 4, wherein the mold layer covers the peripheral edge of the main surface.

6. The semiconductor device according to any one of claims 1 to 5, wherein the mold layer is formed in an annular shape surrounding the inner portion of the main surface in a plan view.

7. The semiconductor device according to any one of claims 1 to 6, wherein the semiconductor layer includes a side surface, and the mold layer has a mold side surface that is connected to the side surface of the semiconductor layer.

8. The side surface of the semiconductor layer is a ground surface, The semiconductor device according to claim 7, wherein the mold side surface of the mold layer is a ground surface.

9. The semiconductor device according to any one of claims 1 to 8, wherein the mold layer has a mold main surface extending along the main surface.

10. The semiconductor device according to claim 9, wherein the pad electrode has an electrode surface that is continuous with the mold main surface of the mold layer.

11. The main surface of the mold layer is made of a ground surface. The semiconductor device according to claim 10, wherein the electrode surface of the pad electrode is a ground surface.

12. The mold layer is thicker than the insulating film. The semiconductor device according to any one of claims 1 to 11, wherein the pad electrode is thicker than the insulating film.

13. The insulating film comprises a photosensitive resin, The semiconductor device according to any one of claims 1 to 12, wherein the mold layer comprises a thermosetting resin.

14. The semiconductor device according to any one of claims 1 to 13, wherein the pad electrode includes a plating layer.

15. The semiconductor device according to any one of claims 1 to 14, wherein the semiconductor layer includes a wide-bandgap semiconductor.

16. The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor layer includes SiC.

17. A semiconductor layer having a main surface, A main surface electrode disposed on the main surface, A photosensitive resin layer covering the peripheral edge of the main surface electrode so as to expose the inner portion of the main surface electrode, A thermosetting resin layer covers the peripheral edge of the main surface electrode, sandwiching the photosensitive resin layer so as to expose the inner portion of the main surface electrode, A semiconductor device comprising: a pad electrode disposed on the inner portion of the main surface electrode;

18. The semiconductor device according to claim 17, wherein the pad electrode is arranged on the main surface electrode so as to be in contact with the thermosetting resin layer and has an electrode surface exposed from the thermosetting resin layer.

19. The thermosetting resin layer partially exposes the photosensitive resin layer on the inner side of the main surface electrode. The semiconductor device according to claim 17 or 18, wherein the pad electrode is in contact with the main surface electrode, the photosensitive resin layer, and the thermosetting resin layer on the inner side of the main surface electrode.

20. The semiconductor device according to any one of claims 17 to 19, wherein the semiconductor layer includes SiC.

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