Switching element
A semiconductor substrate with a p-type electric field relaxation region in the outer periphery alleviates electric field concentration at trench ends, ensuring stable operation and preventing gate insulating film degradation.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2026-04-15
- Publication Date
- 2026-06-18
AI Technical Summary
Existing switching elements with electric field relaxation regions still experience concentration of electric fields at the lower end of trenches, particularly on the outer peripheral portion, leading to potential degradation of the gate insulating film and operational abnormalities.
The design incorporates a semiconductor substrate with trenches, gate insulating film, and gate electrodes, featuring a p-type electric field relaxation region with a higher proportion in the outer periphery, spreading the depletion layer to alleviate electric field concentration.
Effectively suppresses electric field concentration at the lower ends of trenches, stabilizes operation, and prevents gate insulating film degradation, even under high-temperature conditions.
Smart Images
Figure 2026100088000001_ABST
Abstract
Description
Technical Field
[0001] The technology disclosed in this specification relates to a switching element.
[0002] Patent Document 1 discloses a switching element having a trench-type gate electrode. When the switching element is turned off, the drift region is depleted and an electric field is generated in the drift region. In this type of switching element, the electric field tends to concentrate at the lower end of the trench. In order to suppress the electric field concentration at the lower end of the trench, a technique of providing a p-type electric field relaxation region is known. The electric field relaxation region is arranged in a depth range including the lower end of the trench or a depth range below the lower end of the trench. When the electric field relaxation region is provided, the depletion layer tends to spread around the lower end of the trench, and the electric field concentration at the lower end of the trench is alleviated.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] It has been found that even in a switching element provided with an electric field relaxation region, the electric field tends to concentrate at the lower end of the trench on the outer peripheral portion of the element portion (that is, the portion where the trench is provided). In this specification, a technique for alleviating the electric field concentration on the outer peripheral portion of the element portion is proposed.
Means for Solving the Problems
[0005] The switching element disclosed herein comprises a semiconductor substrate having a plurality of trenches on its upper surface, a gate insulating film covering the inner surface of the trenches, and a gate electrode disposed within the trenches and insulated from the semiconductor substrate by the gate insulating film. The portion of the semiconductor substrate in which the plurality of trenches are provided is the element portion. The element portion has a central portion and an outer peripheral portion. The element portion has an n-type source region in contact with the gate insulating film on the side surface of each trench. The element portion and the outer peripheral portion have a body region, a drift region, and an electric field relaxation region. The body region is a p-type region in contact with the gate insulating film on the side surface of each trench. The drift region is located below the body region, separated from the source region by the body region, and is an n-type region in contact with the gate insulating film on the side surface of each trench. The electric field relaxation region is a plurality of p-type regions arranged in a depth range including the lower end of each trench or in a depth range below the lower end of each trench, connected to the body region, and spaced apart laterally on the semiconductor substrate. The drift region is distributed within the spacing between the electric field relaxation regions. The value Wp / Wn, obtained by dividing the lateral width Wp of each electric field relaxation region by the width Wn of the spacing between the electric field relaxation regions, is greater in the outer periphery than in the central part.
[0006] In this switching element, the electric field at the lower end of each trench is relaxed by the electric field relaxation region. Furthermore, the electric field relaxation region is positioned such that the value Wp / Wn is larger in the outer periphery than in the central part. That is, within the depth range of the electric field relaxation region, the proportion of the p-type region is larger in the outer periphery than in the element itself. Therefore, the depletion layer spreads more easily from the electric field relaxation region to its surroundings in the outer periphery than in the element itself. As a result, electric field concentration at the lower end of the trenches in the outer periphery is effectively relaxed. Thus, this switching element can relax electric field concentration in the outer periphery of the element. [Brief explanation of the drawing]
[0007] [Figure 1] A top-down view of the switching element. [Figure 2] A cross-sectional perspective view of the central section 60a. [Figure 3] A longitudinal section of the central portion 60a along the x-direction (i.e., the longitudinal section shown in III-III of Figure 1). [Figure 4] A longitudinal section view of the outer periphery 60b along the x-direction (i.e., the longitudinal section view at IV-IV in Figure 1). [Figure 5] A longitudinal section of the central portion 60a along the y-direction (i.e., a longitudinal section of VV in Figure 1). [Figure 6] A longitudinal section view of the outer periphery 60b along the y-direction (i.e., the longitudinal section view at VI-VI in Figure 1). [Figure 7] A cross-sectional perspective view of the switching element in modified example 1. [Figure 8] A cross-sectional perspective view of the switching element in modified example 2. [Figure 9] A cross-sectional perspective view of the switching element in modified example 3. [Modes for carrying out the invention]
[0008] An example switching element disclosed herein may further include a source electrode (22) that covers the upper surface of the semiconductor substrate in the central and peripheral portions and is in contact with the body region and the source region, and an insulating layer (28) that covers the upper surface of the source electrode in the peripheral portion.
[0009] This configuration makes it possible to suppress the application of a high electric field to the gate insulating film in the outer periphery under high-temperature conditions.
[0010] In one example of a switching element disclosed herein, the outer periphery does not necessarily have to have the source region.
[0011] This configuration allows for stable operation of the switching element by suppressing the current flowing through the outer periphery.
[0012] As shown in Figure 1, the switching element 10 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductors such as Si or GaN. Hereinafter, the direction parallel to the upper surface 12a of the semiconductor substrate 12 will be called the x-direction, the direction parallel to the upper surface 12a and perpendicular to the x-direction will be called the y-direction, and the thickness direction of the semiconductor substrate 12 will be called the z-direction. A source electrode 22 and a plurality of electrode pads 23 are provided on the upper surface 12a of the semiconductor substrate 12. The plurality of electrode pads 23 include an electrode pad that controls the gate potential, an electrode pad that outputs the potential of the source electrode 22, an electrode pad that outputs the temperature of the semiconductor substrate 12, etc. Within the area covered by the source electrode 22, a plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in the y-direction. Each trench 14 is spaced apart in the x-direction. The main part of the switching element 10 is formed in the area where the plurality of trenches 14 are provided. In the following, the portion of the semiconductor substrate 12 in which multiple trenches 14 are provided when the semiconductor substrate 12 is viewed from above as a flat surface (i.e., the portion that overlaps with the source electrode 22) is referred to as the element portion 60. The element portion 60 has a central portion 60a and an outer peripheral portion 60b. The outer peripheral portion 60b is provided around the central portion 60a.
[0013] Figures 2-4 show the structure of the element portion 60. More specifically, Figures 2 and 3 show the structure of the central portion 60a, and Figure 4 shows the structure of the outer peripheral portion 60b. Note that the source electrode 22 is omitted in Figure 2. As shown in Figures 2-4, the inner surface of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is placed inside each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20.
[0014] The source electrode 22 is made of AlSi. As shown in Figure 3, within the central portion 60a, the source electrode 22 is covered by a Ni layer 26. Although not shown, the Ni layer 26 is connected to the external electrode block by solder. As shown in Figure 4, within the outer peripheral portion 60b, the source electrode 22 is covered by an insulating resin layer 28 (e.g., a polyimide layer). The insulating resin layer 28 has low thermal conductivity. Therefore, the central portion 60a has higher heat dissipation than the outer peripheral portion 60b.
[0015] As shown in Figures 2-4, a drain electrode 24 is provided at the bottom of the semiconductor substrate 12. The drain electrode 24 covers the bottom surface 12b of the semiconductor substrate 12.
[0016] As shown in Figures 2-4, the semiconductor substrate 12 has multiple source regions 40, body regions 42, drift regions 44, drain regions 46, and multiple electric field relaxation regions 48.
[0017] Each source region 40 is an n-type region having a high n-type impurity concentration. As shown in Figures 2 and 3, each source region 40 is located within the area enclosed by the trenches 14. Each source region 40 is in ohmic contact with the source electrode 22. Each source region 40 is in contact with the gate insulating film 16 on the side surface of the trench 14. The source regions 40 are located within the central portion 60a. As shown in Figure 4, the source regions 40 are not located within the outer peripheral portion 60b.
[0018] As shown in FIGS. 2 to 4, the body region 42 is distributed across the central portion 60a and the outer peripheral portion 60b. The body region 42 has a plurality of contact regions 42a and low-concentration regions 42b having a lower p-type impurity concentration than each contact region 42a. Each contact region 42a is disposed in a range sandwiched by the trenches 14. Each contact region 42a makes an ohmic contact with the source electrode 22. The low-concentration region 42b contacts the plurality of source regions 40 and the plurality of contact regions 42a from below. The low-concentration region 42b contacts the gate insulating film 16 on the side surface of the trench 14. Inside the central portion 60a, the low-concentration region 42b contacts the gate insulating film 16 below each source region 40.
[0019] As shown in FIGS. 2 to 4, the drift region 44 is distributed across the central portion 60a and the outer peripheral portion 60b. The drift region 44 is an n-type region having a lower n-type impurity concentration than the source region 40. The drift region 44 is distributed across the lower portions of the plurality of trenches 14. As shown in FIG. 2, the upper end portion of the drift region 44 extends to within the range between each trench 14. The drift region 44 contacts the low-concentration region 42b from below within the range between each trench 14. The drift region 44 contacts the gate insulating film 16 below the low-concentration region 42b.
[0020] As shown in FIGS. 2 to 4, the drain region 46 is distributed across the central portion 60a and the outer peripheral portion 60b. The drain region 46 is an n-type region having a higher n-type impurity concentration than the drift region 44. The drain region 46 contacts the drift region 44 from below. The drain region 46 makes an ohmic contact with the drain electrode 24 on the lower surface 12b of the semiconductor substrate 12.
[0021] As shown in Figures 2-4, multiple electric field relaxation regions 48 are provided in the central part 60a and the outer peripheral part 60b. Each electric field relaxation region 48 is located within the range surrounded by drift regions 44. Each electric field relaxation region 48 is located below the low-concentration region 42b, with a gap between them. Drift regions 44 are distributed in the gaps between each electric field relaxation region 48 and the low-concentration region 42b. Each electric field relaxation region 48 extends linearly in the x-direction. Each electric field relaxation region 48 is located with a gap in the y-direction. Drift regions 44 are distributed in each gap between the electric field relaxation regions 48. Hereinafter, the drift regions 44 within each gap between the electric field relaxation regions 48 will be referred to as the gap portion 44a. Each electric field relaxation region 48 is located within the range including the lower end of the trench 14 in the z-direction. Therefore, each electric field relaxation region 48 is in contact with the gate insulating film 16 at the lower end of each trench 14.
[0022] As shown in Figure 2, the semiconductor substrate 12 has a p-type connection region 52. The connection region 52 connects the electric field relaxation region 48 and the low-concentration region 42b. Although only one connection region 52 is shown in Figure 2, at least one connection region 52 is provided for each electric field relaxation region 48. Therefore, the potential of each electric field relaxation region 48 is approximately equal to the potential of the body region 42.
[0023] In Figures 5 and 6, the symbol Wp indicates the width of each electric field relaxation region 48 in the y-direction, and the symbol Wn indicates the width of each interval between the electric field relaxation regions 48 in the y-direction (i.e., the width of the interval 44a). As shown in Figures 5 and 6, the width Wp of the electric field relaxation region 48 is narrower in the central region 60a than in the outer peripheral region 60b. Also, the width Wn of the interval 44a is wider in the central region 60a than in the outer peripheral region 60b. Therefore, the value Wp / Wn, obtained by dividing the width Wp by the width Wn, is smaller in the central region 60a than in the outer peripheral region 60b. The value Wp / Wn represents the ratio of the electric field relaxation region 48 to the interval 44a within the range in the z-direction where the electric field relaxation region 48 exists.
[0024] Next, the operation of the switching element 10 will be described. The switching element 10 is used when a voltage is applied in a direction in which the drain electrode 24 is at a higher potential than the source electrode 22. When a potential above the gate threshold is applied to the gate electrode 18, a channel is formed in the body region 42 near the gate insulating film 16, and the source region 40 and the drift region 44 are connected by the channel. Therefore, electrons flow from the source electrode 22 to the source region 40 and to the drift region 44 through the channel. Electrons that have flowed from the channel into the drift region 44 flow through the gap 44a to the drift region 44 below the electric field relaxation region 48. Electrons then flow from the drift region 44 to the drain electrode 24 through the drain region 46. In this way, when a potential above the gate threshold is applied to the gate electrode 18, the switching element 10 is turned on.
[0025] As described above, when the switching element 10 is turned on, electrons pass through the gap portion 44a. In the central portion 60a, which is the main part of the element portion 60, the value Wp / Wn is small, so the ratio of the gap portion 44a (i.e., the n-type region) is large within the depth range in which the electric field relaxation region 48 exists. Therefore, the resistance of the gap portion 44a is small in the central portion 60a. For this reason, electrons can flow in the central portion 60a with low loss. In the outer peripheral portion 60b, the value Wp / Wn is large, and the resistance of the gap portion 44a is large. However, fewer electrons flow in the outer peripheral portion 60b compared to the central portion 60a. In particular, in this embodiment, since the source region 40 is not provided in the outer peripheral portion 60b, very few electrons flow through the gap portion 44a in the outer peripheral portion 60b. Therefore, even if the resistance of the gap portion 44a is large in the outer peripheral portion 60b, not much loss occurs. For this reason, the on-resistance of the switching element 10 is low.
[0026] Furthermore, during the manufacturing process, it is difficult to form trenches 14 with high precision across the entire element portion 60, and the shape accuracy of the trenches 14 tends to decrease in the outer peripheral portion 60b. Therefore, if a high current is passed through the outer peripheral portion 60b, abnormalities are likely to occur in the outer peripheral portion 60b. In the switching element 10 of this embodiment, since the source region 40 is not provided in the outer peripheral portion 60b, almost no current flows through the outer peripheral portion 60b. As a result, stable operation of the switching element 10 is achieved.
[0027] When the potential of the gate electrode 18 is reduced to a potential below the gate threshold, the channel disappears and the switching element 10 turns off. When the switching element 10 turns off, a reverse voltage is applied to the pn junction at the interface between the body region 42 and the drift region 44. Also, since the electric field relaxation region 48 has approximately the same potential as the body region 42, a reverse voltage is also applied to the pn junction at the interface between the electric field relaxation region 48 and the drift region 44. Therefore, a depletion layer extends from the body region 42 and the electric field relaxation region 48 to the drift region 44. The depleted drift region 44 maintains the voltage between the drain electrode 24 and the source electrode 22. The depletion layer extending from the electric field relaxation region 48 to the drift region 44 depletes the drift region 44 around the lower end of the trench 14. In this way, the depletion of the drift region 44 around the lower end of the trench 14 suppresses electric field concentration in the gate insulating film 16 covering the lower end of the trench 14.
[0028] Furthermore, since there are no trenches 14 outside the element portion 60, the electric field tends to concentrate particularly at the lower end of the trenches 14 within the outer peripheral portion 60b. In contrast, in the switching element 10 of the embodiment, the value Wp / Wn is large in the outer peripheral portion 60b, and the ratio of the electric field relaxation region 48 (i.e., p-type region) to the spacing portion 44a (i.e., n-type region) is large. Therefore, in the outer peripheral portion 60b, the depletion layer tends to spread from the electric field relaxation region 48 to its periphery. Consequently, the effect of mitigating electric field concentration by the electric field relaxation region 48 is higher in the outer peripheral portion 60b than in the central portion 60a. For this reason, electric field concentration at the lower end of the trenches 14 within the outer peripheral portion 60b can be suppressed. As mentioned above, the outer peripheral portion 60b has lower heat dissipation than the central portion 60a, and the outer peripheral portion 60b tends to become hotter than the central portion 60a. When a high electric field is applied to the gate insulating film 16 at a high temperature, the gate insulating film 16 is prone to degradation. By suppressing electric field concentration on the gate insulating film 16 in the outer peripheral portion 60b, which is prone to high temperatures, the degradation of the gate insulating film 16 can be more effectively suppressed.
[0029] In the embodiment described above, the electric field relaxation regions 48 extended linearly in the x-direction (i.e., the direction intersecting the trenches 14) and were spaced apart in the y-direction. However, the electric field relaxation regions 48 may also extend linearly in the y-direction (i.e., the direction parallel to the trenches 14) and be spaced apart in the x-direction. In this case, as shown in Figure 7, the electric field relaxation regions 48 may be positioned between each trench 14 in the x-direction, or as shown in Figure 8, the electric field relaxation regions 48 may be positioned at a location overlapping each trench 14 (i.e., below the trenches 14) in the x-direction. Even with the configurations shown in Figures 7 and 8, by making the value Wp / Wn larger in the outer peripheral portion 60b than in the central portion 60a, electric field concentration on the gate insulating film 16 in the outer peripheral portion 60b can be suppressed.
[0030] Furthermore, in the above-described embodiment, the electric field relaxation region 48 was located in a depth range that included the lower end of the trench 14, but the electric field relaxation region 48 may also be located in a depth range below the lower end of the trench 14. For example, if the electric field relaxation region 48 extends linearly in a direction intersecting the trench 14, the electric field relaxation region 48 may be located below the lower end of the trench 14, as shown in Figure 9. Also, even if the electric field relaxation region 48 extends linearly parallel to the trench 14, as shown in Figures 7 and 8, the electric field relaxation region 48 may be located below the lower end of the trench 14. Even if the electric field relaxation region 48 is located below the lower end of the trench 14, electric field concentration at the lower end of the trench 14 can still be suppressed.
[0031] Furthermore, in the above-described embodiment, the source region 40 was not provided on the outer periphery 60b, but the source region 40 may be provided on the outer periphery 60b.
[0032] Furthermore, in the embodiment described above, the width Wp was wider in the outer perimeter 60b than in the central part 60a, and the width Wn was narrower in the outer perimeter 60b than in the central part 60a. However, as long as the condition that the value Wp / Wn is greater in the outer perimeter 60b than in the central part 60a is met, the widths Wp and Wn in the central part 60a and the outer perimeter 60b can be set in any way. For example, the width Wp may be wider in the outer perimeter 60b than in the central part 60a, and the width Wn may be equal in the outer perimeter 60b and the central part 60a. Furthermore, for example, the width Wp may be equal in the outer perimeter 60b and the central part 60a, while the width Wn may be narrower in the outer perimeter 60b than in the central part 60a.
[0033] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]
[0034] 18: Gate electrode, 22: Source electrode, 24: Drain electrode, 28: Insulating resin layer, 40: Source region, 42: Body region, 44: Drift region, 44a: Gap region, 46: Drain region, 48: Field relaxation region, 60a: Central region, 60b: Outer periphery
Claims
1. A switching element, A semiconductor substrate having multiple trenches (14) on its upper surface, A gate insulating film (16) covering the inner surface of the trench, A gate electrode (18) is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film. It has, The portion of the semiconductor substrate in which the plurality of trenches are provided is the element portion (60), The element portion has a central portion (60a) and an outer peripheral portion (60b), The element portion has an n-type source region (40) that contacts the gate insulating film on the side surface of each trench, The element portion and the outer peripheral portion are A p-shaped body region (42) in contact with the gate insulating film on the side surface of each trench, An n-type drift region (44) is located below the body region, separated from the source region by the body region, and is in contact with the gate insulating film on the side surface of each trench, A plurality of p-type electric field relaxation regions (48) are located in a depth range including the lower end of each trench, or in a depth range below the lower end of each trench, connected to the body region, and spaced apart laterally from the semiconductor substrate. It has, The drift regions are distributed within the interval between the electric field relaxation regions. The value Wp / Wn obtained by dividing the lateral width Wp of each electric field relaxation region by the width Wn of the interval between each electric field relaxation region is greater in the outer periphery than in the central part. Switching element.
2. The central portion and the outer peripheral portion cover the upper surface of the semiconductor substrate, and the source electrode (22) is in contact with the body region and the source region, An insulating layer (28) covering the upper surface of the source electrode in the outer peripheral portion, It further possesses, The switching element according to claim 1.
3. The switching element according to claim 1 or 2, wherein the outer periphery does not have the source region.