Semiconductor device and its manufacturing method

Abstract

The narrow outer circumference region achieves high pressure resistance. [Solution] A semiconductor device comprising a semiconductor substrate having an element region and an outer peripheral region, and an upper electrode in contact with the upper surface of the semiconductor substrate within the element region. The element region has a p-type main region in contact with the upper electrode and an n-type element drift region located below the main region. The outer peripheral region has a plurality of p-type guard rings extending in an annular shape so as to surround the element region in multiple ways when the semiconductor substrate is viewed from above, a plurality of n-type spacing regions arranged between each of the guard rings, and an n-type outer peripheral drift region that is continuous with the element drift region and located below the plurality of guard rings and the plurality of spacing regions. At least one of the plurality of spacing regions is a high-concentration spacing region having a higher n-type impurity concentration than the element drift region.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] In the semiconductor device disclosed in Patent Document 1, an element region and an outer peripheral region are provided on a semiconductor substrate. A MOSFET (metal-oxide-semiconductor field effect transistor) is provided in the element region. The outer peripheral region is arranged around the element region. In the outer peripheral region, a plurality of p-type guard rings extending annularly so as to surround the element region multiple times are provided. When this semiconductor device is turned off, a depletion layer spreads from the element region to the outer peripheral region. At this time, the depletion layer spreads to the outer peripheral region through each guard ring. By spreading the depletion layer in the outer peripheral region in this way, a voltage can be held in the outer peripheral region.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the width of the outer peripheral region is wide, the area ratio occupied by the element region in the entire semiconductor substrate becomes small, and a current cannot flow through the semiconductor substrate at a high density. In this specification, a technology for realizing a high breakdown voltage with a narrow outer peripheral region is proposed.

Means for Solving the Problems

[0005] A semiconductor device disclosed herein includes a semiconductor substrate having an element region and an outer peripheral region disposed around the element region, and an upper electrode in contact with the upper surface of the semiconductor substrate within the element region. The element region has a p-type main region in contact with the upper electrode and an n-type element drift region disposed below the main region. The outer peripheral region has a plurality of p-type guard rings extending in an annular shape so as to enclose the element region in multiple ways when the semiconductor substrate is viewed from above, a plurality of n-type spacing regions disposed between each of the guard rings, and an n-type outer peripheral drift region that is continuous with the element drift region and disposed below the plurality of guard rings and the plurality of spacing regions. At least one of the plurality of spacing regions is a high-concentration spacing region having a higher n-type impurity concentration than the element drift region.

[0006] When this semiconductor device is turned off, a depletion layer spreads from the element region to the outer region. At this time, the depletion layer spreads to the outer region (i.e., each spacing region and the outer drift region) via each guard ring. At least one of the multiple spacing regions is a high-concentration spacing region with a higher n-type impurity concentration than the element drift region. Since a high concentration of fixed charges (i.e., donors) exists within the high-concentration spacing region, a high electric field is generated in the high-concentration spacing region when it becomes depleted. Therefore, a high voltage can be maintained between the pair of guard rings flanking the high-concentration spacing region. For this reason, with this semiconductor device structure, a high breakdown voltage can be achieved by the narrow outer region. [Brief explanation of the drawing]

[0007] [Figure 1] Cross-sectional view of the semiconductor device of the embodiment (cross-sectional view along line II in Figure 2). [Figure 2] A plan view of the semiconductor device of the embodiment. [Figure 3] A diagram showing the electric field distribution within the outer region. [Figure 4] Figure 3 shows a graph illustrating the electric field distribution along the IV-IV line. [Figure 5] A diagram showing the non-depletion region when the guard ring is wide. [Figure 6] A diagram showing the non-depletion region when the guard ring width is narrow. [Figure 7] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 8] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 9] An explanatory diagram of the manufacturing method of the semiconductor device according to the embodiment. [Figure 10] Cross-sectional view of the semiconductor device of the first modified example. [Figure 11] Cross-sectional view of the semiconductor device of the second modified example. [Figure 12] Cross-sectional view of a semiconductor device of the third modified example. [Figure 13] Cross-sectional view of the semiconductor device of the fourth modified example. [Figure 14] Cross-sectional view of the fifth modified semiconductor device. [Figure 15] Cross-sectional view of a semiconductor device of the sixth modified example. [Figure 16] Cross-sectional view of the semiconductor device of the seventh modified example. [Figure 17] Cross-sectional view of the semiconductor device of the eighth modified example. [Figure 18] Cross-sectional view of a semiconductor device of the ninth modified example. [Figure 19] Cross-sectional view of the 10th modified semiconductor device. [Modes for carrying out the invention]

[0008] In one example semiconductor device disclosed herein, a plurality of gate trenches may be provided on the upper surface of the semiconductor substrate within the element region, penetrating the main region and reaching the element drift region. The element region may further comprise a plurality of p-type electric field relaxation regions located below the gate trenches, and a plurality of n-type current path regions located between the electric field relaxation regions. The element drift region may be located below the plurality of electric field relaxation regions and the plurality of current path regions. The positions of each guard ring in the thickness direction of the semiconductor substrate may overlap with the positions of each electric field relaxation region in the thickness direction.

[0009] According to this configuration, it is possible to prevent a high electric field from being applied to the gate trench by the electric field relaxation region.

[0010] In a semiconductor device according to an example disclosed in this specification, at least one of the plurality of current path regions may be a high-concentration current path region having an n-type impurity concentration higher than that of the element drift region.

[0011] According to this configuration, it is possible to reduce the electrical resistance of the high-concentration current path, which is a part of the current path.

[0012] In a semiconductor device according to an example disclosed in this specification, the outer peripheral region may further include an n-type upper region disposed above the plurality of guard rings and the plurality of interval regions. The upper region may have an n-type impurity concentration lower than that of the high-concentration interval region.

[0013] In a semiconductor device according to an example disclosed in this specification, a mesa portion may be provided on the upper surface of the semiconductor substrate in the outer peripheral region, the mesa portion being located below the upper surface of the semiconductor substrate in the element region. The plurality of guard rings may be disposed in a range including the bottom surface of the mesa portion.

[0014] As described above, an upper region or a mesa portion may be provided above the guard ring. In any configuration, a high breakdown voltage in the outer peripheral region can be realized.

[0015] In a semiconductor device according to an example disclosed in this specification, the plurality of interval regions may include a first interval region and a second interval region disposed on the outer peripheral side of the first interval region. The second interval region may be the high-concentration interval region. The n-type impurity concentration of the first interval region may be lower than the n-type impurity concentration of the high-concentration interval region.

[0016] In the inner region of the outer circumference, a higher electric field is more likely to occur than in the outer circumference. With the above configuration, the generation of a high electric field is suppressed by providing a first spacing region (i.e., a region with a low n-type impurity concentration) in the inner region of the outer circumference. Furthermore, by providing a second spacing region (i.e., a high-concentration spacing region) in the outer circumference, it is possible to maintain a high voltage on both sides of the second spacing region. Thus, with this configuration, the high electric field on the inner circumference can be suppressed by the first spacing region, and the width of the outer circumference can be reduced by ensuring withstand voltage with the second spacing region.

[0017] In one example semiconductor device disclosed herein, the width of the multiple guard rings may be narrower than the guard rings located on the outer periphery.

[0018] With this configuration, the generation of high electric fields can be suppressed in the inner region of the outer perimeter by a wide guard ring.

[0019] An example of a method for manufacturing a semiconductor device disclosed herein may include a step of simultaneously ion-implanting n-type impurities into a high-concentration spacing region and a high-concentration current path region.

[0020] This configuration allows for the efficient manufacture of semiconductor devices.

[0021] The semiconductor device 10 in the embodiment shown in Figures 1 and 2 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC. However, the semiconductor substrate 12 may be made of other semiconductor materials (for example, Si, GaN, etc.). An upper electrode 20 is provided on the upper surface 12a of the semiconductor substrate 12. The upper electrode 20 is in contact with the central part of the upper surface 12a of the semiconductor substrate 12. A MOSFET is provided inside the semiconductor substrate 12 in the area covered by the upper electrode 20. Hereinafter, the area of ​​the semiconductor substrate 12 covered by the upper electrode 20 will be referred to as the element region 14. The area surrounding the element region 14 (i.e., the area between the element region 14 and the outer peripheral edge of the semiconductor substrate 12) will be referred to as the outer peripheral region 16. The upper surface 12a of the semiconductor substrate 12 within the outer peripheral region 16 is covered with an interlayer insulating film 22 (in this embodiment, a silicon oxide film). The upper surface of the interlayer insulating film 22 is covered with a protective insulating film 24 (in this embodiment, a polyimide film). A lower electrode 26 is provided on the lower surface 12b of the semiconductor substrate 12. The lower electrode 26 is in contact with the lower surface 12b of the semiconductor substrate 12 in an area that spans the element region 14 and the outer peripheral region 16.

[0022] In the following, the direction perpendicular to the thickness direction of the semiconductor substrate 12 will be referred to as the x-direction, and the direction perpendicular to both the thickness direction and the x-direction of the semiconductor substrate 12 will be referred to as the y-direction.

[0023] Multiple gate trenches 30 are provided on the upper surface 12a of the semiconductor substrate 12 within the element region 14. Each gate trench 30 extends linearly in the y direction on the upper surface 12a. The multiple gate trenches 30 are spaced apart in the x direction. A gate insulating film 32 and a gate electrode 34 are placed within each gate trench 30. The gate insulating film 32 covers the inner surface of the gate trench 30. The gate electrode 34 is insulated from the semiconductor substrate 12 by the gate insulating film 32. The upper surface of the gate electrode 34 is covered by an interlayer insulating film 22. The gate electrode 34 is insulated from the upper electrode 20 by the interlayer insulating film 22.

[0024] The semiconductor substrate 12 is provided with multiple source regions 40, multiple contact regions 42, a body region 44, multiple electric field relaxation regions 46, a deep region 48, and multiple guard rings 50.

[0025] The multiple source regions 40 are n-type regions. The multiple source regions 40 are provided within the element region 14. Each source region 40 is in contact with the gate insulating film 32 at the upper end of the side surface of the corresponding gate trench 30. Each source region 40 is in ohmic contact with the upper electrode 20.

[0026] The multiple contact regions 42 are p-type regions. The multiple contact regions 42 are located within the element region 14. Each contact region 42 is in ohmic contact with the upper electrode 20 adjacent to the source region 40.

[0027] The body region 44 is a p-type region with a lower p-type impurity concentration than the contact region 42. The body region 44 is in contact with the source region 40 and the contact region 42 from below. The body region 44 is in contact with the gate insulating film 32 below the source region 40.

[0028] The multiple field relaxation regions 46 are p-type regions. The multiple field relaxation regions 46 are located within the element region 14. Each field relaxation region 46 extends downward from the body region 44. Each field relaxation region 46 extends from the body region 44 to below the lower end of the gate trench 30. Each field relaxation region 46 is located in a position that does not touch the gate trench 30. Although not shown, each field relaxation region 46 extends linearly in the y-direction, similar to the gate trench 30.

[0029] The deep region 48 is a p-type region. The deep region 48 is located along the boundary between the element region 14 and the outer region 16. The deep region 48 extends downward from the body region 44. The deep region 48 extends from the body region 44 to below the lower end of the gate trench 30. That is, the deep region 48 extends from the body region 44 to approximately the same depth as the lower end of each field relaxation region 46.

[0030] The multiple guard rings 50 are p-type regions. The multiple guard rings 50 are arranged within the outer peripheral region 16. As shown in Figure 2, when the semiconductor substrate 12 is viewed from above, the multiple guard rings 50 extend in an annular shape, enclosing the element region 14 in multiple layers. As shown in Figure 1, each guard ring 50 is separated from the body region 44 and the deep region 48. There is a gap between each guard ring 50, separating them from one another. In the thickness direction of the semiconductor substrate 12, the position of each guard ring 50 overlaps with the position of each electric field relaxation region 46 and the deep region 48. More specifically, each guard ring 50 is located in approximately the same depth range as each electric field relaxation region 46 and the deep region 48. As shown in Figures 1 and 2, each guard ring 50 has a narrower width the further out it is located. That is, the width of each guard ring 50 gradually narrows from the inner circumference to the outer circumference.

[0031] An n-type drain region 60 is provided inside the semiconductor substrate 12. The drain region 60 is distributed across the device region 14 and the outer peripheral region 16. The drain region 60 is in ohmic contact with the lower electrode 26 in the area spanning the device region 14 and the outer peripheral region 16.

[0032] An n-type region 54 is provided inside the semiconductor substrate 12. The n-type impurity concentration in the n-type region 54 is lower than that of the drain region 60 and the source region 40. Within the device region 14, the n-type region 54 is located between the drain region 60 and the body region 44. That is, the n-type region 54 is distributed from the position adjacent to the drain region 60 to the region between each field relaxation region 46. Hereafter, the portion of the n-type region 54 located between each field relaxation region 46 will be referred to as the current path region 55. Also below, the portion of the n-type region 54 within the device region 14 located below each field relaxation region 46 and each current path region 55 will be referred to as the device drift region 56. In Figure 1, regions within the n-type region 54 with a higher n-type impurity concentration than the device drift region 56 (hereinafter referred to as high-concentration n-type regions) are shown by dot hatching. As shown in Figure 1, each current path region 55 is a high-concentration n-type region. In other words, in this embodiment, all current path regions 55 are high-density n-type regions. Each current path region 55 is in contact with the body region 44 from below. Each current path region 55 is in contact with the gate insulating film 32 below the body region 44. Each current path region 55 is in contact with the side surface of the corresponding electric field relaxation region 46. The element drift region 56 is in contact with each current path region 55 and each electric field relaxation region 46 from below.

[0033] The n-type region 54 is distributed across the element region 14 and the outer peripheral region 16. Within the outer peripheral region 16, the n-type region 54 is distributed from the position adjacent to the drain region 60 to the upper surface 12a of the semiconductor substrate 12. The n-type region 54 is distributed in the gaps between each guard ring 50, separating each guard ring 50 from one another. The n-type region 54 also separates the guard ring 50 from the deep region 48 and the body region 44. Hereafter, the portion of the n-type region 54 within the outer peripheral region 16 that is located between each guard ring 50 will be referred to as the gap region 58. Also below, the portion of the n-type region 54 within the outer peripheral region 16 that is located above each guard ring 50 and each gap region 58 will be referred to as the upper region 57. Also below, the portion of the n-type region 54 within the outer peripheral region 16 that is located below each guard ring 50 and each gap region 58 will be referred to as the outer peripheral drift region 59. Each gap region 58 is a high-density n-type region. In other words, in this embodiment, all the spacing regions 58 are high-concentration n-type regions. The upper region 57 and the outer peripheral drift region 59 have approximately the same n-type impurity concentration as the element drift region 56. The upper region 57 is in contact with each guard ring 50 and each spacing region 58 from above. The outer peripheral drift region 59 is in contact with each guard ring 50 and each spacing region 58 from below. The outer peripheral drift region 59 and the element drift region 56 are continuously distributed in the lateral direction.

[0034] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is in use, a higher potential is applied to the lower electrode 26 than to the upper electrode 20. When a potential above the gate threshold is applied to the gate electrode 34, a channel is formed in the body region 44 adjacent to the gate insulating film 32. Then, electrons flow from the source region 40 to the drain region 60 through the channel, the current path region 55, and the element drift region 56. In other words, the MOSFET turns on. Since the n-type impurity concentration in the current path region 55 is high, the electrical resistance of the current path region 55 is low. Therefore, electrons can pass through the current path region 55 with low loss. For this reason, the on-resistance of the MOSFET is low.

[0035] When the potential of the gate electrode 34 is reduced to a value below the gate threshold, the channel disappears and the flow of electrons stops. This turns off the MOSFET. When the MOSFET is turned off, a depletion layer spreads from the body region 44 and the electric field relaxation region 46 to the current path region 55 and the element drift region 56. The depletion layer that spreads to the current path region 55 and the element drift region 56 maintains the voltage applied between the body region 44 and the drain region 60. In addition, the presence of the electric field relaxation region 46 makes it easier for the depletion layer to spread around the lower end of the gate trench 30. This prevents a high electric field from being applied to the gate insulating film 32 located at the lower end of the gate trench 30.

[0036] Furthermore, when the MOSFET is turned off, the depletion layer spreads from the body region 44 and the deep region 48 to the n-type region 54 within the outer peripheral region 16 (i.e., the upper region 57, the spacing region 58, and the outer peripheral drift region 59). The potential of each guard ring 50 is floating. The depletion layer extending from the body region 44 and the deep region 48 extends outward through the n-type region 54 via the multiple guard rings 50. The multiple guard rings 50 promote the outward spreading of the depletion layer. The depletion layer spreading in the n-type region 54 within the outer peripheral region 16 maintains the voltage applied between the body region 44 and the outer peripheral edge of the semiconductor substrate 12.

[0037] Figure 3 shows the distribution of equipotential lines within the outer peripheral region 16 when the MOSFET is off. As shown in Figure 3, in the lower part of the deep region 48, the equipotential lines extend laterally. The equipotential lines bend upward at the lower part of each spacing region 58 and enter each spacing region 58, extending to the upper surface 12a. As equipotential lines enter each spacing region 58 in this way, the electric field of each guard ring 50 is higher for the inner-circumferential guard ring 50 and lower for the outer-circumferential guard ring 50. That is, the electric field of each guard ring 50 decreases as it moves away from the deep region 48. In this embodiment, the n-type impurity concentration in each spacing region 58 is higher than the n-type impurity concentration in the element drift region 56. Therefore, a high electric field is easily generated in each spacing region 58, and many equipotential lines easily enter each spacing region 58. Consequently, a potential difference is easily generated between each guard ring 50. Therefore, the potential difference that can be held between each guard ring 50 is large, and the potential difference that can be held in the outer peripheral region 16 is large. Therefore, even if the width of the outer peripheral region 16 is narrowed, a high breakdown voltage can be achieved in the outer peripheral region 16. In this way, by making the n-type impurity concentration in the spacing region 58 higher than the n-type impurity concentration in the element drift region 56, the breakdown voltage performance of the outer peripheral region 16 can be improved, and the width of the outer peripheral region 16 can be reduced.

[0038] Figure 4 shows the electric field distribution within the outer peripheral drift region 59 at the position of the IV-IV line in Figure 3 (i.e., the position below each guard ring 50). The horizontal axis of Figure 4 shows the position of each guard ring 50 located above the IV-IV line. As described above, the electric field of each guard ring 50 is higher for the inner guard ring 50 and lower for the outer guard ring 50. Therefore, as shown in Figure 4, within the outer peripheral drift region 59 below each guard ring 50, the electric field decreases from the inner side to the outer side. Also, the electric field concentrates at the positions where the equipotential lines bend. For this reason, a localized peak of the electric field is formed near the outer peripheral end A of the lower surface of each guard ring 50. The value of each peak decreases from the inner side to the outer side. Thus, a high electric field is likely to occur near the end A of the inner guard ring 50. A higher electric field is generated near the end A of the inner guard ring 50 than at the bottom of the deep region 48. In contrast, in the semiconductor device of this embodiment, the width of each guard ring 50 is wider towards the inner circumference, thereby suppressing the high electric field near the guard ring 50 on the inner circumference. The suppression of the high electric field near the guard ring 50 on the inner circumference will be explained below with reference to Figures 5 and 6.

[0039] Figure 5 shows the case where the guard ring 50 is wide, and Figure 6 shows the case where the guard ring 50 is narrow. In Figures 5 and 6, the shaded region 50x is the non-depleted region remaining within the guard ring 50 when the MOSFET is off. In other words, outside region 50x in Figures 5 and 6, the guard ring 50 and the n-type region 54 are depleted. As shown in Figure 5, when the guard ring 50 is wide, the volume of the guard ring 50 is large, so the width of the depletion layer extending from the pn junction into the guard ring 50 is small. Therefore, the spacing W1 between non-depleted regions 50x between adjacent guard rings 50 is narrow. On the other hand, as shown in Figure 6, when the guard ring 50 is narrow, the volume of the guard ring 50 is small, so the width of the depletion layer extending from the pn junction into the guard ring 50 is large. Therefore, the spacing W1 between non-depleted regions 50x between adjacent guard rings 50 is wide. As shown in Figure 5, when the spacing W1 is narrow, equipotential lines are less likely to enter the spacing region 58 compared to when the spacing W1 is wide, as shown in Figure 6. Therefore, when the spacing W1 is narrow, as shown in Figure 5, the electric field generated near end A is smaller compared to when the spacing W1 is wide, as shown in Figure 6. As shown in Figure 3, when the width of each guard ring 50 is wider towards the inner circumference, high current concentration near end A of the inner circumference guard ring 50 is suppressed. As a result, as shown in Figure 4, the difference ΔE between the peak value of the electric field near end A of the inner circumference guard ring 50 and the electric field at the bottom of the deep region 48 can be reduced. In addition, electric field concentration is more likely to occur near end A of the outer circumference guard ring 50, but as shown in Figure 4, even if electric field concentration occurs in the outer circumference guard ring 50, the electric field does not become very high, and no problem arises. Furthermore, by reducing the width of the outer circumference guard ring 50, the width of the outer circumference region 16 can be reduced. Thus, with this configuration, it is possible to reduce the overall width of the outer circumference region 16 while suppressing the generation of high electric fields in the inner circumference guard ring 50.

[0040] Next, the manufacturing method of the semiconductor device 10 will be described. The semiconductor device 10 is manufactured from a semiconductor substrate composed of drain regions 60. First, as shown in Figure 7, an n-type layer 90 is epitaxially grown on the drain region 60. The n-type layer 90 has the same n-type impurity concentration as the device drift region 56. Next, as shown in Figure 8, a field relaxation region 46, a deep region 48, and a guard ring 50 are formed by selectively ion-implanting p-type impurities into the n-type layer 90 via a mask 92. Next, as shown in Figure 9, n-type impurities are ion-implanted into the entire semiconductor substrate to the same depth as the field relaxation region 46, the deep region 48, and the guard ring 50. Here, n-type impurities are implanted at a lower concentration than in the field relaxation region 46, the deep region 48, and the guard ring 50. This forms high-concentration n-type regions in the current path region 55 and the spacing region 58, where the n-type impurity concentration is higher than in the device drift region 56. Next, a source region 40, a contact region 42, and a body region 44 are formed by ion implantation. Subsequently, the semiconductor device 10 is completed by forming the necessary electrodes, insulating films, etc.

[0041] This manufacturing method allows for simultaneous ion implantation of p-type impurities into the electric field relaxation region 46 and the guard ring 50, and simultaneous ion implantation of n-type impurities into the current path region 55 and the spacing region 58. Furthermore, this manufacturing method eliminates the need for a mask during ion implantation into the current path region 55 and the spacing region 58. Therefore, this manufacturing method allows for efficient production of the semiconductor device 10.

[0042] In the above-described embodiment, the spacing region 58 where a high-concentration n-type region is formed is an example of a high-concentration spacing region. Also, in the above-described embodiment, the current path region 55 where a high-concentration n-type region is formed is an example of a high-concentration current path region. Furthermore, in the above-described embodiment, the contact region 42 and the body region 44 are examples of main regions.

[0043] In the above embodiment, a high-concentration n-type region (i.e., the region dot-hatched in Figure 1) with a higher n-type impurity concentration than the element drift region 56 was formed in the spacing region 58 within the outer peripheral region 16. However, the high-concentration n-type region may also be formed in the region outside the spacing region 58 in addition to the spacing region 58. For example, as shown in Figure 10, the high-concentration n-type region may be formed spanning the spacing region 58 and the upper region 57. Also, as shown in Figure 11, the high-concentration n-type region may be formed spanning the spacing region 58, the upper region 57, and the outer peripheral drift region 59.

[0044] Furthermore, in the above embodiment, high-concentration n-type regions were formed in all of the spacing regions 58. However, high-concentration n-type regions may be formed in only some of the spacing regions 58. For example, as shown in Figure 12, high-concentration n-type regions may be formed in the spacing regions 58 on the outer periphery side (i.e., closer to the outer surface of the semiconductor substrate 12), and high-concentration n-type regions may not be formed in the spacing regions 58 on the inner periphery side (i.e., closer to the device region 14). In other words, the spacing regions 58 on the outer periphery side may be high-concentration spacing regions, and the spacing regions 58 on the inner periphery side may have a lower n-type impurity concentration than the high-concentration spacing regions. As described above, when high-concentration n-type regions are formed in the spacing regions 58, a high potential difference can be maintained in the spacing regions 58, but a high electric field is likely to be generated within the spacing regions 58. As shown in Figure 12, the electric field can be mitigated by lowering the n-type impurity concentration in the spacing regions 58 on the inner periphery side, where a high electric field is likely to be generated. Furthermore, by increasing the amount of n-type impurities in the outer spacing region 58, where high electric fields are less likely to be generated, it is possible to narrow the line width of the outer spacing region 58. This allows for a reduction in the width of the outer region 16.

[0045] Furthermore, in the above-described embodiment, the electric field relaxation region 46 was connected to the body region 44. However, the electric field relaxation region 46 may be separated from the body region 44, and the potential of the electric field relaxation region 46 may be floating. Also, in the above-described embodiment, the electric field relaxation region 46 was formed at an intermediate position between adjacent gate trenches 30. However, as shown in Figure 13, the electric field relaxation region 46 may be located at the bottom of the gate trench 30. Note that, as shown in Figure 13, the electric field relaxation region 46 may be in contact with the lower end of the gate trench 30, or it may be separated from the lower end of the gate trench 30. Even when the electric field relaxation region 46 is located at the bottom of the gate trench 30, the electric field relaxation region 46 may be connected to the body region 44, or it may be separated from the body region 44.

[0046] Furthermore, in the above-described embodiment, the upper surface 12a of the semiconductor substrate 12 was positioned at the same height in the element region 14 and the outer peripheral region 16. However, as shown in Figure 14, a mesa portion 70 may be provided on the upper surface 12a in the outer peripheral region 16 such that the upper surface 12a in the outer peripheral region 16 is located lower than the upper surface 12a in the element region 14. In this case, each guard ring 50 may be positioned in a range that includes the bottom surface of the mesa portion 70 (i.e., the upper surface 12a in the outer peripheral region 16). In other words, an n-shaped upper region 57 does not have to exist above each guard ring 50. Even with this configuration, the withstand voltage within the outer peripheral region 16 can be improved by each guard ring 50.

[0047] Furthermore, in the embodiment described above, an electric field relaxation region 46 was provided within the element region 14. However, an electric field relaxation region 46 is not required to be provided within the element region 14. In this case, as shown in Figure 15, the guard ring 50 may be formed to a depth that overlaps with the body region 44.

[0048] Furthermore, in the embodiment described above, a MOSFET was formed within the element region 14. However, other switching elements such as IGBTs (insulated gate bipolar transistors) may be formed within the element region 14. Also, as shown in Figure 16, a diode may be formed within the element region 14. In Figure 16, a p-type contact region 142 and a p-type anode region 144 are formed within the element region 14. The anode region 144 has a lower p-type impurity concentration than the contact region 142. The contact region 142 is in ohmic contact with the upper electrode 20, and the anode region 144 is in contact with the contact region 142 from below. The element drift region 56 is in contact with the anode region 144 from below. The guard ring 50 is formed to a depth that overlaps with the anode region 144.

[0049] Furthermore, in the structures shown in Figures 13, 14, and 15, a high-concentration n-type region does not necessarily have to be formed in the inner circumferential spacing region 58, as in Figure 12. For example, as shown in Figures 17, 18, and 19, a high-concentration n-type region may be formed in the outer circumferential spacing region 58, but a high-concentration n-type region may not be formed in the inner circumferential spacing region 58.

[0050] The components of the technology disclosed herein are listed below. (Composition 1) A semiconductor device, A semiconductor substrate having an element region and an outer peripheral region arranged around the element region, Within the element region, an upper electrode in contact with the upper surface of the semiconductor substrate, It has, The element region is A p-shaped main region in contact with the upper electrode, An n-type element drift region located below the main region, It has, The aforementioned outer peripheral region is When the semiconductor substrate is viewed from above, it has multiple p-shaped guard rings that extend in an annular shape to surround the element region in multiple ways, A plurality of n-shaped spacing regions are arranged between each of the aforementioned guard rings, An n-shaped outer peripheral drift region, which is continuous with the element drift region and is located below the multiple guard rings and the multiple spacing regions, It has, At least one of the plurality of aforementioned interval regions is a high-concentration interval region having a higher n-type impurity concentration than the element drift region. Semiconductor equipment. (Configuration 2) Multiple gate trenches are provided on the upper surface of the semiconductor substrate within the element region, penetrating the main region and reaching the element drift region. The element region is Multiple p-type electric field relaxation regions located below the gate trench, A plurality of n-type current path regions are arranged between each of the aforementioned electric field relaxation regions. It further possesses, The element drift region is located below the plurality of electric field relaxation regions and the plurality of current path regions, The positions of each guard ring in the thickness direction of the semiconductor substrate overlap with the positions of each electric field relaxation region in the thickness direction. The semiconductor device described in Configuration 1. (Composition 3) The semiconductor device according to configuration 2, wherein at least one of the multiple current path regions is a high-concentration current path region having a higher n-type impurity concentration than the element drift region. (Composition 4) The outer peripheral region further comprises an n-shaped upper region positioned above the plurality of guard rings and the plurality of spacing regions, The upper region has a lower n-type impurity concentration than the high-concentration interval region. A semiconductor device as described in configuration 2 or 3. (Composition 5) A mesa portion is provided on the upper surface of the semiconductor substrate within the outer peripheral region, located below the upper surface of the semiconductor substrate within the element region. Multiple guard rings are arranged in an area including the bottom surface of the mesa portion. A semiconductor device as described in configuration 2 or 3. (Composition 6) Each of the aforementioned interval regions has a first interval region and a second interval region located on the outer periphery of the first interval region. The second interval region is the high-concentration interval region, The n-type impurity concentration in the first interval region is lower than the n-type impurity concentration in the high-concentration interval region. A semiconductor device as described in any one of Configurations 1 to 5. (Composition 7) The semiconductor device according to configuration 6, wherein the width of the multiple guard rings is narrower for the guard rings located on the outer circumference. (Composition 8) A method for manufacturing a semiconductor device as described in configuration 3, comprising the step of simultaneously ion-implanting n-type impurities into the high-concentration spacing region and the high-concentration current path region.

[0051] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0052] 14: Element region, 16: Outer perimeter region, 44: Body region, 46: Field relaxation region, 50: Guard ring, 55: Current path region, 56: Element drift region, 58: Spacing region, 59: Outer perimeter drift region

Claims

1. A semiconductor device, A semiconductor substrate having an element region and an outer peripheral region arranged around the element region, Within the element region, an upper electrode in contact with the upper surface of the semiconductor substrate, It has, The element region is A p-shaped main region in contact with the upper electrode, An n-type element drift region located below the main region, It has, The aforementioned outer peripheral region is When the semiconductor substrate is viewed from above, it has multiple p-shaped guard rings that extend in an annular shape to surround the element region in multiple ways, A plurality of n-shaped spacing regions are arranged between each of the aforementioned guard rings, An n-type outer peripheral drift region, which is continuous with the element drift region and is located below the multiple guard rings and the multiple spacing regions, It has, At least one of the plurality of aforementioned interval regions is a high-concentration interval region having a higher n-type impurity concentration than the element drift region. Semiconductor equipment.

2. Multiple gate trenches are provided on the upper surface of the semiconductor substrate within the element region, penetrating the main region and reaching the element drift region. The element region is A plurality of p-type electric field relaxation regions located below the gate trench, A plurality of n-type current path regions are arranged between each of the aforementioned electric field relaxation regions. It further possesses, The element drift region is located below the plurality of electric field relaxation regions and the plurality of current path regions, The positions of each guard ring in the thickness direction of the semiconductor substrate overlap with the positions of each electric field relaxation region in the thickness direction. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, wherein at least one of the plurality of current path regions is a high-concentration current path region having a higher n-type impurity concentration than the element drift region.

4. The outer peripheral region further comprises an n-shaped upper region positioned above the plurality of guard rings and the plurality of spacing regions, The upper region has a lower n-type impurity concentration than the high-concentration interval region. The semiconductor device according to claim 2 or 3.

5. A mesa portion is provided on the upper surface of the semiconductor substrate within the outer peripheral region, located below the upper surface of the semiconductor substrate within the element region. Multiple guard rings are arranged in an area including the bottom surface of the mesa portion. The semiconductor device according to claim 2 or 3.

6. Each of the aforementioned interval regions has a first interval region and a second interval region located on the outer periphery of the first interval region. The second interval region is the high-concentration interval region, The n-type impurity concentration in the first interval region is lower than the n-type impurity concentration in the high-concentration interval region. The semiconductor device according to claim 1 or 2.

7. The semiconductor device according to claim 6, wherein the width of the multiple guard rings is narrower for the guard rings arranged on the outer circumference.

8. A method for manufacturing a semiconductor device according to claim 3, comprising the step of simultaneously ion-implanting n-type impurities into the high-concentration spacing region and the high-concentration current path region.

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