Field-effect transistor

Abstract

In a field-effect transistor having a trench lower layer and a p-type deep layer, the on-resistance is reduced. [Solution] A field-effect transistor wherein the trench lower layer is located at the bottom of the trench. The p-type deep layer extends along a first direction intersecting the trench when viewed from above on the semiconductor substrate, and is spaced apart along a second direction perpendicular to the first direction. The drain-side n-type layer is distributed from a position in contact with the bottom surface of the body layer through each gap between each p-type deep layer to a position below the bottom end of each p-type deep layer. The drain-side n-type layer has a high-density layer and a medium-density layer. The high-density layer is distributed in at least a portion of the depth range in which both each p-type deep layer and each trench lower layer exist. The medium-density layer is distributed in at least a portion of the depth range between the bottom end of the high-density layer and the bottom end of each p-type deep layer.

Description

Technical Field

[0001] The technology disclosed in this specification relates to a field - effect transistor.

[0002] Patent Document 1 discloses a trench - gate type field - effect transistor. This field - effect transistor has a plurality of p - type trench lower layers and a plurality of p - type deep layers. Each trench lower layer is disposed at the lower part of the corresponding trench. Each p - type deep layer is disposed at the lower part of the body layer. Each p - type deep layer extends so as to intersect the trench and the trench lower layer when looking at the semiconductor substrate from above. The plurality of p - type deep layers are arranged at intervals in their width direction. An n - type layer is provided within each interval. An n - type drift layer is disposed below the trench lower layer and the p - type deep layer. According to this structure, the breakdown voltage of the field - effect transistor can be improved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the field-effect transistor described in Patent Document 1, the n-type layer adjacent to the trench lower layer and the p-type deep layer (i.e., the n-type layer provided in the space between the trench lower layer and the p-type deep layer) serves as the current path. In the ON state of the field-effect transistor, a depletion layer extends from the trench lower layer and the p-type deep layer to the n-type layer, narrowing the current path within the n-type layer. Because the current path is narrowed in this area, there was a limit to reducing the on-resistance of the field-effect transistor. For example, if the trench spacing (i.e., the spacing between trench lower layers) is narrowed for miniaturization, the width of the n-type layer between the trench lower layers also narrows, increasing the on-resistance. This specification proposes a technique for further reducing the on-resistance in a field-effect transistor having a trench lower layer and a p-type deep layer. [Means for solving the problem]

[0005] The field-effect transistor disclosed herein comprises a semiconductor substrate having a plurality of trenches on its upper surface, a gate insulating film covering the inner surface of each trench, a gate electrode disposed within each trench and insulated from the semiconductor substrate by the gate insulating film, and a source electrode in contact with the upper surface of the semiconductor substrate. The semiconductor substrate comprises an n-type source layer in contact with the source electrode and in contact with the gate insulating film on the side surface of each trench, a p-type body layer in contact with the gate insulating film below the source layer, a plurality of p-type trench lower layers, a plurality of p-type deep layers, and a drain-side n-type layer. Each trench lower layer is located below the corresponding trench, extends along the longitudinal direction of the trench when the semiconductor substrate is viewed from above, and is electrically connected to the source electrode. Each of the aforementioned p-type deep layers is located below the body layer, extends from a position above the lower end of each trench lower layer to a position below the lower end of each trench lower layer, extends along a first direction that intersects the trench when viewed from above on the semiconductor substrate, intersects with each trench lower layer, is spaced apart along a second direction that is perpendicular to the first direction when viewed from above on the semiconductor substrate, and is electrically connected to the source electrode. The drain-side n-type layer is distributed from a position in contact with the lower surface of the body layer through each gap between each of the p-type deep layers to a position below the lower end of each of the p-type deep layers, and is in contact with the gate insulating film below the body layer. The drain-side n-type layer comprises an n-type high-concentration layer, an n-type medium-concentration layer located below the high-concentration layer and having a lower n-type impurity concentration than the high-concentration layer, and an n-type drift layer located below the medium-concentration layer and having a lower n-type impurity concentration than the medium-concentration layer. The high-concentration layer is distributed in at least a portion of the depth range in which both the p-type deep layer and the trench lower layer exist, and is in contact with the sides of the trench lower layer and the sides of the p-type deep layer. The medium-concentration layer is distributed in at least a portion of the depth range between the lower end of the high-concentration layer and the lower end of the p-type deep layer, and is in contact with the sides of the p-type deep layer.

[0006] In this specification, "lower part" refers to a position that overlaps with the object when viewed from above, but is below the object. For example, a trench lower layer located at the bottom of a trench is located at a position that overlaps with the trench when viewed from above, but is below the trench. The trench lower layer may be in contact with the trench or at a distance from the trench and located below the trench. Similarly, a p-type deep layer located at the bottom of a body layer is located at a position that overlaps with the body layer when viewed from above, but is below the body layer. The p-type deep layer may be in contact with the body layer or at a distance from the body layer and located below the body layer.

[0007] Furthermore, the "source layer" described above may be composed of multiple n-type layers.

[0008] Furthermore, the above-mentioned "high-concentration layer" may be distributed only within the depth range between the upper end of each p-type deep layer and the lower end of each trench lower layer, or it may be distributed outside of that depth range, as long as it is distributed within at least a portion of that depth range.

[0009] Furthermore, the above-mentioned "medium-concentration layer" may be distributed only within the depth range between the lower end of the high-concentration layer and the lower end of each p-type deep layer, or it may be distributed outside of that depth range, as long as it is distributed within at least a portion of that depth range.

[0010] In this field-effect transistor, the lower end of the trench lower layer is located above the lower end of the p-type deep layer. Therefore, in the depth range below the lower end of the trench lower layer, the current path in the drain-side n-type layer located between the p-type deep layers is wide, and the resistance of this current path is low. Furthermore, a high-concentration layer is provided in the drain-side n-type layer within the depth range where both the p-type deep layer and the trench lower layer exist, so the resistance of the current path in the drain-side n-type layer is low even within this depth range. Thus, within the gap between the trench lower layer and the p-type deep layer, the resistance of the current path in the drain-side n-type layer is low in all depth ranges. This reduces the on-resistance of the field-effect transistor. Also, because the lower end of the p-type deep layer is located above the lower end of the trench lower layer, the electric field tends to concentrate around the lower end of the p-type deep layer. However, since a medium-concentration layer with a relatively low n-type impurity concentration is provided adjacent to the p-type deep layer, electric field concentration around the lower end of the p-type deep layer is suppressed. Furthermore, the electric field on the gate insulating film located at the bottom of the trench is mitigated by the layer below the trench. Although the depletion layer does not easily extend into the high-density layer surrounding the layer below the trench, the deep p-layer extends below the bottom of the trench, making it difficult for a high electric field to be generated at the bottom of the trench. Therefore, even if the depletion layer does not easily extend from the layer below the trench to the high-density layer, the electric field on the gate insulating film at the bottom of the trench can be sufficiently suppressed. Consequently, this field-effect transistor structure makes it possible to achieve a lower on-resistance than conventional transistors while ensuring sufficient breakdown voltage. [Brief explanation of the drawing]

[0011] [Figure 1] A cross-sectional perspective view of the MOSFET of Example 1 (showing the xz cross-section excluding the p-type deep layer 36). [Figure 2] A cross-sectional perspective view of the MOSFET of Example 1, with the source electrode 22 and interlayer insulating film 20 omitted (showing the xz cross-section without the p-type deep layer 36). [Figure 3] A cross-sectional perspective view of the MOSFET of Example 1 (showing the xz cross-section including the p-type deep layer 36). [Figure 4]A cross-sectional view of the xy cross-section at a location including trench 14, p-type deep layer 36, and high-density layer 37, viewed from above. [Figure 5] A cross-sectional view of the xy cross-section, seen from above, at a location including the lower trench layer 35, the p-type deep layer 36, and the high-density layer 37. [Figure 6] A cross-sectional view of the xy cross-section, seen from above, at a location including the p-type deep layer 36 and the medium-density layer 38 below the lower trench layer 35. [Figure 7] A cross-sectional view showing the distribution of non-depleted regions within the trench lower layer 35 in the off state in the xz section. [Figure 8] A cross-sectional view showing the distribution of non-depleted regions in the trench lower layer 35 and p-type deep layer 36 under a short-circuit condition in the xy cross-section. [Figure 9] Diagram illustrating the manufacturing method of the MOSFET in Example 1. [Figure 10] Diagram illustrating the manufacturing method of the MOSFET in Example 1. [Figure 11] Diagram illustrating the manufacturing method of the MOSFET in Example 1. [Figure 12] A cross-sectional perspective view of the MOSFET of the first modified example, corresponding to Figure 1. [Figure 13] A cross-sectional perspective view of the MOSFET of the second modified example, corresponding to Figure 1. [Figure 14] A cross-sectional perspective view of the MOSFET of the third modified example, corresponding to Figure 1. [Figure 15] A cross-sectional perspective view of the MOSFET of the fourth modified example, corresponding to Figure 1. [Figure 16] A cross-sectional perspective view of the MOSFET of the fifth modified example, corresponding to Figure 1. [Figure 17] A cross-sectional perspective view of the MOSFET of the sixth modified example, corresponding to Figure 1. [Figure 18] A cross-sectional perspective view of the MOSFET of the seventh modified example, corresponding to Figure 1. [Figure 19] Cross-sectional view of the trench area of ​​the MOSFET in the eighth modified example. [Figure 20] Cross-sectional view of the trench area of ​​the MOSFET in the ninth modified example. [Figure 21]Cross-sectional view around the trench of the MOSFET according to the 10th modification example. [Figure 22] Cross-sectional perspective view of the MOSFET according to Example 2 (perspective view corresponding to FIG. 1). [Figure 23] Explanatory drawing of the manufacturing method of the MOSFET according to Example 2. [Figure 24] Explanatory drawing of the manufacturing method of the MOSFET according to Example 2. [Figure 25] Explanatory drawing of the manufacturing method of the MOSFET according to Example 2. [Figure 26] Explanatory drawing of the manufacturing method of the MOSFET according to Example 2.

Mode for Carrying Out the Invention

[0012] In a field effect transistor of an example disclosed in this specification, each of the p-type deep layers may extend from a position above the lower end of each trench to a position below the lower end of each trench lower layer. The high-concentration layer may include a first layer having an n-type impurity concentration higher than that of the medium-concentration layer and a second layer having an n-type impurity concentration higher than that of the first layer. The second layer may be disposed above the lower end of each trench. The first layer may be disposed between the lower end of the second layer and the upper end of the medium-concentration layer.

[0013] According to this configuration, it is possible to further reduce the on-resistance while ensuring a high breakdown voltage.

[0014] In a field effect transistor of an example disclosed in this specification, the p-type impurity concentration of each trench lower layer may be higher than the p-type impurity concentration of each p-type deep layer.

[0015] According to this configuration, the feedback capacitance of the field effect transistor can be reduced.

[0016] In a field effect transistor of an example disclosed in this specification, a non-depletion region may remain in each p-type deep layer in a state where a saturation current is flowing through the field effect transistor.

[0017] This configuration makes the drain-side n-type layer more prone to depletion. Therefore, it is easier to block the current path during a load short circuit, and the saturation current can be reduced. [Examples]

[0018] The MOSFET (metal-oxide-semiconductor field effect transistor) of Example 1 shown in Figures 1-3 has a semiconductor substrate 12. Hereinafter, the thickness direction of the semiconductor substrate 12 will be referred to as the z direction, one direction parallel to the upper surface 12a of the semiconductor substrate 12 (one direction perpendicular to the z direction) will be referred to as the x direction, and the direction perpendicular to both the x and z directions will be referred to as the y direction. The semiconductor substrate 12 is made of silicon carbide (i.e., SiC). However, the semiconductor substrate 12 may be made of other semiconductor materials such as silicon or gallium nitride. Multiple trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in Figure 2, the multiple trenches 14 extend long along the y direction on the upper surface 12a. The multiple trenches 14 are spaced apart in the x direction.

[0019] As shown in Figures 1-3, the inner surface (i.e., the sides and bottom) of each trench 14 is covered with a gate insulating film 16. A gate electrode 18 is placed inside each trench 14. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surface of each gate electrode 18 is covered with an interlayer insulating film 20. A source electrode 22 is provided on the upper part of the semiconductor substrate 12. The source electrode 22 covers each interlayer insulating film 20. The source electrode 22 is insulated from the gate electrode 18 by the interlayer insulating film 20. The source electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 in a position where there is no interlayer insulating film 20. A drain electrode 24 is located on the lower part of the semiconductor substrate 12. The drain electrode 24 is in contact with the entire lower surface 12b of the semiconductor substrate 12.

[0020] The semiconductor substrate 12 has a plurality of source layers 30, a plurality of contact layers 32, a body layer 34, a plurality of trench underlayers 35, a plurality of p-type deep layers 36, and a drain-side n-type layer 42.

[0021] Each source layer 30 is an n-type layer having a high n-type impurity concentration. Each source layer 30 is positioned in a region that partially includes the upper surface 12a of the semiconductor substrate 12. Each source layer 30 is in ohmic contact with the source electrode 22. Each source layer 30 is in contact with the gate insulating film 16 at the uppermost part of the side surface of the trench 14. Each source layer 30 faces the gate electrode 18 via the gate insulating film 16. Each source layer 30 extends elongated in the y-direction along the side surface of the trench 14.

[0022] Each contact layer 32 is a p-type layer having a high p-type impurity concentration. Each contact layer 32 is positioned in an area that partially includes the upper surface 12a of the semiconductor substrate 12. Each contact layer 32 is positioned between two corresponding source layers 30. Each contact layer 32 is in ohmic contact with the source electrode 22. Each contact layer 32 extends elongated in the y-direction.

[0023] The body layer 34 is a p-type layer having a lower p-type impurity concentration than the contact layer 32. The body layer 34 is located below the multiple source layers 30 and the multiple contact layers 32. The body layer 34 is in contact with the multiple source layers 30 and the multiple contact layers 32 from below. The body layer 34 is in contact with the gate insulating film 16 on the side of the trench 14 located below the source layer 30. The body layer 34 faces the gate electrode 18 via the gate insulating film 16.

[0024] Each trench lower layer 35 is a p-type layer located below the corresponding trench 14. Each trench lower layer 35 is positioned in contact with the bottom surface of the corresponding trench 14. That is, each trench lower layer 35 is in contact with the gate insulating film 16 at the bottom surface of the corresponding trench 14. As shown in Figure 5, when the semiconductor substrate 12 is viewed from above, each trench lower layer 35 extends long along the y-direction. That is, each trench lower layer 35 extends long along the y-direction along the bottom surface of the corresponding trench 14. The p-type impurity concentration of each trench lower layer 35 is higher than that of the body layer 34 and lower than that of the contact layer 32. The p-type impurity concentration of each trench lower layer 35 is higher than that of each p-type deep layer 36.

[0025] As shown in Figures 1-3, each p-type deep layer 36 is a p-type layer that protrudes downward from the lower surface of the body layer 34. Multiple p-type deep layers 36 are spaced apart in the y-direction. Each p-type deep layer 36 has a shape that is elongated in the z-direction in a yz cross-section. That is, the dimension of the p-type deep layer 36 in the z-direction is greater than the dimension of the p-type deep layer 36 in the y-direction. Each p-type deep layer 36 extends from the lower surface of the body layer 34 to a depth below the lower end of each trench lower layer 35. As shown in Figures 4-6, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 extends elongated in the x-direction. As shown in Figure 4, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 intersects with each trench 14. Each p-type deep layer 36 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. As shown in Figure 5, when the semiconductor substrate 12 is viewed from above, each p-type deep layer 36 intersects with each trench lower layer 35. Each p-type deep layer 36 is connected to the trench lower layer 35 at the intersection with the trench lower layer 35. The p-type impurity concentration of each p-type deep layer 36 is higher than the p-type impurity concentration of the body layer 34 and lower than the p-type impurity concentration of the contact layer 32.

[0026] Each p-type deep layer 36 is in contact with the body layer 34 from below. Therefore, each p-type deep layer 36 is electrically connected to the source electrode 22 via the body layer 34 and the contact layer 32. Also, as described above, at the intersection of the trench lower layer 35 and the p-type deep layer 36, the trench lower layer 35 is connected to the p-type deep layer 36. Therefore, each trench lower layer 35 is electrically connected to the source electrode 22 via the p-type deep layer 36, the body layer 34 and the contact layer 32.

[0027] Figure 4 shows a cross-section along the xy plane of depth range R1 where both trenches 14 and p-type deep layers 36 exist. Figure 5 shows a cross-section along the xy plane of depth range R2 where both trench lower layers 35 and p-type deep layers 36 exist. Figure 6 shows a cross-section along the xy plane of depth range R3 below the lower end of trench lower layers 35 and above the lower end of p-type deep layers 36. As shown in Figures 4-6, within depth ranges R1, R2, and R3, multiple p-type deep layers 36 are arranged at intervals in the y direction. Hereafter, the intervals between p-type deep layers 36 will be referred to as intervals 39a. As shown in Figure 4, within depth range R1, the trenches 14 and p-type deep layers 36 extend in a grid pattern. Therefore, within each interval 39a, multiple rectangular regions 39s are formed, demarcated by the trenches 14 and p-type deep layers 36. As shown in Figure 5, within the depth range R2, the trench lower layer 35 and the p-type deep layer 36 extend in a grid pattern. As a result, within each interval 39a, multiple rectangular regions 39t are formed, demarcated by the trench lower layer 35 and the p-type deep layer 36.

[0028] As shown in Figures 1 and 2, the drain-side n-type layer 42 is an n-type layer in contact with the drain electrode 24. The drain-side n-type layer 42 is distributed from a position in contact with the lower surface of the body layer 34 through the gap 39a to the lower surface 12b of the semiconductor substrate 12. The drain-side n-type layer 42 is in contact with the gate insulating film 16 on the side surface of the trench 14 located below the body layer 34. The drain-side n-type layer 42 has a high-concentration layer 37, a medium-concentration layer 38, a drift layer 39, and a drain layer 40. The n-type impurity concentration of the medium-concentration layer 38 is higher than that of the drift layer 39. The n-type impurity concentration of the high-concentration layer 37 is higher than that of the medium-concentration layer 38. The n-type impurity concentration of the drain layer 40 is higher than that of the high-concentration layer 37.

[0029] The high-density layer 37 is located below the body layer 34. The high-density layer 37 is distributed in a depth range from the lower end of the body layer 34 to a position below the lower end of each trench lower layer 35. Therefore, as shown in Figures 4 and 5, the high-density layer 37 is distributed within depth ranges R1 and R2. As shown in Figures 1 to 3, the high-density layer 37 is located within each gap 39a. The high-density layer 37 is in contact with the lower surface of the body layer 34. As shown in Figure 4, within depth range R1, the high-density layer 37 is located within the rectangular region 39s. The high-density layer 37 is in contact with the gate insulating film 16 on the side surface of the trench 14. As shown in Figure 5, within depth range R2, the high-density layer 37 is located within the rectangular region 39t. The high-density layer 37 is in contact with the side surface of each trench lower layer 35. As shown in Figures 4 and 5, within depth ranges R1 and R2, the high-density layer 37 is in contact with the side surface of each p-type deep layer 36. As shown in Figure 1, the high-concentration layer 37 is in contact with the lower surface of the trench lower layer 35.

[0030] As shown in Figures 1-3, the medium-concentration layer 38 is located below the high-concentration layer 37. The medium-concentration layer 38 is distributed in a depth range from the bottom end of the high-concentration layer 37 to a position below the bottom end of each p-type deep layer 36. Therefore, as shown in Figure 6, the medium-concentration layer 38 is distributed within the depth range R3. As shown in Figures 1 and 6, the medium-concentration layer 38 is located within each spacing section 39a. The medium-concentration layer 38 is in contact with the bottom surface of the high-concentration layer 37. The medium-concentration layer 38 is in contact with the side and bottom surfaces of each p-type deep layer 36.

[0031] The drift layer 39 is located below the medium-concentration layer 38. The drift layer 39 is distributed across the lower parts of multiple p-type deep layers 36 and multiple spacing sections 39a. The drift layer 39 is in contact with the lower surface of the medium-concentration layer 38.

[0032] The drain layer 40 is located below the drift layer 39. The drain layer 40 is distributed in a depth range from the bottom edge of the drift layer 39 to the bottom surface 12b of the semiconductor substrate 12. The drain layer 40 is in contact with the bottom surface of the drift layer 39. The drain layer 40 is in ohmic contact with the drain electrode 24.

[0033] Next, the operation of the MOSFET in Example 1 will be described. Under normal circumstances, the MOSFET is used with a potential higher than that applied to the drain electrode 24 than to the source electrode 22. When a potential above the gate threshold is applied to each gate electrode 18, a channel is formed in the body layer 34 near the gate insulating film 16. The channel connects the source layer 30 and the high-concentration layer 37. As a result, electrons flow from the source layer 30 to the drain layer 40 via the channel, high-concentration layer 37, medium-concentration layer 38, and drift layer 39. In other words, the MOSFET turns on. When the potential of each gate electrode 18 is lowered from a value above the gate threshold to a value below the gate threshold, the channel disappears and the flow of electrons stops. In other words, the MOSFET turns off.

[0034] Next, we will explain in more detail the operation when the MOSFET is turned on. As described above, when the MOSFET is turned on, electrons flow from the source layer 30 to the drain layer 40 via the channel, high-concentration layer 37, medium-concentration layer 38, and drift layer 39. Therefore, the high-concentration layer 37 and medium-concentration layer 38 constitute part of the current path. In addition, in the ON state of the MOSFET, a depletion layer of a predetermined width extends from the p-type deep layer 36 and the trench lower layer 35 to the high-concentration layer 37 and medium-concentration layer 38 due to the built-in potential. The depletion layer narrows the current path inside the high-concentration layer 37 and medium-concentration layer 38.

[0035] As shown in Figures 4 and 5, within the depth ranges R1 and R2, each spacing 39a is divided into multiple rectangular regions 39s and 39t by the trench 14 and the trench-lower layer 35. Therefore, the area of ​​the high-concentration layer 37 is small in the xy cross-section shown in Figures 4 and 5. If the depletion layer extends widely from the p-type deep layer 36 and the trench-lower layer 35 into such a high-concentration layer 37, the current path within the high-concentration layer 37 becomes extremely narrow. However, because the n-type impurity concentration of the high-concentration layer 37 is high, the extension of the depletion layer from the p-type deep layer 36 and the trench-lower layer 35 into the high-concentration layer 37 is suppressed. Therefore, a wide current path can be secured within the high-concentration layer 37. In addition, the high n-type impurity concentration of the high-concentration layer 37 reduces the resistivity of the current path within the depth ranges R1 and R2. Therefore, the resistance of the current path within the depth ranges R1 and R2 is reduced.

[0036] On the other hand, since the medium-concentration layer 38 has a lower n-type impurity concentration than the high-concentration layer 37, the depletion layer extends relatively widely from the p-type deep layer 36 and the trench lower layer 35 to the medium-concentration layer 38. The depletion layer narrows the current path within the medium-concentration layer 38. However, as shown in Figure 6, the trench 14 and the trench lower layer 35 do not exist within the depth range R3. Therefore, the medium-concentration layer 38 in depth range R3 has a larger area in the xy cross-section compared to the high-concentration layers 37 in depth ranges R1 and R2. For this reason, even if the current path within the medium-concentration layer 38 is narrowed by the depletion layer, a wide current path can be secured within the medium-concentration layer 38. In addition, the presence of the medium-concentration layer 38, which has a higher n-type impurity concentration than the drift layer 39, within the depth range R3 reduces the resistivity of the current path within the depth range R3. Therefore, the resistance of the current path within the depth range R3 is reduced.

[0037] As described above, according to Example 1, the resistance of the current path within the gap 39a can be reduced. Therefore, the on-resistance of the MOSFET in Example 1 is low.

[0038] Next, we will explain in more detail the operation when the MOSFET is turned off. When the channel disappears, a reverse voltage is applied to the pn junction at the interface between the body layer 34 and the drain-side n-type layer 42. Therefore, a depletion layer spreads from the body layer 34 to the drain-side n-type layer 42. In addition, each p-type deep layer 36 is electrically connected to the source electrode 22 and has approximately the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each p-type deep layer 36 and the drain-side n-type layer 42. Therefore, a depletion layer also spreads from each p-type deep layer 36 to the drain-side n-type layer 42. Furthermore, each trench lower layer 35 is electrically connected to the source electrode 22 and has approximately the same potential as the body layer 34. Therefore, when the channel disappears, a reverse voltage is also applied to the pn junction at the interface between each trench lower layer 35 and the drain-side n-type layer 42. Therefore, a depletion layer also spreads from each trench lower layer 35 to the drain-side n-type layer 42. In this way, the depletion layer extends from the body layer 34, each p-type deep layer 36, and each trench lower layer 35 to the drain-side n-type layer 42. Almost the entire high-concentration layer 37, medium-concentration layer 38, and drift layer 39 are depleted. The drain layer 40 is hardly depleted. The depleted high-concentration layer 37, medium-concentration layer 38, and drift layer 39 maintain the high voltage applied between the drain electrode 24 and the source electrode 22. The p-type impurity concentration in the trench lower layer 35 and the p-type deep layer 36 is set so that a non-depleted region remains in the trench lower layer 35 and the p-type deep layer 36 when the MOSFET is off. This promotes the extension of the depletion layer to the high-concentration layer 37, medium-concentration layer 38, and drift layer 39.

[0039] Each p-type deep layer 36 protrudes below the trench lower layer 35 (i.e., towards the drift layer 39), so the electric field tends to concentrate around the lower end of each p-type deep layer 36. However, since the n-type impurity concentration in the medium-concentration layer 38 adjacent to the p-type deep layer 36 is not very high, the area around the lower end of each p-type deep layer 36 is depleted relatively quickly when the MOSFET is turned off. This suppresses the concentration of the electric field around the lower end of each p-type deep layer 36.

[0040] Since each trench lower layer 35 is in contact with the high-concentration layer 37, when the MOSFET is turned off, the depletion layer does not easily extend around each trench lower layer 35. In other words, when the MOSFET is turned off, the rate at which the depletion layer extends around each trench lower layer 35 is slow. If the depletion layer does not extend sufficiently around each trench lower layer 35, a high electric field is applied to the gate insulating film 16 covering the lower end of the trench 14, and the insulating properties of the gate insulating film 16 deteriorate. However, in this embodiment, since the p-type deep layer 36 protrudes below the trench lower layer 35, a high electric field is not easily generated in the region above the lower end of the p-type deep layer 36. Therefore, even if the depletion layer extends slowly around each trench lower layer 35, the electric field applied to the gate insulating film 16 can be sufficiently suppressed.

[0041] As described above, according to Example 1, the generation of high electric fields can be suppressed at the lower end of each p-type deep layer 36 and the lower end of each trench 14. Therefore, the MOSFET of Example 1 has a high breakdown voltage.

[0042] Figure 7 also shows the state of the trench lower layer 35 when the MOSFET is off. As mentioned above, the p-type impurity concentration in the trench lower layer 35 is higher than that of the p-type deep layer 36. Therefore, as shown in Figure 7, when the MOSFET is off, a relatively large undepleted region 60 remains in the area of ​​the trench lower layer 35 that is in contact with the bottom surface of the trench 14. The remaining undepleted region 60 at the bottom of the trench 14 reduces the feedback capacitance (i.e., the capacitance between the gate electrode 18 and the drain electrode 24). Therefore, the MOSFET of this embodiment can be switched at high speed. In addition, the remaining undepleted region 60 at the bottom of the trench 14 reduces the electric field applied to the gate insulating film 16 due to the shielding effect.

[0043] Next, we will describe the operation of the MOSFET in Example 1 when the load connected to the MOSFET is short-circuited while the MOSFET is in the ON state. When the load is short-circuited, the potential of the drain electrode 24 becomes extremely high relative to the potential of the source electrode 22, and a large current flows through the MOSFET. Also, when the load is short-circuited, a high reverse voltage is applied to the pn junction at the interface between the p-type layer, which consists of the body layer 34, the p-type deep layer 36, and the trench lower layer 35, and the drain-side n-type layer 42. As a result, a depletion layer extends from the p-type layer to the drain-side n-type layer 42. Figure 8 shows the state of the p-type deep layer 36 and the trench lower layer 35 when the load is short-circuited. As shown in Figure 8, when the load is short-circuited, a non-depleted region 60 remains in the center of the p-type deep layer 36 and the trench lower layer 35. This promotes the extension of the depletion layer from the p-type deep layer 36 and the trench lower layer 35 to the high-concentration layer 37 and the medium-concentration layer 38. As a result, the high-concentration layer 37 and the medium-concentration layer 38 are instantaneously depleted when the load is short-circuited. Therefore, the current flowing through the MOSFET during a load short circuit (the so-called saturation current) is reduced. In this way, the saturation current can be suppressed by setting the p-type impurity concentration of the p-type deep layer 36 and the trench lower layer 35 to a high enough concentration that a non-depleted region 60 remains within the p-type deep layer 36 and the trench lower layer 35 during a load short circuit.

[0044] Next, the manufacturing method of the MOSFET of Example 1 will be described. First, as shown in Figure 9, a medium-concentration layer 38, a high-concentration layer 37, a p-type deep layer 36, a body layer 34, a source layer 30, and a contact layer 32 are formed by ion implantation into the drift layer 39. The p-type deep layer 36 is formed by deeply implanting p-type impurities into the upper surface 12a. Next, as shown in Figure 10, a trench 14 is formed by etching the upper surface 12a of the semiconductor substrate 12. Next, as shown in Figure 11, a trench lower layer 35 is formed by ion implanting p-type impurities into the bottom surface of the trench 14. Next, as shown in Figure 1, a gate insulating film 16, a gate electrode 18, an interlayer insulating film 20, a source electrode 22, and a drain electrode 24 are formed. This completes the MOSFET of Example 1.

[0045] When forming the trench 14, variations occur in the depth of the trench 14. Also, when forming the trench lower layer 35, variations occur in the ion implantation depth. Therefore, the position of the lower end of the trench lower layer 35 is affected by both the variation in the depth of the trench 14 and the variation in the ion implantation depth. For this reason, the variation in the position of the lower end of the trench lower layer 35 in the z direction is large. In the MOSFET of Example 1, since the p-type deep layer 36 protrudes below the trench lower layer 35, the position of the lower end of the trench lower layer 35 does not have a significant effect on the breakdown voltage of the MOSFET. For this reason, even if the position of the lower end of the trench lower layer 35 is large, there is almost no variation in the breakdown voltage of the MOSFET. On the other hand, the position of the lower end of the p-type deep layer 36 in the z direction has a significant effect on the breakdown voltage of the MOSFET. As described above, the p-type deep layer 36 is formed by implanting p-type impurities into the upper surface 12a of the semiconductor substrate 12. Therefore, variations in the depth of the trench 14 do not affect the position of the lower end of the p-type deep layer 36. Consequently, variations in the position of the lower end of the p-type deep layer 36 are small. Therefore, variations in the breakdown voltage of the MOSFETs are small.

[0046] Next, a modified example of Example 1 will be described.

[0047] In Example 1, the upper end of the p-type deep layer 36 was in contact with the body layer 34. However, as shown in Figures 12 and 13, the upper end of the p-type deep layer 36 may be separated from the lower surface of the body layer 34. In Figure 12, the upper end of the p-type deep layer 36 is located within a depth range that is below the lower surface of the body layer 34 and above the lower end of the trench 14. In Figure 13, the upper end of the p-type deep layer 36 is located within a depth range that is below the lower end of the trench 14 and above the lower end of the trench lower layer 35. In Figures 12 and 13, an n-type layer (e.g., a high-concentration layer 37) is placed between the p-type deep layer 36 and the body layer 34. A partially p-type connecting layer 50 is provided between the p-type deep layer 36 and the body layer 34. The connecting layer 50 connects the p-type deep layer 36 and the body layer 34. The p-type deep layer 36 is electrically connected to the source electrode 22 via the connecting layer 50, the body layer 34, and the contact layer 32. Thus, the upper end of the p-type deep layer 36 may be positioned away from the body layer 34, as long as it is above the lower end of the trench lower layer 35.

[0048] In Example 1, the high-concentration layer 37 was in contact with the body layer 34. However, as shown in Figures 14 and 15, the upper end of the high-concentration layer 37 may be located below the lower surface of the body layer 34. In Figure 14, the upper end of the high-concentration layer 37 is located within a depth range that is below the lower surface of the body layer 34 and above the lower end of the trench 14. In Figure 15, the upper end of the high-concentration layer 37 is located within a depth range that is below the lower end of the trench 14 and above the lower end of the trench lower layer 35. In Figures 14 and 15, an n-type layer 52 with a lower n-type impurity concentration than the high-concentration layer 37 is located between the high-concentration layer 37 and the body layer 34. Thus, as long as the high-concentration layer 37 is present in at least a portion of the depth range where both the trench lower layer 35 and the p-type deep layer 36 exist, the upper end of the high-concentration layer 37 may be located away from the body layer 34.

[0049] In Example 1, the lower end of the high-concentration layer 37 (i.e., the upper end of the medium-concentration layer 38) was located below the lower end of the trench lower layer 35. However, as shown in Figure 16, the lower end of the high-concentration layer 37 may be located below the upper end of the trench lower layer 35 but above the lower end of the trench lower layer 35 within a depth range. Alternatively, the lower end of the high-concentration layer 37 may be located at the same depth as the lower end of the trench lower layer 35. Thus, as long as the high-concentration layer 37 is present in at least a portion of the depth range where both the trench lower layer 35 and the p-type deep layer 36 exist, the lower end of the high-concentration layer 37 may be located at any position in the z-direction.

[0050] In Example 1, the lower end of the intermediate concentration layer 38 was positioned below the lower end of the p-type deep layer 36. However, as shown in Figure 17, the lower end of the intermediate concentration layer 38 may be positioned above the lower end of the p-type deep layer 36. Alternatively, the lower end of the intermediate concentration layer 38 may be positioned at the same depth as the lower end of the p-type deep layer 36. Thus, as long as the intermediate concentration layer 38 exists in at least a portion of the depth range where the p-type deep layer 36 exists and the trench lower layer 35 does not exist, the lower end of the intermediate concentration layer 38 may be positioned at any position in the z-direction.

[0051] In Example 1, the trench lower layer 35 was in contact with the bottom surface of the trench 14. However, as shown in Figure 18, the trench lower layer 35 may be separated from the bottom surface of the trench 14. If the trench lower layer 35 is positioned below the trench 14, the upper end of the trench lower layer 35 may be separated from the bottom surface of the trench 14. Also, in Example 1, the width of the trench lower layer 35 was equal to the width of the trench 14. However, as shown in Figure 19, the width of the trench lower layer 35 may be wider than the width of the trench 14, or as shown in Figure 20, the width of the trench lower layer 35 may be narrower than the width of the trench 14. Furthermore, as shown in Figure 21, the center of the trench lower layer 35 and the center of the trench 14 may be offset. [Examples]

[0052] In the MOSFET of Example 2 shown in Figure 22, the configuration of the trench lower layer 35 and the high-concentration layer 37 differs from that of Example 1, while the other configurations are the same as those of Example 1. In Example 2, the width of the trench lower layer 35 is wider than the width of the bottom surface of the trench 14. The trench lower layer 35 is in contact with the gate insulating film 16 at the lowest part of the side surface of the trench 14. In Example 2, the high-concentration layer 37 has a first layer 37a and a second layer 37b. The first layer 37a has a higher p-type impurity concentration than the medium-concentration layer 38. The second layer 37b has a higher p-type impurity concentration than the first layer 37a. The second layer 37b is in contact with the lower surface of the body layer 34. The second layer 37b is in contact with the gate insulating film 16 on the underside of the body layer 34. The lower end of the second layer 37b is located above the lower end of the trench 14. The first layer 37a is located below the second layer 37b. The first layer 37a is in contact with the lower surface of the second layer 37b. The first layer 37a is in contact with the side and bottom surfaces of the trench lower layer 35. The first layer 37a is in contact with the upper surface of the medium concentration layer 38.

[0053] In the MOSFET of Example 2, the trench lower layer 35 is in contact with the gate insulating film 16 not only at the bottom surface of the trench 14 but also at the lowest part of the side surface of the trench 14. As a result, the electric field applied to the gate insulating film 16 covering the bottom surface of the trench 14 is suppressed more effectively.

[0054] When the MOSFET in Example 2 is turned on, electrons that have passed through the channel flow into the second layer 37b. Since the n-type impurity concentration in the second layer 37b is high, the resistance of the second layer 37b is low. Therefore, electrons that have passed through the channel easily diffuse laterally along the second layer 37b. Consequently, the electrons, having diffused over a wide area laterally, flow downwards within the first layer 37a. This further reduces the on-voltage of the MOSFET in Example 2.

[0055] Next, the manufacturing method of the MOSFET of Example 2 will be described. First, as shown in Figure 23, a medium-concentration layer 38, a high-concentration layer 37, and a p-type deep layer 36 are formed by ion implantation into the drift layer 39. Here, when ion implantation is performed into the high-concentration layer 37, the ion implantation concentration is changed according to the depth to form the first layer 37a and the second layer 37b. Next, as shown in Figure 24, a p-type trench lower layer 35 is formed in the high-concentration layer 37 by ion implantation. Next, as shown in Figure 25, an epitaxial layer is formed on the semiconductor substrate 12, and a body layer 34, a source layer 30, and a contact layer 32 are formed by ion implantation into the formed epitaxial layer. Next, as shown in Figure 26, a trench 14 is formed by etching the upper surface 12a of the semiconductor substrate 12. Here, the depth of the trench 14 is adjusted so that the bottom surface of the trench 14 is located below the bottom surface of the second layer 37b and is included within the trench lower layer 35. Next, as shown in Figure 22, the gate insulating film 16, gate electrode 18, interlayer insulating film 20, source electrode 22, and drain electrode 24 are formed. This completes the MOSFET of Example 2.

[0056] In Example 2, the second layer 37b is located above the lower end of the trench 14. Therefore, when forming the second layer 37b, it is possible to prevent n-type impurities from being injected to a depth near the lower end of the trench 14. As a result, a p-type trench underlayer 35 can be properly formed, and the electric field applied to the gate insulating film 16 by the trench underlayer 35 can be effectively suppressed.

[0057] In Example 2, the configuration of each part may be modified as shown in Figures 12-14 and 16-21.

[0058] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0059] 14: Trench, 22: Source electrode, 34: Body layer, 35: Lower trench layer, 36: p-type deep layer, 37: High-concentration layer, 38: Medium-concentration layer, 39: Drift layer

Claims

1. It is a field-effect transistor, A semiconductor substrate (12) having multiple trenches (14) on its upper surface, A gate insulating film (16) covers the inner surface of each trench, A gate electrode (18) is placed in each of the trenches and is insulated from the semiconductor substrate by the gate insulating film, Source electrode (22) in contact with the upper surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate An n-type source layer (30) is in contact with the source electrode and is in contact with the gate insulating film on the side surface of each trench, A p-type body layer (34) that is in contact with the gate insulating film below the source layer, Multiple p-shaped trench lower layers (35), Multiple p-type deep layers (36), Drain-side n-type layer (42), It has, Each trench lower layer is located below the corresponding trench, extends along the longitudinal direction of the trench when viewed from above on the semiconductor substrate, and is electrically connected to the source electrode. Each of the aforementioned p-type deep layers is located below the body layer, extends from a position above the lower end of each trench lower layer to a position below the lower end of each trench lower layer, extends along a first direction that intersects the trench when viewed from above on the semiconductor substrate, intersects with each trench lower layer, is spaced apart along a second direction that is perpendicular to the first direction when viewed from above on the semiconductor substrate, and is electrically connected to the source electrode. The drain-side n-type layer is distributed from a position in contact with the lower surface of the body layer, through each gap (39a) between each p-type deep layer, to a position below the lower end of each p-type deep layer, and is in contact with the gate insulating film below the body layer. The drain-side n-type layer is n-type high-concentration layer (37), A medium-concentration n-type layer (38) is located below the high-concentration layer and has a lower n-type impurity concentration than the high-concentration layer. An n-type drift layer (39) is located below the aforementioned medium-concentration layer and has a lower n-type impurity concentration than the aforementioned medium-concentration layer. It has, The high-concentration layer is distributed in at least a portion of the depth range in which both the p-type deep layer and the trench sublayer exist, and is in contact with the side surface of the trench sublayer and the side surface of the p-type deep layer. The medium-concentration layer is distributed in at least a portion of the depth range between the lower end of the high-concentration layer and the lower end of each p-type deep layer, and is in contact with the side surface of each p-type deep layer. Field-effect transistor.

2. Each of the aforementioned p-type deep layers extends from a position above the lower end of each trench to a position below the lower end of each trench's lower layer. The high-concentration layer comprises a first layer (37a) having a higher n-type impurity concentration than the medium-concentration layer, and a second layer (37b) having a higher n-type impurity concentration than the first layer. The second layer is positioned above the lower end of each trench, The first layer is positioned between the lower end of the second layer and the upper end of the medium-concentration layer. The field-effect transistor according to claim 1.

3. The field-effect transistor according to claim 1 or 2, wherein the p-type impurity concentration in each trench lower layer is higher than the p-type impurity concentration in each p-type deep layer.

4. The field-effect transistor according to claim 3, wherein a non-depleted region remains within each of the p-type deep layers when a saturation current is flowing through the field-effect transistor.

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