Semiconductor equipment

Abstract

The present invention provides a semiconductor device capable of mounting multiple types of memory chips on a substrate in a suitable configuration. [Solution] According to one embodiment, the semiconductor device comprises a substrate and a chip stack including a plurality of chips stacked on the substrate. The plurality of chips include a first memory chip, a second memory chip of a different type from the first memory chip, and a first bridge chip that electrically connects the first memory chip and the second memory chip.

Description

【Technical Field】 【0001】 Embodiments of the present invention relate to semiconductor devices. 【Background Art】 【0002】 When mounting a plurality of types of memory chips on a package substrate, the manner in which these memory chips are mounted becomes a problem. 【Prior Art Documents】 【Patent Documents】 【0003】 【Patent Document 1】 U.S. Patent Application Publication No. US2021 / 0358794 【Patent Document 2】 U.S. Patent Application Publication No. US2021 / 0296155 【Patent Document 3】 U.S. Patent Application Publication No. US2023 / 0342067 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 To provide a semiconductor device capable of mounting a plurality of types of memory chips on a substrate in a suitable manner. 【Means for Solving the Problems】 【0005】 According to one embodiment, a semiconductor device includes a substrate and a chip stack including a plurality of chips stacked on the substrate. The plurality of chips include a first memory chip, a second memory chip of a different type from the first memory chip, and a first bridge chip that electrically connects the first memory chip and the second memory chip. 【Brief Description of the Drawings】 【0006】 [Figure 1] It is a block diagram showing the configuration of an information processing apparatus according to the first embodiment. [Figure 2] This is a cross-sectional view showing the structure of the semiconductor device of the first embodiment. [Figure 3] This is a cross-sectional view showing two examples of the structure of a semiconductor device according to the first embodiment. [Figure 4] This is a cross-sectional view (1 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] This is a cross-sectional view (2 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] This is a cross-sectional view (3 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] This is a cross-sectional view (4 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] This is a cross-sectional view (5 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view (6 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view (7 / 7) showing a first example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view (1 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a cross-sectional view (2 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view (3 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] This is a cross-sectional view (4 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] This is a cross-sectional view (5 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] This is a cross-sectional view (6 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 17] This is a cross-sectional view (7 / 8) showing a second example of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 18]Cross-sectional view (8 / 8) showing a second example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 19] Block diagram showing the configuration of an information processing apparatus according to the second embodiment. [Figure 20] Cross-sectional view showing the structure of a semiconductor device according to the second embodiment. [Figure 21] Block diagram showing the configuration of an information processing apparatus according to the third embodiment. [Figure 22] Cross-sectional view showing the structure of a semiconductor device according to the third embodiment. **Embodiments for Carrying Out the Invention** 【0007】 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 22, the same components are denoted by the same reference numerals, and redundant descriptions are omitted. 【0008】 (First Embodiment) FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to the first embodiment. 【0009】 [[ID=3)]The information processing apparatus of the present embodiment includes a processor 1, a memory 2, a storage 3, a bus 4, and a bus 5. The information processing apparatus of the present embodiment is, for example, a computer such as a smartphone. 【0010】 The processor 1 executes various information processes. The processor 1 is, for example, a CPU (Central Processing Unit). The memory 2 temporarily stores various data. The memory 2 is, for example, a RAM (Random Access Memory). The storage 3 stores various data. Details of the storage 3 will be described later. 【0011】 The bus 4 is used for communication between the processor 1 and the memory 2. The bus 5 is used for communication between the processor 1 and the storage 3. The bus 4 and the bus 5 may be the same bus or different buses. 【0012】 Storage 3 comprises a memory chip 11, a memory chip 12, a bridge chip 13, and an IF (interface) chip 14. Memory chip 11 is an example of a first memory chip. Memory chip 12 is an example of a second memory chip. Bridge chip 13 is an example of a first bridge chip. 【0013】 Memory chips 11 and 12 are of different types. For example, memory chips 11 and 12 differ in at least one of the following: data retention method, memory capacity, and access speed. Memory chip 11 is, for example, a non-volatile memory such as flash memory. Memory chip 12 is, for example, a non-volatile memory such as storage-class memory. In this case, since both memory chips 11 and 12 retain data non-volatilely, the data retention methods of memory chips 11 and 12 are the same. Also, since memory chip 11 has a large capacity and memory chip 12 has a small capacity, the memory capacities of memory chips 11 and 12 are different. Also, since the access speed of memory chip 11 is slow and the access speed of memory chip 12 is fast, the access speeds of memory chips 11 and 12 are different. Each of memory chips 11 and 12 comprises, for example, a memory cell array containing multiple memory cells and a circuit (e.g., a CMOS circuit) containing multiple transistors that control the multiple memory cells. 【0014】 The bridge chip 13 is positioned between memory chip 11 and memory chip 12 to electrically connect them. The bridge chip 13 has the function of transferring data between memory chips of different types. In this embodiment, since memory chip 11 and memory chip 12 are of different types, the bridge chip 13 is positioned between memory chip 11 and memory chip 12. The bridge chip 13 transfers data from one of memory chips 11 or 12 to the other. 【0015】 The IF chip 14 is electrically connected to the memory chip 11, memory chip 12, bridge chip 13, and bus 5. The IF chip 14 functions as an interface between the memory chips 11, memory chip 12, and bridge chip 13 and bus 5 (processor 1). For example, the IF chip 14 receives signals from processor 1 and accesses the memory chip 11, memory chip 12, or bridge chip 13 based on these signals. As an example, the IF chip 14 sends a command to the bridge chip 13, and the bridge chip 13 transfers data from memory chip 12 to memory chip 11 based on this command. This makes it possible to transfer this data from memory chip 12 to memory chip 11 without temporarily storing it in memory 2. An example of such a command is a write command that writes data to memory chip 11. 【0016】 In this embodiment, storage 3 is used, for example, when information processing related to AI (Artificial Intelligence) is performed by processor 1. According to this embodiment, information processing can be performed at high speed by transferring data between memory chips 11 and 12 without going through memory 2. An example of such information processing is information processing related to AI inference. 【0017】 The storage 3 of this embodiment is a semiconductor device having the form of a semiconductor package P. The memory chip 11, memory chip 12, bridge chip 13, and IF chip 14 of this embodiment are mounted on a package substrate, which will be described later, and are part of the semiconductor package P. 【0018】 Storage 3 further includes a through-electrode 21, which is an example of a first electrode; a through-electrode 22, which is an example of a second electrode; a through-electrode 23, which is an example of a third electrode; a through-electrode 24, which is an example of a fourth electrode; and a through-electrode 25, which is an example of a fifth electrode. The IF chip 14 also includes a metal pad 31, which is an example of a first pad; a metal pad 32, which is an example of a second pad; a metal pad 33, which is an example of a third pad; and a metal pad 34, which is an example of a fourth pad. The through-electrodes 21-25 and metal pads 31-34 are also part of the semiconductor package P. 【0019】 The through-electrode 21 is provided to electrically connect the memory chip 11 and the IF chip 14. The through-electrode 22 is provided to electrically connect the memory chip 12 and the IF chip 14. The through-electrode 23 is provided to electrically connect the bridge chip 13 and the IF chip 14. The IF chip 14 can access the memory chip 11 using the through-electrode 21, the memory chip 12 using the through-electrode 22, and the bridge chip 13 using the through-electrode 23. 【0020】 The through-electrode 24 is provided to electrically connect the memory chip 11 and the bridge chip 13. The through-electrode 25 is provided to electrically connect the memory chip 12 and the bridge chip 13. The bridge chip 13 can transfer data from one of the memory chips 11 and 12 to the other using the through-electrodes 24 and 25. 【0021】 The metal pad 31 is electrically connected to the through electrode 21. The metal pad 32 is electrically connected to the through electrode 22. The metal pad 33 is electrically connected to the through electrode 23. The IF chip 14 can access the memory chip 11 using the metal pad 31, the memory chip 12 using the metal pad 32, and the bridge chip 13 using the metal pad 33. 【0022】 The metal pad 34 is electrically connected to the bus 5. The IF chip 14 can communicate with the processor 1 and memory 2 using the metal pad 34. 【0023】 According to this embodiment, by employing a bridge chip 13 and an IF chip 14, it becomes possible to house and use memory chips 11 and 12 of different types within the same semiconductor package P. This makes it possible to reduce the total area of ​​the storage 3 on the motherboard of the information processing device of this embodiment, and thus make it possible to miniaturize the information processing device of this embodiment. Therefore, the storage 3 of this embodiment is suitable for mobile devices such as smartphones. 【0024】 Further details of the storage 3 in this embodiment will be described below. In the following description, the storage 3 in this embodiment will also be referred to as the "semiconductor device 3". 【0025】 Figure 2 is a cross-sectional view showing the structure of the semiconductor device 3 of the first embodiment. 【0026】 As shown in Figure 2, the semiconductor device 3 comprises a plurality of memory chips 11 and a plurality of memory chips 12. Each memory chip 11 shown in Figure 2 corresponds to the memory chip 11 shown in Figure 1 and has the same structure and function as the memory chip 11 shown in Figure 1. Similarly, each memory chip 12 shown in Figure 2 corresponds to the memory chip 12 shown in Figure 1 and has the same structure and function as the memory chip 12 shown in Figure 1. 【0027】 The semiconductor device 3 further comprises a bridge chip 13, an IF chip 14, through electrodes 21-25, and metal pads 31-34, as described above. The semiconductor device 3 further comprises a plurality of through electrodes 26, a substrate 41, a plurality of bumps 42, a plurality of bumps 43, a plurality of external connection terminals 44, a plurality of wiring 51, a resin layer 52, and a resin layer 53. Each through electrode 26 is an example of a sixth electrode. 【0028】 The substrate 41 is, for example, a package substrate (wiring board). Figure 2 shows the X and Y directions, which are parallel to and perpendicular to the top and bottom surfaces of the substrate 41, and the Z direction, which is perpendicular to the top and bottom surfaces of the substrate 41. The X, Y, and Z directions intersect each other. 【0029】 The substrate 41 includes an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c. Figure 2 shows the upper surface S1 and lower surface S2 of the insulating substrate 41a. The wiring layer 41b and the resin layer 41c are formed sequentially on the upper surface S1 and lower surface S2 of the insulating substrate 41a, and further formed sequentially within through holes provided in the insulating substrate 41a. The wiring layer 41b includes a plurality of wirings. 【0030】 The semiconductor device 3 further includes a chip stack C mounted on a substrate 41. The chip stack C includes a plurality of memory chips 11, a plurality of memory chips 12, and a bridge chip 13 stacked in the Z direction. More specifically, the chip stack C includes a plurality of memory chips 12 stacked on the substrate 41, a bridge chip 13 stacked on the plurality of memory chips 12, and a plurality of memory chips 11 stacked on the bridge chip 13. Thus, the bridge chip 13 is positioned between the plurality of memory chips 11 and the plurality of memory chips 12. On the other hand, the IF chip 14 is positioned between the substrate 41 and the chip stack C and is attached to the chip stack C. 【0031】 Each bump 42 is located on the upper surface of the IF chip 14 and is electrically connected to the IF chip 14. Each bump 43 is located on the upper surface of the substrate 41 and is electrically connected to the wiring layer 41b. Each external connection terminal 44 is located on the lower surface of the substrate 41 and is electrically connected to the wiring layer 41b. The IF chip 14 is electrically connected to the bus 5 (Figure 1) by the multiple external connection terminals 44 and functions as an interface between the multiple chips in the chip stack C and the multiple external connection terminals 44 under the substrate 41. 【0032】 In this embodiment, each external connection terminal 44 is not in contact with the wiring layer 41b in the cross-section shown in Figure 2, but it is in contact with the wiring layer 41b in a cross-section other than that shown in Figure 2. As a result, each external connection terminal 44 in this embodiment is electrically connected to the wiring layer 41b. Each external connection terminal 44 is, for example, a solder ball. 【0033】 Each wiring 51 is located beneath the chip stack C and is positioned between the substrate 41 and the chip stack C. Figure 2 shows the shape of each wiring 51 with a thick line. Each wiring 51 is positioned on a corresponding bump 43 and is electrically connected to a corresponding external connection terminal 44 via the bump 43 and the wiring layer 41b. Each wiring 51 is electrically connected to the chip stack C, the IF chip 14, and the corresponding external connection terminal 44. In Figure 2, the chip stack C is positioned above the substrate 41 via a plurality of bumps 43 and a plurality of wirings 51. 【0034】 Each wiring 51 may be located outside the chip stack C or inside the chip stack C. In the former case, each wiring 51 may be attached to the underside of the bottommost memory chip 12 of the chip stack C. In the latter case, each wiring 51 may be part of the multilayer wiring structure within the bottommost memory chip 12 of the chip stack C. 【0035】 The resin layer 52 is formed to cover the surface of the chip stack C. The resin layer 53 is formed to cover the surface of the resin layer 52. Parts of the resin layers 52 and 53 are formed between the substrate 41 and the chip stack C. In addition, a part of the resin layer 53 is formed around the IF chip 14 and the bumps 42 and 43. 【0036】 The chip stack C includes through-electrodes 21-26. Each of the through-electrodes 21-26 penetrates one or more chips in the chip stack C in the Z direction. Through-electrode 21 is provided to electrically connect multiple memory chips 11 and IF chip 14. Through-electrode 22 is provided to electrically connect multiple memory chips 12 and IF chip 14. Through-electrode 23 is provided to electrically connect bridge chip 13 and IF chip 14. Through-electrode 24 is provided to electrically connect multiple memory chips 11 and bridge chip 13. Through-electrode 25 is provided to electrically connect multiple memory chips 12 and bridge chip 13. Each through-electrode 26 is provided to electrically connect the corresponding external connection terminal 44 to the multiple memory chips 11, multiple memory chips 12, and bridge chip 13. Each through-electrode 26 is located on the corresponding wiring 51 and is electrically connected to the IF chip 14 and external connection terminal 44 via the wiring 51. 【0037】 The IF chip 14 includes metal pads 31-34 on its upper surface. Metal pad 31 is electrically connected to the through electrode 21 by a bump 42. Metal pad 32 is electrically connected to the through electrode 22 by a bump 42. Metal pad 33 is electrically connected to the through electrode 23 by a bump 42. The IF chip 14 shown in Figure 2 includes multiple metal pads 34. Each metal pad 34 is electrically connected to the corresponding wiring 51 by a bump 42, which in turn is electrically connected to the corresponding through electrode 26 and the corresponding external connection terminal 44. 【0038】 As described above, the memory chips 11 and 12 of this embodiment are mounted on the substrate 41 in the form of a chip stack C. This makes it possible to reduce the area of ​​the semiconductor device 3 in a plan view, and thus makes it possible to miniaturize the semiconductor device 3. 【0039】 Furthermore, the bridge chip 13 in this embodiment is positioned between multiple memory chips 11 and multiple memory chips 12 as part of the chip stack C. This makes it possible to perform data transfer between memory chips 11 and 12 of different types within the semiconductor package P using the bridge chip 13, and also makes it possible to suppress an increase in the area of ​​the semiconductor device 3 due to the bridge chip 13. 【0040】 Figure 3 is a cross-sectional view showing two examples of the structure of the semiconductor device 3 according to the first embodiment. 【0041】 Figure 3(a) shows a first example of the semiconductor device 3 of this embodiment. In the first example, the through-electrode 21 includes a plurality of electrodes 61, a plurality of pads 62, and a plurality of bumps 63. Each electrode 61 penetrates one chip (memory chip 11 in Figure 3(a)) within the chip stack C. Each pad 62 is provided on the upper or lower surface of one electrode 61. Each bump 63 is provided between a pad 62 provided on the upper surface of one electrode 61 and a pad 62 provided on the lower surface of another electrode 61, electrically connecting the former pad 62 and the latter pad 62. The plurality of electrodes 61 and the plurality of bumps 63 are arranged alternately in the Z direction. In the first example, the through-electrodes 22 to 26 have the same structure as the through-electrode 21. 【0042】 Figure 3(b) shows a second example of the semiconductor device 3 of this embodiment. In the second example, the through-electrode 21 includes a plurality of electrodes 61 and a plurality of pads 62. Each electrode 61 penetrates one chip (memory chip 11 in Figure 3(b)) within the chip stack C. Each pad 62 is provided between the upper surface of one electrode 61 and the lower surface of another electrode 61, electrically connecting the former electrode 61 and the latter electrode 61. In the second example, the through-electrodes 22 to 26 have a structure similar to that of the through-electrode 21. 【0043】 Note that the through electrodes 21-26 shown in Figure 2 have the same structure as the through electrode 21 in the second example, but they may instead have the same structure as the through electrode 21 in the first example. 【0044】 [Example 1] Figures 4 to 10 are cross-sectional views showing a first example of the method for manufacturing the semiconductor device 3 of the first embodiment. In Figures 4 to 10, the structure of the first example shown in Figure 3(a) is adopted. 【0045】 Figures 4(a) to 4(d) show the process of forming the memory chip 11 on the top layer of the chip stack C. 【0046】 First, pads 62 and bumps 63 of some of the through-electrodes 21-26 are formed on the memory chip 11 (Figure 4(a)). In Figure 4(a), the pads 62 and bumps 63 of the through-electrodes 21, 24, and 26 are formed on the memory chip 11. 【0047】 Next, the memory chip 11 is temporarily bonded to the support substrate 71 (Figure 4(b)). At this time, the memory chip 11 is placed on the support substrate 71 via a resin layer 72. The lower surface of the memory chip 11 shown in Figure 4(b) corresponds to the upper surface of the memory chip 11 shown in Figure 4(a). 【0048】 Next, the memory chip 11 is made thinner (Figure 4(c)). As a result, the thickness of the memory chip 11 shown in Figure 4(c) is thinner than the thickness of the memory chip 11 shown in Figure 4(b). 【0049】 Next, the memory chip 11 is detached from the support substrate 71 and placed on another support substrate 73 (Figure 4(d)). Note that the upper surface of the memory chip 11 shown in Figure 4(d) corresponds to the lower surface of the memory chip 11 shown in Figure 4(c). 【0050】 Figures 5(a) to 5(d) show the process of forming the second memory chip 11 from the top layer of the chip stack C. 【0051】 First, pads 62 and bumps 63 of some of the through-electrodes 21-26 are formed on the memory chip 11 (Figure 5(a)). In Figure 5(a), the pads 62 and bumps 63 of the through-electrodes 21, 24, and 26 are formed on the memory chip 11. 【0052】 Next, the memory chip 11 is temporarily bonded to the support substrate 74 (Figure 5(b)). At this time, the memory chip 11 is placed on the support substrate 74 via a resin layer 75. The lower surface of the memory chip 11 shown in Figure 5(b) corresponds to the upper surface of the memory chip 11 shown in Figure 5(a). 【0053】 Next, the memory chip 11 is made thinner (Figure 5(c)). As a result, the thickness of the memory chip 11 shown in Figure 5(c) is thinner than the thickness of the memory chip 11 shown in Figure 5(b). 【0054】 Next, electrodes 61 and pads 62 of some of the through electrodes 21-26 are formed inside and on the memory chip 11 (Figure 5(c)). In Figure 5(c), electrodes 61 and pads 62 of through electrodes 21, 24, and 26 are formed inside and on the memory chip 11. In Figure 5(c), each electrode 61 is further formed on the corresponding pad 62. In this embodiment, a portion of each electrode 61 is formed in the step shown in Figure 5(a), and the remainder of each electrode 61 is formed in the step shown in Figure 5(c). 【0055】 Next, the memory chip 11 is detached from the support substrate 74, and the detached memory chip 11 is stacked on top of the memory chip 11 placed on the support substrate 73 (Figure 5(d)). As a result, two memory chips 11 are stacked on the support substrate 73. Note that the upper surface of the upper memory chip 11 shown in Figure 5(d) corresponds to the lower surface of the memory chip 11 shown in Figure 5(c). In Figure 5(d), the pads 62 of the upper memory chip 11 are placed on the bumps 63 of the lower memory chip 11. 【0056】 In this embodiment, the other chips of the chip stack C (memory chip 11, memory chip 12, and bridge chip 13) are also formed by the process shown in Figures 5(a) to 5(d). As a result, the chip stack C is formed on the support substrate 74, and through electrodes 21 to 26 are formed within the chip stack C (Figure 6). The through electrodes 21 to 26 shown in Figure 6 have the structure of the first example shown in Figure 3(a). 【0057】 Next, multiple wirings 51 are formed on the chip stack C (Figure 7). Each wiring 51 is placed on the pad 62 of the corresponding through electrode 26. 【0058】 Next, multiple bumps 42 are formed on the metal pads 31-34 of the IF chip 14, and then the IF chip 14 is placed on the chip stack C (Figure 7). The bumps 42 of metal pad 31 are positioned on the pads 62 of the through-electrode 21. The bumps 42 of metal pad 32 are positioned on the pads 62 of the through-electrode 22. The bumps 42 of metal pad 33 are positioned on the pads 62 of the through-electrode 23. The bumps 42 of each metal pad 34 are positioned on the corresponding wiring 51. 【0059】 Next, a substrate 41 including an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c is prepared, and a plurality of bumps 43 are formed on the wiring layer 41b of the substrate 41 (Figure 8). Next, the chip stack C is peeled off the support substrate 73 and placed on the plurality of bumps 43 (Figure 8). Note that the upper surface of the chip stack C shown in Figure 8 corresponds to the lower surface of the chip stack C shown in Figure 7. In Figure 8, each wiring 51 is placed on the corresponding bump 43. 【0060】 Next, a resin layer 54 is formed on the surface of the chip stack C (Figure 9). A portion of the resin layer 54 is embedded between the substrate 41 and the chip stack C. In Figure 9, the resin layer 54 is formed instead of the resin layers 52 and 53 described above. 【0061】 Next, a number of external connection terminals 44 are formed on the lower surface of the substrate 41 (Figure 10). Each external connection terminal 44 is electrically connected to the wiring layer 41b of the substrate 41. 【0062】 In this way, the semiconductor device 3 of this embodiment, having the form of a semiconductor package P, is manufactured. 【0063】 [Second example] Figures 11 to 18 are cross-sectional views showing a second example of the manufacturing method for the semiconductor device 3 of the first embodiment. In Figures 11 to 18, the structure of the second example shown in Figure 3(b) is adopted. 【0064】 Figures 11(a) to 11(c) show the process of forming the memory chip 12 at the bottom layer of the chip stack C. 【0065】 First, electrodes 61 and pads 62 of some through-electrodes 21-26 are formed inside and on the memory chip 12 (Figure 11(a)). In Figure 11(a), electrodes 61 of through-electrodes 21, 22, 23, and 26 are formed inside the memory chip 12, and pads 62 of through-electrodes 21, 22, and 23 are formed on the memory chip 12. Note that each electrode 61 shown in Figure 11(a) is formed so as not to penetrate the memory chip 12. 【0066】 Next, the memory chip 12 is placed on the support substrate 81 (Figure 11(b)). Note that the lower surface of the memory chip 12 shown in Figure 11(b) corresponds to the upper surface of the memory chip 12 shown in Figure 11(a). 【0067】 Figure 11(b) shows a plurality of wirings 51 provided beneath the memory chip 12. In Figure 11(b), the electrodes 61 of each through-electrode 26 are positioned on the corresponding wirings 51. Each wiring 51 may be provided on the upper surface of the memory chip 12 during the process shown in Figure 11(a), or on the lower surface of the memory chip 12 during the process shown in Figure 11(b). 【0068】 Next, a portion of the resin layer 52 is formed on the surface of the memory chip 12, thinning both the resin layer 52 and the memory chip 12 (Figure 11(c)). As a result, the upper surface of the memory chip 12 is exposed from the resin layer 52, and the thickness of the memory chip 11 shown in Figure 11(c) is thinner than the thickness of the memory chip 11 shown in Figure 11(b). Furthermore, the upper surfaces of each electrode 61 are exposed from the memory chip 12, and each electrode 61 penetrates the memory chip 12. 【0069】 Figures 12(a) to 12(c) show the process of forming the second memory chip 12 from the bottom layer of the chip stack C. 【0070】 First, electrodes 61 and pads 62 of some through-electrodes 21-26 are formed inside and on the memory chip 12 (Figure 12(a)). In Figure 12(a), electrodes 61 of through-electrodes 21, 22, 23, 25, and 26 are formed inside the memory chip 12, and pads 62 of through-electrodes 21, 22, 23, 25, and 26 are formed on the memory chip 12. Note that each electrode 61 shown in Figure 12(a) is formed so as not to penetrate the memory chip 12. 【0071】 Next, the memory chip 12 prepared in the process shown in Figure 12(a) is stacked on top of the memory chip 12 placed on the support substrate 81 (Figure 12(b)). Note that the lower surface of the upper memory chip 12 shown in Figure 12(b) corresponds to the upper surface of the memory chip 12 shown in Figure 12(a). In Figure 12(b), the pads 62 of the through electrodes 21, 22, 23, and 26 of the upper memory chip 11 are placed on the electrodes 61 of the through electrodes 21, 22, 23, and 26 of the lower memory chip 12. 【0072】 Next, a portion of the resin layer 52 is formed on the surface of the upper memory chip 12, thinning both the resin layer 52 and the upper memory chip 12 (Figure 12(c)). As a result, the upper surface of the upper memory chip 12 is exposed from the resin layer 52, and the thickness of the upper memory chip 11 shown in Figure 12(c) is thinner than the thickness of the upper memory chip 11 shown in Figure 12(b). Furthermore, the upper surfaces of each electrode 61 of the upper memory chip 12 are exposed from the upper memory chip 12, and each electrode 61 of the upper memory chip 12 penetrates the upper memory chip 12. 【0073】 In this embodiment, the other chips of the chip stack C (memory chip 11, memory chip 12, and bridge chip 13) are also formed by the processes shown in Figures 12(a) to 12(c). As a result, the chip stack C is formed on the support substrate 81, and through electrodes 21 to 26 are formed within the chip stack C (Figure 13). The through electrodes 21 to 26 shown in Figure 13 have the structure of the second example shown in Figure 3(b). In addition, in the process shown in Figure 13, a portion of the resin layer 52 is also formed on the upper surface of the memory chip 11, the uppermost layer of the chip stack C. 【0074】 Next, the chip stack C is peeled off from the support substrate 81 along with the wiring 51 and resin layer 52, and the chip stack C and other components are placed on another support substrate 82 (Figure 14). Note that the upper surface of the chip stack C shown in Figure 14 corresponds to the lower surface of the chip stack C shown in Figure 13. 【0075】 Next, multiple bumps 42 are formed on the metal pads 31-34 of the IF chip 14, and then the IF chip 14 is placed on the chip stack C (Figure 15). The bumps 42 of metal pad 31 are positioned on the pads 62 of the through-electrode 21. The bumps 42 of metal pad 32 are positioned on the pads 62 of the through-electrode 22. The bumps 42 of metal pad 33 are positioned on the pads 62 of the through-electrode 23. The bumps 42 of each metal pad 34 are positioned on the corresponding wiring 51. 【0076】 Next, a substrate 41 including an insulating substrate 41a, a wiring layer 41b, and a resin layer 41c is prepared, and a plurality of bumps 43 are formed on the wiring layer 41b of the substrate 41 (Figure 16). Next, the chip stack C is peeled off the support substrate 82 and placed on the plurality of bumps 43 (Figure 16). Note that the upper surface of the chip stack C shown in Figure 16 corresponds to the lower surface of the chip stack C shown in Figure 15. In Figure 16, each wiring 51 is placed on the corresponding bump 43. 【0077】 Next, a resin layer 53 is formed on the surface of the resin layer 52 (Figure 17). A portion of the resin layer 53 is embedded between the substrate 41 and the resin layer 52. 【0078】 Next, a number of external connection terminals 44 are formed on the lower surface of the substrate 41 (Figure 18). Each external connection terminal 44 is electrically connected to the wiring layer 41b of the substrate 41. 【0079】 In this way, the semiconductor device 3 of this embodiment, having the form of a semiconductor package P, is manufactured. 【0080】 As described above, the semiconductor device 3 of this embodiment includes memory chips 11 and 12 of different types and a bridge chip 13 that electrically connects the memory chips 11 and 12. Furthermore, the semiconductor device 3 of this embodiment includes a chip stack C that includes the memory chips 11 and 12 and the bridge chip 13 stacked on a substrate 41. 【0081】 Therefore, according to this embodiment, it is possible to mount multiple types of memory chips 11 and 12 on the substrate 41 in a suitable manner. For example, it is possible to reduce the area of ​​the semiconductor device 3 in a plan view, thereby enabling miniaturization of the semiconductor device 3. Furthermore, it is possible to perform data transfer between memory chips 11 and 12 of different types using the bridge chip 13, and it is possible to suppress the increase in the area of ​​the semiconductor device 3 caused by the bridge chip 13. 【0082】 (Second Embodiment) Figure 19 is a block diagram showing the configuration of the information processing device according to the second embodiment. 【0083】 The information processing device of this embodiment (Figure 19) has the same components as the information processing device of the first embodiment (Figure 1). However, the storage 3 of this embodiment further includes a memory chip 11' and a bridge chip 13'. The memory chip 11' is an example of a third memory chip. The bridge chip 13' is an example of a second bridge chip. 【0084】 Memory chips 11', 11, and 12 are of different types. For example, memory chips 11', 11, and 12 differ in at least one of the following: data retention method, memory capacity, and access speed. Memory chip 11' is, for example, a non-volatile memory such as flash memory. Memory chip 11 is, for example, a non-volatile memory such as storage-class memory. Memory chip 12 is, for example, a volatile memory such as DRAM (Dynamic Random Access memory). In this case, the data retention method (non-volatile) of memory chips 11' and 11 is the same, while the data retention method (volatile) of memory chip 12 is different from that of memory chips 11' and 11. Also, since memory chip 11' has a large capacity, memory chip 11 has a small capacity, and memory chip 12 has an even smaller capacity, the memory capacities of memory chips 11', 11, and 12 are different. Furthermore, the access speed of memory chip 11' is slow, the access speed of memory chip 11 is fast, and the access speed of memory chip 12 is even faster, so the access speeds of memory chips 11', 11, and 12 are different. Each of the memory chips 11', 11, and 12 includes, for example, a memory cell array containing multiple memory cells and a circuit (e.g., a CMOS circuit) containing multiple transistors that control the multiple memory cells. 【0085】 The bridge chip 13' is positioned between the memory chip 11' and the memory chip 11 to electrically connect the two memory chips 11' and 11. The bridge chip 13' has the function of transferring data between memory chips of different types. In this embodiment, since the memory chips 11' and 11 are of different types, the bridge chip 13' is positioned between the memory chips 11' and 11. The bridge chip 13' transfers data from one of the memory chips 11', 11 to the other of the memory chips 11', 11. 【0086】 In this embodiment, the IF chip 14 is electrically connected to the memory chips 11', 11, 12, the bridge chips 13', 13, and the bus 5. The IF chip 14 functions as an interface between the memory chips 11', 11, 12 and the bridge chips 13', 13 and the bus 5 (processor 1). For example, the IF chip 14 receives a signal from the processor 1 and accesses one of the memory chips 11', 11, 12 and the bridge chips 13', 13 based on this signal. As an example, the IF chip 14 sends a command to the bridge chip 13', and the bridge chip 13' transfers data from the memory chip 11 to the memory chip 11' based on this command. This makes it possible to transfer this data from the memory chip 11 to the memory chip 11' without temporarily storing it in memory 2. An example of such a command is a write command that writes data to the memory chip 11'. 【0087】 Similar to the first embodiment, the storage 3 of this embodiment is used, for example, when AI-related information processing is performed by the processor 1. According to this embodiment, information processing can be performed at high speed by transferring data between memory chips 11', 11, and 12 without going through memory 2. An example of such information processing is information processing related to AI inference. 【0088】 Similar to the first embodiment, the storage 3 of this embodiment is a semiconductor device having the form of a semiconductor package P. The memory chips 11', 11, 12, bridge chips 13', 13, and IF chip 14 of this embodiment are mounted on the aforementioned substrate 41 and are part of the semiconductor package P. 【0089】 The storage 3 of this embodiment includes, in addition to through electrodes 21-25, through electrodes 21', 23', 24', and 25'. The IF chip 14 of this embodiment includes, in addition to metal pads 31-34, metal pads 31' and 33'. The through electrodes 21', 23', 24', and 25' and the metal pads 31' and 33' are also part of the semiconductor package P. 【0090】 The through-electrode 21' is provided to electrically connect the memory chip 11' and the IF chip 14. The through-electrode 23' is provided to electrically connect the bridge chip 13' and the IF chip 14. The IF chip 14 can access the memory chip 11' using the through-electrode 21' and the bridge chip 13' using the through-electrode 23'. 【0091】 The through-electrode 24' is provided to electrically connect the memory chip 11' and the bridge chip 13'. The through-electrode 25' is provided to electrically connect the memory chip 11 and the bridge chip 13'. The bridge chip 13' can transfer data from one of the memory chips 11', 11 to the other of the memory chips 11', 11 using the through-electrodes 24' and 25'. 【0092】 The metal pad 31' is electrically connected to the through electrode 21'. The metal pad 33' is electrically connected to the through electrode 23'. The IF chip 14 can access the memory chip 11' using the metal pad 31' and access the bridge chip 13' using the metal pad 33'. 【0093】 According to this embodiment, by employing bridge chips 13', 13 and IF chip 14, it becomes possible to house and use memory chips 11', 11, and 12 of different types within the same semiconductor package P. This makes it possible to reduce the total area of ​​the storage 3 on the motherboard of the information processing device of this embodiment, and thus make it possible to miniaturize the information processing device of this embodiment. Therefore, the storage 3 of this embodiment is suitable for mobile devices such as smartphones. 【0094】 Further details of the storage 3 in this embodiment will be described below. In the following description, the storage 3 in this embodiment will also be referred to as the "semiconductor device 3". 【0095】 Figure 20 is a cross-sectional view showing the structure of the semiconductor device 3 of the second embodiment. 【0096】 The semiconductor device 3 of this embodiment (Figure 20) has the same components as the semiconductor device 3 of the first embodiment (Figure 2). However, the semiconductor device 3 of this embodiment further includes a plurality of memory chips 11', as shown in Figure 20. Each memory chip 11' shown in Figure 20 corresponds to the memory chip 11' shown in Figure 19 and has the same structure and function as the memory chip 11' shown in Figure 19. The semiconductor device 3 of this embodiment further includes a bridge chip 13', through electrodes 21', 23', 24', 25', and metal pads 31', 33', as described above in Figure 19. 【0097】 The chip stack C of this embodiment includes a plurality of memory chips 11', a plurality of memory chips 11, a plurality of memory chips 12, a bridge chip 13', and a bridge chip 13 stacked in the Z direction. More specifically, the chip stack C of this embodiment includes a plurality of memory chips 12 stacked on a substrate 41, a bridge chip 13 stacked on the plurality of memory chips 12, a plurality of memory chips 11 stacked on the bridge chip 13, a bridge chip 13' stacked on the plurality of memory chips 11, and a plurality of memory chips 11' stacked on the bridge chip 13'. Thus, the bridge chip 13' is positioned between the plurality of memory chips 11' and the plurality of memory chips 11, and the bridge chip 13 is positioned between the plurality of memory chips 11 and the plurality of memory chips 12. 【0098】 The chip stack C of this embodiment includes through electrodes 21', 23', 24', and 25'. Each of the through electrodes 21', 23', 24', and 25' penetrates one or more chips in the chip stack C in the Z direction. The through electrode 21' is provided to electrically connect a plurality of memory chips 11' and an IF chip 14. The through electrode 23' is provided to electrically connect a bridge chip 13' and an IF chip 14. The through electrode 24' is provided to electrically connect a plurality of memory chips 11' and a bridge chip 13'. The through electrode 25' is provided to electrically connect a plurality of memory chips 11 and a bridge chip 13'. 【0099】 The IF chip 14 of this embodiment includes metal pads 31' and 33' on its upper surface. The metal pad 31' is electrically connected to the through electrode 21' by a bump 42. The metal pad 33' is electrically connected to the through electrode 23' by a bump 42. 【0100】 As described above, the memory chips 11', 11, and 12 of this embodiment are mounted on the substrate 41 in the form of a chip stack C. This makes it possible to reduce the area of ​​the semiconductor device 3 in a plan view, and thus makes it possible to miniaturize the semiconductor device 3. 【0101】 Furthermore, the bridge chips 13' and 13 of this embodiment are positioned as part of the chip stack C, between multiple memory chips 11' and multiple memory chips 11, or between multiple memory chips 11 and multiple memory chips 12. This makes it possible to perform data transfer between memory chips 11', 11, and 12 of different types using the bridge chips 13' and 13, and also makes it possible to suppress an increase in the area of ​​the semiconductor device 3 due to the bridge chips 13' and 13. 【0102】 Note that the through electrodes 21', 23', 24', and 25' shown in Figure 20 have the same structure as the through electrode 21 of the second example shown in Figure 3(b), but they may instead have the same structure as the through electrode 21 of the first example shown in Figure 3(a). When the semiconductor device 3 of this embodiment is manufactured as in the first example shown in Figures 4 to 10, the process shown in Figure 6 is also applied to each memory chip 11' and bridge chip 13'. On the other hand, when the semiconductor device 3 of this embodiment is manufactured as in the second example shown in Figures 11 to 18, the process shown in Figure 13 is also applied to each memory chip 11' and bridge chip 13'. 【0103】 As described above, the semiconductor device 3 of this embodiment includes memory chips 11', 11, and 12 of different types, and bridge chips 13' and 13 that electrically connect these memory chips 11', 11, and 12. Furthermore, the semiconductor device 3 of this embodiment includes a chip stack C that includes the memory chips 11', 11, and 12 and the bridge chips 13' and 13 stacked on a substrate 41. 【0104】 Therefore, according to this embodiment, similar to the first embodiment, it is possible to mount multiple types of memory chips 11', 11, and 12 on the substrate 41 in a preferred manner. 【0105】 In addition, the semiconductor device 3 of the first or second embodiment may include N+1 memory chips of different types and N bridge chips that electrically connect these N+1 memory chips, as shown in Figure 1 or Figure 19 (where N is an integer of 3 or more). When such a configuration is applied to Figure 2 or Figure 20, the semiconductor device 3 of the first or second embodiment may include multiple memory chips of the same type. In other words, the semiconductor device 3 of the first or second embodiment may include N+1 types of memory chips and N bridge chips that electrically connect these N+1 types of memory chips, as shown in Figure 2 or Figure 20. In this case, each bridge chip is placed between one or more memory chips of one type and one or more memory chips of another type. If the number of memory chips in the semiconductor device 3 in this case is K, then the relationship K≧N+1 holds between N and K. 【0106】 Furthermore, the semiconductor device 3 of the first embodiment may include both non-volatile memory chips and volatile memory chips, similar to the semiconductor device 3 of the second embodiment. Conversely, the semiconductor device 3 of the second embodiment may include only non-volatile memory chips, similar to the semiconductor device 3 of the first embodiment. 【0107】 (Third embodiment) Figure 21 is a block diagram showing the configuration of the information processing device according to the third embodiment. 【0108】 The information processing device of this embodiment (Figure 21) has the same components as the information processing device of the first embodiment (Figure 1). However, the storage 3 of this embodiment further includes a capacitor 15. In Figure 21, the capacitor 15 is electrically connected to the metal pad 34 of the IF chip 14. The capacitor 15 is, for example, a thin capacitor such as a silicon capacitor. 【0109】 Further details of the storage 3 in this embodiment will be described below. In the following description, the storage 3 in this embodiment will also be referred to as the "semiconductor device 3". 【0110】 Figure 22 is a cross-sectional view showing the structure of the semiconductor device 3 of the third embodiment. 【0111】 The semiconductor device 3 of this embodiment (Figure 22) has the same components as the semiconductor device 3 of the first embodiment (Figure 2). However, the semiconductor device 3 of this embodiment further includes a plurality of capacitors 15, as shown in Figure 22. Each capacitor 15 shown in Figure 22 corresponds to the capacitor 15 shown in Figure 21 and has the same structure and function as the capacitor 15 shown in Figure 21. 【0112】 The semiconductor device 3 of this embodiment further comprises a plurality of through electrodes 27, a plurality of through electrodes 28, and a plurality of bumps 45. Each through electrode 27 is an example of a seventh electrode. Each through electrode 28 is an example of an eighth electrode. Note that Figure 22 omits the illustration of the through electrode 26. The through electrodes 27 and 28 are provided within the chip stack C, similar to the through electrodes 21 to 26. The through electrode 26 is provided, for example, in an XZ cross-section different from the XZ cross-section shown in Figure 22. 【0113】 Each through-electrode 27 is electrically connected to a plurality of memory chips 11, a plurality of memory chips 12, a bridge chip 13, and an IF chip 14. Each through-electrode 27 is further electrically connected to a corresponding capacitor 15. In this embodiment, each through-electrode 27 is, for example, a power supply wire (VDD wire). 【0114】 Each through-electrode 28 is electrically connected to a plurality of memory chips 11, a plurality of memory chips 12, and a bridge chip 13. Each through-electrode 28 is further electrically connected to a corresponding capacitor 15. In this embodiment, each through-electrode 28 is, for example, a ground wire (GND wire). 【0115】 Each bump 45 is provided on the upper surface of the corresponding capacitor 15. In Figure 22, multiple bumps 45 are provided on the upper surface of each capacitor 15. Specifically, each capacitor 15 is provided with a bump 45 that electrically connects the capacitor 15 to the through electrode 27 and a bump 45 that electrically connects the capacitor 15 to the through electrode 28. 【0116】 Each capacitor 15 is electrically connected to the corresponding through electrode 27 via a bump 45, and also electrically connected to the corresponding through electrode 28 via a bump 45. Each capacitor 15 has two capacitor electrodes (not shown), one of which is electrically connected to the through electrode 27 and the IF chip 14, and the other capacitor electrode is electrically connected to the through electrode 28. With each capacitor 15 of this embodiment, it is possible to suppress noise between the through electrode 27 (power supply wiring) and the through electrode 28 (grounding wiring). 【0117】 Figure 22, like Figure 2, shows multiple wirings 51. The multiple wirings 51 shown in Figure 22 include wirings 51 electrically connected to the through-electrode 27 for the capacitor 15 on the left side of Figure 22, and wirings 51 electrically connected to the through-electrode 27 for the capacitor 15 on the right side of Figure 22. The through-electrode 27 for the capacitor 15 on the left side is electrically connected to the IF chip 14 via the former wirings 51, and the through-electrode 27 for the capacitor 15 on the right side is electrically connected to the IF chip 14 via the latter wirings 51. Note that Figure 22 omits the illustration of the through-electrode 26 and the illustration of the wiring 51 for the through-electrode 26. The wiring 51 for the through-electrode 26 is provided, for example, in an XZ cross-section different from the XZ cross-section shown in Figure 22. 【0118】 In Figure 22, each wiring 51 is located beneath the chip stack C and is positioned between the substrate 41 and the chip stack C. Each wiring 51 is positioned on a corresponding bump 43 and is electrically connected to a corresponding external connection terminal 44 via the bump 43 and the wiring layer 41b. Each wiring 51 is electrically connected to the chip stack C, the IF chip 14, and the corresponding external connection terminal 44. The details of each wiring 51 shown in Figure 22 are generally the same as the details of each wiring 51 shown in Figure 2. 【0119】 In Figure 22, each capacitor 15 is located beneath the chip stack C and is positioned between the substrate 41 and the chip stack C. Each capacitor 15 is attached to the lower surface of the through electrodes 27 and 28 via bumps 45. 【0120】 Note that the through electrodes 27 and 28 shown in Figure 22 have the same structure as the through electrode 21 in the second example shown in Figure 3(b), but they may instead have the same structure as the through electrode 21 in the first example shown in Figure 3(a). When the semiconductor device 3 of this embodiment is manufactured as in the first example shown in Figures 4 to 10, each capacitor 15 is placed on the chip stack C in the process shown in Figure 7. On the other hand, when the semiconductor device 3 of this embodiment is manufactured as in the second example shown in Figures 11 to 18, each capacitor 15 is placed on the chip stack C in the process shown in Figure 15. 【0121】 As described above, the semiconductor device 3 of this embodiment comprises memory chips 11 and 12 of different types and a bridge chip 13 that electrically connects the memory chips 11 and 12. Furthermore, the semiconductor device 3 of this embodiment comprises a chip stack C including the memory chips 11 and 12 and the bridge chip 13 stacked on a substrate 41. Furthermore, the semiconductor device 3 of this embodiment comprises a capacitor 15 between the through-electrode 27 and the through-electrode 28. 【0122】 Therefore, according to this embodiment, similar to the first embodiment, it is possible to mount multiple types of memory chips 11 and 12 on the substrate 41 in a suitable manner. Furthermore, according to this embodiment, it is possible to suppress noise between the through-electrode 27 and the through-electrode 28 with the capacitor 15. 【0123】 In addition, the capacitor 15 of this embodiment may be applied to the semiconductor device 3 of the second embodiment instead of the semiconductor device 3 of the first embodiment. Furthermore, the capacitor 15 of this embodiment may be placed in a position other than the position shown in Figure 22. 【0124】 Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus described herein can be implemented in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the apparatus described herein without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of Symbols] 【0125】 1: Processor, 2: Memory, 3: Storage (semiconductor device), 4: Bus, 5: Bus, 11: Memory chip, 11': Memory chip, 12: Memory chip, 13: Bridge tip, 13': Bridge tip, 14: IF chip, 15: Capacitor, 21: Through electrode, 21': Through electrode, 22: Through electrode, 23: Through electrode, 23': Through electrode, 24: Through electrode, 24': Through electrode, 25: Through electrode, 25': Through electrode, 26: Through electrode, 27: Through electrode, 28: Through electrode, 31: Metal pad, 31': Metal pad, 32: Metal pad, 33: Metal pad, 33': Metal pad, 34: Metal pad, 41: substrate, 41a: insulating substrate, 41b: wiring layer, 41c: resin layer, 42: Bump, 43: Bump, 44: External connection terminal, 45: Bump, 51: Wiring, 52: Resin layer, 53: Resin layer, 54: Resin layer, 61: Electrode, 62: Pad, 63: Bump, 71: Support substrate, 72: Resin layer, 73: Support substrate, 74: Support substrate, 75: Resin layer, 81: Support substrate, 82: Support substrate

Claims

[Claim 1] circuit board and The system comprises a chip stack including a plurality of chips stacked on the substrate, The aforementioned multiple chips are First memory chip and A second memory chip of a different type from the first memory chip, The first memory chip and the second memory chip are electrically connected by a first bridge chip, Semiconductor equipment. [Claim 2] The first memory chip is positioned above the substrate, The second memory chip is positioned between the substrate and the first memory chip. The first bridge chip is positioned between the first memory chip and the second memory chip and transfers data between the first memory chip and the second memory chip. The semiconductor device according to claim 1. [Claim 3] The semiconductor device according to claim 1, wherein the first memory chip and the second memory chip differ in at least one of the data retention method, memory capacity, and access speed. [Claim 4] The semiconductor device according to claim 1, wherein the memory capacity of the first memory chip is greater than the memory capacity of the second memory chip, and the access speed of the first memory chip is slower than the access speed of the second memory chip. [Claim 5] An external connection terminal provided beneath the aforementioned circuit board, An interface (IF) chip is disposed between the substrate and the chip stack, electrically connected to the first memory chip, the second memory chip, the first bridge chip, and the external connection terminal, and functions as an interface between the first memory chip, the second memory chip, the first bridge chip, and the external connection terminal. The semiconductor device according to claim 1, further comprising: [Claim 6] The aforementioned chip stack is A first electrode electrically connects the first memory chip and the IF chip, A second electrode electrically connects the second memory chip and the IF chip, A third electrode electrically connects the first bridge chip and the IF chip, A fourth electrode electrically connects the first memory chip and the bridge chip, A fifth electrode electrically connects the second memory chip and the bridge chip, A sixth electrode electrically connects the first memory chip, the second memory chip, and the bridge chip to the external connection terminal, The semiconductor device according to claim 5, including [Claim 7] One of the first to sixth electrodes includes a plurality of electrodes provided within each of the plurality of chips, and a plurality of bumps provided alternately with the plurality of electrodes. The semiconductor device according to claim 6, wherein one of the plurality of electrodes and one of the plurality of bumps are electrically connected via a pad. [Claim 8] One of the first to sixth electrodes includes a plurality of electrodes provided within each of the plurality of chips, The semiconductor device according to claim 6, wherein one of the plurality of electrodes and another of the plurality of electrodes are electrically connected via a pad. [Claim 9] The semiconductor device according to claim 6, further comprising wiring provided beneath the chip stack and electrically connected to the sixth electrode, the IF chip, and the external connection terminal. [Claim 10] The system further includes a bump provided beneath the aforementioned wiring, which electrically connects the wiring to the external connection terminal, The semiconductor device according to claim 9, wherein the bump is electrically connected to the external connection terminal via a wiring layer in the substrate. [Claim 11] The aforementioned IF chip is A first pad electrically connected to the first electrode, A second pad electrically connected to the second electrode, A third pad electrically connected to the third electrode, A fourth pad electrically connected to the external connection terminal, The semiconductor device according to claim 6, including the following: [Claim 12] The semiconductor device according to claim 11, further comprising wiring provided beneath the chip stack and electrically connected to the sixth electrode, the fourth pad, and the external connection terminal. [Claim 13] The aforementioned multiple chips further, A third memory chip that is of a different type from the first memory chip and also of a different type from the second memory chip, A second bridge chip electrically connects the first memory chip and the third memory chip, A semiconductor device according to claim 1, including the above. [Claim 14] The third memory chip is positioned above the substrate, The first memory chip is positioned between the substrate and the third memory chip. The second memory chip is positioned between the substrate and the first memory chip. The first bridge chip is positioned between the first memory chip and the second memory chip and transfers data between the first memory chip and the second memory chip. The second bridge chip is positioned between the first memory chip and the third memory chip and transfers data between the first memory chip and the third memory chip. The semiconductor device according to claim 13. [Claim 15] The semiconductor device according to claim 13, wherein the first memory chip, the second memory chip, and the third memory chip differ in at least one of the data retention method, memory capacity, and access speed. [Claim 16] The aforementioned chip stack is A seventh electrode electrically connected to the first memory chip, the second memory chip, the bridge chip, and the IF chip, The first memory chip, the second memory chip, and the eighth electrode electrically connected to the bridge chip, The semiconductor device according to claim 5, further comprising capacitors electrically connected to the seventh electrode and the eighth electrode. [Claim 17] The semiconductor device according to claim 16, further comprising wiring provided beneath the chip stack and electrically connected to the seventh electrode, the IF chip, and the external connection terminal. [Claim 18] The semiconductor device according to claim 16, wherein the seventh electrode is a power supply wire and the eighth electrode is a ground wire. [Claim 19] First memory chip and A second memory chip of a different type from the first memory chip, A first bridge chip electrically connects the first memory chip and the second memory chip and transfers data between the first memory chip and the second memory chip, A semiconductor device equipped with a semiconductor device. [Claim 20] A third memory chip that is of a different type from the first memory chip and also of a different type from the second memory chip, A second bridge chip electrically connects the first memory chip and the third memory chip and transfers data between the first memory chip and the third memory chip, The semiconductor device according to claim 19, further comprising:

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