Semiconductor memory

Abstract

To provide a semiconductor memory device that operates optimally. [Solution] The semiconductor memory device comprises a plurality of semiconductor layers and a plurality of insulating layers stacked alternately in the stacking direction and extending in a first direction; a plurality of conductive layers stacked in the stacking direction and connected to the ends of the plurality of semiconductor layers; a plurality of first via electrodes aligned in the first direction and facing the plurality of semiconductor layers; a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of first via electrodes; and a plurality of second via electrodes provided between the plurality of conductive layers and the plurality of first via electrodes, aligned in the first direction and facing the plurality of semiconductor layers. In a first cross-section, the surface of the second via electrode facing one of the plurality of semiconductor layers is along a first circle, and the surface of the second via electrode opposite to the plurality of semiconductor layers is along a second circle. In a second cross-section, the outer circumferential surface of the second via electrode is along a third circle. The radius of at least one of the first circle and the second circle is different from the radius of the third circle.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that comprises a plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, a plurality of via electrodes aligned in the first direction and stretched in the stacking direction, facing the plurality of semiconductor layers, and a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of first via electrodes. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-076886 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] To provide a semiconductor memory device that operates optimally. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment comprises: a plurality of semiconductor layers and a plurality of insulating layers alternately stacked in the stacking direction and extending in a first direction intersecting the stacking direction; a plurality of conductive layers stacked in the stacking direction corresponding to the plurality of semiconductor layers, extending in a second direction intersecting the stacking direction and the first direction, and connected to the ends of the plurality of semiconductor layers in the first direction; a plurality of first via electrodes aligned in the first direction along the sides of the plurality of semiconductor layers in the second direction, extending in the stacking direction, and facing the plurality of semiconductor layers; a plurality of charge storage layers provided between the plurality of semiconductor layers and the plurality of first via electrodes; and a plurality of second via electrodes provided between the plurality of conductive layers and the plurality of first via electrodes, aligned in the first direction along the sides of the plurality of semiconductor layers in the second direction, extending in the stacking direction, and facing the plurality of semiconductor layers. In a first cross-section extending in the first and second directions and including one of the plurality of semiconductor layers, the surface of the second via electrode facing one of the plurality of semiconductor layers is along a first circle, and the surface of the second via electrode opposite to the plurality of semiconductor layers is along a second circle. In a second cross-section extending in a first and second direction and including one of a plurality of insulating layers, the outer surface of the second via electrode aligns with a third circle. The radius of the first circle and at least one of the second circle are different from the radius of the third circle. [Brief explanation of the drawing]

[0006] [Figure 1] This is a schematic perspective view showing a part of the configuration of a semiconductor memory device according to the first embodiment. [Figure 2] This is a schematic circuit diagram showing a part of the configuration of the semiconductor memory device. [Figure 3] This is a schematic plan view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 4] This is a schematic cross-sectional view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 5] This is a schematic cross-sectional view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 6] This is a schematic plan view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 7]This is a schematic plan view showing a portion of the configuration of the memory cell array layer (LMCA). [Figure 8] This is a schematic circuit diagram illustrating the writing operation of the semiconductor memory device according to this embodiment. [Figure 9] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the second embodiment. [Figure 10] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the third embodiment. [Figure 11] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the fourth embodiment. [Figure 12] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the fifth embodiment. [Figure 13] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. [Figure 14] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the seventh embodiment. [Figure 15] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the eighth embodiment. [Figure 16] This is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the eighth embodiment. [Figure 17] This is a schematic plan view illustrating the method for manufacturing a semiconductor memory device according to the eighth embodiment. [Figure 18] This is a schematic plan view illustrating the manufacturing method. [Figure 19] This is a schematic plan view illustrating the manufacturing method. [Figure 20] This is a schematic plan view illustrating the manufacturing method. [Figure 21] This is a schematic plan view illustrating the manufacturing method. [Figure 22] This is a schematic plan view showing a partial configuration of a semiconductor memory device according to the ninth embodiment. [Modes for carrying out the invention]

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and some components may be omitted for illustrative purposes. Also, common parts in multiple embodiments are denoted by the same reference numerals, and their descriptions may be omitted.

[0008] Furthermore, in this specification, the term "semiconductor memory device" may refer to a memory die, or to a memory system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a configuration including a host computer, such as a smartphone, tablet device, or personal computer.

[0009] Furthermore, in this specification, when we say that the first configuration is "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration, or it may be connected to the second configuration via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

[0010] Furthermore, in this specification, when it is said that the first configuration is "connected between" the second and third configurations, it may mean that the first, second, and third configurations are connected in series, and that the second configuration is connected to the third configuration via the first configuration.

[0011] Furthermore, in this specification, when it is said that a circuit "conducts" two wires, it may mean, for example, that the circuit includes a transistor, that this transistor is located in the current path between the two wires, and that this transistor is in the ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is referred to as the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction perpendicular to the upper surface of the substrate is referred to as the Z direction.

[0013] Furthermore, in this specification, the direction along a predetermined plane may be referred to as the first direction, the direction intersecting the first direction along this predetermined plane may be referred to as the second direction, and the direction intersecting this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] Furthermore, in this specification, expressions such as "top" and "bottom" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "top," and the direction approaching the substrate along the Z direction is called "bottom." Also, when referring to the bottom surface or bottom end of a configuration, it means the surface or end of that configuration that is on the substrate side, and when referring to the top surface or top end, it means the surface or end of that configuration that is on the opposite side from the substrate. In addition, surfaces that intersect with the X direction or Y direction are called sides, etc.

[0015] [First Embodiment] [composition] Figure 1 is a schematic perspective view showing a part of the configuration of a semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a semiconductor substrate Sub and a memory cell array layer L provided above the semiconductor substrate Sub. MCA It is equipped with the following.

[0016] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing P-type impurities such as boron (B). On the upper surface of the semiconductor substrate Sub is a memory cell array layer L. MCA It is also acceptable to include some peripheral circuits that control the internal configuration.

[0017] Memory cell array layer L MCA It comprises multiple memory layers ML and multiple insulating layers 101 that are alternately stacked in the Z direction. The insulating layers 101 include, for example, silicon oxide (SiO2).

[0018] Figure 2 is a schematic circuit diagram showing a part of the configuration of the semiconductor memory device according to this embodiment.

[0019] Memory cell array layer L according to this embodiment MCA This functions as a memory cell array MCA. The memory cell array MCA comprises multiple string units SU. Each string unit SU comprises multiple memory units MU, which correspond to multiple memory layers ML. Each of the multiple memory units MU comprises two memory strings MS. Each of these two memory strings MS comprises multiple memory cells MC (memory transistors) connected in series. One end of these two memory strings MS is connected to the bit line BL via a common drain-side selection transistor STD. The other end of these two memory strings MS is connected to the source line SL via a common source-side selection transistor STS. Hereinafter, the drain-side selection transistor STD and the source-side selection transistor STS may simply be referred to as selection transistors STD and STS.

[0020] A memory cell MC is a field-effect transistor. The memory cell MC comprises a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating layer includes a charge storage layer. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage layer. The memory cell MC stores one or more bits of data. Each gate electrode of multiple memory cell MCs contained within a single memory unit MU is connected to a word line WL. These word lines WL are each commonly connected to all memory units MU in multiple string units SU.

[0021] The selection transistors STD and STS are field-effect transistors. The selection transistors STD and STS include a semiconductor layer, a gate insulating layer, and a gate electrode. The semiconductor layer functions as a channel region. Selection gate lines SGD and SGS are respectively connected to the gate electrodes of the selection transistors STD and STS. The drain-side selection gate line SGD is commonly connected to all the memory units MU in the corresponding string unit SU. The source-side selection gate line SGS is commonly connected to all the memory units MU in the corresponding string unit SU.

[0022] FIG. 3 is a schematic plan view showing a partial configuration of the memory cell array layer L MCA FIGS. 4 and 5 are schematic cross-sectional views showing a partial configuration of the memory cell array layer L MCA FIG. 4 shows a view obtained by cutting the structure shown in FIG. 3 along the line A-A' and viewing it along the direction of the arrow. FIG. 5 shows a view obtained by cutting the structure shown in FIG. 3 along the lines B-B' and C-C' and viewing it along the direction of the arrow. FIGS. 6 and 7 are schematic plan views showing a partial configuration of the memory cell array layer L MCA FIG. 6 shows an XY cross-section at the height position corresponding to the memory layer ML. FIG. 7 shows an XY cross-section at the height position corresponding to the insulating layer 101.

[0023] The memory cell array layer L MCA As shown in FIG. 3, includes bit line regions R BL arranged in order in the Y direction, selection transistor regions R SGD memory cell regions R MC selection transistor regions R SGS and source line regions R SL

[0024] The memory layer ML includes a plurality of semiconductor layers 110 arranged in the X direction and extending in the Y direction. Each of these plurality of semiconductor layers 110 is respectively in the selection transistor region R SGD memory cell region R MC selection transistor region R SGS and source line region R SL ​It extends in the Y direction over the bit line region R BL The semiconductor layer 110 functions, for example, as the channel region of multiple memory cells MC (Figure 2) connected in series, and the selection transistors STD and STS connected thereto. The semiconductor layer 110 may also contain, for example, undoped polycrystalline silicon (Si).

[0025] An insulating layer 111 is provided between two semiconductor layers 110 aligned in the X direction. The insulating layer 111 may contain, for example, silicon oxide (SiO2). The insulating layer 111 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 1, for example.

[0026] Memory cell region R MC Multiple via electrodes 120 are provided along the Y-direction along one and the other side surfaces of the semiconductor layer 110 in the X-direction. In the illustrated example, the multiple via electrodes 120 are arranged in the Y-direction with a pitch p1 on one and the other side of the semiconductor layer 110 in the X-direction. Also, the memory cell region R MC In this configuration, the memory layer ML comprises a plurality of gate insulating layers 130 provided between a plurality of via electrodes 120 and a semiconductor layer 110.

[0027] In the XY cross-section illustrated in Figure 6, a portion of the outer surface of the via electrode 120 faces the semiconductor layer 110 via the gate insulating layer 130, and the remaining portion faces the insulating layer 111. The outer surface of the via electrode 120 is aligned with a circle c1 concentric with the via electrode 120. The contact surface of the gate insulating layer 130 with the semiconductor layer 110 is aligned with a circle c2 concentric with circle c1. The radius of circle c2 is larger than the radius of circle c1. Furthermore, the outer surface of the via electrode 120 is aligned with circle c1 even in the XY cross-section illustrated in Figure 7.

[0028] The via electrode 120 functions, for example, as the gate electrode of multiple memory cells MC and the word line WL connected thereto. The via electrode 120 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The via electrode 120 extends in the Z direction, penetrating multiple memory layers ML, as shown in Figure 1, for example.

[0029] As shown in Figure 4, the gate insulating layer 130 includes, for example, a tunnel insulating layer 131 provided on the X-direction side of the semiconductor layer 110, a charge storage layer 132 provided on the X-direction side, and a block insulating layer 133 provided on the X-direction side.

[0030] The tunnel insulating layer 131 may contain, for example, silicon oxide (SiO2).

[0031] The charge storage layer 132 may contain, for example, polycrystalline silicon (Si). Furthermore, this polycrystalline silicon (Si) may contain N-type impurities such as phosphorus (P) or P-type impurities such as boron (B), or it may not contain these impurities.

[0032] The block insulating layer 133 may contain, for example, silicon oxide (SiO2). Alternatively, the block insulating layer 133 may contain aluminum oxide (AlO), hafnium oxide (HfO), or other insulating metal oxide films (ferroelectric films).

[0033] Selected transistor region R SGD Figure 3 shows a plurality of via electrodes 140 and 141 arranged in the Y direction along one side surface in the X direction of the semiconductor layer 110, and a via wiring 150 provided on the opposite side of the center line CL from these plurality of via electrodes 140 and 141. Also, a selected transistor region R SGD In this configuration, the memory layer ML comprises a semiconductor layer 160 connected to one end in the Y direction of a plurality of semiconductor layers 110.

[0034] The center line CL referred to here is the center line of the semiconductor layer 110 in the XY cross-section. The center line CL is a hypothetical straight line extending in the Y direction. The position of the center line CL in the X direction can be defined, for example, by the average value of the central positions in the X direction of multiple via electrodes 120 facing one side surface of the semiconductor layer 110 in the X direction, and the average value of the central positions in the X direction of multiple via electrodes 120 facing the other side surface of the semiconductor layer 110 in the X direction.

[0035] In the XY cross-section illustrated in Figure 6, a portion of the outer surface of via electrodes 140 and 141 faces the semiconductor layer 110, and the remaining portion faces the insulating layer 111. The surfaces of via electrodes 140 and 141 facing the semiconductor layer 110 are aligned with circle c4. The surfaces of via electrodes 140 and 141 facing the insulating layer 111 are aligned with circle c3, which is concentric with circle c4. The radius of circle c4 is greater than the radius of circle c3.

[0036] Furthermore, the outer surfaces of via electrodes 140 and 141 are aligned with circle c3 even in the XY cross-section as illustrated in Figure 7. In the cross-section as illustrated in Figure 7, circle c3 is concentric with via electrodes 140 and 141. The radius of circle c3 may be approximately the same as the radius of circle c1. In addition, multiple circles c1 and multiple circles c3 may be arranged in the Y direction with a pitch p1, as shown in Figure 3.

[0037] Selected transistor region R SGD The via electrode 140 inside functions, for example, as the gate electrode of a plurality of drain-side selection transistors STD, and the drain-side selection gate line SGD connected thereto. The via electrode 140 may include, for example, a barrier conductive layer such as titanium nitride (TiN) and a conductive layer such as tungsten (W). The via electrode 140 extends in the Z direction, penetrating a plurality of memory layers ML, as shown in Figure 5, for example. In addition, an insulating layer 142 such as silicon oxide (SiO2) or aluminum oxide (Al2O3) is provided on the outer surface of the via electrode 140.

[0038] As shown in Figure 3 or Figure 6, the via electrode 141 is positioned between the multiple via electrodes 140 and the semiconductor layer 160. The via electrode 141 is basically configured similarly to the via electrode 140. However, it is possible to supply a different voltage to the via electrode 141 than to the via electrode 140.

[0039] The via wiring 150 functions, for example, as contact wiring for supplying holes to the semiconductor layer 110. The via wiring 150 may include, for example, polycrystalline silicon (Si) containing P-type impurities such as boron (B), and may include a semiconductor column formed in a cylindrical or cylindrical shape. Furthermore, this semiconductor column may be in contact with a plurality of semiconductor layers 110 stacked in the Z direction. The via wiring 150 extends in the Z direction, penetrating a plurality of memory layers ML, as shown in Figure 5, for example.

[0040] The semiconductor layer 160 may include, for example, a semiconductor layer such as polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P), and may be in contact with the semiconductor layer 110.

[0041] Bit line region R BL In Figure 3, the memory layer ML includes a conductive layer 170. Also, the bit line region R BL The conductive layer 170 is provided with a plurality of insulating layers 171 arranged in the X direction.

[0042] The conductive layer 170 functions, for example, as a bit line BL (Figure 2). The conductive layer 170 may contain, for example, titanium nitride (TiN). The conductive layer 170 is stretched in the X direction and is electrically connected to a plurality of semiconductor layers 110 via a plurality of semiconductor layers 160.

[0043] The insulating layer 171 may contain, for example, silicon oxide (SiO2). The insulating layer 171 extends in the Z direction, penetrating multiple memory layers ML.

[0044] Selected transistor region R SGSFigure 3 shows a plurality of via electrodes 140 arranged in the Y direction along one side of the semiconductor layer 110 in the X direction, and a via wiring 150 provided on the opposite side of the center line CL from these plurality of via electrodes 140.

[0045] Selected transistor region R SGS The via electrode 140 inside functions, for example, as the gate electrode of multiple source-side selection transistors STS, and the source-side selection gate line SGS connected thereto.

[0046] Source line region R SL A via wiring 180 is provided there.

[0047] The via wiring 180 functions, for example, as a source wire SL. The via wiring 180 may contain, for example, polycrystalline silicon (Si) containing N-type impurities such as phosphorus (P), and may include a semiconductor column formed in a cylindrical or cylindrical shape. This semiconductor column may also be in contact with a plurality of semiconductor layers 110 stacked in the Z direction. The via wiring 180 extends in the Z direction, penetrating a plurality of memory layers ML.

[0048] [Write operation] Figure 8 is a schematic circuit diagram illustrating the writing operation of the semiconductor memory device according to this embodiment.

[0049] During a write operation, multiple memory cells MC connected to a single word line WL within a single string unit SU become selected memory cells MC. Hereafter, such a single word line WL will be referred to as the "selected word line WL". S They call this "" and the remaining word lines WL "unselected word lines WL" U It is sometimes called "..."

[0050] During the write operation, for example, an electric field is generated between the control gate electrode and the channel in some of the multiple selective memory cells MC, causing electrons in the channel of the semiconductor layer 110 to tunnel into the charge storage layer 132 (Figure 4), thereby increasing the threshold voltage of these selected memory cells MC.

[0051] Hereinafter, among the selected memory cells (MCs), those whose threshold voltage is a certain distance away from the target value will be referred to as "write memory cells (MCs)." Also, the bit line BL connected to the write memory cell (MC) will be referred to as the bit line BL. W This is called a "weak write memory cell MC". Furthermore, among the selected memory cells MCs, those whose threshold voltage is relatively close to the target value are called "weak write memory cell MCs". Also, the bit line BL connected to the weak write memory cell MC is called a bit line BL. QPW It is called that.

[0052] Furthermore, during the write operation, the threshold voltage of only some of the selected memory cells (MCs) is increased, while the threshold voltage of the remaining selected memory cells (MCs) is not increased. Hereafter, such selected memory cells (MCs) whose threshold voltage is not increased will be referred to as "forbidden memory cells (MCs)." Also, the bit line BL connected to the forbidden memory cell (MC) will be referred to as the bit line BL. P It is called that.

[0053] In the write operation, for example, bit line BL W Voltage V SRC It supplies bit lines BL. QPW Voltage V QPW It supplies bit lines BL. P Voltage V DD It supplies voltage V. DD is the voltage V SRC ,V QPW Larger than. Voltage V QPW is the voltage V SRC Larger than, voltage V DD It is smaller than that.

[0054] Furthermore, during the write operation, a voltage V is applied to the drain-side selected gate line SGD corresponding to the string unit SU that is the target of the write operation. SGD It supplies voltage V to the other drain-side selected gate line SGD. OFF To supply.

[0055] Voltage V SGD is the voltage V SRC ,V QPW It is larger than that. Also, the voltage VSGD And, voltage V SRC ,V QPW The voltage difference between and is greater than the threshold voltage required to make the drain-side selection transistor STD function as an NMOS transistor. Therefore, the bit line BL W BL QPW An electron channel is formed in the channel region of the drain-side select transistor STD connected to it, and the voltage V SRC ,V QPW It will be forwarded.

[0056] On the other hand, voltage V SGD and voltage V DD The voltage difference is smaller than the threshold voltage required to make the drain-side selection transistor STD function as an NMOS transistor. Therefore, bit line BL P The drain-side selection transistor STD connected to it will be in the OFF state.

[0057] Voltage V OFF The voltage V is such that the drain-side selection transistor STD is in the OFF state regardless of the voltage of the bit line BL. OFF For example, it may have a negative magnitude.

[0058] Furthermore, during the writing operation, a voltage V is applied to the source line SL. SRC A ground voltage V is supplied to the source-side selected gate line SGS. SS A voltage V is supplied. SRC And the ground voltage V SS The voltage difference between and is smaller than the threshold voltage required for the source-side selection gate line SGS to function as an NMOS transistor. Therefore, the source-side selection transistor STS remains in the OFF state.

[0059] Furthermore, during the write operation, the non-selected word line WL U Write path voltage V PASS It supplies the write path voltage V. PASS and voltage V SRC ,V QPWThe voltage difference is greater than the threshold voltage required for the memory cell MC to function as an NMOS transistor, regardless of the data recorded in the memory cell MC. Therefore, the bit line BL W BL QPW In the channel region of the electrically connected non-selective memory cell MC, an electron channel is formed, and in the write memory cell MC and the weak write memory cell MC, a voltage V SRC ,V QPW It will be forwarded.

[0060] Furthermore, during the writing operation, the selected word line WL S Program voltage V PGM It supplies the program voltage V. PGM The write path voltage V PASS It is larger than that.

[0061] Here, bit line BL W The channel of the semiconductor layer 110 connected to it has a voltage V SRC Such a semiconductor layer 110 and a selected word line WL are supplied. S A relatively large electric field is generated between the two. As a result, electrons in the channel of the semiconductor layer 110 tunnel through the tunnel insulating layer 131 (Figure 4) into the charge storage layer 132 (Figure 4). This causes the threshold voltage of the write memory cell MC to increase relatively significantly.

[0062] Also, bit line BL QPW The channel of the semiconductor layer 110 connected to it has a voltage V QPW Such a semiconductor layer 110 and a selected word line WL are supplied. S A smaller electric field than the one described above is generated between the two points. As a result, electrons in the channel of the semiconductor layer 110 tunnel through the tunnel insulating layer 131 (Figure 4) into the charge storage layer 132 (Figure 4). This causes the threshold voltage of the weak write memory cell MC to increase relatively small.

[0063] Also, bit line BL P The channel of the semiconductor layer 110 connected to it is electrically floating, and the potential of this channel is the non-selected word line WLU has increased to a certain extent due to capacitive coupling with the write path voltage V PASS to such an extent. Between such a semiconductor layer 110 and the select word line WL S only an electric field smaller than the above-described electric field is generated. Therefore, electrons in the channel of the semiconductor layer 110 do not tunnel into the charge storage layer 132 (FIG. 4). Therefore, the threshold voltage of the prohibit memory cell MC does not increase.

[0064] [Interference between memory layers ML in the write operation] In the semiconductor memory device as described above, via electrodes 120 that function as gate electrodes of the memory cell MC and the like, and via electrodes 140 that function as select transistors and the like are provided along the side surfaces in the X direction of the semiconductor layer 110. Therefore, during read operations, write operations, etc., a channel (inversion layer) is mainly formed on the side surfaces in the X direction of the semiconductor layer 110.

[0065] Here, in the semiconductor layer 110, regions that are relatively far from the via electrodes 120 and 140 are less affected by the electric field from the via electrodes 120 and 140. On the other hand, they tend to be relatively strongly affected by the electric field from the semiconductor layer 110 in other memory layers ML adjacent in the Z direction.

[0066] For example, in a write operation, when one of two memory layers ML adjacent in the Z direction corresponds to the bit line BL W and the other corresponds to the bit line BL QPW in such a case, due to the influence of the electric field from the semiconductor layer 110 corresponding to the bit line BL W it becomes difficult to form a channel (inversion layer) in the semiconductor layer 110 corresponding to the bit line BL QPW and there is a possibility that it becomes difficult for the drain side select transistor STD to turn on. As a result, there is a possibility that the threshold voltage of the weak write memory cell MC cannot be adjusted.

[0067] Also, for example, when one of two memory layers ML adjacent in the Z direction corresponds to the bit line BL W and the other corresponds to the bit line BL PWhen corresponding thereto, focusing on the non-selected string unit SU, in the bit line BL P In the semiconductor layer 110 corresponding thereto, in a region relatively far from the via electrode 140, there is a possibility that the voltage V DD will be supplied. Also, due to the influence of the electric field from this semiconductor layer 110, a channel (inversion layer) may be formed in the semiconductor layer 110 corresponding to the bit line BL W and there is a possibility that an OFF leakage current will occur in the drain side selection transistor STD. As a result, there is a possibility that incorrect writing will occur in the string unit SU other than the operation target.

[0068] Here, for example, in order to surely turn on the drain side selection transistor STD, for example, the pitch in the Y direction where the via electrode 140 is arranged is reduced, or the area in the XY cross section of the via electrode 140 is increased, and the distance between the via electrodes 140 and the distance between the via electrode 140 - gate insulating layer 130 are reduced. However, in relation to the manufacturing method of the semiconductor memory device, there may be restrictions on the position and size of the via electrode 140.

[0069] Therefore, in the present embodiment, when manufacturing the semiconductor memory device, after forming the via hole corresponding to the via electrode 140, a part of the semiconductor layer 110 is removed, and a member of the via electrode 140 is formed here. As a result, the radius of the circle c4 corresponding to the facing surface of the via electrode 140 and the semiconductor layer 110 becomes larger than the radius of the circle c3 corresponding to the facing surface of the via electrode 140 and the insulating layer 111.

[0070] According to such a configuration, the distance between the via electrodes 140 and the distance between the via electrode 140 - gate insulating layer 130 can be reduced, and it is possible to make the electric field reach the entire side surface in the X direction of the semiconductor layer 110. As a result, even when one of the two memory layers ML adjacent in the Z direction corresponds to the bit line BL W and the other corresponds to the bit line BL QPW in the case where the bit line BL QPWIt is possible to suitably turn ON the corresponding drain-side selection transistor STD.

[0071] Furthermore, in this embodiment, the selected transistor region R SGD A via wiring 150 is provided. With this configuration, it is possible to fix the potential of a region in the semiconductor layer 110 that is relatively far from the via electrodes 120 and 140 via the via wiring 150. This allows the bit line BL P In the semiconductor layer 110 corresponding to the above, in a region relatively far from the via electrode 140, a voltage V DD This makes it possible to prevent the supply of data. This also makes it possible to suppress the occurrence of incorrect writing.

[0072] [Interference of GIDL current during write operations] As described above, during the write operation, a voltage V is applied to the drain-side selected gate line SGD (via electrode 140) of string units SU other than the target of the operation. OFF By supplying this, the drain-side selection transistor STD is turned OFF.

[0073] Here, as shown in Figures 3 and 6, for example, the via electrode 141 may be in close proximity to the semiconductor layer 160. For example, bit line PL P A voltage V is applied to the corresponding semiconductor layer 160. DD A voltage V with a negative magnitude is supplied to the via electrode 141. OFF When this is supplied, the electric field may concentrate between the semiconductor layer 160 and the via electrode 141. This can cause a sharp change in the energy band, potentially leading to GIDL (Gate Induced Drain Leakage).

[0074] Therefore, in this embodiment, the via electrode 141 is configured to be able to supply a different voltage from the via electrode 140. In addition, during the writing operation, the via electrode 141 is supplied with a voltage V DD and voltage V OFF A voltage is supplied between the two points. This method makes it possible to suppress the generation of GIDL.

[0075] [Second Embodiment] In the via electrodes 140 and 141 according to the first embodiment, the surface facing the semiconductor layer 110 is aligned with circle c4, and the surface facing the insulating layer 111 is aligned with circle c3. However, such a configuration is merely illustrative, and the specific configuration can be adjusted as appropriate.

[0076] For example, during the manufacturing of a semiconductor memory device, after forming via holes corresponding to via electrodes 140, a portion of the insulating layer 111 may be removed instead of the semiconductor layer 110. In such a case, the radius of the circle corresponding to the surface of the via electrode 140 facing the insulating layer 111 will be larger than the radius of the circle corresponding to the surface of the via electrode 140 facing the semiconductor layer 110.

[0077] The following describes an example of a semiconductor memory device according to the second embodiment.

[0078] Figure 9 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the second embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0079] The semiconductor memory device according to the second embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes via electrodes 240 and 241 instead of via electrodes 140 and 141.

[0080] Via electrodes 240 and 241 are basically constructed in the same way as via electrodes 140 and 141. However, the surfaces of via electrodes 240 and 241 facing the semiconductor layer 110 are aligned with circle c3. Also, the surfaces of via electrodes 240 and 241 facing the insulating layer 111 are aligned with circle c4.

[0081] With this configuration, as in the first embodiment, it is possible to reduce the distance between via electrodes 240 and the distance between via electrodes 240 and the gate insulating layer 130, making it easier for the electric field to reach the entire X-side surface of the semiconductor layer 110.

[0082] Furthermore, if insulating layer 111 and insulating layer 101 contain the same material, removing a portion of insulating layer 111 after forming via holes corresponding to via electrodes 240 and 241 may also remove insulating layer 101 simultaneously. In such cases, the outer surfaces of via electrodes 240 and 241 may be aligned with circle c4 in the XY cross-section as shown in Figure 7.

[0083] [Third Embodiment] In the manufacturing of the semiconductor memory device according to the first embodiment, after forming via holes corresponding to via electrodes 140 and 141, a portion of the semiconductor layer 110 is removed. Similarly, in the manufacturing of the semiconductor memory device according to the second embodiment, after forming via holes corresponding to via electrodes 240 and 241, a portion of the insulating layer 111 is removed. However, these configurations are merely examples, and the specific configuration can be adjusted as appropriate.

[0084] For example, when manufacturing a semiconductor memory device, after forming via holes corresponding to via electrodes 140 and 141, both a portion of the semiconductor layer 110 and a portion of the insulating layer 111 may be removed. For example, if the radius of circle c3 is approximately equal to the radius of c1, then the radii of the circles corresponding to the faces of the via electrodes 140 and 141 facing the semiconductor layer 110, and the radii of the circles corresponding to the faces of the insulating layer 111, will both be larger than the radius of circle c1.

[0085] The following describes an example of a semiconductor memory device according to the third embodiment.

[0086] Figure 10 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the third embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0087] The semiconductor memory device according to the third embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the third embodiment includes via electrodes 340 and 341 instead of via electrodes 140 and 141.

[0088] The via electrodes 340 and 341 are basically constructed in the same way as the via electrodes 140 and 141. However, the surfaces of the via electrodes 340 and 341 facing the semiconductor layer 110 are aligned with circle c4. Also, the surfaces of the via electrodes 340 and 341 facing the insulating layer 111 are aligned with circle c4.

[0089] With this configuration, as in the first embodiment, it is possible to reduce the distance in the Y direction between via electrodes 340 and the distance in the Y direction between via electrodes 340 and gate insulating layer 130, thereby making it easier for the electric field to reach the entire X-direction side surface of the semiconductor layer 110.

[0090] Furthermore, the surfaces of the via electrodes 340 and 341 facing the semiconductor layer 110 and the surfaces facing the insulating layer 111 may be aligned with circles having different radii. Also, the surfaces of the via electrodes 340 and 341 facing the insulating layer 111 may be aligned with a circle corresponding to the outer circumferential surface of the via electrodes 340 and 341 in an XY cross-section as shown in Figure 7.

[0091] [Fourth Embodiment] In the first to third embodiments, via electrodes 140, 141, via electrodes 240, 241, or via electrodes 340, 341 (hereinafter referred to as "via electrodes 140, etc.") are arranged in the Y direction with the same pitch p1 as via electrode 120. However, these configurations are merely examples, and the specific configuration can be adjusted as appropriate.

[0092] For example, via electrodes 140 may be arranged in the Y direction at a pitch smaller than the pitch p1. With such a configuration, after forming via holes corresponding to the via electrodes 140, it is possible to reduce the distance in the Y direction between the via electrodes 140 and the distance in the Y direction between the via electrodes 140 and the gate insulating layer 130, without removing a part of the semiconductor layer 110 or a part of the insulating layer 111, thereby making it easier for the electric field to reach the entire X-direction side surface of the semiconductor layer 110.

[0093] The following describes an example of a semiconductor memory device according to the fourth embodiment.

[0094] Figure 11 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the fourth embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0095] The semiconductor memory device according to the fourth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fourth embodiment includes via electrodes 440 and 441 instead of via electrodes 140 and 141.

[0096] The via electrodes 440 and 441 are basically configured in the same way as the via electrodes 140 and 141. However, both the surface of the via electrodes 440 and 441 facing the semiconductor layer 110 and the surface facing the insulating layer 111 are aligned along circle c3. Furthermore, in this embodiment, the circles c3 corresponding to these multiple via electrodes 440 and 441 are aligned in the Y direction with a pitch p2 smaller than the pitch p1.

[0097] [Fifth Embodiment] In manufacturing semiconductor memory devices according to the first to fourth embodiments, circular holes are formed as via holes corresponding to via electrodes 140, etc. However, these configurations are merely examples, and the shape of the via holes corresponding to via electrodes 140, etc. can be adjusted as appropriate.

[0098] For example, the shape of the via hole corresponding to via electrode 140, etc., may be an ellipse or oval (racetrack shape), or it may be a triangle, square, or other geometric shape.

[0099] The following describes an example of a semiconductor memory device according to the fifth embodiment.

[0100] Figure 12 is a schematic plan view showing a partial configuration of a semiconductor memory device according to the fifth embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0101] The semiconductor memory device according to the fifth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the fifth embodiment includes via electrodes 540 and 541 instead of via electrodes 140 and 141.

[0102] The via electrodes 540 and 541 are basically constructed in the same way as the via electrodes 140 and 141. However, both the surface facing the semiconductor layer 110 and the surface facing the insulating layer 111 of the via electrodes 540 and 541 are aligned with the ellipse c5. In the illustrated example, the perpendicular axis of the ellipse c5 extends in the Y direction. The minor axis of the ellipse c5 extends in the X direction. In the illustrated example, the size of the minor axis of the ellipse c5 is approximately equal to the diameter of the circle c1.

[0103] With this configuration, as in the first embodiment, it is possible to reduce the distance in the Y direction between via electrodes 540 and the distance in the Y direction between via electrodes 540 and gate insulating layer 130, thereby making it easier for the electric field to reach the entire X-direction side surface of the semiconductor layer 110.

[0104] [Sixth Embodiment] In the semiconductor memory devices according to the first to fifth embodiments, the selected transistor region R SGD In this configuration, via electrodes 140, etc., are provided only on one side of the semiconductor layer 110 in the X direction, while via electrodes 140, etc., are not provided on the other side in the X direction. However, such configurations are merely examples, and the arrangement of via electrodes 140, etc., can be adjusted as appropriate.

[0105] For example, via electrodes 140 may be provided not only on one side of the semiconductor layer 110 in the X direction, but also on the other side of the semiconductor layer 110 in the X direction.

[0106] The following describes an example of a semiconductor memory device according to the sixth embodiment.

[0107] Figure 13 is a schematic plan view showing a part of the configuration of a semiconductor memory device according to the sixth embodiment. In the following description, parts the same as those in the fifth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0108] The semiconductor memory device according to the sixth embodiment is basically configured the same as the semiconductor memory device according to the fifth embodiment. However, in the semiconductor memory device according to the sixth embodiment, via electrodes 540 are provided not only on one side of the semiconductor layer 110 in the X direction, but also on the other side of the semiconductor layer 110 in the X direction.

[0109] With this configuration, as in the first embodiment, it is possible to reduce the distance in the Y direction between via electrodes 540 and the distance in the Y direction between via electrodes 540 and gate insulating layer 130, thereby making it easier for the electric field to reach the entire X-direction side surface of the semiconductor layer 110.

[0110] [Seventh Embodiment] The semiconductor memory devices according to the fifth and sixth embodiments include via electrodes 540 and 541 having a shape along an ellipse c5. Here, in the fifth and sixth embodiments, the major axis of the ellipse c5 extends in the Y direction. However, the angles of the via electrodes 540 and 541 in the XY cross-section can also be adjusted as appropriate.

[0111] Below, an example of a semiconductor memory device according to the seventh embodiment in which via electrodes 540 and 541 are rotated in the XY cross-section will be described.

[0112] Figure 14 is a schematic plan view showing a partial configuration of the semiconductor memory device according to the seventh embodiment. In the following description, parts similar to those in the sixth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0113] The semiconductor memory device according to the seventh embodiment is basically configured the same as the semiconductor memory device according to the sixth embodiment. However, in the semiconductor memory device according to the seventh embodiment, the major axes of the via electrodes 540 and 541 are extended along the oblique direction in the XY cross-section. More specifically, the major axes of the via electrodes 540 and 541 are arranged to intersect at a single point on the semiconductor layer 110.

[0114] With this configuration, as in the first embodiment, it is possible to reduce the distance in the Y direction between via electrodes 540 and the distance in the Y direction between via electrodes 540 and gate insulating layer 130, thereby making it easier for the electric field to reach the entire X-direction side surface of the semiconductor layer 110.

[0115] [Eighth Embodiment] In the semiconductor memory devices according to the first to seventh embodiments, the selected transistor region R SGD A via wiring 150 is provided. With this configuration, the potential in a region of the semiconductor layer 110 that is relatively far from the via electrode 140, etc., can be fixed via the via wiring 150, thereby suppressing the occurrence of the aforementioned erroneous writing. However, such erroneous writing can also be suppressed by other methods.

[0116] For example, the semiconductor layer 110 is a selected transistor region R SGD In this configuration, if the via electrode 140 is located within a certain range, there is no region that is relatively far from the via electrode 140, etc. Therefore, the drain-side selection transistor STD can be suitably turned OFF, thereby suppressing the occurrence of the aforementioned erroneous writing.

[0117] The following describes an example of a semiconductor memory device according to the eighth embodiment.

[0118] Figures 15 and 16 are schematic plan views showing a partial configuration of the semiconductor memory device according to the eighth embodiment. In the following description, parts similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0119] The semiconductor memory device according to the eighth embodiment is basically configured the same as the semiconductor memory device according to the first embodiment. However, the semiconductor memory device according to the eighth embodiment includes a semiconductor layer 810 and an insulating layer 811 instead of the semiconductor layer 110 and insulating layer 111. Also, the semiconductor memory device according to the eighth embodiment does not include via wiring 150.

[0120] The semiconductor layer 810 and the insulating layer 811 are basically constructed in the same way as the semiconductor layer 110 and the insulating layer 111. However, the semiconductor layer 810 has a selected transistor region R SGD In this configuration, it is provided within a certain range from the via electrode 140, etc. That is, for example, as shown in Figure 16, the side of the semiconductor layer 810 opposite the via electrode 140 in the X direction is the selected transistor region R SGD In this region, it aligns with multiple circles c6 that are concentric with multiple circles c3 and c4. The radius of circle c6 is larger than the radius of circle c4, and the memory cell region R MC The width of the semiconductor layer 810 in the X direction X 810 It is smaller than [the specified value]. Also, the side of the semiconductor layer 810 on the via electrode 140 side in the X direction is aligned with multiple circles c4. Furthermore, the region between the two semiconductor layers 810 aligned in the X direction is filled with an insulating layer 811.

[0121] With this configuration, as with the first embodiment, it is possible to suppress the occurrence of the aforementioned erroneous writing.

[0122] Figures 17 to 21 are schematic plan views illustrating the method for manufacturing a semiconductor memory device according to the eighth embodiment.

[0123] In manufacturing the semiconductor memory device according to the eighth embodiment, the sacrificial layer 110A and the insulating layer 101 are stacked alternately in the Z direction. The sacrificial layer 110A includes, for example, silicon nitride (SiN). This process is carried out by, for example, a method such as CVD (Chemical Vapor Deposition).

[0124] Next, as shown in Figure 17, for example, multiple openings are formed that penetrate multiple sacrificial layers 110A and multiple insulating layers 101 which are alternately stacked in the Z direction. Opening 111A is formed at a position corresponding to insulating layer 111. Opening 120A is formed at a position corresponding to via electrode 120. Opening 140A is formed at a position corresponding to via electrodes 140 and 141. Opening 171A is formed at a position corresponding to insulating layer 171. This process is carried out by a method such as RIE (Reactive Ion Etching). Sacrificial layers such as silicon (Si) and carbon (C) are embedded inside each opening.

[0125] Next, as shown in Figure 18, for example, the memory cell region R MC The sacrificial layer inside the opening 111A is removed, a portion of the sacrificial layer 110A is removed by a method such as wet etching through the opening 111A, and a portion of the insulating layer 811 is formed by a method such as CVD.

[0126] Next, as shown in Figure 19, for example, the sacrificial layer inside the opening 120A is removed, a portion of the sacrificial layer 110A is removed by a method such as wet etching through the opening 120A, and a portion of the semiconductor layer 810 is formed by a method such as CVD. Furthermore, a portion of the semiconductor layer 810 is removed by a method such as wet etching through the opening 120A, and the gate insulating layer 130 and via electrode 120 are formed by a method such as CVD.

[0127] Next, as shown in Figure 20, for example, the sacrificial layer inside the opening 140A is removed, a portion of the sacrificial layer 110A is removed by a method such as wet etching through the opening 140A, and a portion of the semiconductor layer 810 is formed by a method such as CVD. By adjusting the amount of etching at this timing, the channel width of the drain-side selection transistor STD according to this embodiment can be adjusted. Furthermore, a portion of the semiconductor layer 810 is removed by a method such as wet etching through the opening 140A, and via electrodes 140 and 141 are formed by a method such as CVD.

[0128] Next, as shown in Figure 21, for example, the selected transistor region RSGD The sacrificial layer inside the opening 111A is removed, a portion of the sacrificial layer 110A is removed by a method such as wet etching through the opening 111A, and a portion of the insulating layer 811 is formed by a method such as CVD.

[0129] Next, for example, the sacrificial layer inside the opening 171A is removed, the sacrificial layer 110A is removed by a method such as wet etching through the opening 171A, and the semiconductor layer 160, conductive layer 170, and insulating layer 171 are formed by a method such as CVD. This forms a structure as described with reference to Figure 15.

[0130] [Ninth Embodiment] In the manufacturing of the semiconductor memory device according to the eighth embodiment, the opening 111A is embedded by a portion of the insulating layer 811 in the process described with reference to Figure 21. However, this method is merely illustrative, and via electrodes may be formed in the opening 111A in the process described with reference to Figure 21. With such a configuration, the ON and OFF operations of the drain-side selection transistor STD can be performed more stably.

[0131] The following describes an example of a semiconductor memory device according to the ninth embodiment.

[0132] Figure 22 is a schematic plan view showing a partial configuration of the semiconductor memory device according to the ninth embodiment. In the following description, parts similar to those in the eighth embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0133] The semiconductor memory device according to the ninth embodiment is basically configured the same as the semiconductor memory device according to the eighth embodiment. However, in the semiconductor memory device according to the ninth embodiment, the selected transistor region R SGD In this configuration, a via electrode 940 is provided on the opposite side of via electrodes 140 and 141 in the X direction. The via electrode 940 may be formed in the same manner as, for example, via electrode 140.

[0134] With this configuration, it becomes possible to more favorably set the drain-side selection transistor STD to either the ON or OFF state.

[0135] [others] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0136] 110... Semiconductor layer, 120... Via electrode, 130... Gate insulating layer, 140, 141... Via electrode, 150... Via wiring, 160... Semiconductor layer, 170... Conductive layer, 180... Via wiring.

Claims

1. Multiple semiconductor layers and multiple insulating layers are stacked alternately in the stacking direction and extend in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the stacking direction corresponding to the plurality of semiconductor layers, are extended in a second direction intersecting the stacking direction and the first direction, and are connected to the ends of the plurality of semiconductor layers in the first direction. A plurality of first via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of first via electrodes, A plurality of conductive layers and a plurality of first via electrodes are provided between the plurality of conductive layers and the plurality of first via electrodes, arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers. Equipped with, Extending in the first and second directions, in a first cross-section including one of the plurality of semiconductor layers, The surface of the second via electrode facing one of the plurality of semiconductor layers is aligned with the first circle. The side of the second via electrode opposite to the plurality of semiconductor layers is aligned with the second circle. In a second cross-section extending in the first and second directions and including one of the plurality of insulating layers, the outer surface of the second via electrode is aligned with a third circle. The radius of at least one of the first circle and the second circle is different from the radius of the third circle. Semiconductor memory device.

2. The radius of the first circle is greater than the radius of the third circle. The semiconductor memory device according to claim 1.

3. The radius of the first circle is smaller than the radius of the second circle. The semiconductor memory device according to claim 1.

4. The radius of the second circle is the same as the radius of the third circle. The semiconductor memory device according to claim 1.

5. In the second cross-section, the outer surface of the first via electrode is aligned with the fourth circle. The radius of at least one of the first circle and the second circle is greater than the radius of the fourth circle. The semiconductor memory device according to claim 1.

6. The plurality of first via electrodes and the plurality of second via electrodes are arranged in the first direction at a constant pitch. The semiconductor memory device according to claim 1.

7. A plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the aforementioned stacking direction, extended in a second direction intersecting the aforementioned stacking direction and the first direction, and connected to the ends of the plurality of semiconductor layers in the first direction, A plurality of first via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of first via electrodes, A plurality of conductive layers and a plurality of first via electrodes are provided between them, arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers. A semiconductor column is provided on the side opposite to the plurality of second via electrodes with respect to the central position in the second direction of the plurality of semiconductor layers, is extended in the stacking direction, and is in contact with the plurality of semiconductor layers. A semiconductor memory device equipped with the following features.

8. The semiconductor column contains P-type impurities. The semiconductor memory device according to claim 7.

9. A plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the aforementioned stacking direction, extended in a second direction intersecting the aforementioned stacking direction and the first direction, and connected to the ends of the plurality of semiconductor layers in the first direction, A plurality of first via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of first via electrodes, A plurality of conductive layers and a plurality of first via electrodes are provided between them, arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers. A third via electrode is provided between the plurality of conductive layers and the plurality of second via electrodes, is stretched in the stacking direction, and faces the plurality of semiconductor layers. Equipped with, The third via electrode can be supplied with a voltage different from that of the second via electrode. Semiconductor memory device.

10. During the write operation, A first voltage is supplied to at least a portion of the plurality of conductive layers. A second voltage, smaller than the first voltage, is supplied to the plurality of second via electrodes. A third voltage greater than the second voltage and less than the first voltage is supplied to the third via electrode. The semiconductor memory device according to claim 9.

11. A plurality of semiconductor layers stacked in the stacking direction and stretched in a first direction intersecting the stacking direction, A plurality of conductive layers are stacked in the aforementioned stacking direction, extended in a second direction intersecting the aforementioned stacking direction and the first direction, and connected to the ends of the plurality of semiconductor layers in the first direction, A plurality of first via electrodes are arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers, A plurality of charge storage layers are provided between the plurality of semiconductor layers and the plurality of first via electrodes, A plurality of conductive layers and a plurality of first via electrodes are provided between the plurality of conductive layers and the plurality of first via electrodes, arranged in the first direction along the side surfaces of the plurality of semiconductor layers in the second direction, extended in the stacking direction, and facing the plurality of semiconductor layers. Equipped with, Extending in the first and second directions, in a first cross-section including the first semiconductor layer among the plurality of semiconductor layers, A portion of the side surface of the first semiconductor layer in the second direction on the side of the plurality of second via electrodes lies along a plurality of circles whose center points overlap with the plurality of second via electrodes and which have a first radius. A portion of the side surface of the first semiconductor layer in the second direction, opposite to the plurality of second via electrodes, is concentric with the plurality of circles and aligns with a plurality of other circles having a second radius greater than the first radius. Semiconductor memory device.

12. The first semiconductor layer further comprises other via electrodes that are stretched in the lamination direction and face the side surfaces opposite to the plurality of second via electrodes in the second direction. The semiconductor memory device according to claim 11.

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