Image sensor

Abstract

To provide an image sensor with improved electrical characteristics. [Solution] The image sensor of the present invention comprises a substrate including a photoelectric conversion unit, a first capacitor and a second capacitor spaced apart in a first direction on the substrate, and a first via disposed between the first capacitor and the second capacitor. The first capacitor includes a first electrode, a second electrode, and a first dielectric film interposed between the first electrode and the second electrode. The second capacitor includes a third electrode, a fourth electrode, and a second dielectric film interposed between the third electrode and the fourth electrode. The first via is connected to the first electrode and the third electrode.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly to an image sensor including a stacked capacitor.

Background Art

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors are classified into CCD (Charge coupled device) type and CMOS (Complementary metal oxide semiconductor) type. A CMOS image sensor is abbreviated as CIS. CIS includes a plurality of pixels two-dimensionally arranged. Each pixel includes a photodiode (PD). The photodiode serves to convert incident light into an electrical signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above prior art, and an object of the present invention is to provide an image sensor with improved electrical characteristics.

Means for Solving the Problems

[0005] An image sensor according to one aspect of the present invention, made to achieve the above objective, comprises a substrate including a photoelectric conversion unit, a first capacitor and a second capacitor spaced apart in a first direction on the substrate, and a first via disposed between the first capacitor and the second capacitor, wherein the first capacitor includes a first electrode, a second electrode, and a first dielectric film interposed between the first electrode and the second electrode, the second capacitor includes a third electrode, a fourth electrode, and a second dielectric film interposed between the third electrode and the fourth electrode, and the first via is connected to the first electrode and the third electrode.

[0006] An image sensor according to another aspect of the present invention made to achieve the above objectives comprises a substrate including a photoelectric conversion unit, a first capacitor and a second capacitor spaced apart on the substrate in a first direction parallel to the upper surface of the substrate, a first via disposed between the first capacitor and the second capacitor, a second via superimposed on the first capacitor, and a third via superimposed on the second capacitor, wherein the first capacitor and the second capacitor each include a plurality of stacked electrodes and a dielectric film provided on the plurality of electrodes, the first via is connected to some electrodes of the first capacitor and some electrodes of the second capacitor, the second via is connected to the remaining electrodes of the first capacitor excluding the electrodes connected to the first via, and the third via is connected to the remaining electrodes of the second capacitor excluding the electrodes connected to the first via.

[0007] An image sensor according to yet another aspect of the present invention made to achieve the above objectives comprises a substrate having a first surface and a second surface facing each other and including a photoelectric conversion unit; a first capacitor and a second capacitor spaced apart in a first direction on the first surface of the substrate; a first via disposed between the first capacitor and the second capacitor; a second via superimposed on the first capacitor; and a third via superimposed on the second capacitor, wherein the first capacitor includes alternately stacked first electrodes and second electrodes, and a first dielectric film interposed between the first electrode and the second electrode; the second capacitor includes alternately stacked third electrodes and fourth electrodes, and a second dielectric film interposed between the third electrode and the fourth electrode; the first via is connected to the first electrode and the third electrode; the second via is connected to the second electrode; the third via is connected to the fourth electrode; and the first electrode and the third electrode, located at the same level, form a first plate. [Effects of the Invention]

[0008] The image sensor of the present invention includes a plurality of capacitors and vias placed between them to which the power supply voltage is applied. Here, the plurality of capacitors are connected to the power supply voltage through a common via. This increases the contact area of ​​the plurality of electrodes stacked within each capacitor. As a result, the effective area and capacitance of the capacitors are increased, and noise is improved, thereby improving the electrical characteristics of the image sensor. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing an image processing device according to one embodiment of the present invention. [Figure 2] This is a circuit diagram of an image sensor according to one embodiment of the present invention. [Figure 3] This is a plan view showing one pixel region of an image sensor according to one embodiment of the present invention. [Figure 4] This is a plan view showing a portion of a capacitor according to one embodiment of the present invention. [Figure 5] This is a plan view showing a portion of a capacitor according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view along the line A-A' in Figure 3. [Figure 7] This is a cross-sectional view along the line B-B' in Figure 3. [Figure 8] This is a cross-sectional view along the line C-C' in Figure 3. [Figure 9] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 10] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 11] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 12] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 14] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 15] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Figure 16] This is a cross-sectional view showing the manufacturing process of an image sensor according to one embodiment of the present invention. [Modes for carrying out the invention]

[0010] Hereinafter, specific examples of embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0011] Figure 1 is a block diagram showing an image processing apparatus according to one embodiment of the present invention.

[0012] Referring to FIG. 1, an image processing apparatus 500 according to an embodiment of the present invention includes an image sensor 510, an image signal processing unit 520 (ISP: Image Signal Processing Unit), a display device 530, and a storage device 540.

[0013] The image processing apparatus 500 includes one of electronic devices that acquire external images, such as a smart phone and a digital camera.

[0014] The image sensor 510 converts an image from an external object into an electrical signal or a data signal. The image sensor 510 includes a plurality of pixel regions. Each of the plurality of pixel regions receives light reflected from an external object and converts the received light into an electrical image signal or a photographic signal.

[0015] The image signal processing unit 520 performs signal processing on the frame data FR (i.e., image data or photographic data) received from the image sensor 510 and outputs corrected image data IMG. For example, the image signal processing unit 520 performs signal processing operations such as color interpolation, color correction, gamma correction, color space conversion, edge correction, etc. on the received frame data FR to generate the image data IMG.

[0016] The display device 530 outputs image data IMG from the image signal processing unit 520 for the user to view. For example, the display device 530 includes at least one of various display panels, such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, or an electrowetting display panel. The display device 530 outputs image data IMG through the display panel.

[0017] The storage device 540 is configured to store image data IMG from the image signal processing unit 520. The storage device 540 includes volatile memory elements such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), etc., or non-volatile memory elements such as ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory devices, PRAM (Phase-change RAM), MRAM (Magnetic RAM), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), etc.

[0018] As described later, the image sensor 510 according to one embodiment of the present invention includes a capacitor as a storage element for storing an electrical signal corresponding to the charge generated from the photoelectric conversion unit. A circuit diagram of the image sensor 510 of the present invention is shown exemplarily in Figure 2, but the present invention is not limited thereto and can be applied to all image sensors having a capacitor.

[0019] Figure 2 is a circuit diagram of an image sensor according to one embodiment of the present invention.

[0020] Referring to Figure 2, an image sensor according to one embodiment of the present invention has an in-pixel correlated double sampling (CDS) structure.

[0021] Specifically, each pixel region PX of the image sensor includes a photoelectric conversion unit PD, a transmission transistor TX including a transmission gate TG, a first reset transistor RX1 including a first reset gate RG1, a second reset transistor RX2 including a second reset gate RG2, a first source follower transistor FX1 including a first source follower gate SF1, a precharge transistor CX including a precharge gate PC, a first precharge selection transistor PS1 including a first precharge selection gate PSEL1, a second precharge selection transistor PS2 including a second precharge selection gate PSEL2, a first sampling transistor AX1 including a first sampling gate SAM1, a second sampling transistor AX2 including a second sampling gate SAM2, a second source follower transistor FX2 including a second source follower gate SF2, a selection transistor SX including a selection gate SEL, a first capacitor C1, and a second capacitor C2.

[0022] The photoelectric converter PD is a photodiode. The first terminal of the transmission transistor TX is connected to the photoelectric converter PD. The second terminal of the transmission transistor TX is understood as a floating diffusion region FD. The floating diffusion region FD is connected to the first terminal of the first reset transistor RX1. The floating diffusion region FD is electrically connected to the first source follower gate SF1 of the first source follower transistor FX1. In this specification, 'connected' includes not only physical contact between some components but also electrical connection between components.

[0023] The first terminal of the first source follower transistor FX1 is connected to the precharge transistor CX and the first precharge selector transistor PS1. The first terminal of the precharge transistor CX is connected to the second precharge selector transistor PS2. The first terminal of the second precharge selector transistor PS2 is connected to the precharge source line PC-SRC.

[0024] The first terminal of the first precharge selection transistor PS1 is connected to the first terminal of the first sampling transistor AX1 and the first terminal of the second sampling transistor AX2. The second terminal of the first sampling transistor AX1 is connected to the first capacitor C1. The second terminal of the second sampling transistor AX2 is connected to the second capacitor C2.

[0025] The power supply voltage VPIX is applied to the second terminal of the second reset transistor RX2, the second terminal of the first source follower transistor FX1, the first capacitor C1, the second capacitor C2, and the first terminal of the second source follower transistor FX2. Specifically, the first capacitor C1 is connected between the second terminal of the first sampling transistor AX1 and the power supply voltage VPIX. The second capacitor C2 is connected between the second terminal of the second sampling transistor AX2 and the power supply voltage VPIX. The first terminal of the selection transistor SX is connected to the output line Vout.

[0026] The image sensor operation shown in Figure 2 involves a step of sampling a reset value and a step of sampling a signal value. Before photoaccumulation, the photoelectric converter PD is reset through the floating diffusion region FD. After the photoelectric converter PD is reset, photoaccumulation (frame capture) begins. This induces a noise component in the reset value. The reset value containing the noise component is stored in the first capacitor C1 through the first sampling transistor AX1.

[0027] Before the sampling phase begins, the first capacitor C1 and the second capacitor C2 are pre-charged by removing the previously sampled voltage so that the first and second source follower transistors (SF1, SF2) can sample the new voltage. This pre-charging operation is performed using the pre-charge transistor CX and the first and second pre-charge selection transistors (PS1, PS2).

[0028] After the sampling stage, the charge is transmitted from the photoelectric conversion unit PD to the floating diffusion region FD, which then acquires a new voltage (signal value). The signal value of the floating diffusion region FD is sampled into the second capacitor C2 via the second sampling transistor AX2. By subtracting the reset value stored in the first capacitor C1 from the signal value stored in the second capacitor C2, and obtaining the accurate signal value with noise components removed, a clear image sensor can be realized.

[0029] An image sensor according to one embodiment of the present invention operates in global shutter mode. In global shutter mode, electrical signals (data) generated in all pixel regions PX of the image sensor are sampled and stored simultaneously or sequentially in the first capacitor C1 and the second capacitor C2 located in each pixel region, respectively, and the image signal processing unit 520 in Figure 1 reads out the data sequentially row by row. Thus, global shutter mode is realized. The image sensor of the present invention is also referred to as a voltage-type global shutter image sensor. At least one transmission transistor TX is arranged in each pixel region PX. According to one embodiment, all or part of the other transistors are arranged on each pixel region PX and are shared by adjacent pixel regions PX.

[0030] Figure 3 is a plan view showing one pixel region of an image sensor according to one embodiment of the present invention. Figure 4 is a plan view showing a portion of a capacitor according to one embodiment of the present invention. Figure 5 is a plan view showing a portion of a capacitor according to one embodiment of the present invention. Figure 6 is a cross-sectional view along the line A-A' in Figure 3. Figure 7 is a cross-sectional view along the line B-B' in Figure 3. Figure 8 is a cross-sectional view along the line C-C' in Figure 3.

[0031] Referring to Figures 3 to 8, an image sensor 510 according to one embodiment of the present invention includes a substrate 1. The substrate 1 has a first surface 1a and a second surface 1b that face each other. Light is incident into the substrate 1 through the second surface 1b. The substrate 1 is a single crystal wafer, epitaxial layer, or SOI (Silicon on Insulator) substrate containing silicon and / or germanium.

[0032] In this specification, the first direction D1 is defined as a direction parallel to the first surface 1a of the substrate 1. The second direction D2 is defined as a direction parallel to the first surface 1a of the substrate 1 and perpendicular to the first direction D1. The third direction D3 is defined as a direction perpendicular to the first surface 1a of the substrate 1. The substrate 1 is doped with a first impurity and has a first conductivity type. The first impurity is, for example, boron. The first conductivity type is, for example, P-type.

[0033] The photoelectric conversion unit PD is placed within the substrate 1. Although not shown, multiple photoelectric conversion units PD are provided within the image sensor 510 and are separated from each other by a separation structure DTI, which will be described later. The photoelectric conversion unit PD is doped with a second impurity to have a second conductivity type different from the first conductivity type. The second impurity is, for example, phosphorus or arsenic. The second conductivity type is, for example, N-type. Here, the N-type region of the photoelectric conversion unit PD described above forms a PN junction with the P-type region of the surrounding substrate 1 to constitute a photodiode, and when light is incident, electron-hole pairs are generated by the PN junction. The electrons generated in the above process move to the photoelectric conversion unit PD.

[0034] The element isolation unit STI is placed within the substrate 1 to isolate elements such as transistors. The element isolation unit STI includes at least one of silicon oxide, silicon nitride, and silicon oxidnitride.

[0035] A separation structure DTI is placed within the substrate 1 to separate the photoelectric conversion unit PD. The separation structure DTI penetrates the substrate 1. The width of the separation structure DTI in the first direction D1 narrows as it moves from the first surface 1a to the second surface 1b.

[0036] The separation structure DTI includes a first separation pattern 111 and a second separation pattern 113. The first separation pattern 111 is positioned separately from the substrate 1. The first separation pattern 111 contains a conductive material having a different refractive index than the substrate 1. The first separation pattern 111 may contain, for example, polysilicon or metal doped with impurities.

[0037] The second separation pattern 113 is interposed between the first separation pattern 111 and the substrate 1. As an example, the second separation pattern 113 contains silicon oxide.

[0038] A negative bias voltage is applied to the first isolation pattern 111. The first isolation pattern 111 acts as a common bias line. Therefore, it can capture holes present on the surface of the substrate 1 in contact with the isolation structure DTI and improve the dark current characteristics.

[0039] The diagram shows a case where there is a boundary between the element isolation section STI and the isolation structure DTI, but in other cases, no boundary may be observed between the element isolation section STI and the isolation structure DTI. For example, there is no interface between the element isolation section STI and the second isolation pattern 113.

[0040] The first sampling gate SAM1 and the second sampling gate SAM2 are arranged on the first surface 1a of the substrate 1. The first sampling gate SAM1 and the second sampling gate SAM2 are spaced apart in the first direction D1.

[0041] A first gate insulating film GI1 is interposed between the first sampling gate SAM1 and the substrate 1. A second gate insulating film GI2 is interposed between the second sampling gate SAM2 and the substrate 1. Impurity regions SD are placed on both sides of the first sampling gate SAM1 and the second sampling gate SAM2. The impurity regions SD are provided within the substrate 1. The impurity regions SD are doped with the second impurity described above. The first sampling gate SAM1 and the impurity regions SD constitute the first sampling transistor AX1 as described in Figure 2. The second sampling gate SAM2 and the impurity regions SD constitute the second sampling transistor AX2 as described in Figure 2.

[0042] A transmission gate TG is positioned on the first surface 1a of the substrate 1. As an example, a portion of the transmission gate TG is provided within the substrate 1. The remaining portion of the transmission gate TG is provided on the first surface 1a. That is, a portion of the transmission gate TG extends into the substrate 1. A third gate insulating film GI3 is interposed between the transmission gate TG and the substrate 1.

[0043] A floating diffusion region FD is positioned within substrate 1 adjacent to the transmission gate TG. The floating diffusion region FD is doped with a second impurity to have a second conductivity type. When a voltage is applied to the transmission gate TG, electrons move to the floating diffusion region FD. In Figures 3 to 8, only the transmission gate TG, the first sampling gate SAM1, and the second sampling gate SAM2 are shown, and the other transistors described in Figure 2 are omitted.

[0044] The first to eighth interlayer insulating films (IL1 to IL8) are arranged on the first surface 1a of the substrate 1. Each of the interlayer insulating films (IL1 to IL8) contains at least one of silicon oxide and silicon nitride. For example, the first to third interlayer insulating films (IL1 to IL3) contain silicon oxide. The fourth interlayer insulating film IL4 contains silicon nitride. The fifth to eighth interlayer insulating films (IL5 to IL8) contain silicon oxide.

[0045] A first contact plug CT1 and a second contact plug CT2 are provided penetrating the first interlayer insulating film IL1. The first contact plug CT1 is positioned separated in a first direction D1 via a first sampling gate SAM1. The first contact plug CT1 is connected to the impurity region SD of the first sampling gate SAM1. The second contact plug CT2 is positioned separated in a first direction D1 via a second sampling gate SAM2. The second contact plug CT2 is connected to the impurity region SD of the second sampling gate SAM2.

[0046] A first wiring pattern M1 is provided within the first to fifth interlayer insulating films (IL1 to IL5). A portion of the first wiring pattern M1 is connected to the substrate 1 through the first contact plug CT1 and the second contact plug CT2.

[0047] The first capacitor C1 and the second capacitor C2 are arranged within the sixth interlayer insulating film IL6 on the substrate 1. As shown in Figure 3, the first capacitor C1 and the second capacitor C2 are provided on one pixel region PX. The first capacitor C1 and the second capacitor C2 are superimposed on the photoelectric conversion unit PD. The first capacitor C1 and the second capacitor C2 are arranged separated in the first direction D1. The first capacitor C1 and the second capacitor C2 each include a plurality of stacked electrodes and a dielectric film provided on the electrodes.

[0048] The first capacitor C1 includes alternately stacked first electrodes ET1 and second electrodes ET2, and a first dielectric film DL1 interposed between the first electrode ET1 and the second electrode ET2. For example, the first electrode ET1 corresponds to an odd-numbered electrode stacked on the substrate 1. The second electrode ET2 corresponds to an even-numbered electrode stacked on the substrate 1. The number of first electrodes ET1 and second electrodes ET2 is not limited to those shown in the figure, and more electrodes may be provided. Some of the electrodes among the multiple electrodes included in the first capacitor C1 have a step structure. As shown in Figure 7, some portions of the first electrode ET1 located on the same level have an opening OP. The second electrode ET2 is provided stacked on top of the opening OP. The first dielectric film DL1 is not provided on the first electrode ET1 located at the uppermost end.

[0049] The second capacitor C2 includes alternately stacked third electrodes ET3 and fourth electrodes ET4, and a second dielectric film DL2 interposed between the third electrode ET3 and the fourth electrode ET4. For example, the third electrode ET3 corresponds to an odd-numbered electrode stacked on the substrate 1. The fourth electrode ET4 corresponds to an even-numbered electrode stacked on the substrate 1. Some of the electrodes among the multiple electrodes included in the second capacitor C2 have a step structure. As shown in Figure 8, some portions of the third electrode ET3 located on the same level have an opening OP. The fourth electrode ET4 is provided on top of the opening OP. The second dielectric film DL2 is not provided on the uppermost third electrode ET3.

[0050] Referring to Figures 3 to 5, the first electrode ET1 of the first capacitor C1 and the third electrode ET3 of the second capacitor C2, located at the same level, constitute a single first plate PLA1 in a plan view. The first plate PLA1 is connected to the first via VA1.

[0051] Each of the second electrodes ET2 of the first capacitor C1 constitutes a second plate PLA2 in a plan view. Each of the fourth electrodes ET4 of the second capacitor C2 constitutes a third plate PLA3 in a plan view. The second plate PLA2 is connected to the second via VA2. The third plate PLA3 is connected to the third via VA3.

[0052] The first plate PLA1 is superimposed on the second plate PLA2 and the third plate PLA3. That is, the first capacitor CA1 is a configuration in which multiple first plates PLA1 and second plates PLA2 are stacked. The second capacitor CA2 is a configuration in which multiple first plates PLA1 and third plates PLA3 are stacked. The second plate PLA2 and the third plate PLA3 are separated in the first direction D1. The area of ​​the first plate PLA1 is larger than the area of ​​the second plate PLA2 and the area of ​​the third plate PLA3.

[0053] The first capacitor C1 and the second capacitor C2 are each MIM (Metal-Insulator-Metal) type capacitors. Two or more of each of the first electrode ET1, second electrode ET2, third electrode ET3, and fourth electrode ET4 are provided as an example. The number of electrodes ET1, ET2, ET3, and ET4 is not limited to those shown in the illustration, and more electrodes may be provided.

[0054] The first electrode ET1, the second electrode ET2, the third electrode ET3, and the fourth electrode ET4 include, for example, at least one of the following impurity-doped materials: polysilicon, aluminum, copper, tungsten, ruthenium, rhodium, titanium, tantalum, titanium nitride, and tantalum nitride. The first dielectric film DL1 and the second dielectric film DL2 include, for example, at least one of the following: aluminum oxide, hafnium oxide, iridium oxide, and ruthenium oxide.

[0055] The first via VA1 is positioned between the first capacitor C1 and the second capacitor C2. The first via VA1 penetrates the fourth to sixth interlayer insulating films (IL4 to IL6). The first capacitor C1 and the second capacitor C2 have a symmetrical structure with respect to the first via VA1. The first via VA1 is positioned between the first sampling gate SAM1 and the second sampling gate SAM2.

[0056] The first via VA1 is connected to some electrodes of the first capacitor C1 and some electrodes of the second capacitor C2. Specifically, the first via VA1 is connected to the first electrode ET1 included in the first capacitor C1 and the third electrode ET3 included in the second capacitor C2. The first via VA1 is separated from the second electrode ET2 included in the first capacitor C1 and the fourth electrode ET4 included in the second capacitor C2.

[0057] The separation distance DS of the second electrode ET2 and the fourth electrode ET4 in the first direction D1 is 1.5 times or more the width VA1W of the first via VA1 in the first direction D1. One end of the first via VA1 is connected to the first wiring pattern M1. The first via VA1 is not electrically connected to the substrate 1. The power supply voltage VPIX described in Figure 2 is applied to the first via VA1. Alternatively, according to one embodiment, the ground voltage is applied to the first via VA1.

[0058] The first via VA1 includes a first conductive pattern FM1 and a first barrier pattern BM1 on the first conductive pattern FM1. The first barrier pattern BM1 surrounds the bottom and sides of the first conductive pattern FM1. As an example, the first conductive pattern FM1 includes at least one metal from aluminum, copper, tungsten, molybdenum, and cobalt. The first barrier pattern BM1 includes a metal film / metal nitride film.

[0059] As shown in Figure 7, the second via VA2 is positioned to penetrate the first capacitor C1 and the interlayer insulating films (IL4 to IL6) of the fourth to sixth layers. The second via VA2 is superimposed on the first capacitor C1. The second via VA2 is connected to some of the electrodes of the first capacitor C1. Specifically, the second via VA2 is connected to the second electrode ET2 included in the first capacitor C1. The second via VA2 is separated from the first electrode ET1 included in the first capacitor C1. That is, the second via VA2 is connected to the remaining electrodes in the electrodes of the first capacitor C1 that are not connected to the first via VA1.

[0060] One end of the second via VA2 is connected to the first wiring pattern M1. The second via VA2 is electrically connected to the substrate 1 through the first wiring pattern M1 and the first contact plug CT1. The second via VA2 is a node-selection via.

[0061] The second via VA2 includes a second conductive pattern FM2 and a second barrier pattern BM2 on the second conductive pattern FM2. The second barrier pattern BM2 surrounds the bottom and sides of the second conductive pattern FM2. As an example, the second conductive pattern FM2 includes at least one metal from aluminum, copper, tungsten, molybdenum, and cobalt. The second barrier pattern BM2 includes a metal film / metal nitride film.

[0062] As shown in Figure 8, the third via VA3 is positioned to penetrate the second capacitor C2 and the fourth to sixth interlayer insulating films (IL4 to IL6). The third via VA3 is superimposed on the second capacitor C2. The third via VA3 is connected to some of the electrodes of the second capacitor C2. Specifically, the third via VA3 is connected to the fourth electrode ET4 included in the second capacitor C2. The third via VA3 is separated from the third electrode ET3 included in the second capacitor C2. That is, the third via VA3 is connected to the remaining electrodes in the electrodes of the second capacitor C2 that are not connected to the first via VA1.

[0063] One end of the third via VA3 is connected to the first wiring pattern M1. The third via VA3 is electrically connected to the substrate 1 through the first wiring pattern M1 and the second contact plug CT2. The third via VA3 is a node-selection via. The positions in the first capacitor C1 and the second capacitor C2 where the signal values ​​are stored are determined through the second via VA2 and the third via VA3.

[0064] The third via VA3 includes a third conductive pattern FM3 and a third barrier pattern BM3 on the third conductive pattern FM3. The third barrier pattern BM3 surrounds the bottom and sides of the third conductive pattern FM3. As an example, the third conductive pattern FM3 includes at least one metal from aluminum, copper, tungsten, molybdenum, and cobalt. The third barrier pattern BM3 includes a metal film / metal nitride film. Referring to Figures 4 and 5, the width of the opening OP in the first plate PLA1 is greater than the widths of the second via VA2 and the third via VA3.

[0065] The seventh interlayer insulating film IL7 and the eighth interlayer insulating film IL8 are arranged on the sixth interlayer insulating film IL6. The second wiring pattern M2 is provided within the seventh interlayer insulating film IL7 and the eighth interlayer insulating film IL8. The second wiring pattern M2 is connected to the first via VA1, the second via VA2, and the third via VA3.

[0066] A fixed charge film 42 is placed on the second surface 100b of the substrate 1. The fixed charge film 42 is formed of a metal oxide film or metal fluoride film containing an amount of oxygen or fluorine that is less than the stoichiometric ratio. As a result, the fixed charge film 42 has a negative fixed charge. The fixed charge film 42 is formed of a metal oxide or metal fluoride containing at least one metal selected from the group including hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. Hole accumulation occurs around the fixed charge film 42. Therefore, the generation of dark current and white spots can be effectively reduced. Preferably, the fixed charge film 42 contains at least one of aluminum oxide and hafnium oxide.

[0067] A grid 45 is provided on a fixed charge film 42. The grid 45 superimposes on the separation structure DTI in some regions, but does not superimpose on the separation structure DTI in other regions, taking into account the angle of incidence. The grid 45 includes a first material pattern 44 and a second material pattern 46. The first material pattern 44 includes a material that does not transmit light, such as titanium. The sidewalls of the second material pattern 46 are aligned with the sidewalls of the first material pattern 44. The first material pattern 44 and the second material pattern 46 prevent crosstalk between adjacent pixels. The second material pattern 46 includes an organic material. The second material pattern 46 has a refractive index of approximately 1.3 or less, as an example.

[0068] A color filter CF is placed on a fixed charge film 42. The color filter CF contains a photoresist material to which a dye or pigment is added. Although not shown in the diagram, on multiple photoelectric conversion units PD, the color filters CF are arranged in the form of a Bayer pattern, a 2x2 Tetra pattern, a 3x3 nona pattern, or a 4x4 hexadeca pattern. A microlens ML is placed on the color filter CF.

[0069] In the comparative example, the image sensor had vias individually connected to each of the multiple capacitors, to which the power supply voltage was applied. The vias reduced the contact area between the multiple electrodes stacked in the capacitor, thus reducing the effective area of ​​the capacitor. As a result, there was a problem of reduced electrical characteristics of the image sensor due to the decrease in capacitor capacitance.

[0070] On the other hand, an image sensor according to one embodiment of the present invention includes a plurality of capacitors and vias placed between them to which the power supply voltage is applied. Since the plurality of capacitors are connected to the power supply voltage through a common via, the contact area of ​​the plurality of electrodes stacked within each capacitor increases. As a result, the effective area of ​​the capacitors increases, thereby increasing the capacitance of the capacitors. This can improve the noise of the image sensor and enhance its electrical characteristics.

[0071] Figures 9, 10, 11, 12, 13, 14, 15, and 16 are cross-sectional views showing the manufacturing process of an image sensor according to one embodiment of the present invention. Specifically, Figures 9, 11, 13, and 15 are cross-sectional views along the line A-A' in Figure 3. Figures 10, 12, 14, and 16 are cross-sectional views along the line B-B' in Figure 3.

[0072] Referring to Figures 9 and 10, a substrate 1 is prepared. The substrate 1 has a first surface 1a and a second surface 1b that face each other. An element isolation section STI is formed on the first surface 1a of the substrate 1. The element isolation section STI is formed, for example, through an STI (Shallow Trench Isolation) process.

[0073] An isolation structure DTI is formed through the element isolation section STI and the substrate 1. The isolation structure DTI includes a first isolation pattern 111 and a second isolation pattern 113. A photoelectric conversion section PD and a floating diffusion region FD are formed within the substrate 1 through an ion implantation process.

[0074] A first sampling gate SAM1, a second sampling gate SAM2, a transmission gate TG, and first to third gate insulating films (GI to GI3) interposed between the substrate 1 and each gate are formed on the first surface 1a of the substrate 1. Within the substrate 1, impurity regions SD, which are located on both sides of the first sampling gate SAM1 and the second sampling gate SAM2, are formed through an ion implantation process.

[0075] A first interlayer insulating film IL1 is formed on the first surface 1a. A first contact plug CT1 and a second contact plug CT2 are formed penetrating the first interlayer insulating film IL1. Subsequently, the second to fifth interlayer insulating films (IL2 to IL5) and the first wiring pattern M1 provided inside them are formed.

[0076] Referring to Figures 11 and 12, a preliminary electrode ET is formed on the fifth interlayer insulating film IL5. Subsequently, a dielectric film DL is formed on the preliminary electrode ET. The formation of the preliminary electrode ET and the formation of the dielectric film DL on the preliminary electrode ET are repeated. In some cases, the preliminary electrode ET is deposited to have a step structure. After deposition, some of the preliminary electrode ET is patterned. As an example, preliminary electrode ET formed on even-numbered layers are provided in multiples separated in the first direction D1. No dielectric film DL is formed on the uppermost preliminary electrode ET. Subsequently, a sixth interlayer insulating film IL6 is formed covering the preliminary electrode ET.

[0077] Referring to Figures 13 and 14, the first via VA1 is formed by penetrating a plurality of preliminary electrodes ET, dielectric films DL, and interlayer insulating films (IL4 to IL6) from the fourth to the sixth layer. The first via VA1 includes a first conductive pattern FM1 and a first barrier pattern BM1 on the first conductive pattern FM1.

[0078] The first via VA1 penetrates the multiple preliminary electrodes ET formed in Figures 11 and 12, thereby forming the first capacitor C1 and the second capacitor C2 from the multiple preliminary electrodes ET. The first capacitor C1 and the second capacitor C2 are separated in the first direction D1 via the first via VA1.

[0079] The first capacitor C1 includes alternately stacked first electrodes ET1 and second electrodes ET2, and a first dielectric film DL1 interposed between the first electrode ET1 and the second electrode ET2. The second capacitor C2 includes alternately stacked third electrodes ET3 and fourth electrodes ET4, and a second dielectric film DL2 interposed between the third electrode ET3 and the fourth electrode ET4. In this case, the first via VA1 is connected to the first electrode ET1 included in the first capacitor C1 and the third electrode ET3 included in the second capacitor C2.

[0080] Subsequently, a second via VA2 is formed, penetrating the first capacitor C1 and the fourth to sixth interlayer insulating films (IL4 to IL6). The second via VA2 includes a second conductive pattern FM2 and a second barrier pattern BM2 on the second conductive pattern FM2. The second via VA2 is connected to a second electrode ET2 included in the first capacitor C1.

[0081] Although not shown in the diagram, the third via VA3 is also formed by a process similar to that used to form the second via VA2. The third via VA3 penetrates the second capacitor C2 and the fourth to sixth interlayer insulating films (IL4 to IL6). As shown in Figure 8, the third via VA3 is connected to the fourth electrode ET4 included in the second capacitor C2. For example, the formation of the third via VA3 can be performed simultaneously with or separately from the process of forming the second via VA2.

[0082] Referring to Figures 15 and 16, the seventh interlayer insulating film IL7, the eighth interlayer insulating film IL8, and the second wiring pattern M2, which is placed inside them, are formed on the sixth interlayer insulating film IL6. Here, a portion of the second wiring pattern M2 is connected to the first to third vias (VA1 to VA3).

[0083] Subsequently, referring to Figures 6 to 8, an image sensor according to one embodiment of the present invention is completed by forming a fixed charge film 42, a color filter CF, and a microlens ML on the second surface 1b of the substrate 1.

[0084] Although embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the embodiments described above, and can be modified and implemented in various ways without departing from the technical spirit of the present invention. [Explanation of Symbols]

[0085] 1 circuit board 1a, 1b First and second surfaces of the substrate 42 Fixed charge membrane 44, 46 First and second material patterns 45 grid 111, 113 First and second separation patterns 500 Image Processing Devices 510 Image Sensor 520 Image Signal Processing Unit (ISP) 530 Display device 540 Storage device AX1, AX2: First and second sampling transistors BM1, BM2, BM3: 1st to 3rd barrier patterns C1, C2: First and second capacitors CF Color Filter CT1, CT2 First and second contact plugs CX precharge transistor DL Dielectric Film DL1, DL2 First and Second Dielectric Films DTI separation structure ET spare electrode ET1, ET2, ET3, ET4 1st to 4th electrode FD (Floating Diffusion) Region FM1, FM2, FM3: First to third conductive patterns FR frame data FX1, FX2: First and second source follower transistors GI1, GI2, GI3: 1st to 3rd gate insulating film IL1-IL8 Interlayer Insulation Films (1st-8th layers) IMG Image Data M1, M2 First and Second Wiring Patterns ML Microlens PC Precharge Gate PC-SRC Precharge Source Line PD Photoelectric Conversion Unit PLA1, PLA2, PLA3 (Plates 1-3) PS1, PS2 1st and 2nd precharge selection transistors PSEL1, PSEL2: First and second pre-charge selection gates PX pixel area RG1, RG2 First and Second Reset Gates RX1, RX2 First and second reset transistors SAM1, SAM2: First and second sampling gates SD impurity region SEL Selection Gate SF1, SF2 First and Second Source Follower Gates STI element isolation section SX Select Transistor TG transmission gate TX transmission transistor VA1, VA2, VA3 (Vias 1-3) Vout output line VPIX Power Supply Voltage

Claims

1. A substrate including a photoelectric conversion unit, A first capacitor and a second capacitor are spaced apart in a first direction on the substrate, A first via is disposed between the first capacitor and the second capacitor, The first capacitor includes a first electrode, a second electrode, and a first dielectric film interposed between the first electrode and the second electrode. The second capacitor includes a third electrode, a fourth electrode, and a second dielectric film interposed between the third electrode and the fourth electrode. The first via is connected to the first electrode and the third electrode, and is characterized by being an image sensor.

2. The image sensor according to claim 1, characterized in that the first via is provided at a distance from the second electrode and the fourth electrode.

3. The image sensor according to claim 1, characterized in that the separation distance between the second electrode and the fourth electrode in the first direction is 1.5 times or more the width of the first via in the first direction.

4. The first electrode and the third electrode are located at the same level. The image sensor according to claim 1, characterized in that the second electrode and the fourth electrode are located at the same level.

5. Further including a second via that penetrates the first capacitor, The image sensor according to claim 1, characterized in that the second via is separated from the first electrode and connected to the second electrode.

6. Further including a third via that passes through the second capacitor, The image sensor according to claim 5, characterized in that the third via is separated from the third electrode and connected to the fourth electrode.

7. An interlayer insulating film disposed between the substrate and the first capacitor and the second capacitor, The present invention further includes a first contact plug that penetrates the interlayer insulating film and is connected to the substrate, The image sensor according to claim 6, characterized in that the second via is connected to the substrate through the first contact plug.

8. The present invention further includes a second contact plug that penetrates the interlayer insulating film and is connected to the substrate, The image sensor according to claim 7, characterized in that the third via is connected to the substrate through the second contact plug.

9. The image sensor according to claim 1, characterized in that a power supply voltage is applied to the first via.

10. The image sensor according to claim 1, characterized in that the photoelectric conversion unit is superimposed on the first capacitor and the second capacitor.

11. The first to fourth electrodes are provided in multiple quantities. The first electrode and the second electrode are stacked alternately. The image sensor according to claim 1, characterized in that the third electrode and the fourth electrode are stacked alternately.

12. A substrate including a photoelectric conversion unit, A first capacitor and a second capacitor are spaced apart on the substrate in a first direction parallel to the upper surface of the substrate, A first via is disposed between the first capacitor and the second capacitor, A second via superimposed on the first capacitor, The device comprises a third via superimposed on the second capacitor, The first capacitor and the second capacitor each include a plurality of stacked electrodes and a dielectric film provided on the plurality of electrodes. The first via is connected to a portion of the electrodes of the first capacitor and a portion of the electrodes of the second capacitor. The second via is connected to the remaining electrodes of the first capacitor, excluding the electrode connected to the first via. The image sensor is characterized in that the third via is connected to the remaining electrodes of the second capacitor, excluding the electrode connected to the first via.

13. The substrate further includes a first sampling gate and a second sampling gate, The image sensor according to claim 12, characterized in that the first via is arranged between the first sampling gate and the second sampling gate.

14. The image sensor according to claim 10, characterized in that a portion of the electrodes included in the first capacitor and the second capacitor have a stepped structure.

15. The image sensor according to claim 10, characterized in that the first capacitor and the second capacitor have a symmetrical structure with respect to the first via.

16. A substrate having a first surface and a second surface facing each other, which include a photoelectric conversion section, A first capacitor and a second capacitor are spaced apart in a first direction on the first surface of the substrate, A first via is disposed between the first capacitor and the second capacitor, A second via superimposed on the first capacitor, The device comprises a third via superimposed on the second capacitor, The first capacitor includes first and second electrodes stacked alternately, and a first dielectric film interposed between the first and second electrodes. The second capacitor includes alternately stacked third and fourth electrodes, and a second dielectric film interposed between the third and fourth electrodes. The first via is connected to the first electrode and the third electrode, The second via is connected to the second electrode, The third via is connected to the fourth electrode, An image sensor characterized in that the first electrode and the third electrode, located at the same level, form a first plate.

17. Each of the second electrodes forms a second plate, Each of the fourth electrodes forms a third plate, The image sensor according to claim 16, characterized in that the first plate is superimposed on the second plate and the third plate.

18. The image sensor according to claim 17, characterized in that the area of ​​the first plate is larger than the area of ​​the second plate and the area of ​​the third plate.

19. The image sensor according to claim 16, characterized in that two or more of each of the first to fourth electrodes are provided.

20. The first electrode is an odd-numbered electrode in the first capacitor, The second electrode is an electrode positioned in an even position on the first capacitor, The third electrode is an odd-numbered electrode in the second capacitor, The image sensor according to claim 16, characterized in that the fourth electrode is an electrode positioned in an even position on the second capacitor.

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