Semiconductor equipment

Abstract

This enables miniaturization and high integration of semiconductor devices, including semiconductor modules of different heights and semiconductor devices with multiple electronic components. [Solution] The semiconductor device 1 comprises a semiconductor module 4, a component-embedded substrate 3, a support substrate 2 on which these are mounted, and a wiring layer 7. The component-embedded substrate 3 contains at least one electronic component of a different height from the semiconductor module 4, and its height is aligned with that of the semiconductor module 4. The wiring layer 7 has wiring 72 that is electrically connected to the power semiconductor element 41 and at least one electronic component in the semiconductor module 4, and is positioned on the opposite side from the support substrate 2, with the semiconductor module 4 and the component-embedded substrate 3 in between. The electronic components 31 and 32 have terminals 311 and 312 that are connected to the wiring 72, and are positioned so that terminals 311 and 312 are closer to the wiring layer 7 than to the support substrate 2.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device in which a semiconductor module having a power semiconductor element such as a power MOSFET and one or more electronic components such as passive components and IC chips are mounted on a core material having a plurality of frame-shaped cavities is known (for example, Patent Document 1). MOSFET is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor.

[0003] In the semiconductor device described in Patent Document 1, a wiring layer having a plurality of wirings connected to terminals of a power semiconductor element or an electronic component is formed on one surface of the core material. In this semiconductor device, the power semiconductor element and one or more electronic components are respectively housed in different cavities, and the heat dissipation surfaces on the side opposite to the wiring layer are arranged in alignment.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the semiconductor device described above, the wiring layers connected to the power semiconductor elements and electronic components are formed in the same process, and a current exceeding a predetermined level flows when the power semiconductor elements are driven, so their thickness is greater than that of the signal wiring used solely for signal transmission. Furthermore, in the semiconductor device described above, the power semiconductor elements are taller than the electronic components, so the vias connecting the terminals and the wiring layers are taller on the electronic components. Vias have a roughly conical shape, with their diameter increasing from the terminal side towards the wiring layer side, and those formed on electronic components have a larger diameter than those formed on semiconductor elements.

[0006] In this type of semiconductor device, when it has multiple electronic components in addition to power semiconductor elements, in order to reliably remove the portion of the thick wiring layer that spans multiple electronic components by patterning, the space in the wiring layer that spans these components must be greater than a predetermined amount. In order to secure the space between wirings necessary to reliably remove the portion of the thick wiring layer that connects electronic components, the distance between electronic components must be increased. Furthermore, in this type of semiconductor device, the via diameter of the electronic components is large, and due to the via diameter and space, the required area on one side of the wiring layer becomes large. For this reason, when this type of semiconductor device has power semiconductor elements and multiple electronic components, the overall planar size of the device becomes large, making miniaturization and high integration difficult.

[0007] In view of the above, this disclosure aims to provide a semiconductor device having semiconductor modules and electronic components of different heights, having a smaller planar size than conventional devices, and enabling miniaturization and high integration. [Means for solving the problem]

[0008] One aspect of this disclosure describes a semiconductor device, A semiconductor module (4) having a power semiconductor element (41), A semiconductor module has at least one electronic component (31, 32) of a different height embedded in it, and a component-embedded substrate (3) whose height is the same as that of the semiconductor module, A support substrate (2) on which a semiconductor module and a component-embedded substrate are mounted, The wiring layer (7) has wiring (72) electrically connected to at least one of the power semiconductor elements and electronic components, and is located on the opposite side of the support substrate, sandwiching the semiconductor module and the component-embedded substrate. The electronic component has terminals (311, 321) that connect to the wiring, and the terminals are positioned on the component-embedded substrate closer to the wiring layer than to the support substrate.

[0009] This semiconductor device features semiconductor modules and component-embedded substrates mounted on a support substrate, with wiring layers formed to connect to the terminals of the semiconductor modules and component-embedded substrates. The component-embedded substrate contains electronic components of different heights than the semiconductor modules. Each component-embedded substrate contains at least one electronic component, and its terminals are positioned closer to the wiring layer than to the support substrate. Power semiconductor elements are also positioned closer to the wiring layer than to the support substrate, similar to the electronic components. Therefore, even with a configuration that includes semiconductor modules of different heights and multiple electronic components, the power semiconductor elements and electronic components remain close to the wiring layer, suppressing the increase in via diameter formed on their terminals. Furthermore, the component-embedded substrate is a single component containing at least one electronic component, and the wiring connected to the electronic component's terminals can be formed in a separate process from the wiring connected to the power semiconductor elements, resulting in smaller spacing between wirings. Consequently, even with semiconductor modules of different heights and at least one electronic component, this semiconductor device has a smaller planar size than conventional devices, enabling miniaturization and high integration.

[0010] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view showing a semiconductor device of the first embodiment. [Figure 2] It is a cross-sectional view showing a semiconductor device of a comparative example. [Figure 3A] It is a cross-sectional view showing the first step in the manufacturing process of the semiconductor device of FIG. 1. [Figure 3B] It is a cross-sectional view showing the step following FIG. 3A. [Figure 3C] It is a cross-sectional view showing the step following FIG. 3B. [Figure 3D] It is a cross-sectional view showing the step following FIG. 3C. [Figure 3E] It is a cross-sectional view showing the step following FIG. 3D. [Figure 3F] It is a cross-sectional view showing the step following FIG. 3E. [Figure 3G] It is a cross-sectional view showing the step following FIG. 3F. [Figure 3H] It is a cross-sectional view showing the step following FIG. 3G. [Figure 4] It is a cross-sectional view showing a semiconductor device of the second embodiment. [Figure 5] It is an explanatory view of a component-embedded substrate according to the second embodiment. [Figure 6] It is a cross-sectional view showing a semiconductor device of the third embodiment. [Figure 7] It is a cross-sectional view showing a semiconductor device of the fourth embodiment. [Figure 8] It is a cross-sectional view showing a component-embedded substrate in a semiconductor device of the fifth embodiment. [Figure 9] It is a cross-sectional view taken along line IX-IX of FIG. 8. [Figure 10] It is a cross-sectional view taken along line X-X of FIG. 8. [Figure 11] It is a cross-sectional view showing a component-embedded substrate of a comparative example. [Figure 12] It is a cross-sectional view taken along line XII-XII of FIG. 11. [Figure 13] It is a cross-sectional view taken along line XIII-XIII of FIG. 11. [Figure 14] It is a cross-sectional view showing a component-embedded substrate in a semiconductor device of the sixth embodiment. [Figure 15] It is a cross-sectional view taken along line XV-XV of FIG. 14. [Figure 16] This is a cross-sectional view showing a component-embedded substrate of a comparative example. [Figure 17] This is a cross-sectional view of the line XVII-XVII in Figure 16. [Modes for carrying out the invention]

[0012] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0013] (First Embodiment) The semiconductor device 1 of the first embodiment will be described.

[0014] [Basic configuration] The semiconductor device 1 of this embodiment, as shown in Figure 1 for example, comprises a support substrate 2, a component-embedded substrate 3, a semiconductor module 4, a core material 5, a resin material 6, and a wiring layer 7. In the semiconductor device 1, the semiconductor module 4 constitutes a power circuit through which a predetermined or larger current flows, and the component-embedded substrate 3 constitutes a control circuit for controlling the semiconductor module 4. The semiconductor device 1 is preferably used, for example, as an electronic circuit device for various electronic devices driven by high currents.

[0015] The support substrate 2 is a component that supports the component-embedded substrate 3, the semiconductor module 4, and the core material 5 on which they are mounted. The support substrate 2 can be any support that can mount the above-mentioned multiple components, for example, a printed circuit board or an insulating heat dissipation circuit board such as an AMB substrate or a DCB substrate. AMB and DCB are abbreviations for Active Metal Brazing and Direct Copper Bonding, respectively. From the viewpoint of efficiently dissipating heat from the component-embedded substrate 3 and the semiconductor module 4 to the outside, it is preferable that the support substrate 2 is made of a high heat dissipation material with a high thermal conductivity configuration.

[0016] The component-embedded substrate 3 comprises, for example, multiple electronic components such as an IC chip 31 and a passive component 32, a sealing material 33, an insulating material 34, and wiring 35. The component-embedded substrate 3 is formed in advance as a single control member before being mounted on the support substrate 2. The component-embedded substrate 3 has the IC chip 31 and the passive component 32 arranged so that the forming surfaces of the terminals 311 and 321, which will be described later, are aligned. The component-embedded substrate 3 has approximately the same height dimension as the semiconductor module 4, and the IC chip 31 and the passive component 32 are positioned closer to the wiring layer 7 than the support substrate 2. "Approximately the same" includes not only cases where they are completely identical, but also cases where they are not completely identical due to unavoidable errors in component dimensions and manufacturing processes, but can be considered nearly identical. Hereinafter, for the sake of convenience of explanation, the direction along the thickness direction of the semiconductor device 1 may be referred to as the "height direction Dh," as indicated by the arrows in Figure 1, etc. Furthermore, the component-embedded substrate 3 only needs to have a configuration with at least one electronic component, but in this embodiment, a configuration with two electronic components is described as a representative example.

[0017] The IC chip 31 is a semiconductor element having an integrated circuit for, for example, signal processing and driving control of the semiconductor module 4. The IC chip 31 has a plurality of terminals 311 formed on one side, and this side is exposed from the encapsulating material 33. Vias 312 are connected to the terminals 311 of the IC chip 31, and wiring 35 is connected to the vias 312. The vias 312 and wiring 35 are formed in advance before being mounted on the support substrate 2.

[0018] Passive component 32 is, for example, a passive element such as a capacitor, resistor, or coil. Passive component 32 has, for example, two terminals 321. Vias 322 are connected to terminals 321 of passive component 32, and wiring 35 is connected to vias 322. Vias 322, like vias 312, are formed in advance before being mounted on the support substrate 2. Vias 312 and 322 are made of, for example, a conductive material such as copper and are formed by electroplating. Because vias 312 and 322 are formed before being mounted on the support substrate 2, their height dimension along the height direction Dh is small, and consequently, their diameter in the planar direction of the semiconductor device 1 is kept small.

[0019] The encapsulating material 33 is a component that covers a surface of the IC chip 31 and passive component 32 that is different from the surface on which the vias 312 and 322 are formed. The encapsulating material 33 is made of an insulating material such as a prepreg.

[0020] The insulating material 34 is an insulating member that covers part or all of the forming surface of the terminal 311 of the IC chip 31 and the forming surface of the terminal 321 of the passive component 32. The insulating material 34 is, for example, an insulating adhesive used for fixing when positioning the IC chip 31 and the passive component 32 in the manufacturing process of the component-embedded substrate 3. The insulating material 34 has openings formed to expose the terminal 311 or terminal 321, and vias 312 or vias 322 are formed to fill the openings.

[0021] The wiring 35 is formed on the surface of the component-embedded substrate 3 that faces vias 312 and 322, and is connected to via 312 or via 322. The wiring 35 is made of any conductive material, such as copper.

[0022] The metal layer 36 is a layer formed on the side of the component-embedded substrate 3 opposite to the vias 312 and 322. The metal layer 36 is formed, for example, by electroplating using the same process and materials as the wiring 35. Note that the component-embedded substrate 3 is not limited to a configuration having wiring 35 and a metal layer 36, and may also have a configuration without the metal layer 36.

[0023] The semiconductor module 4 comprises, for example, a power semiconductor element 41 and a heat sink 42, with the power semiconductor element 41 mounted on the heat sink 42. The semiconductor module 4 is a vertical power semiconductor device in which a current exceeding a predetermined value is generated in the thickness direction of the power semiconductor element 41 and the heat sink 42. The power semiconductor element 41 is, for example, a power element such as a power MOSFET or IGBT, and is mounted on the heat sink 42 by a bonding material (not shown) such as solder. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. The heat sink 42 is made of, for example, a material with high thermal conductivity such as copper.

[0024] The core material 5 is a component having a plurality of cavities 51 on which the component-embedded substrate 3 or semiconductor module 4 is placed. The core material 5 is made of, for example, a metallic material such as copper, or a composite material including an inorganic material such as glass and a resin material. In the case of metal, it is fixed to the support substrate 2 by a bonding material not shown, such as solder, and in the case of composite material, by a crimp bond or the like. The core material 5 has a thickness that is, for example, greater than or equal to the thickness of the component-embedded substrate 3 or semiconductor module 4. The cavities 51 are through holes, and their planar size is larger than the component-embedded substrate 3 or semiconductor module 4. The cavities 51 are formed by any method, for example, drilling, photolithography etching, or laser processing.

[0025] The resin material 6 fills the gap between the cavity 51 of the core material 5 and the component-embedded substrate 3 or semiconductor module 4. The resin material 6 is, for example, composed of the resin material in the prepreg that constitutes the insulating layer 71 of the wiring layer 7.

[0026] The wiring layer 7 is formed on the side opposite the support substrate 2, with the component-embedded substrate 3 and semiconductor module 4 in between, and comprises an insulating layer 71 and a plurality of wirings 72. The insulating layer 71 is made up of multiple layers stacked together, for example, a first layer 711, a second layer 712, a third layer 713, and a fourth layer 714. The first layer 711, the second layer 712, and the third layer 713 are made of, for example, prepreg. The fourth layer 714 is made of, for example, solder resist. The first layer 711 has a plurality of openings formed in it, for example by laser processing, and the wirings 72 formed on the first layer 711 are electrically connected to the wirings 35 of the component-embedded substrate 3 and terminals of the power semiconductor element 41 (not shown) through these openings. The second layer 712 and the third layer 713 have a plurality of openings formed in them, similar to the first layer 711, and the wirings 72 are led out to the fourth layer 714 side through these openings. The fourth layer 714 has multiple openings formed in it, for example, by photolithography etching, to expose a portion of the wiring 72 to the outside.

[0027] Multiple wirings 72 are formed on each of the layers 711 to 713 that constitute the insulating layer 71 and are connected to the terminals of the IC chip 31, passive components 32, and power semiconductor elements 41 of the component-embedded substrate 3. Multiple wirings 72 are made of any conductive material, such as copper. Multiple wirings 72 are formed, for example, by electroplating and given a predetermined pattern shape by photolithography etching. Parts of multiple wirings 72 are exposed to the outside on the outermost surface of the insulating layer 71, and wires (not shown) or the like are connected to them.

[0028] In Figure 1, an example is shown in which the insulating layer 71 has a laminated structure of four layers 711 to 714 and four wirings 72. However, the design is not limited to this, and the number of layers in the insulating layer 71 and the number of wirings 72 can be changed as appropriate.

[0029] The above describes the basic configuration of the semiconductor device 1 of this embodiment. The semiconductor device 1 itself can be considered a single large component-embedded substrate that incorporates the component-embedded substrate 3. In this specification, "component-embedded substrate" refers, unless otherwise specified, to a small component that incorporates at least one electronic component and is incorporated into the semiconductor device 1.

[0030] [Effects of miniaturization of semiconductor devices] Next, the effects of miniaturization and high integration of semiconductor device 1 will be explained in comparison with the comparative example semiconductor device 100 shown in Figure 2.

[0031] As shown in Figure 2, the comparative semiconductor device 100 differs from semiconductor device 1 in that it does not have a component-embedded substrate 3, the IC chip 31 and passive components 32 are arranged on the support substrate 2, and vias 313 and 323 are formed that directly connect the wiring 72 of the wiring layer 7 to the electronic components 31 and 32.

[0032] The IC chip 31 and passive components 32 are mounted directly on the support substrate 2 and are smaller in height than the semiconductor module 4. Therefore, the vias 313 and 323 have a larger height dimension along the height direction Dh due to the vias connected to the semiconductor module 4. In addition, since the vias 313 and 323 are formed by creating inverted cone-shaped through holes in the resin material 6 by laser processing, for example, and then filling these through holes by electroplating, the diameter Dp at the portion in contact with the wiring 72 of the wiring layer 7 is large.

[0033] Furthermore, in the comparative example semiconductor device 100, multiple wirings 72 in the wiring layer 7 are connected to the IC chip 31, the passive component 32, and the power semiconductor element 41, respectively, but the multiple wirings 72 are formed in the same process. Since at least a portion of the multiple wirings 72 has wirings 723 that are connected to the power semiconductor element 41 of the semiconductor module 4, the thickness of the other wirings 721 and 722, in addition to wiring 723, is similarly made to be greater than a predetermined thickness to accommodate high currents. On the other hand, among the multiple wirings 72, the wiring 721 connected to the IC chip 31 is separated by patterning so that it is not directly connected to the wiring 722 connected to the passive component 32. From the viewpoints of two things, namely the need for the wiring 72 to be thick enough to accommodate high currents, and the need to ensure that the wirings 721 and 722 are reliably separated by patterning, a space S between adjacent wirings 721 and 722 must be secured to be greater than a predetermined amount. For this reason, the distance between the IC chip 31 and the passive component 32 on the support substrate 2 is set to be greater than a predetermined amount in order to secure the above space S.

[0034] The comparative example semiconductor device 100 is difficult to miniaturize and integrate due to two factors: the diameter Dp of vias 313 and 323 is large, and the space S between wiring 721 and wiring 722 is large.

[0035] In contrast, the semiconductor device 1 of this embodiment is composed of a single component substrate 3 before the IC chip 31 and passive components 32 are mounted on the support substrate 2. Furthermore, vias 312 and 322 have a smaller height dimension and a smaller diameter than vias 313 and 323. As a result, the IC chip 31 and passive components 32 are positioned closer together than in the comparative example semiconductor device 100.

[0036] Furthermore, in the semiconductor device 1, the component-embedded substrate 3 has approximately the same dimensions in the height direction Dh as the semiconductor module 4, and the component-embedded substrate 3 is positioned such that the terminal-forming surfaces of the IC chip 31 and passive component 32 are closer to the wiring layer 7 than the support substrate 2. The wirings 721 and 722 of the wiring layer 7 are connected to the wirings 35 of the component-embedded substrate 3. Therefore, even if the distance between the IC chip 31 and the passive component 32 is small, the adjacent wirings 721 and 722 of the wiring layer 7 have sufficient space compared to the comparative example semiconductor device 100.

[0037] Therefore, by using the component-embedded substrate 3, the semiconductor device 1 reduces the distance between the IC chip 31 and the passive component 32, and also secures space for wirings 721 and 722 in the wiring layer 7, resulting in a smaller planar size compared to the comparative example. As a result, the semiconductor device 1 can be miniaturized and highly integrated.

[0038] [Manufacturing process for semiconductor devices] Next, an example of a manufacturing method for the semiconductor device 1 will be described.

[0039] First, as shown in Figure 3A, for example, a support 30, an IC chip 31, and a passive component 32 are prepared, and the IC chip 31 and the passive component 32 are temporarily fixed onto the support 30 with an adhesive insulating material 34. At this time, the IC chip 31 and the passive component 32 are temporarily fixed with the forming surfaces of the terminals 311 and 321 facing the support 30, and these forming surfaces are aligned. As the support 30, for example, a film support made of any resin material can be used.

[0040] Next, as shown in Figure 3B, for example, the IC chip 31 and passive components 32 temporarily fixed on the support 30 are covered with a sealing material 33. As the sealing material 33, for example, a prepreg can be used, in which case the resin material in the prepreg can seal the IC chip 31 and passive components 32.

[0041] Next, as shown in Figure 3C, for example, the support 30 is peeled off by any method such as laser peeling, and then vias 312, 322, wiring 35, and a metal layer 36 are formed. The vias 312, 322, and wiring 35 are formed by, for example, creating through holes in the insulating material 34 that expose a portion of the terminals 311, 321 by laser processing, forming a seed layer (not shown) by sputtering, and then forming them by electrolytic plating and photolithography etching. The metal layer 36 is formed simultaneously with the vias 312, 322, and wiring 35 when they are formed by electrolytic plating. The component-embedded substrate 3 can be manufactured by the above steps.

[0042] Subsequently, as shown in Figure 3D, for example, the component-embedded substrate 3, along with temporary fixing tape 8, semiconductor module 4, and core material 5 are prepared. The core material 5 has multiple cavities 51 pre-formed, which serve as spaces for housing the components to be mounted. The arrangement and size of the multiple cavities 51 are appropriately changed according to the arrangement and dimensions of the components to be mounted, such as the component-embedded substrate 3 and semiconductor module 4. The temporary fixing tape 8 is used to attach and fix the component-embedded substrate 3, semiconductor module 4, and core material 5 until the wiring layer 7 is formed.

[0043] Then, as shown in Figure 3E, for example, the component-embedded substrate 3, semiconductor module 4, and core material 5 are temporarily fixed by attaching them to the temporary fixing tape 8. At this time, the component-embedded substrate 3 and semiconductor module 4 are placed in different cavities 51. In addition, a prepreg is prepared as the insulating material that constitutes the first layer 711 of the insulating layer 71. Note that in the process shown in Figure 3E, it is sufficient to temporarily fix each component, and if necessary, an adhesive may be used in addition to the temporary fixing tape 8. Thus, the materials and methods used for temporarily fixing the component-embedded substrate 3, semiconductor module 4, and core material 5 may be changed as appropriate.

[0044] Next, as shown in Figure 3F, for example, the first layer 711 is placed so as to cover one side of the component substrate 3, the semiconductor module 4, and the core material 5, and then thermocompression bonding is performed to bond the component substrate 3, the semiconductor module 4, and the core material 5 to the first layer 711. In this process, the gap between the cavity 51 of the core material 5 and the component substrate 3 or the semiconductor module 4 is filled with the resin material in the first layer 711, forming the resin material 6. Then, for example, laser processing is performed on the first layer 711 to create openings that expose the wiring 35 of the IC chip 31, the wiring 35 of the passive component 32, and a portion of the terminals (not shown) of the semiconductor module 4.

[0045] Next, a seed layer (not shown) is formed in the first layer 711 and its openings, and a metal film constituting vias and wiring 72 that fill the openings is formed by electroplating. Then, a resist (not shown) is deposited on the aforementioned metal film, and a portion of the wiring is formed by patterning the resist film and the metal film by photolithography etching, and the resist film is removed with a stripping solution or the like. As a result, for example as shown in Figure 3G, a portion of the wirings 721 to 723 and vias connected to the component substrate 3 or semiconductor module 4 are formed in the first layer 711.

[0046] Subsequently, for example, by repeating the same process as the formation of the first layer 711 and vias / wirings, the second layer 712, the third layer 713 and wiring 72 are laminated on the first layer 711 as shown in Figure 3H. At this time, for example, a support substrate 2 is prepared, and the temporary fixing tape 8 is peeled off from the workpiece obtained by thermocompressing the prepreg that will become the third layer 713 onto the second layer 712, and the side of the workpiece in which the component-embedded substrate 3 and semiconductor module 4 are exposed is connected to the support substrate 2. After that, the prepreg laminated on the second layer 712 is processed and the wiring 72 is laminated, resulting in the state shown in Figure 3H. Then, for example, solder resist is pattern-coated onto the third layer 713 and wiring 72 by screen printing or the like, and then cured by heating or ultraviolet irradiation, etc., to form a fourth layer 714 with a pattern shape having openings that expose some of the wiring 72.

[0047] By following the above steps, the semiconductor device 1 of this embodiment can be manufactured.

[0048] According to this embodiment, the semiconductor device 1 has a component-embedded substrate 3 in which the distance between the IC chip 31 and the passive component 32 is small, and a power semiconductor element 41, and the diameter of the vias connected to the wiring layer 7 is small, thus enabling miniaturization and high integration.

[0049] (Second Embodiment) A semiconductor device 1 of the second embodiment will be described.

[0050] The semiconductor device 1 of this embodiment differs from that of the first embodiment in the configuration of the component-embedded substrate 3, as shown in Figure 4, for example. This embodiment will mainly describe these differences.

[0051] In this embodiment, the component-embedded substrate 3 has, for example, two IC chips 31 and two passive components 32, and these components are electrically connected by through electrodes 37 formed along the height direction Dh of the encapsulating material 33. The component-embedded substrate 3 is manufactured by, for example as shown in Figure 5, by first fabricating a first component 3A and a second component 3B, which have the same configuration as in the first embodiment except for the thickness of the encapsulating material 33, and then joining them back to back with their encapsulating material 33-side faces facing each other. The component-embedded substrate 3 is joined by any method, such as joining the first component 3A and the second component 3B with an adhesive (not shown) or by pressure bonding using a prepreg, but the height dimension is substantially the same as that of the semiconductor module 4. After joining the first component 3A and the second component 3B, through holes are formed that penetrate the encapsulating material 33 of these components by any method, such as laser processing or drilling. The component-embedded substrate 3 then has through-electrodes 37 formed on it that fill through-holes that penetrate the sealing material 33 of the first member 3A and the second member 3B.

[0052] In the component-embedded substrate 3, for example, the IC chip 31 and passive components 32 of the first member 3A are positioned close to the wiring layer 7, and the IC chip 31 and passive components 32 of the second member 3B are positioned close to the support substrate 2. In the component-embedded substrate 3, for example, in the height direction Dh, the IC chip 31 of the first member 3A and the passive components 32 of the second member 3B face each other, and the passive components 32 of the first member 3A and the IC chip 31 of the second member 3B face each other. In this embodiment, the component-embedded substrate 3 has a configuration in which the IC chip 31 and passive components 32 are arranged in the area of ​​the encapsulating material 33 that was only present in the first embodiment due to the difference in height dimension with the semiconductor module 4, i.e., the dead space.

[0053] According to this embodiment, in addition to the effects of the first embodiment described above, the semiconductor device 1 is obtained in which the dead space within the component-embedded substrate 3 is effectively utilized, and the integration density of electronic components is improved.

[0054] (Third embodiment) A semiconductor device 1 of the third embodiment will be described.

[0055] The semiconductor device 1 of this embodiment differs from that of the first embodiment in the configuration of the component-embedded substrate 3, as shown in Figure 6, for example. This embodiment will mainly describe these differences.

[0056] In this embodiment, the component-embedded substrate 3 has a laminated wiring structure in which multiple wirings 351 and 352 are stacked in the height direction Dh, connecting the wiring 35 to the IC chip 31 and the passive component 32. The laminated wiring 35 is formed by stacking the first wiring 351 and the second wiring 352 in the same process as the wiring 72 of the wiring layer 7, for example, from the IC chip 31 and the passive component 32 side. Because the wiring 35 of the component-embedded substrate 3 is a laminated wiring structure, the degree of freedom in the layout of the signal transmission wiring connected to the IC chip 31 and the passive component 32 is improved compared to the case of single-layer wiring, enabling miniaturization and high integration.

[0057] In Figure 6, a typical example is shown where the wiring 35 has a two-layer configuration of wiring 351 and 352, but it is not limited to this, and the number of layers of wiring 35, the wiring pattern, etc. can be changed as appropriate. Also, the wiring 35 is formed as a multilayer wiring before being mounted on the support substrate 2.

[0058] According to this embodiment, the effects of the first embodiment are obtained, and the degree of freedom in the layout of the wiring 35 of the component-embedded substrate 3 is improved, resulting in a semiconductor device 1 with a structure that further enhances the effects of miniaturization and high integration.

[0059] (Fourth Embodiment) The semiconductor device 1 of the fourth embodiment will now be described.

[0060] The semiconductor device 1 of this embodiment differs from that of the first embodiment in the configuration of the component-embedded substrate 3, as shown in Figure 7, for example. This embodiment will mainly describe these differences.

[0061] In this embodiment, the component-embedded substrate 3 has heat dissipation wiring 38 formed on the heat dissipation surface of the IC chip 31, which is the side opposite to the terminals 311. The heat dissipation wiring 38 is made of a metal material with high thermal conductivity, such as copper, and is laminated and formed by the same process as the wiring 72 of the wiring layer 7. For example, the heat dissipation wiring 38 is laminated in the order of a first heat dissipation layer 381, a second heat dissipation layer 382, ​​and a third heat dissipation layer 383 from the IC chip 31 side, and these are connected via vias. The heat dissipation wiring 38 serves as a heat dissipation path that transfers heat from the IC chip 31 to the support substrate 2 side.

[0062] Figure 7 shows an example where the heat dissipation wiring 38 has the three-layer laminated configuration described above, but the configuration is not limited to this, and the number of layers, wiring pattern, etc. can be changed as appropriate. The first heat dissipation layer 381, the second heat dissipation layer 382, ​​and the third heat dissipation layer 383 are, for example, solid blocks that cover the entire planar area of ​​the component-embedded substrate 3, but they may also be in a predetermined patterned shape. Furthermore, the heat dissipation wiring 38 may be connected not only to the IC chip 31 but also to the passive component 32, or it may be connected only to the passive component 32, and the target of heat dissipation can be changed as appropriate.

[0063] Furthermore, although the wiring 35 in Figure 7 is configured as a plurality of wirings laminated with a sealing material 33, similar to the third embodiment described above, it is not limited to this and may be a single-layer configuration. From the viewpoint of reducing manufacturing costs, it is preferable that each layer of the wiring 35 and the heat dissipation wiring 38 is formed in the same process and that the number of layers is the same.

[0064] According to this embodiment, the semiconductor device 1 has a structure that provides the effects of the first embodiment described above, while also improving the heat dissipation of the electronic components embedded in the component-embedded substrate 3.

[0065] (Fifth embodiment) A semiconductor device 1 of the fifth embodiment will now be described.

[0066] The semiconductor device 1 of this embodiment differs from that of the first embodiment in the configuration of the component-embedded substrate 3, as shown in Figure 8, for example. This embodiment will mainly describe these differences.

[0067] In this embodiment, as shown in Figure 8, the component-embedded substrate 3 has a encapsulating material 33 comprising a plurality of prepreg layers 331, a core layer 332, an auxiliary core layer 333, and a resin layer 334. The encapsulating material 33 is stacked in the following order, for example, from the terminal-forming surface side of the IC chip 31 and the passive component 32: prepreg layer 331, core layer 332, prepreg layer 331, auxiliary core layer 333, and prepreg layer 331. The encapsulating material 33 is configured such that the resin layer 334 fills the gaps between the IC chip 31 or passive component 32 and the prepreg layers 331, core layer 332, and auxiliary core layer 333.

[0068] The prepreg layer 331 is arranged, for example, one on the terminal formation side of the IC chip 31 and the passive component 32, one on the back of the IC chip 31, and one on the back of the passive component 32. The back is the surface opposite to the terminal formation surface. The prepreg layer 331 arranged on the back of the IC chip 31 is, for example, a continuous frame shape with an opening surrounding the passive component 32, similar to the core layer 332 described later. The prepreg layer 331 arranged on the back of the passive component 32 is, for example, a rectangular plate shape that covers the entire area of ​​the passive component 32 and the auxiliary core layer 333 described later.

[0069] The core layer 332, like the prepreg layer 331, is composed of a base material such as glass cloth or carbon fiber and a thermosetting resin material. The core layer 332 is harder than the prepreg layer 331 because the thermosetting resin material has hardened more than the prepreg layer 331, and is a component that hardly deforms when laminated on the prepreg layer 331. The core layer 332 is adjusted so that its height when laminated on the prepreg layer 331 is approximately the same as the height of the IC chip 31. As shown in Figure 9, for example, the core layer 332 has an opening that surrounds the IC chip 31 and the passive component 32, and has a continuous frame shape.

[0070] The auxiliary core layer 333 has the same configuration as the core layer 332, for example, and is arranged on the IC chip 31 via a prepreg layer 331. As shown in Figure 10, for example, the auxiliary core layer 333 covers the IC chip 31 and has a single continuous frame shape that surrounds only the passive components 32. The auxiliary core layer 333 is a component that fills the gap caused by the difference in height between the IC chip 31 and the passive components 32, thereby ensuring the flatness of the component-embedded substrate 3, preventing a decrease in strength and deterioration of pressure resistance of the component-embedded substrate 3, and improving reliability.

[0071] Here, we consider a case where the encapsulating material 33 does not have an auxiliary core layer 333, as in the comparative example component-embedded substrate 110 shown in Figure 11. The comparative example component-embedded substrate 110 has the same configuration as the component-embedded substrate 3, except for the configuration of the encapsulating material 33. In the comparative example component-embedded substrate 110, the encapsulating material 33 has multiple prepreg layers 331 and a core layer 332, and does not have an auxiliary core layer 333. Furthermore, the core layer 332 has a continuous frame shape with one opening surrounding the IC chip 31 and the passive component 32, as shown in Figures 12 and 13. In this case, due to the difference in height between the IC chip 31 and the passive component 32, a space S1 is created between the encapsulating material 33 and the prepreg layer 331 placed on the IC chip 31 and the passive component 32, as shown by the dashed line in Figure 13. Furthermore, the sealing material 33 fills the space S1 with the resin material in the prepreg layer 331 placed on the passive component 32. However, if the space S1 is large, it may not be filled with the resin material, which could lead to a decrease in strength or deterioration of pressure resistance.

[0072] The auxiliary core layer 333 can be configured such that the largest electronic component among the multiple electronic components embedded in the component-embedded substrate 3 is designated as the large electronic component, and the other electronic components are designated as other electronic components. The auxiliary core layer 333 is then placed on top of these other electronic components to bridge the height difference between the large electronic component and the other electronic components. Therefore, the auxiliary core layer 333 is not limited to being placed on the IC chip 31; if the IC chip 31 has a greater component height than the passive component 32, it may be placed on the passive component 32. Furthermore, if the component-embedded substrate 3 has other electronic components in addition to the IC chip 31 and passive component 32, the placement of the auxiliary core layer 333 on which electronic component it is placed can be appropriately changed depending on the height relationship between the multiple electronic components.

[0073] According to this embodiment, the effects of the first embodiment are obtained, and the flatness and strength of the component-embedded substrate 3 are ensured, the voltage drop is suppressed, and the semiconductor device 1 has a structure that improves reliability.

[0074] (Sixth Embodiment) The semiconductor device 1 of the sixth embodiment will now be described.

[0075] The semiconductor device 1 of this embodiment differs from that of the first embodiment in the configuration of the component-embedded substrate 3, as shown in Figure 14, for example. This embodiment will mainly describe these differences.

[0076] In this embodiment, the component-embedded substrate 3, as shown in Figure 14 for example, has a encapsulating material 33 comprising a plurality of prepreg layers 331, a core layer 332, a resin layer 334, and an independent auxiliary core layer 335. The component-embedded substrate 3, as shown in Figures 14 and 15 for example, has one IC chip 31 and a plurality of passive components 32, with the plurality of passive components 32 arranged to surround the IC chip 31. The encapsulating material 33 is laminated in the order of prepreg layer 331, core layer 332, and prepreg layer 331 from the terminal-forming surface side of the IC chip 31 and passive components 32. The encapsulating material 33 has one independent auxiliary core layer 335 arranged within a region surrounded by a frame-shaped core layer 332. The gaps between the IC chip 31, the plurality of passive components 32, the core layer 332, and the independent auxiliary core layer 335 in the encapsulating material 33 are filled with the resin layer 334.

[0077] In this embodiment, the core layer 332 has a continuous frame shape with one large opening surrounding the IC chip 31 and the multiple passive components 32. The core layer 332 has, for example, a height greater than that of the IC chip 31 and the multiple passive components 32.

[0078] The independent auxiliary core layer 335 is, for example, placed on the component with the smallest height among multiple electronic components embedded in the component-embedded substrate 3, and is a member that fills the height difference between the multiple electronic components. As shown in Figures 14 and 15, for example, the independent auxiliary core layer 335 is placed on the IC chip 31 within the opening of the core layer 332, and fills the space created by the height difference between the IC chip 31 and the passive component 32. The independent auxiliary core layer 335 is fixed on the IC chip 31 by an adhesive (not shown), for example, so that no misalignment occurs when the prepreg layer 331 is laminated and pressed onto the core layer 332. The independent auxiliary core layer 335 is a member that fills the space created by the height difference between multiple electronic components, ensures the flatness of the component-embedded substrate 3, prevents a decrease in strength and deterioration of voltage resistance of the component-embedded substrate 3, and improves reliability.

[0079] For example, in the case of the comparative example component-embedded substrate 120 shown in Figure 16, where the encapsulating material 33 does not have an independent auxiliary core layer 335, a space S2, indicated by the dashed line, is created within the encapsulating material 33 due to the height difference between the IC chip 31 and the surrounding passive components 32. The comparative example component-embedded substrate 120 has the same structure as the component-embedded substrate 3, except that it does not have an independent auxiliary core layer 335. In the comparative example component-embedded substrate 120, as shown in Figure 17, for example, a space S2 surrounded by multiple passive components 32 is created within the encapsulating material 33, and it is necessary to fill the space S2 with the resin material in the prepreg layer 331 placed on the core layer 332. However, in the comparative example component-embedded substrate 120, if the space S2 is large, it may not be possible to completely fill the space S2 with the resin material, making it impossible to ensure flatness and strength, and potentially leading to a deterioration in pressure resistance.

[0080] On the other hand, in the component-embedded substrate 3 according to this embodiment, the space S2 is filled with an independent auxiliary core layer 335, ensuring the flatness of the prepreg layer 331 mounted on the core layer 332, thereby suppressing a decrease in strength and deterioration of voltage resistance. Note that there may be more than one independent auxiliary core layer 335, and their number, arrangement, and shape can be appropriately changed depending on the height relationship and arrangement of the multiple electronic components embedded in the component-embedded substrate 3.

[0081] According to this embodiment, the effects of the first embodiment are obtained, and the flatness and strength of the component-embedded substrate 3 are ensured, the voltage drop is suppressed, and the semiconductor device 1 has a structure that improves reliability.

[0082] (Other embodiments) This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less of those elements, fall within the scope and concept of this disclosure.

[0083] It goes without saying that, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated to be particularly essential or unless they are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of the embodiment are mentioned, the embodiment is not limited to those specific numbers unless explicitly stated to be particularly essential or unless it is clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shape, positional relationship, etc., of the components are mentioned, the embodiment is not limited to those shapes, positional relationships, etc., unless explicitly stated or unless it is clearly limited to a specific shape, positional relationship, etc., in principle.

[0084] (Perspective of this disclosure) The above disclosure can be understood from the following perspectives, for example. [First point of view] A semiconductor device, A semiconductor module (4) having a power semiconductor element (41), A component-embedded substrate (3) has a height equal to that of the semiconductor module and incorporates at least one electronic component (31, 32) of a different height from the semiconductor module, The semiconductor module and the component-embedded substrate are mounted on a support substrate (2), The wiring layer (7) has wiring (72) electrically connected to at least one of the power semiconductor element and the electronic component, and is located on the opposite side of the support substrate, sandwiching the semiconductor module and the component-embedded substrate. A semiconductor device wherein the electronic component has terminals (311, 321) connected to the wiring, and the terminals are positioned on the component-embedded substrate closer to the wiring layer than the support substrate. [Second perspective] The aforementioned component-integrated circuit board is The device has multiple of the aforementioned electronic components, and the multiple electronic components are arranged so that the forming surfaces of the terminals to which the wiring is connected are aligned. Among the multiple electronic components, the one with the greatest height is designated as the large electronic component, and the other electronic components are designated as other electronic components, and a prepreg layer (331) that contacts the large electronic component is provided. A semiconductor device according to the first aspect, comprising a continuous auxiliary core layer (333) disposed on top of the other electronic component, filling the gap between the other electronic component and the prepreg layer, and surrounding the large electronic component. [Third perspective] The aforementioned component-integrated circuit board is The device has multiple of the aforementioned electronic components, and the multiple electronic components are arranged so that the forming surfaces of the terminals to which the wiring is connected are aligned. A single continuous core layer (332) in the shape of a frame surrounding multiple electronic components, A prepreg layer (331) in contact with the core layer, A semiconductor device according to the first or second aspect, comprising: at least one independent auxiliary core layer (335) fixed to at least one of the plurality of electronic components, disposed between one of the electronic components and the prepreg layer, and independent of the core layer. [Fourth perspective] The aforementioned component-integrated circuit board has wiring (35) connected to the terminal, The semiconductor device according to any one of the first to third aspects, wherein the wiring of the component-embedded substrate has a laminated structure in which two or more layers of wiring are stacked. [Fifth perspective] The semiconductor device according to any one of the first to fourth views, wherein the component-embedded substrate has a plurality of electronic components, the plurality of electronic components are arranged so that the terminal-forming surfaces of the terminals to which the wiring is connected are aligned, and the surface of the plurality of electronic components opposite to the terminals is used as a heat dissipation surface, and a heat dissipation wiring (38) for heat dissipation is connected to the heat dissipation surface of at least one of the electronic components. [Sixth perspective] The semiconductor device according to any one of the first to fourth views, wherein the component-embedded substrate has a plurality of electronic components, the plurality of electronic components are arranged so that the terminal-forming surfaces of the terminals to which the wiring is connected are aligned, and the substrate has a first member (3A) in which the plurality of electronic components are embedded, and a second member (3B) in which a plurality of other electronic components (31, 32) of different height from the semiconductor module are embedded, and the first member and the second member are joined back to back. [Explanation of symbols]

[0085] 2...Support substrate, 3...Component-embedded substrate, 3A...First component, 3B...Second component, 31, 32...Electronic components, 311, 321...Terminals (of electronic components), 331...Prepreg layer, 332...Core layer, 333...Auxiliary core layer, 335...Independent auxiliary core layer, 35...Wiring (of component-embedded substrate), 37...Heat dissipation wiring, 4...Semiconductor module, 41...Power semiconductor element, 7...Wiring layer, 72...Wiring (of wiring layer)

Claims

1. A semiconductor device, A semiconductor module (4) having a power semiconductor element (41), A component-embedded substrate (3) has a height equal to that of the semiconductor module and incorporates at least one electronic component (31, 32) of a different height from the semiconductor module, The semiconductor module and the component-embedded substrate are mounted on a support substrate (2), The wiring layer (7) has wiring (72) electrically connected to at least one of the power semiconductor element and the electronic component, and is located on the opposite side of the support substrate, sandwiching the semiconductor module and the component-embedded substrate. A semiconductor device wherein the electronic component has terminals (311, 321) connected to the wiring, and the terminals are positioned on the component-embedded substrate closer to the wiring layer than the support substrate.

2. The aforementioned component-integrated circuit board is The system has multiple of the aforementioned electronic components, and the multiple electronic components are arranged so that the forming surfaces of the terminals to which the wiring is connected are aligned. Among the multiple electronic components, the one with the greatest height is designated as the large electronic component, and the other electronic components are designated as other electronic components, and a prepreg layer (331) that contacts the large electronic component is provided. The semiconductor device according to claim 1, further comprising a continuous auxiliary core layer (333) disposed on top of the other electronic component, filling the gap between the other electronic component and the prepreg layer, and surrounding the large electronic component.

3. The aforementioned component-integrated circuit board is The system has multiple of the aforementioned electronic components, and the multiple electronic components are arranged so that the forming surfaces of the terminals to which the wiring is connected are aligned. A single continuous core layer (332) in the shape of a frame surrounding multiple electronic components, A prepreg layer (331) in contact with the core layer, The semiconductor device according to claim 1, comprising at least one independent auxiliary core layer (335) fixed to at least one of the plurality of electronic components, disposed between one of the electronic components and the prepreg layer, and independent of the core layer.

4. The aforementioned component-integrated circuit board has wiring (35) connected to the terminal, The semiconductor device according to any one of claims 1 to 3, wherein the wiring of the component-embedded substrate has a laminated structure in which two or more layers of wiring are stacked.

5. The semiconductor device according to claim 1, wherein the component-embedded substrate has a plurality of electronic components, the plurality of electronic components are arranged so that the terminal-forming surfaces of the terminals to which the wiring is connected are aligned, and the surface of the plurality of electronic components opposite to the terminals is used as a heat dissipation surface, and a heat dissipation wiring (38) for heat dissipation is connected to the heat dissipation surface of at least one of the electronic components.

6. The semiconductor device according to claim 1, wherein the component-embedded substrate has a plurality of electronic components, the plurality of electronic components are arranged so that the terminal-forming surfaces of the terminals to which the wiring is connected are aligned, and the substrate has a first member (3A) in which the plurality of electronic components are embedded, and a second member (3B) in which a plurality of other electronic components (31, 32) of different height from the semiconductor module are embedded, and the first member and the second member are joined back to back.

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