Semiconductor device and method for manufacturing the same

Abstract

To improve the reliability of semiconductor devices with non-volatile memory. [Solution] A gate electrode CG is formed on a semiconductor substrate SB via a gate insulating film GF1, and a floating gate electrode FG is formed on the semiconductor substrate SB via a gate insulating film GF2. A sidewall spacer SW1 is formed on the side surface of the gate electrode CG, and a sidewall spacer SW2 is formed on the side surface of the floating gate electrode FG. The floating gate electrode is covered by an insulating film BL, and the gate electrode CG, floating gate electrode FG, sidewall spacers SW1 and SW2, and insulating film BL are covered by an insulating film SN. The insulating film SN is made of silicon nitride. The insulating film BL is made of silicon oxide. The insulating film BL is interposed between the upper surface of the floating gate electrode FG and the insulating film SN. The density of the upper part of the insulating film BL is higher than the density of the lower part of the insulating film BL.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and can be suitably used, for example, for a semiconductor device having a nonvolatile memory and a method for manufacturing the same.

Background Art

[0002] As a nonvolatile memory, a nonvolatile memory having a floating gate electrode is known. The nonvolatile memory having a floating gate electrode stores information by accumulating charges in the floating gate electrode.

[0003] Japanese Patent Application Laid-Open No. 2011-199124 (Patent Document 1) discloses a technique related to a nonvolatile memory having a floating gate electrode.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] It is desired to improve the reliability of a semiconductor device including a nonvolatile memory having a floating gate electrode.

[0006] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0007] According to one embodiment, the semiconductor device includes a semiconductor substrate, a floating gate electrode formed on the semiconductor substrate via a first gate insulating film, a first sidewall spacer formed on the side surface of the floating gate electrode, and a first insulating film covering the floating gate electrode. The semiconductor device further includes a silicon nitride film covering the floating gate electrode, the first sidewall spacer, and the first insulating film. The first insulating film is made of silicon oxide. The first insulating film is interposed between the upper surface of the floating gate electrode and the silicon nitride film. The density of the upper part of the first insulating film is higher than the density of the lower part of the first insulating film. [Effects of the Invention]

[0008] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view of the main part of the semiconductor device according to Embodiment 1. [Figure 3] This is a cross-sectional view of a key part during the manufacturing process of the semiconductor device according to Embodiment 1. [Figure 4] Figure 3 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 5] Figure 4 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 6] Figure 5 is a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 7] Figure 6 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 8] Figure 7 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 9] Figure 8 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 10] Figure 9 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device. [Figure 11]It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 10. [Figure 12] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 12. [Figure 14] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 13. [Figure 15] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 14. [Figure 16] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 15. [Figure 17] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 16. [Figure 18] It is a cross-sectional view of the main part during the manufacturing process of the semiconductor device following FIG. 17. [Figure 19] It is a cross-sectional view of the main part of the semiconductor device of the first study example. [Figure 20] It is a cross-sectional view of the main part of the semiconductor device of the first study example. [Figure 21] It is a cross-sectional view of the main part of the semiconductor device of Embodiment 2. [Figure 22] It is a plan view of the main part of the semiconductor device of Embodiment 2. [Figure 23] It is a plan view of the main part of the semiconductor device of the first modification example of Embodiment 2. [Figure 24] It is a plan view of the main part of the semiconductor device of the second modification example of Embodiment 2. [Figure 25] It is a plan view of the main part of the semiconductor device of the third modification example of Embodiment 2. [Figure 26] It is a cross-sectional view of the main part of the semiconductor device of Embodiment 3. [Figure 27] It is a cross-sectional view of the main part of the semiconductor device of Embodiment 4. [Figure 28] It is a cross-sectional view of the main part of the semiconductor device of Embodiment 4.

Modes for Carrying Out the Invention

[0010] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.) in the following embodiments, unless otherwise specified or clearly limited to a specific number in principle, it is not limited to that specific number, and may be greater than or less than that number. Moreover, in the following embodiments, it goes without saying that the constituent elements (including element steps, etc.) are not necessarily essential unless otherwise specified or clearly considered essential in principle. Similarly, when referring to the shape, positional relationship, etc. of constituent elements, etc. in the following embodiments, unless otherwise specified or clearly considered not to be so in principle, it shall include those that substantially approximate or resemble that shape, etc. The same applies to the numerical values ​​and ranges mentioned above.

[0011] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0012] Furthermore, in the drawings used in the embodiments, hatching may be omitted even in cross-sectional views to improve readability. Conversely, hatching may be added to plan views to improve readability.

[0013] Furthermore, a planar view refers to viewing the semiconductor substrate (SB) from a plane approximately parallel to its main or back surface. Also, "bottom surface" and "bottom surface" have the same meaning.

[0014] Furthermore, in this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFETs using an oxide film as the gate insulating film, but also MOSFETs using insulating films other than oxide films as the gate insulating film.

[0015] (Embodiment 1) <About the structure of semiconductor devices> Figures 1 and 2 show the X, Y, and Z directions. The X and Y directions are approximately parallel to the main surface of the semiconductor substrate SB, and the Z direction is approximately perpendicular to the main surface of the semiconductor substrate SB. The X, Y, and Z directions are orthogonal to each other. The cross-sectional view shown in Figure 1 is parallel to the X and Z directions and perpendicular to the Y direction. The cross-sectional view shown in Figure 2 is parallel to the Y and Z directions and perpendicular to the X direction.

[0016] As shown in Figures 1 and 2, the semiconductor device of Embodiment 1 comprises a semiconductor substrate SB, an STI region 2, a p-type well PW, a control gate electrode CG, a floating gate electrode FG, a gate insulating film GF1, a gate insulating film GF2, an n-type semiconductor region SD1, an n-type semiconductor region SD2, an n-type semiconductor region SD3, a sidewall spacer SW1, and a sidewall spacer SW2. As shown in Figures 1 and 2, the semiconductor device of Embodiment 1 further comprises an insulating film BL, a metal silicide layer SL, an insulating film SN, an insulating film SO, a plug PG, and wiring M1.

[0017] The semiconductor substrate SB is made of, for example, p-type single-crystal silicon. The semiconductor substrate SB has a main surface and a back surface opposite to the main surface.

[0018] The STI (Shallow Trench Isolation) region 2 consists of an insulating film embedded in a groove formed within the semiconductor substrate SB. The STI region 2 can be considered an insulating region.

[0019] The p-type well PW and the n-type semiconductor region SD1, n-type semiconductor region SD2, and n-type semiconductor region SD3 are formed within the semiconductor substrate SB.

[0020] The control gate electrode CG is formed on the main surface (on the p-type well PW) of the semiconductor substrate SB via a gate insulating film GF1. Therefore, the gate insulating film GF1 is interposed between the control gate electrode CG and the semiconductor substrate SB. The gate width direction of the control gate electrode CG is the Y direction, and the gate length direction of the control gate electrode CG is the X direction.

[0021] The floating gate electrode (FG) is formed on the main surface (on the p-type well PW) of the semiconductor substrate SB via a gate insulating film GF2. Therefore, the gate insulating film GF2 is interposed between the floating gate electrode FG and the semiconductor substrate SB. The gate width direction of the floating gate electrode FG is the Y direction, and the gate length direction of the floating gate electrode FG is the X direction. The control gate electrode CG and the floating gate electrode FG are separated from each other.

[0022] A sidewall spacer SW1 is formed on the side (side wall) of the control gate electrode CG as a sidewall insulating film. A sidewall spacer SW2 is formed on the side (side wall) of the floating gate electrode FG as a sidewall insulating film.

[0023] The control gate electrode CG and the floating gate electrode FG are adjacent to each other in the X direction. In a plan view (specifically in the X direction), the control gate electrode CG, n-type semiconductor region SD2, and floating gate electrode FG are located between n-type semiconductor region SD1 and n-type semiconductor region SD3, and n-type semiconductor region SD2 is located between the control gate electrode CG and the floating gate electrode FG. In a plan view (specifically in the X direction), the control gate electrode CG is located between n-type semiconductor region SD1 and n-type semiconductor region SD2, and the floating gate electrode FG is located between n-type semiconductor region SD2 and n-type semiconductor region SD3.

[0024] n-type semiconductor regions SD1, SD2, and SD3 are formed within a p-type well PW. n-type semiconductor region SD1 functions as either a source or a drain. n-type semiconductor region SD1 contains n-type semiconductor region E1 and n-type semiconductor region H1. The n-type impurity concentration in n-type semiconductor region H1 is higher than that in n-type semiconductor region E1. Therefore, n-type semiconductor region SD1 has an LDD (Lightly Doped Drain) structure. n-type semiconductor region E1 is located below the sidewall spacer SW1. In a plan view, n-type semiconductor region E1 is located between n-type semiconductor region H1 and the control gate electrode CG.

[0025] The n-type semiconductor region SD2 functions as either a source or a drain. The n-type semiconductor region SD2 includes n-type semiconductor regions E2a, E2b, and H2. The n-type impurity concentration in n-type semiconductor region H2 is higher than that in n-type semiconductor region E2a and also higher than that in n-type semiconductor region E2b. Therefore, the n-type semiconductor region SD2 has an LDD structure. n-type semiconductor region E2a is located below sidewall spacer SW1, and n-type semiconductor region E2b is located below sidewall spacer SW2. In a plan view, n-type semiconductor region E2a is located between n-type semiconductor region H2 and control gate electrode CG, and n-type semiconductor region E2b is located between n-type semiconductor region H2 and floating gate electrode FG.

[0026] The n-type semiconductor region SD3 functions as either a source or a drain. The n-type semiconductor region SD3 includes n-type semiconductor regions E3 and H3. The n-type impurity concentration in n-type semiconductor region H3 is higher than that in n-type semiconductor region E3. Therefore, the n-type semiconductor region SD3 has an LDD structure. The n-type semiconductor region E3 is located below the sidewall spacer SW2. In a plan view, the n-type semiconductor region E3 is located between the n-type semiconductor region H3 and the floating gate electrode FG. Note that the n-type semiconductor region E3 may not always be formed.

[0027] A metal silicide layer SL is formed on the upper surface of n-type semiconductor region H1, on the upper surface of n-type semiconductor region H2, on the upper surface of n-type semiconductor region H3, and on the upper surface of the control gate electrode CG. No metal silicide layer SL is formed on the floating gate electrode FG. In some cases, the metal silicide layer SL is not formed on the upper surface of n-type semiconductor region H2.

[0028] The insulating film (silicon oxide film) BL is formed to cover at least the upper surface of the floating gate electrode FG, and preferably to cover the floating gate electrode FG and the sidewall spacer SW2. The entire upper surface of the floating gate electrode FG is covered by the insulating film BL. In a plan view, the floating gate electrode FG is enclosed within the insulating film BL. The control gate electrode CG is not covered by the insulating film BL. That is, in a plan view, the control gate electrode CG does not overlap with the insulating film BL.

[0029] The insulating film BL consists of a multilayer film including insulating film (silicon oxide film) BL1 and insulating film (silicon oxide film) BL2 on insulating film BL1. Insulating film BL1 is made of silicon oxide and is formed using the thermal CVD (Chemical Vapor Deposition) method. Insulating film BL2 is made of silicon oxide and is formed using the plasma CVD (Chemical Vapor Deposition) method. That is, although insulating films BL1 and BL2 are both made of silicon oxide, the deposition methods for insulating film BL1 and insulating film BL2 are different. Reflecting that insulating film BL1 is formed using the thermal CVD method and insulating film BL2 is formed using the plasma CVD method, the density (atomic density) of insulating film BL1 is smaller than the density (atomic density) of insulating film BL2. Here, atomic density corresponds to the number of atoms per unit volume. The upper surface of the floating gate electrode FG is in contact with insulating film BL1.

[0030] In the X direction, one end of the insulating film BL is located on the n-type semiconductor region H2, and the other end is located on the n-type semiconductor region H3. Therefore, a portion of the n-type semiconductor region H2 is covered by the insulating film BL, while the other portion of the n-type semiconductor region H2 is not covered and is exposed from the insulating film BL. A metal silicide layer SL is formed on the n-type semiconductor region H2 that is exposed from the insulating film BL. No metal silicide layer SL is formed on the n-type semiconductor region H2 that is covered by the insulating film BL. A portion of the n-type semiconductor region H3 is covered by the insulating film BL, while the other portion of the n-type semiconductor region H3 is not covered and is exposed from the insulating film BL. A metal silicide layer SL is formed on the n-type semiconductor region H3 that is exposed from the insulating film BL. No metal silicide layer SL is formed on the n-type semiconductor region H3 that is covered by the insulating film BL.

[0031] An insulating film (silicon nitride film) SN is formed on the main surface of the semiconductor substrate SB, covering the control gate electrode CG, the floating gate electrode FG, the sidewall spacers SW1 and SW2, the metal silicide layer SL, and the insulating film BL. An insulating film SO is formed on top of the insulating film SN.

[0032] The insulating film SN is made of silicon nitride. The thickness of the insulating film SN is less than the thickness of the insulating film SO. The insulating film SO is made of a different material from the insulating film SN, preferably silicon oxide. A low-dielectric-constant film (low-k film) having a dielectric constant lower than that of silicon oxide can also be used as the insulating film SO. A multilayer film containing insulating film SN and insulating film SO can function as an interlayer insulating film.

[0033] An insulating film BL is interposed between the upper surface of the floating gate electrode FG and the insulating film SN. Therefore, the floating gate electrode FG is not in contact with the insulating film SN. The distance (spacing) in the Z direction from the insulating film SN to the upper surface of the floating gate electrode FG is the same as the thickness T1 of the insulating film BL. The upper surface of insulating film BL (upper surface of insulating film BL2) is in contact with the insulating film SN. The upper surface of the metal silicide layer SL on the control gate electrode CG is in contact with the insulating film SN. Therefore, the distance between the floating gate electrode FG and the insulating film SN is greater than the distance between the metal silicide layer SL on the control gate electrode CG and the insulating film SN.

[0034] A conductive plug PG is formed within a contact hole that penetrates the insulating film SO and insulating film SN. Wiring M1 is formed on the insulating film SO. The upper surface of plug PG is in contact with wiring M1.

[0035] Plug PG is positioned on the n-type semiconductor region H1, the n-type semiconductor region H3, and the control gate electrode CG, respectively. Figure 1 shows plug PG positioned on the n-type semiconductor region H3. Since the potential of the floating gate electrode FG is a floating potential, plug PG is not positioned on the floating gate electrode FG.

[0036] Illustrations and descriptions of the insulating film SO and the structure above wiring M1 are omitted.

[0037] A non-volatile memory element (memory element, memory cell) MC has a configuration in which two MOSFETs are connected in series: a control transistor (selection transistor) having a control gate electrode CG, and a memory transistor (storage transistor) having a floating gate electrode FG. The n-type semiconductor region SD1 functions as the drain region of the control transistor, the n-type semiconductor region SD3 functions as the source region of the memory transistor, and the n-type semiconductor region SD2 serves as both the source region of the control transistor and the drain region of the memory transistor. Alternatively, the n-type semiconductor region SD1 functions as the source region of the control transistor, the n-type semiconductor region SD3 functions as the drain region of the memory transistor, and the n-type semiconductor region SD2 serves as both the drain region of the control transistor and the source region of the memory transistor. By accumulating or holding charge within the floating gate electrode FG, information can be stored in the memory element MC.

[0038] During the write operation of the memory element MC, charge (electrons in this case) is injected from the semiconductor substrate SB to the floating gate electrode FG. During the erase operation of the memory element MC, the charge (electrons in this case) accumulated in the floating gate electrode FG is moved out of the floating gate electrode FG. For example, the charge accumulated in the floating gate electrode FG is moved to the insulating film surrounding the floating gate electrode FG or to the semiconductor substrate SB. Because the threshold voltage of the memory transistor differs depending on whether charge (electrons in this case) is accumulated in the floating gate electrode FG or not, the information stored in the memory element MC can be read out based on the difference in the threshold voltage of the memory transistor.

[0039] Furthermore, Figure 1 shows a single memory element MC. In reality, multiple memory elements MC are formed in an array on the main surface of the semiconductor substrate SB.

[0040] The case where both the control transistor and the memory transistor are n-channel MOSFETs has been explained. It is also possible that both the control transistor and the memory transistor are p-channel MOSFETs.

[0041] <Regarding the manufacturing process of semiconductor devices> Figures 3 to 18 show cross-sections corresponding to Figure 1 above.

[0042] As shown in Figure 3, a semiconductor substrate (semiconductor wafer) SB made of p-type single-crystal silicon or the like is prepared.

[0043] Next, an STI region 2 (see Figure 2 above) that defines the active region is formed on the main surface of the semiconductor substrate SB using the STI method.

[0044] After forming grooves in the semiconductor substrate SB, an insulating film, such as a silicon oxide film, is formed on the main surface of the semiconductor substrate SB to fill the grooves. Subsequently, the insulating film located outside the grooves is removed using a method such as CMP (Chemical Mechanical Polishing). This allows for the formation of an STI region 2 consisting of the insulating film embedded in the grooves.

[0045] Next, as shown in Figure 3, p-type wells PW are formed in the semiconductor substrate SB using ion implantation. The p-type wells PW are formed to a predetermined depth from the main surface of the semiconductor substrate SB.

[0046] Next, as shown in Figure 4, an insulating film GF is formed on the main surface (upper surface of the p-type well PW) of the semiconductor substrate SB. The insulating film GF consists of a silicon oxide film or the like and can be formed using methods such as thermal oxidation.

[0047] Next, as shown in Figure 4, a silicon film PS is formed as a conductive film on the main surface of the semiconductor substrate SB, i.e., on the insulating film GF. The silicon film PS consists of a doped polysilicon film and can be formed using methods such as CVD.

[0048] Next, as shown in Figure 5, the control gate electrode CG and the floating gate electrode FG are formed by patterning the silicon film PS using photolithography and dry etching techniques. The control gate electrode CG and the floating gate electrode FG consist of the patterned silicon film PS and are formed on the main surface of the semiconductor substrate SB via an insulating film GF. The control gate electrode CG and the floating gate electrode FG are spaced apart from each other.

[0049] The insulating film GF remaining beneath the control gate electrode CG is the gate insulating film GF1, and the insulating film GF remaining beneath the floating gate electrode FG is the gate insulating film GF2. The control gate electrode CG is formed on a p-type well PW via the gate insulating film GF1. The floating gate electrode FG is formed on a p-type well PW via the gate insulating film GF2.

[0050] Next, as shown in Figure 6, n-type semiconductor regions E1, E2, and E3 are formed within the semiconductor substrate SB using ion implantation.

[0051] n-type semiconductor regions E1, E2, and E3 are formed within the p-type well PW. The control gate electrode CG and the floating gate electrode FG can each function as ion implantation blocking masks.

[0052] Therefore, the n-type semiconductor region E1 is formed within the p-type well PW, self-aligned with one side of the control gate electrode CG. The n-type semiconductor region E3 is formed within the p-type well PW, self-aligned with one side of the floating gate electrode FG. The n-type semiconductor region E2 is formed within the p-type well PW, self-aligned with the other side of the control gate electrode CG and the other side of the floating gate electrode FG. In a plan view, the n-type semiconductor region E2 is formed between the control gate electrode CG and the floating gate electrode FG.

[0053] Next, as shown in Figure 7, sidewall spacers SW1 and SW2 are formed. Sidewall spacer SW1 is formed on the side (side wall) of the control gate electrode CG. Sidewall spacer SW2 is formed on the side (side wall) of the floating gate electrode FG.

[0054] For example, an insulating film (e.g., a silicon oxide film) is formed on the main surface of a semiconductor substrate SB so as to cover the control gate electrode CG and the floating gate electrode FG, and then the insulating film is etched back using an anisotropic etching technique. As a result, sidewall spacers SW1 and SW2 can be formed by the insulating film selectively remaining on the respective sides of the control gate electrode CG and the floating gate electrode FG.

[0055] Next, as shown in Figure 8, n-type semiconductor regions H1, H2, and H3 are formed within the semiconductor substrate SB using ion implantation. The control gate electrode CG and sidewall spacer SW1, and the floating gate electrode FG and sidewall spacer SW2 can each function as ion implantation blocking masks.

[0056] Therefore, the n-type semiconductor region H1 is formed in the p-type well PW by self-aligning with the sidewall spacer SW1 on one side of the control gate electrode CG. The n-type semiconductor region H3 is formed in the p-type well PW by self-aligning with the sidewall spacer SW2 on one side of the floating gate electrode FG. The n-type semiconductor region H2 is formed in the p-type well PW by self-aligning with the sidewall spacer SW1 on the other side of the control gate electrode CG and the sidewall spacer SW2 on the other side of the floating gate electrode FG. The n-type semiconductor region E2 below the sidewall spacer SW1 is the n-type semiconductor region E2a, and the n-type semiconductor region E2 below the sidewall spacer SW2 is the n-type semiconductor region E2b.

[0057] As a result, an n-type semiconductor region SD1 consisting of n-type semiconductor region E1 and n-type semiconductor region H1, an n-type semiconductor region SD2 consisting of n-type semiconductor region E2a, n-type semiconductor region E2b and n-type semiconductor region H2, and an n-type semiconductor region SD3 consisting of n-type semiconductor region E3 and n-type semiconductor region H3 are formed within the p-type well PW.

[0058] Next, as shown in Figure 9, an insulating film BL1a is formed on the main surface of the semiconductor substrate SB so as to cover the control gate electrode CG, the floating gate electrode FG, the sidewall spacers SW1 and SW2, and the n-type semiconductor regions H1, H2, and H3. The insulating film BL1a is made of silicon oxide and can be formed using a thermal CVD method. An atmospheric pressure CVD method is preferred as the thermal CVD method for forming the insulating film BL1a. The thickness of the insulating film BL1a after formation is referred to as the formation thickness of the insulating film BL1a.

[0059] Next, an activation annealing treatment (heat treatment) is performed to activate the impurities (p-type and n-type impurities) introduced into the p-type well PW, n-type semiconductor region E1, n-type semiconductor region H1, n-type semiconductor region E2 (E2a, E2b), n-type semiconductor region H2, n-type semiconductor region E3, and n-type semiconductor region H3. For example, lamp annealing can be used as the activation annealing treatment.

[0060] Next, as shown in Figure 10, an insulating film (silicon oxide film) BL2a is formed on the insulating film BL1a. The insulating film BL2a is made of silicon oxide and can be formed using plasma CVD. The thickness of the insulating film BL2a after its formation is referred to as the formation thickness of the insulating film BL2a.

[0061] A multilayer film including insulating film BL1a and insulating film BL2a on insulating film BL1a is referred to as insulating film BLa. Insulating film BLa is formed on the main surface of the semiconductor substrate SB so as to cover the control gate electrode CG, the floating gate electrode FG, the sidewall spacer SW1, the sidewall spacer SW2, and the n-type semiconductor region H1, n-type semiconductor region H2, and n-type semiconductor region H3.

[0062] Next, as shown in Figure 11, a photoresist pattern (mask layer) RP1 is formed on the insulating film BLa (i.e., on the insulating film BL2a) using photolithography technology.

[0063] In a plan view, the photoresist pattern RP1 contains the floating gate electrode FG. In other words, in a plan view, the entire floating gate electrode FG overlaps with the photoresist pattern RP1. In Figure 11, the floating gate electrode FG and sidewall spacer SW2 are contained within the photoresist pattern RP1 in a plan view. The control gate electrode CG and sidewall spacer SW1 do not overlap with the photoresist pattern RP1 in a plan view.

[0064] Next, as shown in Figure 12, the photoresist pattern RP1 is used as an etching mask to etch the insulating film BLa exposed from the photoresist pattern RP1. This etching process is referred to as the etching process in Figure 12. The etching process in Figure 12 removes the insulating film BLa exposed from the photoresist pattern RP1, leaving the insulating film BLa behind the photoresist pattern RP1. The insulating film BL is formed by the insulating film BLa remaining beneath the photoresist pattern RP1. The planar dimensions and position of the insulating film BL are approximately the same as those of the photoresist pattern RP1.

[0065] The insulating film BL consists of a patterned insulating film BLa. The insulating film BL1 that makes up the insulating film BL consists of a patterned insulating film BL1a. The insulating film BL2 that makes up the insulating film BL consists of a patterned insulating film BL2a. The thickness of insulating film BL1 that makes up the insulating film BL is approximately the same as the formation thickness of insulating film BL1a. The thickness of insulating film BL2 that makes up the insulating film BL is approximately the same as the formation thickness of insulating film BL2a.

[0066] The insulating film BL is formed to cover at least the floating gate electrode FG, and preferably to cover the floating gate electrode FG and the sidewall spacer SW2. The control gate electrode CG is not covered by the insulating film BL. In a plan view, the entire floating gate electrode FG overlaps with the insulating film BL, while the control gate electrode CG does not overlap with the insulating film BL.

[0067] The etching process shown in Figure 12 removes the insulating film BLa that is not covered by the photoresist pattern RP1 (i.e., the insulating film BLa that does not overlap with the photoresist pattern RP1 in a plan view). As a result of performing the etching process shown in Figure 12, the top surface of the control gate electrode CG, the top surface of the n-type semiconductor region H1, the top surface of the n-type semiconductor region H2, and the top surface of the n-type semiconductor region H3 are exposed.

[0068] In the case of Figure 12, the insulating film BL covers a portion of the upper surface of the n-type semiconductor region H2 and a portion of the upper surface of the n-type semiconductor region H3. In this case, the upper surface of the n-type semiconductor region H2 has a portion covered by the insulating film BL and a portion not covered by the insulating film BL, and the upper surface of the n-type semiconductor region H3 also has a portion covered by the insulating film BL and a portion not covered by the insulating film BL.

[0069] Next, remove the photoresist pattern RP1.

[0070] Next, as shown in Figure 13, a metal film ME is formed on the main surface (entire main surface) of the semiconductor substrate SB so as to cover the control gate electrode CG, the floating gate electrode FG, the sidewall spacers SW1 and SW2, the n-type semiconductor regions H1, H2 and H3, and the insulating film BL. The metal film ME consists of, for example, a cobalt film, a nickel film, or a nickel-platinum alloy film, and can be formed using a sputtering method or the like.

[0071] The metal film ME is in contact with the upper surface of the control gate electrode CG, the upper surface of the n-type semiconductor region H1, the upper surface of the n-type semiconductor region H2, and the upper surface of the n-type semiconductor region H3. Because an insulating film BL is interposed between the metal film ME and the floating gate electrode FG, the metal film ME is not in contact with the floating gate electrode FG.

[0072] Next, the semiconductor substrate SB is subjected to heat treatment to react the upper surfaces of the control gate electrode CG and the n-type semiconductor regions H1, H2, and H3 with the metal film ME. As a result, as shown in Figure 14, metal silicide layers SL, which are reaction layers between silicon and metal, are formed on the control gate electrode CG, n-type semiconductor region H1, n-type semiconductor region H2, and n-type semiconductor region H3, respectively. Because the insulating film BL is interposed between the metal film ME and the floating gate electrode FG, the metal film ME does not react with the floating gate electrode FG, and therefore, the metal silicide layer SL is not formed on the floating gate electrode FG. In other words, since the metal silicide layer SL formation process is performed with the insulating film BL covering the floating gate electrode FG, the metal silicide layer SL is not formed on the floating gate electrode FG.

[0073] Next, the unreacted metal film ME is removed by wet etching or the like. Figure 14 shows the state after the removal of the unreacted metal film ME. Thus, the metal silicide layer SL is formed using salicide (Self-Aligned Silicide) technology.

[0074] Next, as shown in Figure 15, an insulating film (silicon nitride film) SN is formed on the main surface of the semiconductor substrate SB so as to cover the control gate electrode CG, the floating gate electrode FG, the sidewall spacers SW1 and SW2, the n-type semiconductor region H1, n-type semiconductor region H2, n-type semiconductor region H3, the metal silicide layer SL, and the insulating film BL. The insulating film SN is made of silicon nitride and can be formed using methods such as CVD.

[0075] Because the insulating film BL is interposed between the floating gate electrode FG and the insulating film SN, the floating gate electrode FG is not in contact with the insulating film SN. The metal silicide layer SL on the control gate electrode CG, the metal silicide layer SL on the n-type semiconductor region H1, the metal silicide layer SL on the n-type semiconductor region H2, and the metal silicide layer SL on the n-type semiconductor region H3 are in contact with the insulating film SN.

[0076] Next, as shown in Figure 15, an insulating film SO is formed on the insulating film SN. The thickness of the insulating film SO is greater than the thickness of the insulating film SN. The insulating film SO is made of a different material from the insulating film SN, and is preferably made of silicon oxide. A low dielectric constant film can also be used as the insulating film SO. After forming the insulating film SO, the upper surface of the insulating film SO is polished and flattened using a method such as CMP (Chemical Mechanical Polishing) as needed.

[0077] Next, as shown in Figure 15, a photoresist pattern (mask layer) RP2 is formed on the insulating film SO using photolithography technology.

[0078] Next, as shown in Figure 16, contact holes CT are formed in the insulating film SO by etching the insulating film SO using the photoresist pattern RP2 as an etching mask. This etching is performed under conditions where the etching rate of the insulating film SN is smaller than that of the insulating film SO. As a result, contact holes CT are formed that penetrate the insulating film SO, and the insulating film SN exposed from the contact holes CT functions as an etching stopper film. Therefore, the contact holes CT penetrate the insulating film SO but do not penetrate the insulating film SN.

[0079] Next, as shown in Figure 17, the photoresist pattern RP2 is used as an etching mask to etch the insulating film SN exposed from the insulating film SO. This etching is performed under conditions where the etching rate of the insulating film SN is greater than the etching rate of the insulating film SO. As a result, the contact hole CT penetrates the insulating film SN, and the metal silicide layer SL is exposed through the contact hole CT. This forms a contact hole CT that penetrates both the insulating film SO and the insulating film SN.

[0080] Next, as shown in Figure 18, a conductive plug PG is formed in the contact hole CT.

[0081] For example, a barrier conductor film is formed on the bottom surface of the contact hole CT, on the side surface of the contact hole CT, and on the top surface of the insulating film SO. Next, a main body film made of tungsten or the like is formed on the barrier conductor film so as to fill the inside of the contact hole CT. After that, the main body film and barrier conductor film located outside the contact hole CT are removed by a method such as CMP. This allows the plug PG to be formed.

[0082] Next, as shown in Figure 18, multiple wirings M1 are formed on the insulating film SO. For example, a conductive film is formed on the insulating film SO. Then, by patterning the conductive film using photolithography and etching techniques, multiple wirings M1 made of the conductive film can be formed. Aluminum wiring is preferred as the wiring M1, but wiring using other metal materials, such as tungsten wiring, can also be used. In addition, copper wiring formed using damascene techniques can also be used as the wiring M1.

[0083] The illustration and explanation of the process of forming an insulating film and wiring on top of the wiring M1 and insulating film SO are omitted.

[0084] <Background of the consideration> In the semiconductor device of the first example shown in Figure 19, an insulating film BL101 is formed instead of the insulating film BL mentioned above.

[0085] The insulating film BL101 is a single layer of silicon oxide film. The insulating film BL101 is formed to cover the floating gate electrode FG and the sidewall spacer SW2. Therefore, the insulating film BL101 (silicon oxide film) is interposed between the upper surface of the floating gate electrode FG and the insulating film SN (silicon nitride film). The control gate electrode CG is not covered by the insulating film BL101.

[0086] The present inventors are investigating a non-volatile memory having a floating gate electrode. A non-volatile memory having a floating gate electrode can store information by accumulating charge on the floating gate electrode. Therefore, it is important to improve the charge retention characteristics of the non-volatile memory and to prevent charge from unintentionally escaping from the floating gate electrode.

[0087] Non-volatile memory is erased using either electrical erasure or ultraviolet (UV) light. In the case of electrical erasure, for example, by applying a predetermined positive potential to the n-type semiconductor region SD3 with the potentials of the n-type semiconductor region SD1, the control gate electrode CG, and the p-type well PW all set to 0V, electrons accumulated in the floating gate electrode FG are drawn out into the n-type semiconductor region SD3 by passing through the gate insulating film GF2 (tunneling). As a result, the number of electrons accumulated in the floating gate electrode FG decreases, and the memory element enters an erased state. In the case of UV light erasure, by irradiating the floating gate electrode FG with UV light, electrons accumulated in the floating gate electrode FG are excited, causing them to move out of the floating gate electrode FG. As a result, the number of electrons accumulated in the floating gate electrode FG decreases, and the memory element enters an erased state.

[0088] When ultraviolet light is irradiated onto the floating gate electrode FG during the erase operation, the insulating film SN (silicon nitride film) located above the floating gate electrode FG is also irradiated with ultraviolet light. In other words, since ultraviolet light that has passed through the insulating film SO, insulating film SN, and insulating film BL101 is incident on the floating gate electrode FG, it is unavoidable that the insulating film SN is irradiated with ultraviolet light.

[0089] According to the inventors' research, it was found that irradiation of the insulating film SN (silicon nitride film) with ultraviolet light may cause a decrease in the charge retention characteristics of non-volatile memory.

[0090] The hydrogen content of silicon nitride films tends to be higher than that of silicon oxide films. Therefore, when ultraviolet light is irradiated onto the insulating film SN (silicon nitride film), the insulating film SN becomes a source of hydrogen ions, and the hydrogen ions generated within the insulating film SN are released from the insulating film SN into the insulating film BL101 (silicon oxide film), promoting their movement within the insulating film BL101. It is thought that the hydrogen bonds within the silicon nitride film (bonds between hydrogen atoms and silicon atoms, bonds between hydrogen atoms and nitrogen atoms, or bonds between hydrogen atoms themselves) are broken by ultraviolet irradiation, making the hydrogen atoms (hydrogen ions) able to move.

[0091] When hydrogen ions that have moved within the insulating film BL101 reach the floating gate electrode FG, it can affect the charge retention characteristics (in this case, electrons) within the floating gate electrode FG. Specifically, the charge (in this case, electrons) accumulated within the floating gate electrode FG may combine with hydrogen ions present in the vicinity of the floating gate electrode FG, potentially reducing the effective amount of charge (electrons) accumulated within the floating gate electrode FG. An unintended decrease in the effective amount of charge (electrons) accumulated within the floating gate electrode FG degrades the charge retention characteristics of non-volatile memory and should therefore be prevented as much as possible.

[0092] <Main Features and Effects> In Embodiment 1, the insulating film BL is made of silicon oxide and is a laminated film having an insulating film (silicon oxide film) BL1 and an insulating film (silicon oxide film) BL2 on insulating film BL1. The insulating film BL is formed to cover the upper surface of the floating gate electrode FG. Therefore, the insulating film BL made of silicon oxide is interposed between the upper surface of the floating gate electrode FG and the insulating film SN (silicon nitride film). The control gate electrode CG is not covered by the insulating film BL.

[0093] As explained in relation to the first example, when an erasure operation using ultraviolet light is applied to the erasure operation of non-volatile memory, the insulating film SN (silicon nitride film) is irradiated with ultraviolet light, causing the insulating film SN to become a source of hydrogen, and hydrogen ions are generated within the insulating film SN. The hydrogen ions generated within the insulating film SN are released from the insulating film SN into the insulating film BL (silicon oxide film), and the phenomenon of them moving within the insulating film BL is promoted.

[0094] The probability that hydrogen ions released from insulating film SN into insulating film BL and moving within insulating film BL will reach the floating gate electrode FG decreases as the thickness T1 of insulating film BL increases. In other words, hydrogen ions released from insulating film SN into insulating film BL become less likely to reach the floating gate electrode FG as the thickness T1 of insulating film BL increases.

[0095] Therefore, it is preferable to increase the thickness T1 of the insulating film BL, and specifically, it is preferable that the thickness T1 of the insulating film BL in the manufactured semiconductor device be 40 nm or more. That is, it is preferable that the thickness T1 of the insulating film BL be 40 nm or more after the insulating film SN is formed. In other words, it is preferable that the thickness T1 of the insulating film BL immediately before the insulating film SN is formed be 40 nm or more. This makes it possible to suppress or prevent hydrogen ions released from the insulating film SN into the insulating film BL due to irradiation of the insulating film SN with ultraviolet light from reaching the floating gate electrode FG. As a result, the number of hydrogen ions present near the floating gate electrode FG can be suppressed, and thus it is possible to suppress or prevent the charge (electrons in this case) accumulated in the floating gate electrode FG from combining with hydrogen ions present near the floating gate electrode FG. As a result, it is possible to suppress or prevent the effective amount of charge (electrons) accumulated in the floating gate electrode FG from unintentionally decreasing, and thus the charge retention characteristics of the non-volatile memory can be improved. Accordingly, the reliability of the semiconductor device equipped with non-volatile memory can be improved.

[0096] The case where the thickness of the insulating film BL101 is increased is referred to as the second study example. The thickness T102 of the insulating film BL101 shown in Figure 20 is greater than the thickness T101 of the insulating film BL101 shown in Figure 19. The semiconductor device of the first study example shown in Figure 19 and the semiconductor device of the second study example shown in Figure 20 have the same structure except for the thickness of the insulating film BL101.

[0097] In the second example shown in Figure 20, increasing the thickness T102 of the insulating film BL101 suppresses or prevents hydrogen ions released from the insulating film SN into the insulating film BL101 due to irradiation of the insulating film SN with ultraviolet light from reaching the floating gate electrode FG. As a result, the effective amount of charge (electrons) accumulated in the floating gate electrode FG is suppressed or prevented from decreasing unintentionally, thereby improving the charge retention characteristics of the non-volatile memory.

[0098] However, in the second example shown in Figure 20, the following problems may occur.

[0099] In the second example shown in Figure 20, we assume the first case where a single silicon oxide film formed by thermal CVD is used as the insulating film BL101. The silicon oxide film formed by thermal CVD has a lower density (atomic density) and therefore a higher thermal shrinkage rate compared to the silicon oxide film formed by plasma CVD. The lower the density (atomic density) of the silicon oxide film, the greater its thermal shrinkage rate, and the more easily the silicon oxide film shrinks during heat treatment.

[0100] In the first case of the second study example, the thermal shrinkage rate of the insulating film BL101 formed by the thermal CVD method is large, resulting in a large amount of stress generated due to the thermal shrinkage of the insulating film BL101. For example, when activation annealing is performed after the formation of the insulating film BL101 but before patterning of the insulating film BL101, the insulating film BL101 undergoes thermal shrinkage, thereby generating stress within the semiconductor substrate SB. Large stress generated due to the thermal shrinkage of the insulating film BL101 may reduce the reliability of the semiconductor device. For example, if the stress generated due to the thermal shrinkage of the insulating film BL101 is large, it increases the number of crystal defects generated within the semiconductor substrate SB due to the stress. Therefore, it is desirable to suppress the stress generated due to the thermal shrinkage of the insulating film BL101 as much as possible. Reducing the thickness of the insulating film BL101 can reduce the stress generated due to the thermal shrinkage of the insulating film BL101, but reducing the thickness of the insulating film BL101 leads to a decrease in the charge retention characteristics of the non-volatile memory, as explained in relation to the first study example.

[0101] Therefore, in the second example shown in Figure 20, we assume a second case in which a single silicon oxide film formed by plasma CVD is applied as the insulating film BL101. The silicon oxide film formed by plasma CVD has a higher density (atomic density) and therefore a lower thermal shrinkage rate compared to the silicon oxide film formed by thermal CVD. For this reason, in the second case, the stress generated due to the thermal shrinkage of the insulating film BL101 can be reduced compared to the first case.

[0102] However, silicon oxide films formed by plasma CVD have lower coverage than silicon oxide films formed by thermal CVD. Furthermore, silicon oxide films formed by plasma CVD are more susceptible to unintended impurities during deposition compared to those formed by thermal CVD. Therefore, in the second case of the second study example, it becomes difficult to fill the space between the control gate electrode CG and the floating gate electrode FG (between sidewall spacers SW1 and SW2) with the insulating film BL101, making it difficult to accurately form the insulating film BL101. Additionally, multiple MOSFETs are formed on the semiconductor substrate, and each MOSFET has multiple gate electrodes. It becomes difficult to fill the spaces between adjacent gate electrodes with the insulating film BL101, making it difficult to accurately form the insulating film BL101. Moreover, in the second case of the second study example, there is concern that impurities in the insulating film BL101 may diffuse into the floating gate electrode FG or the semiconductor substrate SB. The diffusion of impurities in the insulating film BL101 into the floating gate electrode FG or semiconductor substrate SB may reduce the reliability of the semiconductor device, so it is desirable to prevent this as much as possible.

[0103] In contrast, in the semiconductor device of Embodiment 1, a laminated film is used as the insulating film BL, which includes a silicon oxide film formed by thermal CVD (insulating film BL1) and a silicon oxide film formed by plasma CVD (insulating film BL2). Insulating film BL1 is located below insulating film BL2, and insulating film BL2 is formed on insulating film BL1.

[0104] Assume that the thickness T1 of the insulating film BL is the same as the thickness T102 of the insulating film BL101 in the first case of the second study example. Compared to the stress caused by the thermal shrinkage of the insulating film BL101 in the first case of the second study example, the stress caused by the thermal shrinkage of the insulating film BL(BLa) in Embodiment 1 can be suppressed. This is because the insulating film BL(BLa) includes the insulating film BL2(BL2a) formed by the plasma CVD method, and the insulating film BL2(BL2a) has a higher density (atomic density) and a lower thermal shrinkage rate compared to the insulating film BL1(BL1a) formed by the thermal CVD method. By including the insulating film BL2(BL2a), which has a lower density than the insulating film BL1(BL1a), the thermal shrinkage of the entire insulating film BL(BLa) can be suppressed, and as a result, the stress caused by the thermal shrinkage of the insulating film BL(BLa) can be suppressed. Therefore, the reliability of the semiconductor device can be improved.

[0105] As described above, silicon oxide films formed by thermal CVD have superior coverage compared to silicon oxide films formed by plasma CVD. In the second example of the second study, the entire insulating film BL101 is formed by plasma CVD, while in the first embodiment, the insulating film BLa includes insulating film BL1a, which has superior coverage. This makes it easier to fill the space between the control gate electrode CG and the floating gate electrode FG (between the sidewall spacers SW1 and SW2) with insulating film BLa, allowing for accurate formation of the insulating film BLa.

[0106] Furthermore, as mentioned above, compared to the silicon oxide film formed by the thermal CVD method (insulating film BL1a), the silicon oxide film formed by the plasma CVD method (insulating film BL2a) is more prone to the inclusion of unintended impurities during film formation. Conversely, compared to the silicon oxide film formed by the plasma CVD method (insulating film BL2a), the silicon oxide film formed by the thermal CVD method (insulating film BL1a) is less prone to the inclusion of unintended impurities and is a cleaner film.

[0107] In Embodiment 1, since the insulating film BL2 (BL2a) is formed on the insulating film BL1 (BL1a), the insulating film BL2 (BL2a) is not in contact with the floating gate electrode FG and is not in contact with the semiconductor substrate SB. Therefore, the diffusion of impurities in the insulating film BL2 (BL2a) into the floating gate electrode FG or the semiconductor substrate SB can be suppressed or prevented by the insulating film BL1 (BL1a).

[0108] Furthermore, in the first embodiment, the floating gate electrode FG and the semiconductor substrate SB are in contact with the clean insulating film BL1 (BL1a) rather than the insulating film BL2 (BL2a), thus suppressing or preventing diffusion from the insulating film BL1 (BL1a) into the floating gate electrode FG or the semiconductor substrate SB.

[0109] Therefore, the reliability of the semiconductor device can be improved by having an insulating film BL(BLa) that includes an insulating film BL1(BL1a) and an insulating film BL2(BL2a) on the insulating film BL1(BL1a).

[0110] Since insulating film BL1 and insulating film BL2 are made of the same material (silicon oxide), insulating film BL1 can be considered as the lower part of insulating film BL made of silicon oxide, and insulating film BL2 can be considered as the upper part of insulating film BL made of silicon oxide. The density (atomic density) of the upper part of insulating film BL (insulating film BL2) is greater than the density (atomic density) of the lower part of insulating film BL (insulating film BL1). Therefore, the thermal shrinkage rate of the upper part of insulating film BL (insulating film BL2) is smaller than the thermal shrinkage rate of the lower part of insulating film BL (insulating film BL1). Also, the wet etching rate of the upper part of insulating film BL (insulating film BL2) is smaller than the wet etching rate of the lower part of insulating film BL (insulating film BL1).

[0111] It is preferable that the thickness of insulating film BL2 is greater than the thickness of insulating film BL1. In other words, it is preferable that the thickness of insulating film BL2a is greater than the thickness of insulating film BL1a. As described above, reflecting the fact that the density of insulating film BL2(BL1a) is greater than that of insulating film BL1(BL1a), the thermal shrinkage rate of insulating film BL2(BL2a) is smaller than that of insulating film BL1(BL1a). Therefore, by allocating more than half of the thickness of insulating film BL(BLa) to insulating film BL2(BL2a), which has a lower thermal shrinkage rate, the overall thermal shrinkage rate of insulating film BL(BLa) can be suppressed. That is, because the thermal shrinkage rate of insulating film BL2(BL2a), which is thicker than insulating film BL1(BL1a), is smaller than that of insulating film BL1(BL1a), the overall thermal shrinkage rate of insulating film BL(BLa) can be efficiently suppressed. As a result, the stress generated due to the thermal shrinkage of insulating film BL(BLa) can be accurately suppressed, and the reliability of the semiconductor device can be further improved. The thickness of insulating film BL1a can be, for example, 10 nm or more and 30 nm or less. The thickness of insulating film BL2a can be, for example, 40 nm or more and 70 nm or less.

[0112] The thickness T1 of the insulating film BL is the sum of the thicknesses of insulating film BL1 and insulating film BL2. Note that in the process of removing the metal film ME by wet etching after forming the metal silicide layer SL, the thickness of insulating film BL2 may decrease due to etching. Therefore, the thickness of insulating film BL in the manufactured semiconductor device may be less than the sum of the formation thickness of insulating film BL1a and insulating film BL2a. It is preferable to set the formation thicknesses of insulating film BL1a and insulating film BL2a so that the thickness T1 of insulating film BL in the manufactured semiconductor device is 40 nm or more.

[0113] It is preferable that the direction of stress in insulating film BL1 (BL1a) and the direction of stress in insulating film BL2 (BL2a) are opposite to each other. That is, it is preferable that the stress in insulating film BL1 (BL1a) is tensile stress and the stress in insulating film BL2 (BL2a) is compressive stress, or that the stress in insulating film BL1 (BL1a) is compressive stress and the stress in insulating film BL2 (BL2a) is tensile stress. This allows the stress in insulating film BL1 (BL1a) and the stress in insulating film BL2 (BL2a) to cancel each other out, thereby further suppressing the overall stress of insulating film BL(BLa). Consequently, the reliability of the semiconductor device can be further improved.

[0114] Furthermore, it is preferable that the direction of stress in the insulating film BL(BLa) and the direction of stress in the STI region 2 are opposite. That is, it is preferable that the stress in the STI region 2 is tensile stress and the stress in the insulating film BL(BLa) is compressive stress, or that the stress in the STI region 2 is compressive stress and the stress in the insulating film BL(BLa) is tensile stress. This allows the stress in the STI region 2 and the stress in the insulating film BL(BLa) to cancel each other out, thereby suppressing the stress generated in the semiconductor substrate SB due to the STI region 2 and the insulating film BL(BLa). Consequently, the reliability of the semiconductor device can be further improved.

[0115] In Embodiment 1, it is preferable to perform the activation annealing treatment after the formation of the insulating film BL1a and before the formation of the insulating film BL2a. This allows the activation annealing treatment to be performed with the semiconductor substrate SB (n-type semiconductor region H1, n-type semiconductor region H2, and n-type semiconductor region H3) covered with the insulating film BL1a, thereby suppressing or preventing n-type or p-type impurities in the semiconductor substrate SB from being released outside the semiconductor substrate SB during the activation annealing treatment. Furthermore, since the activation annealing treatment is performed with the semiconductor substrate SB (n-type semiconductor region H1, n-type semiconductor region H2, and n-type semiconductor region H3) covered with the insulating film BL1a and with no insulating film BL2a formed on the insulating film BL1a, it is possible to prevent stress caused by the insulating film BL2a from occurring in the semiconductor substrate SB during the activation annealing treatment. As a result, stress generated in the semiconductor substrate SB during the activation annealing treatment can be suppressed, and the occurrence of crystal defects in the semiconductor substrate SB can be suppressed or prevented.

[0116] In Embodiment 1, the activation annealing treatment can also be performed after the formation of the insulating film BL2a and before the formation of the photoresist pattern RP1. As a result, the activation annealing treatment is performed with the semiconductor substrate SB (n-type semiconductor region H1, n-type semiconductor region H2, and n-type semiconductor region H3) covered with the insulating film BLa, which suppresses or prevents n-type or p-type impurities in the semiconductor substrate SB from being released outside the semiconductor substrate SB during the activation annealing treatment.

[0117] (Embodiment 2) Figure 21 is a cross-sectional view along line AA in Figure 22.

[0118] The semiconductor device of Embodiment 2 shown in Figures 21 and 22 differs from the semiconductor device of Embodiment 1 shown in Figure 1 in that it uses an insulating film BL3 instead of the insulating film BL, and that it has wiring M1a. In Figure 21, an insulating film (interlayer insulating film) IL1 is formed on the insulating film SO so as to cover the wiring M1. In Figure 1, the insulating film IL1 is not shown, but in reality, the insulating film IL1 is also formed.

[0119] The insulating film (silicon oxide film) BL3 shown in Figure 21 is made of silicon oxide. The formation position of insulating film BL3 is the same as the formation position of insulating film BL described above, so a repeated explanation is omitted.

[0120] As described in Embodiment 1 above, when the non-volatile memory is erased, ultraviolet light is irradiated onto the insulating film SN (silicon nitride film), causing hydrogen ions generated within the insulating film SN to reach the floating gate electrode FG, which may degrade the charge retention characteristics of the non-volatile memory. The methods used to address this differ between Embodiment 1 and Embodiment 2.

[0121] In the first embodiment described above, by increasing the thickness of the insulating film BL interposed between the insulating film SN and the floating gate electrode FG, hydrogen ions generated within the insulating film SN are made less likely to reach the floating gate electrode FG. Furthermore, the structure of the insulating film BL is devised to address potential problems that may arise due to the increased thickness of the insulating film BL.

[0122] In Embodiment 2, by suppressing the amount (irradiation area) of ultraviolet light in the insulating film SN (silicon nitride film), the amount (number) of hydrogen ions generated in the insulating film SN due to ultraviolet light is suppressed, thereby suppressing the amount (number) of hydrogen ions that reach the floating gate electrode FG.

[0123] Therefore, in Embodiment 2, the thickness of the insulating film BL3, which corresponds to the insulating film BL, may be smaller than the thickness of the insulating film BL in Embodiment 1. Furthermore, the insulating film BL3 may be a single layer silicon oxide film.

[0124] In Embodiment 2, the plurality of wirings M1 arranged on the insulating film SO include wirings M1a and M1b. Since each of the wirings M1a and M1b is made of metal, they can also be considered as metal films.

[0125] As shown in Figures 21 and 22, wiring M1a is formed on the insulating film SO and, in a plan view, covers a portion of the control gate electrode CG and the floating gate electrode FG. Wiring M1b is formed on the insulating film SO and is electrically connected to the control gate electrode CG via plug PG.

[0126] In a plan view, wiring M1a partially overlaps with the floating gate electrode FG. In a plan view, the floating gate electrode FG has a portion that overlaps with wiring M1a and a portion that does not overlap with wiring M1a.

[0127] In Figure 22, the outer periphery of wiring M1a surrounds the floating gate electrode FG in a plan view. That is, the outer periphery of the floating gate electrode FG is located inside the outer periphery of wiring M1a.

[0128] In Figures 21 and 22, the wiring M1a has an opening OP1. The opening OP1 penetrates the wiring M1a so as to reach from the top surface of the wiring M1a to the bottom surface of the wiring M1a. In a plan view, the opening OP1 of the wiring M1a is contained within the floating gate electrode FG. That is, in a plan view, the opening OP1 is located inside the outer circumference of the floating gate electrode FG. Therefore, in a plan view, a part of the floating gate electrode FG overlaps with the opening OP1 of the wiring M1a, and the other part of the floating gate electrode FG overlaps with the wiring M1a. In other words, the floating gate electrode FG integrally has a portion that overlaps with the wiring M1a in a plan view and a portion that overlaps with the opening OP1 of the wiring M1a in a plan view. In a plan view, it is preferable that the entire opening OP1 of the wiring M1a overlaps with the floating gate electrode FG. The potential of the floating gate electrode FG is the floating potential. Wiring M1a is not electrically connected to the floating gate electrode FG via a conductor. Therefore, a plug PG is not placed between the floating gate electrode FG and wiring M1a. In a plan view, it is preferable that no other wiring included in the semiconductor device (wiring above wiring M1) is present in a position that overlaps with the opening OP1 of wiring M1a.

[0129] In Figure 21, wiring M1a is electrically connected to the n-type semiconductor region H3 (n-type semiconductor region SD3) via plug PG. Wiring other than the wiring electrically connected to the n-type semiconductor region H3 can also be used as wiring M1a. Furthermore, wiring M1a may be electrically floating.

[0130] Ultraviolet light can pass through insulating films used in semiconductor devices, but it cannot pass through metal films such as wiring. Therefore, ultraviolet light can pass through the opening in wiring M1a, but it cannot pass through the metal portion of wiring M1a. In the semiconductor device of Embodiment 2 shown in Figures 21 and 22, when performing an erase operation of non-volatile memory using ultraviolet light, ultraviolet light that has passed through the opening OP1 of wiring M1a passes through insulating film SO, insulating film SN, and insulating film BL3, and irradiates the floating gate electrode FG. As a result, electrons accumulated in the floating gate electrode FG are excited, and as a result, electrons in the floating gate electrode FG move out of the floating gate electrode FG, thereby erasing the non-volatile memory. The floating gate electrode FG has a portion that does not overlap with wiring M1a in a plan view, so ultraviolet light can be irradiated onto the floating gate electrode FG.

[0131] During the erase operation, ultraviolet light can pass through the opening OP1 of wiring M1a, but it cannot pass through wiring M1a itself. Therefore, compared to the case where wiring M1a is not present, when wiring M1a is present, the amount of ultraviolet light irradiated to the insulating film SN can be reduced because the ultraviolet light is shielded by wiring M1a. In other words, ultraviolet light is irradiated to the insulating film SN located directly below the opening OP1 of wiring M1a, but not to the insulating film SN located directly below wiring M1a. Therefore, during the erase operation, the amount of ultraviolet light irradiated (irradiated area) in the insulating film SN located near the floating gate electrode FG can be reduced, thereby suppressing the amount (number) of hydrogen ions generated in the insulating film SN due to ultraviolet light, and thereby suppressing the amount (number) of hydrogen ions that reach the floating gate electrode FG from the insulating film SN through the insulating film BL3, etc. In other words, because the floating gate electrode FG has a portion that overlaps with wiring M1a in a plan view, the amount of hydrogen ions generated in the insulating film SN located near the floating gate electrode FG can be suppressed. This suppresses the number of hydrogen ions present in the vicinity of the floating gate electrode FG, thereby preventing or inhibiting the binding of charge (electrons in this case) accumulated within the floating gate electrode FG to hydrogen ions present in the vicinity. As a result, it is possible to suppress or prevent an unintended decrease in the effective amount of charge (electrons) accumulated within the floating gate electrode FG, thereby improving the charge retention characteristics of the non-volatile memory. Consequently, the reliability of semiconductor devices equipped with non-volatile memory can be improved.

[0132] A modified example of the semiconductor device of Embodiment 2 will be described.

[0133] The planar dimensions (area) of the opening OP1 of wiring M1a shown in Figure 23 differ from the planar dimensions (area) of the opening OP1 of wiring M1a shown in Figure 22. For example, the planar dimensions of the opening OP1 of wiring M1a shown in Figure 23 are larger than the planar dimensions of the opening OP1 of wiring M1a shown in Figure 22.

[0134] The planar dimensions of the opening OP1 of wiring M1a can be set as needed. It is preferable to set the planar dimensions of the opening OP1 of wiring M1a so that an appropriate amount of ultraviolet light is irradiated onto the floating gate electrode FG during the erase operation. For example, the larger the planar dimensions of the opening OP1 of wiring M1a, the greater the amount (area) of ultraviolet light that passes through the opening OP1 of wiring M1a and irradiates the floating gate electrode FG during the erase operation. On the other hand, if the planar dimensions of the opening OP1 of wiring M1a are made too large, the amount (area) of ultraviolet light that passes through the opening OP1 of wiring M1a and irradiates the insulating film SN will also increase, and therefore the amount (number) of hydrogen ions generated in the insulating film SN and supplied from the insulating film SN to the insulating film BL3 will also increase.

[0135] Therefore, the planar dimensions of the opening OP1 of the wiring M1a should be set by considering the appropriate amount of ultraviolet light to be irradiated onto the floating gate electrode FG for erasure. This makes it possible to achieve both accurate erasure of non-volatile memory using ultraviolet light and improved charge retention characteristics of the non-volatile memory.

[0136] Furthermore, Embodiment 2 describes the case where the wiring M1a has one opening OP1. However, there may also be cases where the wiring M1a has multiple openings OP1.

[0137] Other variations of the semiconductor device of Embodiment 2 will be described.

[0138] In Figure 22 above, in a plan view, wiring M1a overlapped not only with the floating gate electrode FG but also with a portion of the control gate electrode CG. In Figure 24, in a plan view, wiring M1a overlapped with the floating gate electrode FG but not with the control gate electrode CG.

[0139] Compared to the case in Figure 24, in the case of Figure 22, the amount of ultraviolet light irradiated onto the insulating film SN during the erase operation (irradiated area) can be further reduced. Therefore, compared to the case in Figure 24, in the case of Figure 22, the amount (number) of hydrogen ions generated in the insulating film SN due to ultraviolet light can be suppressed, which is advantageous for improving the charge retention characteristics of non-volatile memory.

[0140] Compared to the case shown in Figure 22, the planar dimensions (planar area) of wiring M1a can be reduced in the case shown in Figure 24. This makes it easier to improve the flatness of the insulating film IL1.

[0141] For example, after forming wiring M1, insulating film IL1 is formed on insulating film SO so as to cover wiring M1, and then the upper surface of insulating film IL1 is flattened by polishing using the CMP method. In this case, if the planar dimensions of wiring M1a are too large, the flatness of the upper surface of insulating film IL1 may decrease during the CMP process in which insulating film IL1 is polished. In the case of Figure 24, by reducing the planar dimensions of wiring M1a, it becomes easier to improve the flatness of the upper surface of insulating film IL1 during the CMP process in which insulating film IL1 is polished.

[0142] Further variations of the semiconductor device of Embodiment 2 will be described.

[0143] In Figure 25, instead of wiring M1a, wirings M1a1, M1a2, and M1a3 are formed. Wires M1a1, M1a2, and M1a3 each partially overlap the floating gate electrode FG in a plan view. Wires M1a1 and M1a2 are adjacent to each other, wires M1a2 and M1a3 are adjacent to each other, and wiring M1a2 is positioned between wires M1a1 and M1a3. Wire M1a2 is, for example, a signal line.

[0144] In the case of Figure 25, the floating gate electrode FG has, in a plan view, a portion that overlaps with wiring M1a1, a portion that overlaps with wiring M1a2, a portion that overlaps with wiring M1a3, and a portion that does not overlap with any of wiring M1a1, M1a2, or M1a3. For example, in a plan view, the floating gate electrode FG is exposed between wiring M1a1 and wiring M1a2, and between wiring M1a2 and wiring M1a3.

[0145] During the erase operation, ultraviolet light can pass between wiring M1a1 and wiring M1a2, and between wiring M1a2 and wiring M1a3, but cannot pass through wiring M1a1, wiring M1a2, or wiring M1a3 itself. The ultraviolet light that passes between wiring M1a1 and wiring M1a2, and the ultraviolet light that passes between wiring M1a2 and wiring M1a3, passes through the insulating film SO, insulating film SN, and insulating film BL3, and irradiates the floating gate electrode FG, thereby erasing the non-volatile memory. The floating gate electrode FG has a portion that does not overlap with any of the wirings M1a1, M1a2, or wiring M1a3 in a plan view, allowing ultraviolet light to irradiate the floating gate electrode FG.

[0146] During the erase operation, ultraviolet light is shielded by wirings M1a1, M1a2, and M1a3, thereby reducing the amount of ultraviolet light irradiated onto the insulating film SN. As a result, the floating gate electrode FG has portions that overlap with wiring M1a1, wiring M1a2, and wiring M1a3 in a plan view, which suppresses the amount of hydrogen ions generated in the insulating film SN located near the floating gate electrode FG. This suppresses the number of hydrogen ions present in the vicinity of the floating gate electrode FG, thereby preventing or suppressing an unintended decrease in the effective amount of charge accumulated within the floating gate electrode FG.

[0147] (Embodiment 3) As shown in Figure 26, the semiconductor device of Embodiment 3 has a wiring M2a formed on an insulating film IL1, and an insulating film (interlayer insulating film) IL2 formed on the insulating film IL1 so as to cover the wiring M2a. The wiring M2a is electrically connected to the wiring M1a via a plurality of conductive plugs PG2. Each plug PG2 is positioned between the wiring M1a and the wiring M2a and penetrates the insulating film IL1.

[0148] With respect to the wiring M1a(M1), the insulating film SO, and the structure below the insulating film SO, the semiconductor device of Embodiment 3 shown in Figure 26 is the same as the semiconductor device of Embodiment 2 shown in Figure 21.

[0149] Similar to wiring M1a, the outer periphery of wiring M2a surrounds the floating gate electrode FG in a plan view. That is, the outer periphery of the floating gate electrode FG is located inside the outer periphery of wiring M2a. Wiring M2a has an opening OP2. The opening OP2 penetrates wiring M2a so as to reach from the top surface of wiring M2a to the bottom surface of wiring M2a.

[0150] In a plan view, the opening OP1 of wiring M2a overlaps with the opening OP1 of wiring M1a. Therefore, similar to the opening OP1 of wiring M1a, the opening OP2 of wiring M2a is contained within the floating gate electrode FG in a plan view.

[0151] In the semiconductor device of Embodiment 3 shown in Figure 26, when the non-volatile memory is erased using ultraviolet light, ultraviolet light passing through the opening OP2 of wiring M2a and the opening OP1 of wiring M1a passes through the insulating film SO, insulating film SN, and insulating film BL3 and irradiates the floating gate electrode FG. Therefore, ultraviolet light traveling in a direction substantially perpendicular to the main surface of the semiconductor substrate SB can pass through the opening OP2 of wiring M2a and the opening OP1 of wiring M1a and be incident on the floating gate electrode FG, but ultraviolet light traveling in an oblique direction cannot pass through the opening OP1 of wiring M1a after passing through the opening OP2 of wiring M2a, and therefore cannot be incident on the floating gate electrode FG. Here, the oblique direction corresponds to a direction inclined from the direction substantially perpendicular to the main surface of the semiconductor substrate SB.

[0152] Therefore, ultraviolet light traveling at an angle can be prevented from passing through the opening OP1 of the wiring M1a, traveling through the insulating film SO, and entering the insulating film SN. As a result, the amount of ultraviolet irradiation (irradiated area) in the insulating film SN located near the floating gate electrode FG can be further reduced compared to when wiring M2a is not formed. Consequently, the amount (number) of hydrogen ions generated in the insulating film SN due to ultraviolet light can be further suppressed, and thereby the amount (number) of hydrogen ions that reach the floating gate electrode FG from the insulating film SN through the insulating film BL3 can be further suppressed. Therefore, the charge retention characteristics of the non-volatile memory can be further improved.

[0153] Furthermore, the scattering of ultraviolet light that passes through the opening OP2 of wiring M2a and is reflected by wiring M1a between wiring M2a and wiring M1a can be suppressed or prevented by the multiple plugs PG2. For this reason, it is preferable that the multiple plugs PG2 be arranged so as to surround the opening OP1 of wiring M1a in a plan view.

[0154] (Embodiment 4) Figure 27 is a cross-sectional view along line BB in Figure 28.

[0155] The semiconductor device of Embodiment 4 shown in Figures 27 and 28 differs from the semiconductor device of Embodiment 2 shown in Figures 21 and 22 in that it uses a metal film (metal film pattern) MP instead of the wiring M1a.

[0156] As shown in Figure 27, the metal film MP is formed on the insulating film SN. The insulating film SO is formed on the insulating film SN so as to cover the metal film MP. Another insulating film may be placed between the metal film MP and the insulating film SN.

[0157] The metal film MP consists of, for example, a tungsten film. For instance, the metal film MP can be formed by first forming an insulating film SN, then forming a tungsten film, and then patterning the tungsten film using photolithography and dry etching techniques. The insulating film SO is formed on the insulating film SN after the metal film MP is formed, covering the metal film MP.

[0158] As shown in Figures 27 and 28, the metal film MP covers the floating gate electrode FG in a plan view. The metal film MP is not electrically connected to the floating gate electrode FG via a conductor.

[0159] As shown in Figures 27 and 28, the outer periphery of the metal film MP surrounds the floating gate electrode FG in a plan view. That is, the outer periphery of the floating gate electrode FG is located inside the outer periphery of the metal film MP.

[0160] As shown in Figures 27 and 28, the metal film MP has an opening OP3. The opening OP3 penetrates the metal film MP so as to reach from the top surface to the bottom surface. In a plan view, the opening OP3 of the metal film MP is contained within the floating gate electrode FG. That is, in a plan view, the opening OP3 is located inside the outer circumference of the floating gate electrode FG. Therefore, in a plan view, a part of the floating gate electrode FG overlaps with the opening OP3 of the metal film MP, and the other part of the floating gate electrode FG overlaps with the metal film MP. In a plan view, it is preferable that the entire opening OP3 of the metal film MP overlaps with the floating gate electrode FG. In a plan view, it is preferable that there are no wirings included in the semiconductor device at a position overlapping with the opening OP3 of the metal film MP.

[0161] In the semiconductor device of Embodiment 4 shown in Figures 27 and 28, when the non-volatile memory is erased using ultraviolet light, ultraviolet light passing through the aperture OP3 of the metal film MP passes through the insulating film SN and insulating film BL3 and irradiates the floating gate electrode FG. As a result, electrons within the floating gate electrode FG move out of the floating gate electrode FG, causing the non-volatile memory to enter an erased state.

[0162] Ultraviolet light can pass through the aperture OP3 of the metal film MP, but it cannot pass through the metal film MP itself. Therefore, ultraviolet light irradiates the insulating film SN located directly below the aperture OP2 of the metal film MP, but not the insulating film SN located directly below the metal film MP. Consequently, compared to the case where the metal film MP is absent, the amount of ultraviolet light irradiated onto the insulating film SN can be reduced due to the shielding effect of the metal film MP. During the erase operation, the amount of ultraviolet light irradiated (irradiated area) in the insulating film SN located near the floating gate electrode FG can be reduced, thereby suppressing the amount (number) of hydrogen ions generated in the insulating film SN due to ultraviolet light, and consequently suppressing the amount (number) of hydrogen ions that reach the floating gate electrode FG from the insulating film SN through the insulating film BL3. This improves the charge retention characteristics of the non-volatile memory. Consequently, the reliability of semiconductor devices equipped with non-volatile memory can be improved.

[0163] The present inventors have described the invention in detail based on its embodiments, but it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0164] 2 STI area BL, BL1, BL2, BL3, BL101 insulating film CG Control Terminal E1, E2, E2a, E2b, E3 n-type semiconductor region H1,H2,H3 n-type semiconductor region IL1, IL2 insulating film FG Floating Gate GF insulating film GF1, GF2 gate insulating film M1, M1a, M1b, M2a wiring MC memory element OP1, OP2, OP3 opening PG, PG2 plugs PS Silicone Film PW p-type well RP1, RP2 Photoresist Pattern SB Semiconductor Substrate SD1, SD2, SD3 n-type semiconductor regions SL metal silicide layer SN insulating film SO insulating film SW1, SW2 Sidewall Spacers

Claims

1. Semiconductor substrate and A floating gate electrode of a first transistor for memory, formed on the semiconductor substrate via a first gate insulating film, A gate electrode of a second transistor is formed on the semiconductor substrate via a second gate insulating film, A first sidewall spacer formed on the side surface of the floating gate electrode, A second sidewall spacer formed on the side surface of the gate electrode, A first insulating film covering the floating gate electrode, The floating gate electrode, the gate electrode, the first sidewall spacer, the second sidewall spacer, and the silicon nitride film covering the first insulating film, It has, The first insulating film is made of silicon oxide, The first insulating film is interposed between the upper surface of the floating gate electrode and the silicon nitride film. A semiconductor device wherein the density of the upper part of the first insulating film is greater than the density of the lower part of the first insulating film.

2. In the semiconductor device described in claim 1, The first insulating film consists of a first silicon oxide film and a second silicon oxide film on the first silicon oxide film. The upper part of the first insulating film is composed of the second silicon oxide film, A semiconductor device wherein the lower part of the first insulating film is composed of the first silicon oxide film.

3. In the semiconductor device described in claim 2, A semiconductor device wherein the thickness of the first insulating film is 40 nm or more.

4. In the semiconductor device according to claim 3, A semiconductor device wherein the thickness of the second silicon oxide film is greater than the thickness of the first silicon oxide film.

5. In the semiconductor device described in claim 2, The semiconductor substrate further comprises an STI region formed within the aforementioned semiconductor substrate. The direction of stress in the first silicon oxide film and the direction of stress in the second silicon oxide film are opposite to each other. A semiconductor device in which the direction of stress in the first insulating film and the direction of stress in the STI region are opposite to each other.

6. In the semiconductor device described in claim 1, A metal silicide layer is formed on the gate electrode, whereas no metal silicide layer is formed on the floating gate electrode. A semiconductor device wherein the silicon nitride film covers the metal silicide layer on the gate electrode.

7. In the semiconductor device according to claim 6, A semiconductor device wherein the silicon nitride film is not in contact with the floating gate electrode, but is in contact with the metal silicide layer on the gate electrode.

8. In the semiconductor device described in claim 1, A semiconductor device wherein the first insulating film covers the floating gate electrode and the first sidewall spacer.

9. In the semiconductor device described in claim 1, A semiconductor device that stores information by accumulating electric charge in the floating gate electrode.

10. In the semiconductor device described in claim 1, A semiconductor device wherein the shrinkage rate of the upper part of the first insulating film is smaller than the shrinkage rate of the lower part of the first insulating film.

11. (a) A process of preparing a semiconductor substrate, (b) A step of forming a floating gate electrode of a first memory transistor on the main surface of the semiconductor substrate via a first gate insulating film, and forming a gate electrode of a second transistor on the main surface of the semiconductor substrate via a second gate insulating film. (c) A step of forming a first sidewall spacer on the side surface of the floating gate electrode and forming a second sidewall spacer on the side surface of the gate electrode. (d) A step of forming a first silicon oxide film on the main surface of the semiconductor substrate using a thermal CVD method so as to cover the floating gate electrode, the gate electrode, the first sidewall spacer, and the second sidewall spacer. (e) A step of forming a second silicon oxide film on the first silicon oxide film using a plasma CVD method, (f) A step of forming a first insulating film consisting of the patterned laminated film by patterning the laminated film comprising the first silicon oxide film and the second silicon oxide film. (g) After step (f), a step of forming a metal silicide layer on the gate electrode, (h) After step (g), a step of forming a silicon nitride film on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the first sidewall spacer, the second sidewall spacer, the metal silicide layer, and the first insulating film. It has, The first insulating film covers the floating gate electrode, A method for manufacturing a semiconductor device, wherein in step (h), the first insulating film is interposed between the floating gate electrode and the silicon nitride film.

12. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein, after step (h), the thickness of the first insulating film is 40 nm or more.

13. In the method for manufacturing a semiconductor device according to claim 12, A method for manufacturing a semiconductor device, wherein the thickness of the second silicon oxide film formed in step (e) is greater than the thickness of the first silicon oxide film formed in step (d).

14. In the method for manufacturing a semiconductor device according to claim 11, The (g) step is performed with the first insulating film covering the floating gate electrode and the gate electrode exposed. A method for manufacturing a semiconductor device, wherein in step (g) above, the metal silicide layer is formed on the gate electrode, while the metal silicide layer is not formed on the floating gate electrode.

15. In the method for manufacturing a semiconductor device according to claim 11, (i) After step (h) above, a step of forming a second insulating film on the silicon nitride film, (j) A step of forming a contact hole that penetrates the second insulating film and the silicon nitride film, (k) After step (j) above, a step of forming a conductive plug in the contact hole, A method for manufacturing a semiconductor device, further comprising the above.

16. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the direction of stress in the second silicon oxide film formed in step (e) and the direction of stress in the first silicon oxide film formed in step (d) are opposite to each other.

17. In the method for manufacturing a semiconductor device according to claim 11, (b1) After step (b) and before step (d), a step of forming a first semiconductor region of the first conductivity type, a second semiconductor region of the first conductivity type, and a third semiconductor region of the first conductivity type within the semiconductor substrate. It further possesses, The floating gate electrode is located between the first semiconductor region and the second semiconductor region in a plan view. The gate electrode is located between the second semiconductor region and the third semiconductor region in a plan view. The second semiconductor region is located between the floating gate electrode and the gate electrode in a plan view. The first semiconductor region functions as the source region or drain region of the first transistor. The second semiconductor region functions as the source region or drain region of the first transistor, and also functions as the source region or drain region of the second transistor. A method for manufacturing a semiconductor device, wherein the third semiconductor region functions as the source region or drain region of the second transistor.

18. In the method for manufacturing a semiconductor device according to claim 11, A method for manufacturing a semiconductor device, wherein the first insulating film covers the floating gate electrode and the first sidewall spacer.

19. In the method for manufacturing a semiconductor device according to claim 11, (d1) After step (d) and before step (e), a step of performing an activation annealing treatment on the semiconductor substrate. A method for manufacturing a semiconductor device, further comprising the above.

20. Semiconductor substrate and A floating gate electrode of a first transistor for memory, formed on the semiconductor substrate via a first gate insulating film, A gate electrode of a second transistor is formed on the semiconductor substrate via a second gate insulating film, A first sidewall spacer formed on the side surface of the floating gate electrode, A second sidewall spacer formed on the side surface of the gate electrode, A first insulating film covering the floating gate electrode, The floating gate electrode, the gate electrode, the first sidewall spacer, the second sidewall spacer, and the silicon nitride film covering the first insulating film, A metal film formed on the silicon nitride film, It has, The first insulating film is made of silicon oxide, The first insulating film is interposed between the upper surface of the floating gate electrode and the silicon nitride film. In a plan view, the metal film overlaps the floating gate electrode, In a plan view, the floating gate electrode has a portion that does not overlap with the metal film, wherein the semiconductor device.

Images