Semiconductor device and method for manufacturing the same
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS CORP
- Filing Date
- 2024-12-11
- Publication Date
- 2026-06-23
AI Technical Summary
【0012】 一実施の形態によれば、半導体装置の信頼性を向上できる。
Smart Images
Figure 2026102316000001_ABST
Abstract
Claims
1. A first-type conductive semiconductor substrate having an upper surface, An interlayer insulating film formed on the upper surface of the semiconductor substrate, A plurality of wirings formed on the interlayer insulating film, Equipped with, The interlayer insulating film comprises a BPSG film and a PSG film formed on the BPSG film. A gettering layer containing phosphorus is formed in the PSG film. A semiconductor device wherein the concentration of phosphorus in the gettering layer is higher than the concentration of phosphorus in the PSG film.
2. In the semiconductor device described in claim 1, The gettering layer is a semiconductor device having the function of capturing hydrogen ions.
3. In the semiconductor device described in claim 1, The gettering layer is formed at a position away from the upper surface of the PSG film in a semiconductor device.
4. In the semiconductor device described in claim 1, The interlayer insulating film is formed on the PSG film and further comprises a phosphorus-free first silicon oxide film. A semiconductor device wherein the thickness of the first silicon oxide film is smaller than the thickness of the PSG film.
5. In the semiconductor device according to claim 4, The first silicon oxide film is an NSG film, wherein the semiconductor device is a semiconductor device.
6. In the semiconductor device described in claim 1, A plurality of first impurity regions formed in the semiconductor substrate and having a second conductivity type opposite to the first conductivity type, A plurality of first holes are formed in the interlayer insulating film such that each reaches the plurality of first impurity regions, Furthermore, The aforementioned multiple wirings include multiple field plate wirings, Each of the aforementioned field plate wirings is also formed inside the aforementioned first holes so as to be connected to the aforementioned first impurity regions. A semiconductor device in which the plurality of field plate wirings and the plurality of first impurity regions are each electrically floating.
7. In the semiconductor device described in claim 6, A cell region in which multiple semiconductor elements are formed, In a plan view, the outer peripheral region surrounding the cell region, Furthermore, A semiconductor device wherein the plurality of field plate wirings and the plurality of first impurity regions are each formed in the outer peripheral region so as to surround the plurality of semiconductor elements in a plan view.
8. In the semiconductor device described in claim 6, A semiconductor device in which the plurality of semiconductor elements each have a gate insulating film and a gate electrode, and are covered by the interlayer insulating film.
9. In the semiconductor device described in claim 8, The semiconductor substrate further has a lower surface, The aforementioned semiconductor device is A drain electrode formed on the lower surface of the semiconductor substrate, A drain region of the first conductivity type formed in the semiconductor substrate so as to be in contact with the drain electrode, A drift region of the first conductivity type formed in the semiconductor substrate and located on the drain region, The second conductive body region formed in the semiconductor substrate, The first conductive source region formed in the body, It further possesses, A semiconductor device comprising the plurality of semiconductor elements, the gate insulating film, the gate electrode, the drift region, the body region, the source region, and the drain region.
10. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface, (b) A step of forming a BPSG film on the upper surface of the semiconductor substrate, (c) A step of forming a PSG film on the BPSG film, (d) After step (c), a step of forming a gettering layer in the PSG film by implanting phosphorus into the PSG film by ion implantation, and (e) After step (d), a step of forming a plurality of wirings on the PSG film, Equipped with, A method for manufacturing a semiconductor device, wherein the concentration of phosphorus in the gettering layer is higher than the concentration of phosphorus in the PSG film.
11. In the method for manufacturing a semiconductor device according to claim 10, The method for manufacturing a semiconductor device, wherein the gettering layer has the function of capturing hydrogen ions.
12. In the method for manufacturing a semiconductor device according to claim 10, The gettering layer is formed at a position away from the upper surface of the PSG film, in a method for manufacturing a semiconductor device.
13. In the method for manufacturing a semiconductor device according to claim 10, In step (d) above, the dose of ion implantation is 1.0 × 10 １６ / cm ２ The above and 5.0 x 10 １６ / cm ２ The following is a method for manufacturing a semiconductor device.
14. In the method for manufacturing a semiconductor device according to claim 10, (f) Between step (d) and step (e), a step of forming a phosphorus-free first silicon oxide film on the PSG film, It further includes, The thickness of the first silicon oxide film is smaller than the thickness of the PSG film. A method for manufacturing a semiconductor device, wherein in step (e), the plurality of wirings are formed on the first silicon oxide film.
15. In the method for manufacturing a semiconductor device according to claim 14, A method for manufacturing a semiconductor device, wherein the first silicon oxide film is an NSG film.
16. In the method for manufacturing a semiconductor device according to claim 10, (g) A step between step (a) and step (b) of forming a plurality of first impurity regions of a second conductivity type opposite to the first conductivity type in the semiconductor substrate. (h) Between step (d) and step (e), a step of forming a plurality of first pores in the PSG film and the BPSG film that reach the plurality of first impurity regions, Furthermore, The aforementioned multiple wirings include multiple field plate wirings, Each of the aforementioned field plate wirings is also formed inside the aforementioned first holes so as to be connected to the aforementioned first impurity regions. A method for manufacturing a semiconductor device, wherein the plurality of field plate wirings and the plurality of first impurity regions are each electrically floating.
17. In the method for manufacturing a semiconductor device according to claim 16, (i) A step of forming a plurality of semiconductor elements between step (a) and step (b), Furthermore, The semiconductor device comprises a cell region on which the plurality of semiconductor elements are formed, and an outer peripheral region surrounding the cell region in a plan view. A method for manufacturing a semiconductor device, wherein the plurality of field plate wirings and the plurality of first impurity regions are each formed in the outer peripheral region so as to surround the plurality of semiconductor elements in a plan view.
18. In the method for manufacturing a semiconductor device according to claim 17, A method for manufacturing a semiconductor device, wherein the plurality of semiconductor elements each have a gate insulating film and a gate electrode, and are covered by the BPSG film and the PSG film.
19. In the method for manufacturing a semiconductor device according to claim 18, The semiconductor substrate further comprises a lower surface, a drain region of the first conductivity type, and a drift region of the first conductivity type located on the drain region. The above step (i) is, (i1) A step of forming the second conductive body region in the semiconductor substrate, (i2) A step of forming the first conductive type source region in the body, (i3) A step of forming a drain electrode on the lower surface of the semiconductor substrate, and It has, A method for manufacturing a semiconductor device, wherein the plurality of semiconductor elements each have a gate insulating film, a gate electrode, a drift region, a body region, a source region, and a drain region.
20. In the method for manufacturing a semiconductor device according to claim 10, The above step (b) is, (b1) A step of forming the BPSG film on the upper surface of the semiconductor substrate by a film deposition process using the CVD method, (b2) A step of performing a reflow treatment on the BPSG film, It has, The above step (c) is, (c1) A step of forming the PSG film on the upper surface of the semiconductor substrate by a film deposition process using the CVD method, (c2) A step of performing a reflow treatment on the PSG film, A method for manufacturing a semiconductor device having the following characteristics.