Semiconductor device and method for manufacturing the same

Abstract

This invention simplifies the manufacturing process for semiconductor devices, including low-Vth LDMOSFETs and depletion-type LDMOSFETs, thereby reducing the manufacturing cost of semiconductor devices. [Solution] The semiconductor device has an n-type offset drain region OD2, an n-type semiconductor region 10B, and a gate electrode GE2. The n-type semiconductor region 10B is located away from the n-type offset drain region OD2.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing technology thereof, and is applicable to, for example, a semiconductor device including a plurality of field effect transistors (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) having different threshold voltages and an effective technology for its manufacturing technology.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2020-129597 (Patent Document 1) describes a technology related to a laterally diffused MOSFET (referred to as a Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor: LDMOSFET).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For example, as an LDMOSFET used in a circuit, not only an enhancement-mode LDMOSFET and a depletion-mode LDMOSFET, but also an enhancement-mode low Vth LDMOSFET having a relatively low threshold voltage is required.

[0005] Therefore, a semiconductor device including not only an enhancement-mode LDMOSFET and a depletion-mode LDMOSFET but also a low Vth LDMOSFET has been studied.

[0006] In this regard, improvements to the structure of low-Vth LDMOSFETs and the manufacturing process of semiconductor devices are desired in order to simplify the manufacturing process of low-Vth LDMOSFETs and reduce the manufacturing cost of semiconductor devices.

[0007] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0008] In one embodiment, the device comprises an epitaxial layer of a first conductivity type, a first well of the first conductivity type formed within the epitaxial layer, a first offset drain region of a second conductivity type formed within the epitaxial layer and separated from the first well, a first source region of a second conductivity type formed within the first well, a first semiconductor region of a second conductivity type formed within the first well, in contact with the first source region and separated from the first offset drain region, and having a lower impurity concentration than the first source region, and a first gate electrode formed on a part of the first offset drain region, on a portion of the epitaxial layer located between the first offset drain region and the first semiconductor region, and on the first semiconductor region via a first gate insulating film. Here, the length of the portion of the first gate electrode located between the first offset drain region and the first semiconductor region in the gate length direction is less than or equal to the length of the first semiconductor region in the gate length direction of the first gate electrode.

[0009] In one embodiment, the method for manufacturing a semiconductor device is: (a) forming an epitaxial layer of a first conductivity type having a first portion and a second portion; (b) forming a first well of the first conductivity type in the first portion and a second well of the first conductivity type in the second portion by injecting impurities into the epitaxial layer; (c) forming a first offset drain region of the second conductivity type in the first portion at a position away from the first well; (d) forming a second offset drain region of the second conductivity type in the second portion at a position away from the second well; (e) forming an epitaxial layer in contact with the first offset drain region and the first offset drain region. (f) A mask that covers a portion of a first portion of the epitaxial layer while exposing a portion of a first well, the mask covering a portion of a second offset drain region while exposing the other portion of the second offset drain region, the portion between the second offset drain region and the second well, and the second well, is formed on the epitaxial layer; (f) With the mask formed, an impurity of a second conductivity type is introduced into the epitaxial layer, thereby forming a first semiconductor region in the first well and a second semiconductor region in the second well and in a portion of the second portion of the epitaxial layer located between the second offset drain region and the second well. [Effects of the Invention]

[0010] According to one embodiment, the manufacturing process for semiconductor devices including low-Vth LDMOSFETs can be simplified, thereby reducing the manufacturing cost of semiconductor devices. [Brief explanation of the drawing]

[0011] [Figure 1] This is a cross-sectional view showing the configuration formed within region 1A of the semiconductor device. [Figure 2] This is a cross-sectional view showing the configuration formed within region 1B of the semiconductor device. [Figure 3] This figure shows the configuration of the channel formation region located between the n-type offset drain region and the source region. [Figure 4]Graph (1) shows the relationship between the position of the mask edge and the threshold voltage Vth, graph (2) shows the relationship between the mask edge D and length LA, and graph (3) shows the relationship between the position of the mask edge and length LB. [Figure 5] This figure shows the manufacturing process of a semiconductor device in an embodiment. [Figure 6] This figure shows the manufacturing process of semiconductor devices, following Figure 5. [Figure 7] This figure shows the manufacturing process of semiconductor devices, following Figure 6. [Figure 8] This figure shows the manufacturing process of semiconductor devices, following Figure 7. [Figure 9] This figure shows the manufacturing process of semiconductor devices, following Figure 8. [Figure 10] This figure shows the manufacturing process of semiconductor devices, following Figure 9. [Figure 11] This figure shows the manufacturing process of semiconductor devices, following Figure 10. [Figure 12] This figure shows the manufacturing process of semiconductor devices, following Figure 11. [Modes for carrying out the invention]

[0012] In all the drawings illustrating the embodiments, the same reference numeral is used for identical components, and repeated explanations of them are omitted. Hatching may be used even in plan views to improve clarity.

[0013] In this specification, for example, it is stated that the impurity concentrations or lengths of two components are the same (similar). This statement does not mean that the impurity concentrations or lengths are exactly the same. In reality, manufacturing variations exist. Therefore, "same" as used in this specification includes cases where there are deviations of a degree corresponding to manufacturing variations.

[0014] As LDMOSFETs, depletion-mode LDMOSFETs and enhancement-mode LDMOSFETs are known. LDMOSFETs include p-channel LDMOSFETs and n-channel LDMOSFETs. The technical idea of the present disclosure is applicable to both p-channel LDMOSFETs and n-channel LDMOSFETs. However, in this specification, the description will be made assuming an n-channel LDMOSFET.

[0015] When the depletion-mode LDMOSFET is an n-channel LDMOSFET, the depletion-mode LDMOSFET has a negative threshold voltage. On the other hand, when the enhancement-mode LDMOSFET is an n-channel LDMOSFET, the enhancement-mode LDMOSFET has a positive threshold voltage.

[0016] The depletion-mode LDMOSFET is also called a normally-on LDMOSFET. The enhancement-mode LDMOSFET is also called a normally-off LDMOSFET. In this specification, the enhancement-mode LDMOSFET includes two types of LDMOSFETs having different threshold voltages. The LDMOSFET having a relatively high threshold voltage among the two types may be simply called an LDMOSFET. On the other hand, the LDMOSFET having a relatively low threshold voltage among the two types is called a low Vth LDMOSFET.

[0017] For example, a depletion-type LDMOSFET is being considered for use as a constant current source. This is because using a depletion-type LDMOSFET as a constant current source can reduce the power consumption of the semiconductor device. Therefore, there is a need to use a depletion-type LDMOSFET as a constant current source. On the other hand, a low Vth LDMOSFET is being considered for use in a sense circuit. This is because using a low Vth LDMOSFET in a sense circuit can improve the stability of the sense circuit. Also, when using a low Vth LDMOSFET in a sense circuit, the capacitor provided in the sense circuit becomes unnecessary, resulting in a reduction in chip size. For this reason, there is a need to use a low Vth LDMOSFET in a sense circuit.

[0018] From the above, semiconductor devices including not only LDMOSFETs but also low Vth LDMOSFETs and depletion-type LDMOSFETs are being considered. In this regard, there is room for improvement in semiconductor devices. The room for improvement will be described below.

[0019] <Room for improvement> The adjustment of the threshold voltage of a MOSFET can be achieved by adjusting the work function of the gate electrode material and the gate insulating film capacitance per unit area. However, generally, the adjustment of the threshold voltage of a MOSFET is often performed by adjusting the impurity concentration in the well and the upper surface region of the well without adjusting the work function of the gate electrode material and the gate insulating film capacitance per unit area. This is because the impurity concentration in the well and the upper surface region of the well can be easily adjusted by the ion implantation amount of the impurity.

[0020] For example, the impurity concentration in the well of an LDMOSFET is the same as that of a depletion-type LDMOSFET. Similarly, the impurity concentration in the upper surface region of the well of an LDMOSFET is the same as that of a depletion-type LDMOSFET. However, in a depletion-type LDMOSFET, an n-type semiconductor region is formed that extends from the upper surface region of the well through the upper surface of the epitaxial layer to the offset drain region. As a result, a negative threshold voltage is achieved in a depletion-type LDMOSFET with an n-type semiconductor region. In contrast, a positive threshold voltage is achieved in an LDMOSFET without an n-type semiconductor region.

[0021] On the other hand, in low-Vth LDMOSFETs, to achieve a lower positive threshold voltage than LDMOSFETs, the impurity concentration in the wells of low-Vth LDMOSFETs differs from that of LDMOSFETs. Similarly, the impurity concentration in the upper surface region of the wells of low-Vth LDMOSFETs differs from that of LDMOSFETs.

[0022] Therefore, in order to manufacture a semiconductor device that includes not only LDMOSFETs but also low-Vth LDMOSFETs and depletion-type LDMOSFETs, it is necessary to add (1) a mask and ion implantation process for forming n-type semiconductor regions by ion implantation, and (2) a mask and ion implantation process for forming the wells and upper well regions of the low-Vth LDMOSFETs by ion implantation, compared to manufacturing a semiconductor device that includes only LDMOSFETs. In this case, the manufacturing cost of the semiconductor device increases.

[0023] Therefore, in order to simplify the manufacturing process of semiconductor devices, including not only LDMOSFETs but also low-Vth LDMOSFETs and depletion-type LDMOSFETs, and reduce the manufacturing cost of semiconductor devices, improvements to the structure of low-Vth LDMOSFETs and the manufacturing process of semiconductor devices are desired. The improvements described in this disclosure are explained below.

[0024] <Basic philosophy> The impurity concentration in the wells of low-Vth LDMOSFETs is similar to that of LDMOSFETs and depletion-type LDMOSFETs. The impurity concentration in the upper surface region of the wells of low-Vth LDMOSFETs is similar to that of LDMOSFETs and depletion-type LDMOSFETs. Low-Vth LDMOSFETs include n-type semiconductor regions formed in the same process as those formed in depletion-type LDMOSFETs, but the layout of the n-type semiconductor regions in low-Vth LDMOSFETs differs from that of depletion-type LDMOSFETs.

[0025] As a result, the impurity concentrations in the wells of LDMOSFETs, low-Vth LDMOSFETs, and depletion-type LDMOSFETs are the same. Similarly, the impurity concentrations in the upper surface regions of the wells of LDMOSFETs, low-Vth LDMOSFETs, and depletion-type LDMOSFETs are the same. Therefore, the wells for each of the LDMOSFETs, low-Vth LDMOSFETs, and depletion-type LDMOSFETs can be formed in the same ion implantation process, and the upper surface regions of the wells can also be formed in the same ion implantation process. In other words, according to the basic concept, there is no need to add an ion implantation process to form the wells and upper surface regions of the low-Vth LDMOSFETs.

[0026] Furthermore, the n-type semiconductor region of a low-Vth LDMOSFET can be formed in the same ion implantation process as the n-type semiconductor region of a depletion-type LDMOSFET. In this case, the layout of the n-type semiconductor region of the low-Vth LDMOSFET and the n-type semiconductor region of the depletion-type LDMOSFET can be changed by using a mask that is also used in the same ion implantation process.

[0027] Based on the above, according to the basic concept, by modifying the structure of low-Vth LDMOSFETs as described above, the manufacturing process for semiconductor devices, including not only LDMOSFETs but also low-Vth LDMOSFETs and depletion-type LDMOSFETs, can be simplified. As a result, according to the basic concept, the manufacturing cost of semiconductor devices can be reduced.

[0028] The following describes embodiments that embody the basic concept.

[0029] <Embodiment> <<Configuration of semiconductor device>> The semiconductor device 100 has region 1A and region 1B. The semiconductor device 100 has a p-type semiconductor substrate and a p-type epitaxial layer formed across region 1A and region 1B. A depletion-type LDMOSFET is formed in region 1A. In contrast, a low Vth LDMOSFET is formed in region 1B.

[0030] Here, region 1A shown in Figure 1 (described later) includes the second portion of the p-type epitaxial layer EPI. Region 1B shown in Figure 2 (described later) includes the first portion of the p-type epitaxial layer EPI. The depletion-type LDMOSFET is formed in the second portion of the p-type epitaxial layer EPI. The low Vth LDMOSFET is formed in the first portion of the p-type epitaxial layer EPI.

[0031] Figure 1 is a cross-sectional view showing the configuration formed within region 1A of the semiconductor device 100.

[0032] A depletion-type LDMOSFET is formed within region 1A.

[0033] In Figure 1, the semiconductor device 100 includes a p-type semiconductor substrate SUB, an n-type embedded layer NBL, a p-type epitaxial layer EPI, a p-type resurf layer HPW1, a p-type well PW1, an n-type well NW1, an n-type offset drain region OD1, an insulating region STI1, a drain region DR1, a source region SR1, a body contact region BC1, an n-type semiconductor region 10A, a gate insulating film GOX1, a gate electrode GE1, an interlayer insulating film IL, a plug PLG1A, a plug PLG2A, a source wiring WL1A, and a drain wiring WL2A.

[0034] An n-type burying layer NBL is formed between the p-type semiconductor substrate SUB and the p-type epitaxial layer EPI. The n-type burying layer NBL may be formed within the p-type semiconductor substrate SUB or within the p-type epitaxial layer EPI.

[0035] Within the p-type epitaxial layer EPI, a p-type resurf layer HPW1, a p-type well PW1, an n-type well NW1, an n-type offset drain region OD1, an insulating region STI1, a drain region DR1, a source region SR1, a body contact region BC1, and an n-type semiconductor region 10A are formed.

[0036] The impurity concentration in the p-type resurf layer HPW1 is higher than that in the p-type epitaxial layer EPI. Similarly, the impurity concentration in the p-type well PW1 is higher than that in the p-type epitaxial layer EPI. Furthermore, the impurity concentration in the n-type offset drain region OD1 is lower than that in the n-type well NW1.

[0037] The insulating region STI1 is formed within the n-type offset drain region OD1 and the n-type well NW1. The insulating region STI1 has a trench formed on the upper surface of the p-type epitaxial layer EPI and an insulating film embedded within the trench. In the X direction of Figure 1, the insulating region STI1 is located between the source region SR1 and the drain region DR1.

[0038] A drain region DR1 is formed within the n-type well NW1. The drain region DR1 is in contact with the insulating region STI1. The drain region DR1 is an n-type semiconductor region. The impurity concentration in the drain region DR1 is higher than the impurity concentration in the n-type well NW1.

[0039] Within the p-type well PW1, a source region SR1 and a body contact region BC1 are formed. The source region SR1 and the body contact region BC1 are in contact with each other. The source region SR1 is an n-type semiconductor region, while the body contact region BC1 is a p-type semiconductor region. The impurity concentration in the source region SR1 is higher than that of the n-type offset drain region OD1 and is about the same as that of the drain region DR1. The impurity concentration in the body contact region BC1 is higher than that of the p-type well PW1.

[0040] An n-type semiconductor region 10A is formed on the upper surface of the p-type epitaxial layer EPI. Specifically, in the X direction of Figure 1, the n-type semiconductor region 10A is formed within the p-type well PW1, within the n-type offset drain region OD1, and within the p-type epitaxial layer EPI located between the p-type well PW1 and the n-type offset drain region OD1. The n-type semiconductor region 10A is in contact with the source region SR1 and the insulating region STI1. However, the n-type semiconductor region 10A does not have to be formed within the n-type offset drain region OD1. In this case, the n-type semiconductor region 10A is not in contact with the insulating region STI1, but is in contact with the n-type offset drain region OD1.

[0041] A gate electrode GE1 is formed on a portion of the insulating region STI1, on the n-type semiconductor region 10A, and on a portion of the source region SR1 via a gate insulating film GOX1.

[0042] Here, the X direction in Figure 1 is the gate length direction of the gate electrode GE1. Therefore, the n-type semiconductor region 10A is formed in the p-type well PW1, the n-type offset drain region OD1, and the p-type epitaxial layer EPI located between the p-type well PW1 and the n-type offset drain region OD1, in the gate length direction of the gate electrode GE1.

[0043] An interlayer insulating film IL is formed on the drain region DR1, a portion of the insulating region STI1, the gate electrode GE1, the source region SR1, and the body contact region BC1. Within the interlayer insulating film IL, plugs PLG1A and PLG2A are formed, penetrating the interlayer insulating film IL. Plug PLG1A is connected to the source region SR1 and the body contact region BC1. Therefore, the source region SR1 and the body contact region BC1 are electrically connected to each other via plug PLG1A. On the other hand, plug PLG2A is connected to the drain region DR1.

[0044] Source wiring WL1A and drain wiring WL2A are formed on the interlayer insulating film IL. Source wiring WL1A is connected to plug PLG1A. Therefore, source wiring WL1A is electrically connected to source region SR1 and body contact region BC1 via plug PLG1A. Drain wiring WL2A is connected to plug PLG2A. Therefore, drain wiring WL2A is electrically connected to drain region DR1 via plug PLG2A.

[0045] In enhancement-type LDMOSFETs, which are not shown in the figures, a p-type semiconductor region with a different impurity concentration than the p-type well is formed in the upper surface region of the p-type well. This p-type semiconductor region adjusts the threshold voltage for channel formation and has the function of realizing a positive threshold voltage in enhancement-type LDMOSFETs. In other words, enhancement-type LDMOFETs not shown in this specification have the above-mentioned p-type semiconductor region.

[0046] In this regard, in the depletion-type LDMOSFET formed within region 1A, the p-type well PW1 is formed in the same process as the p-type well of the enhancement-type LDMOSFET. As a result, the impurity concentration of the p-type well PW1 is the same as that of the p-type well of the LDMOSFET. Furthermore, in the depletion-type LDMOSFET, a p-type semiconductor region with the same impurity concentration as the p-type semiconductor region of the LDMOSFET is formed in the upper surface region of the p-type well PW1 in the same process. However, in the depletion-type LDMOSFET, n-type impurities are introduced into the upper surface region of the well to counteract the p-type impurities constituting this p-type semiconductor region. As a result, in Figure 1, an n-type semiconductor region 10A is formed in the upper surface region of the well, rather than a p-type semiconductor region. Thus, in region 1A, a depletion-type LDMOSFET is realized by the n-type semiconductor region 10A.

[0047] Figure 2 is a cross-sectional view showing the configuration formed within region 1B of the semiconductor device 100.

[0048] A low Vth LDMOSFET is formed within region 1B.

[0049] In Figure 2, the semiconductor device 100 includes a p-type semiconductor substrate SUB, an n-type embedded layer NBL, a p-type epitaxial layer EPI, a p-type resurf layer HPW2, a p-type well PW2, an n-type well NW2, an n-type offset drain region OD2, an insulating region STI2, a drain region DR2, a source region SR2, a body contact region BC2, an n-type semiconductor region 10B, a gate insulating film GOX2, a gate electrode GE2, an interlayer insulating film IL, a plug PLG1B, a plug PLG2B, a source wiring WL1B, and a drain wiring WL2B.

[0050] Within the p-type epitaxial layer EPI, a p-type resurf layer HPW2, a p-type well PW2, an n-type well NW2, an n-type offset drain region OD2, an insulating region STI2, a drain region DR2, a source region SR2, a body contact region BC2, and an n-type semiconductor region 10B are formed. The n-type offset drain region OD2 is located separately from the p-type well PW2. Therefore, the portion located between the n-type offset drain region OD2 and the p-type well PW2 is part of the p-type epitaxial layer EPI.

[0051] The impurity concentration in the p-type resurfacing layer HPW2 is higher than that in the p-type epitaxial layer EPI. Similarly, the impurity concentration in the p-type well PW2 is higher than that in the p-type epitaxial layer EPI. Furthermore, the impurity concentration in the n-type offset drain region OD2 is lower than that in the n-type well NW2. The impurity concentration in the p-type resurfacing layer HPW2 is the same as that in the p-type resurfacing layer HPW1. Similarly, the impurity concentration in the p-type well PW2 is the same as that in the p-type well PW1. Furthermore, the impurity concentration in the n-type offset drain region OD2 is the same as that in the n-type offset drain region OD1.

[0052] The insulating region STI2 is formed within the n-type offset drain region OD2 and the n-type well NW2. The insulating region STI2 has a trench formed on the upper surface of the p-type epitaxial layer EPI and an insulating film embedded in the trench. The insulating region STI2 has the same configuration as the insulating region STI1. In the X direction of Figure 2, the insulating region STI2 is located between the source region SR2 and the drain region DR2.

[0053] A drain region DR2 is formed within the n-type well NW2. The drain region DR2 is in contact with the insulating region STI2. The drain region DR2 is an n-type semiconductor region. The impurity concentration in the drain region DR2 is higher than the impurity concentration in the n-type well NW2. The impurity concentration in the drain region DR2 is the same as the impurity concentration in the drain region DR1.

[0054] Within the p-type well PW2, a source region SR2 and a body contact region BC2 are formed. The source region SR2 and the body contact region BC2 are in contact with each other. The source region SR2 is an n-type semiconductor region, while the body contact region BC2 is a p-type semiconductor region. The impurity concentration in the source region SR2 is higher than that of the n-type offset drain region OD2 and is about the same as that of the drain region DR2. The impurity concentration in the body contact region BC2 is higher than that of the p-type well PW2.

[0055] Furthermore, the impurity concentration in source region SR2 is the same as that in source region SR1. Also, the impurity concentration in body contact region BC2 is the same as that in body contact region BC1.

[0056] An n-type semiconductor region 10B is formed on the upper surface of the p-type well PW2. Specifically, in the X direction of Figure 2, a part of the n-type offset drain region OD2, a p-type semiconductor region between the n-type offset drain region OD2 and the n-type semiconductor region 10B, and the n-type semiconductor region 10B are formed between the insulating region STI2 and the source region SR2. For example, the n-type semiconductor region 10B is in contact with the boundary between the p-type epitaxial layer EPI and the p-type well PW2, as well as with the source region SR2.

[0057] In Figure 2, the p-type semiconductor region between the n-type offset drain region OD2 and the n-type semiconductor region 10B is the p-type epitaxial layer EPI located between the n-type offset drain region OD2 and the p-type well PW2. That is, the n-type semiconductor region 10B is located separately from the n-type offset drain region OD2. For example, in Figure 2, the n-type semiconductor region 10B extends to the boundary between the p-type epitaxial layer EPI and the p-type well PW2. However, the n-type semiconductor region 10B may not extend to the boundary between the p-type epitaxial layer EPI and the p-type well PW2. In this case, the p-type semiconductor region between the n-type offset drain region OD2 and the n-type semiconductor region 10B includes the portion of the p-type epitaxial layer EPI located between the n-type offset drain region OD2 and the p-type well PW2, and a portion of the upper surface region of the p-type well PW2 located between the p-type epitaxial layer EPI and the n-type semiconductor region 10B.

[0058] The gate electrode GE2 is formed via the gate insulating film GOX2 on a portion of the insulating region STI2, a portion of the n-type offset drain region OD2, a portion of the p-type epitaxial layer EPI located between the n-type offset drain region OD2 and the p-type well PW2, the n-type semiconductor region 10B, and a portion of the source region SR2. Here, the X direction in Figure 2 is the gate length direction of the gate electrode GE2.

[0059] An interlayer insulating film IL is formed on the drain region DR2, a portion of the insulating region STI2, the gate electrode GE2, the source region SR2, and the body contact region BC2. Within the interlayer insulating film IL, plugs PLG1B and PLG2B are formed, penetrating the interlayer insulating film IL. Plug PLG1B is connected to the source region SR2 and the body contact region BC2. Therefore, the source region SR2 and the body contact region BC2 are electrically connected to each other via plug PLG1B. On the other hand, plug PLG2B is connected to the drain region DR2.

[0060] Source wiring WL1B and drain wiring WL2B are formed on the interlayer insulating film IL. Source wiring WL1B is connected to plug PLG1B. Therefore, source wiring WL1B is electrically connected to the source region SR2 and the body contact region BC2 via plug PLG1B. Drain wiring WL2B is connected to plug PLG2B. Therefore, drain wiring WL2B is electrically connected to the drain region DR2 via plug PLG2B.

[0061] In the low-Vth LDMOSFET formed within region 1B, the p-type well PW2 is formed using the same process as the p-type well of the enhancement-type LDMOSFET. As a result, the impurity concentration of the p-type well PW2 is the same as that of the p-type well of the LDMOSFET. Furthermore, in the low-Vth LDMOSFET, a p-type semiconductor region with the same impurity concentration as the p-type semiconductor region of the LDMOSFET is formed in the upper surface region of the p-type well PW2 using the same process. However, in the low-Vth LDMOSFET, n-type impurities are introduced into the upper surface region of the well to counteract the p-type impurities constituting this p-type semiconductor region. As a result, in Figure 2, an n-type semiconductor region 10B is formed in the upper surface region of the well, rather than a p-type semiconductor region. Thus, in region 1B, the low-Vth LDMOSFET is realized by the n-type semiconductor region 10B. Here, for example, if the n-type semiconductor region 10B does not reach the boundary between the p-type epitaxial layer EPI and the p-type well PW2, then a p-type semiconductor region is formed in the upper surface region of the well located between the boundary and the n-type semiconductor region 10B.

[0062] In region 1A, a depletion-type LDMOSFET is realized by the n-type semiconductor region 10A shown in Figure 1. In contrast, in region 1B, a low Vth LDMOSFET is realized by the n-type semiconductor region 10B shown in Figure 2.

[0063] In other words, as shown in Figure 1, a depletion-type LDMOSFET is realized by forming an n-type semiconductor region 10A that reaches at least the n-type offset drain region OD1 and is in contact with the source region SR1. On the other hand, as shown in Figure 2, a low Vth LDMOSFET is realized by forming an n-type semiconductor region 10B that is away from the n-type offset drain region OD2 and is in contact with the source region SR2.

[0064] For example, the length of the n-type semiconductor region 10A in the gate length direction of the gate electrode GE1 is greater than the length of the n-type semiconductor region 10B in the gate length direction of the gate electrode GE2. As a result, a depletion-type LDMOSFET is realized in region 1A, while a low Vth LDMOSFET is realized in region 1B.

[0065] The following explains how forming an n-type semiconductor region 10B can enable the realization of a low-Vth LDMOSFET that has a positive threshold voltage while having a lower threshold voltage than an LDMOSFET.

[0066] Figure 3 shows the configuration of the channel formation region CH located between the n-type offset drain region OD and the source region SR. In Figure 3, the channel formation region CH is formed between the n-type offset drain region OD and the source region SR. A body contact region BC is formed so as to be in contact with the source region SR. An insulating region STI is formed so as to be in contact with the n-type offset drain region OD.

[0067] A gate electrode GE is formed on the insulating region STI, on a portion of the n-type offset drain region OD, on the channel formation region CH, and on a portion of the source region SR via the gate insulating film GOX.

[0068] The channel-forming region CH comprises an n-type semiconductor region 10 and a p-type semiconductor region 20. The sum of the length LA of the p-type semiconductor region 20 in the X direction and the length LB of the n-type semiconductor region 10 in the X direction is the length Lch of the channel-forming region CH in the X direction.

[0069] For example, if length LA is set to 0, the channel formation region CH is composed of n-type semiconductor regions 10. In this case, the configuration shown in Figure 1 is realized, and the n-type semiconductor region 10 becomes n-type semiconductor region 10A. As a result, in Figure 3, if length LA is set to 0, a depletion-type LDMOSFET with a negative threshold voltage is obtained. In contrast, if length LB is set to 0, the channel formation region CH is composed of p-type semiconductor regions 20. In this case, an enhancement-type LDMOSFET with a positive threshold voltage is obtained.

[0070] Therefore, qualitatively, it can be understood that, for example, if certain conditions are met when length LA is greater than 0 and length LB is greater than 0, a low Vth LDMOSFET with a positive threshold voltage and a lower threshold voltage than the enhancement-type LDMOSFET described above can be realized. This point will be explained in detail below.

[0071] Figure 4 shows graphs (1) showing the relationship between the mask edge position D and the threshold voltage Vth, graph (2) showing the relationship between the mask edge position D and the length LA, and graph (3) showing the relationship between the mask edge position D and the length LB.

[0072] The horizontal axis in Figure 4 shows the position D of the mask edge. The vertical axis in Figure 4 shows the threshold voltage Vth in graph (1), the length LA in graph (2), and the length LB in graph (3). Referring to Figure 3, the following qualitative findings can be obtained.

[0073] The mask is used for ion implantation to form the n-type semiconductor region 10. The horizontal axis in Figure 4 shows the position D of the mask edge from the edge of the insulating region STI in the X direction. When the mask edge is located on the edge of the insulating region STI, the position D of this mask edge is 0. Therefore, when D=0, an n-type semiconductor region 10 is formed that is in contact with both the insulating region STI and the source region SR. As a result, a depletion-type LDMOSFET with a negative threshold voltage is realized.

[0074] When position D is greater than 0, the length Lch is the same as the length LB until position D reaches the edge of the n-type offset drain region OD, resulting in a depletion-type LDMOSFET. When position D is greater than the position of the edge of the n-type offset drain region OD from the insulating region STI, the length LA becomes greater than 0, and a p-type semiconductor region 20 is formed in the channel formation region CH. As a result, the threshold voltage gradually increases due to the p-type semiconductor region 20. Subsequently, as position D increases, the length of the p-type semiconductor region 20 in the X direction increases, resulting in a further increase in the threshold voltage, changing from a negative threshold voltage to a positive threshold voltage. For example, if position D is increased further, the length of the p-type semiconductor region 20 in the X direction increases even further, resulting in a further increase in the threshold voltage, and eventually the threshold voltage saturates.

[0075] Based on this finding, looking at graph (1) in Figure 4, the above finding can explain the behavior of graph (1). In Figure 4, based on graphs (2) and (3), Figure 4 has the following three regions. Region R1 represents a state where length LA is 0. In region R1, since there is no p-type semiconductor region 20, it is a region where a depletion-type LDMOSFET with a negative threshold voltage is realized. Region R3 represents a state where length LA is greater than length LB. In region R3, looking at graph (1) in Figure 4, it is a region where the positive threshold voltage is almost saturated, so an enhancement-type LDMOSFET with a positive threshold voltage is realized. In contrast, region R2 represents a state where length LA is greater than 0 and less than or equal to length LB. In region R2, looking at graph (1) in Figure 4, the positive threshold voltage is gradually increasing. From this, it can be seen that in region R2, a low Vth LDMOSFET with a positive threshold voltage and a lower threshold voltage than the enhancement-type LDMOSFET is realized.

[0076] Therefore, a low Vth LDMOSFET can be realized by satisfying the conditions within the range of region R2. That is, a low Vth LDMOSFET can be realized when the length LA of the portion located between the n-type offset drain region OD and the n-type semiconductor region 10 in the gate length direction (X direction) of the gate gate GE is less than or equal to the length LB of the n-type semiconductor region 10 in the gate length direction of the gate gate GE. In other words, a low Vth LDMOSFET can be realized when the length LA of the p-type semiconductor region 20 in the gate length direction (X direction) of the gate gate GE is less than or equal to the length LB of the n-type semiconductor region 10 in the gate length direction of the gate gate GE.

[0077] <<Structural Characteristics of Semiconductor Devices>> For example, the channel formation region of an enhancement-type LDMOSFET is composed of a p-type semiconductor region. Similarly, the channel formation region of a low-Vth LDMOSFET, which has a positive threshold voltage and a lower threshold voltage than the aforementioned LDMOSFET, is also generally composed of a p-type semiconductor region. In this case, the impurity concentration of the p-type semiconductor region of the low-Vth LDMOSFET with a low threshold voltage is different from the impurity concentration of the p-type semiconductor region of the aforementioned LDMOSFET. This enables the realization of a low-Vth LDMOSFET. Furthermore, the channel formation region of a depletion-type LDMOSFET is composed of an n-type semiconductor region.

[0078] Therefore, in order to manufacture semiconductor devices that include low-Vth LDMOSFETs and depletion-type LDMOSFETs along with LDMOSFETs, it is necessary to add steps to form the n-type semiconductor region of the depletion-type LDMOSFET and the p-type semiconductor region of the low-Vth LDMOSFET, which has a different impurity concentration than the p-type semiconductor region of the LDMOSFET. In this case, the manufacturing cost of the semiconductor device increases.

[0079] Therefore, the embodiment has the following features. That is, the channel formation region of the low Vth LDMOSFET has a p-type semiconductor region with the same impurity concentration as the p-type semiconductor region of an enhancement-type LDMOSFET, and an n-type semiconductor region with the same impurity concentration as the n-type semiconductor region of a depletion-type LDMOSFET. The p-type semiconductor region and the n-type semiconductor region are formed to satisfy the conditions within the range of region R2 in Figure 4 described above. As a result, a low Vth LDMOSFET can be realized according to this embodiment.

[0080] The following explains that by employing a low-Vth LDMOSFET with such a structure, the manufacturing process for semiconductor devices, including not only LDMOSFETs but also low-Vth LDMOSFETs and depletion-type LDMOSFETs, can be simplified.

[0081] <<Manufacturing Method for Semiconductor Devices>> As shown in Figure 5, n-type impurities are introduced into the p-type semiconductor substrate SUB using ion implantation. This forms an n-type embedded layer NBL within the p-type semiconductor substrate SUB. Next, a p-type epitaxial layer EPI is formed on the p-type semiconductor substrate SUB on which the n-type embedded layer NBL has been formed, for example, by using an epitaxial growth method.

[0082] Next, p-type impurities are introduced into the p-type epitaxial layer EPI formed in region 1A and the p-type epitaxial layer EPI formed in region 1B using photolithography and ion implantation techniques. This forms a p-type resurfacing layer HPW1, a p-type well PW1, and a p-type semiconductor region CD1 within the p-type epitaxial layer EPI in region 1A. A p-type resurfacing layer HPW2, a p-type well PW2, and a p-type semiconductor region CD2 are formed within the p-type epitaxial layer EPI in region 1B.

[0083] Furthermore, p-type impurities are introduced into the p-type epitaxial layer EPI formed within the enhancement-type LDMOSFET formation region (not shown). As a result, a p-type resurf layer, a p-type well, and a p-type semiconductor region are formed within the p-type epitaxial layer EPI formed within the enhancement-type LDMOSFET formation region (not shown).

[0084] The p-type semiconductor region is formed in the enhancement-type LDMOSFET to achieve a positive threshold voltage. Here, the p-type wells, p-type well PW1, and p-type well PW2 are formed in the same ion implantation process using a mask that opens up the formation region of the p-type well, the formation region of p-type well PW1, and the formation region of p-type well PW2, respectively. Then, using this mask, the p-type semiconductor region is formed on the upper surface region of the p-type well, so inevitably, the p-type semiconductor region CD1 is formed on the upper surface region of p-type well PW1, and the p-type semiconductor region CD2 is formed on the upper surface region of p-type well PW2.

[0085] The impurity concentrations in the p-type resurfacing layer HPW1, p-type resurfacing layer HPW2, and the p-type resurfacing layer are identical. The impurity concentrations in the p-type well PW1, p-type well PW2, and the p-type well are identical. The impurity concentrations in the p-type semiconductor region CD1, p-type semiconductor region CD2, and the p-type semiconductor region are identical.

[0086] Next, n-type impurities are introduced into the p-type epitaxial layer EPI formed in region 1A and the p-type epitaxial layer EPI formed in region 1B using photolithography and ion implantation techniques. This forms an n-type well NW1 and an n-type offset drain region OD1 within the p-type epitaxial layer EPI in region 1A. An n-type well NW2 and an n-type offset drain region OD2 are formed within the p-type epitaxial layer EPI in region 1B. The n-type offset drain region OD1 is formed at a location separate from the p-type well PW1. The n-type offset drain region OD2 is formed at a location separate from the p-type well PW2.

[0087] Furthermore, n-type impurities are also introduced into the p-type epitaxial layer EPI formed within the enhancement-type LDMOSFET formation region (not shown). As a result, an n-type well and an n-type offset drain region are formed within the p-type epitaxial layer EPI formed within the enhancement-type LDMOSFET formation region (not shown). The n-type offset drain region is formed at a location separate from the p-type well.

[0088] The impurity concentrations in n-type well NW1, n-type well NW2, and the n-type well are the same. The impurity concentrations in n-type offset drain region OD1, n-type offset drain region OD2, and the n-type offset drain region are the same. In the following process description, the enhancement-type LDMOSFET formation region, which is not shown in the figures, will not be mentioned, but may be mentioned as necessary.

[0089] Next, as shown in Figure 6, a resist film PR is formed on the p-type epitaxial layer EPI, and then a mask is formed by patterning the resist film PR using photolithography. The patterning of the resist film PR is performed such that in region 1A, the edge of the resist film PR is located at "X1", and in region 1B, the edge of the resist film PR is located at "X2". "X1" and "X2" are not limited to the positions shown in Figure 6. That is, in region 1B, a mask is formed on the p-type epitaxial layer EPI that covers the n-type offset drain region OD2 and a portion of the p-type epitaxial layer EPI that is in contact with the n-type offset drain region OD2, while exposing at least a portion of the p-type well PW2, and in region 1A, a mask is formed that covers a portion of the n-type offset drain region OD1 while exposing the other portion of the n-type offset drain region OD1, the portion between the n-type offset drain region OD1 and the p-type well PW1, and the p-type well PW1. In Figure 6, region 1B illustrates a state where the entire p-type well PW2 is exposed from the resist film PR. However, it is also possible for only a portion of the p-type well PW2 to be exposed while the rest of the p-type well PW2 is covered by the resist film PR.

[0090] Next, as shown in Figure 7, n-type impurities are introduced into the p-type epitaxial layer EPI while a mask consisting of a patterned resist film PR is formed using ion implantation. As a result, in region 1B, an n-type semiconductor region 10B is formed within the p-type well PW2, and in region 1A, an n-type semiconductor region 10A is formed within the p-type well PW1, within a portion of the p-type epitaxial layer EPI located between the n-type offset drain region OD1 and the p-type well PW1, and within a portion of the n-type offset drain region OD1.

[0091] Subsequently, as shown in Figure 8, the mask consisting of the patterned resist film PR is removed by using ashing technology.

[0092] Next, as shown in Figure 9, in region 1A, an insulating region STI1 is formed within the n-type well NW1 and the n-type offset drain region OD1, and in region 1B, an insulating region STI2 is formed within the n-type well NW2 and the n-type offset drain region OD2.

[0093] For example, the process of forming the insulating region STI1 consists of forming trenches in the n-type well NW1 and the n-type offset drain region OD1, and filling the trenches with an insulating film. Similarly, the process of forming the insulating region STI2 consists of forming trenches in the n-type well NW2 and the n-type offset drain region OD2, and filling the trenches with an insulating film.

[0094] Next, as shown in Figure 10, in region 1A, gate electrode GE1 is formed on a portion of the insulating region STI1 and a portion of the n-type semiconductor region 10A via gate insulating film GOX1. In region 1B, gate electrode GE2 is formed on the insulating region STI2, a portion of the n-type offset drain region OD2, a portion of the p-type epitaxial layer EPI located between the n-type offset drain region OD2 and the n-type semiconductor region 10B, and a portion of the n-type semiconductor region 10B via gate insulating film GOX2.

[0095] Subsequently, as shown in Figure 11, a source region SR1 is formed in the p-type well PW1 and a drain region DR1 is formed in the n-type well NW1 in region 1A using photolithography and ion implantation techniques. The source region SR1 has a higher impurity concentration than the n-type semiconductor region 10A. The drain region DR1 has a higher impurity concentration than the n-type well NW1. In addition, a source region SR2 is formed in the p-type well PW2 and a drain region DR2 is formed in the n-type well NW2 in region 1B. The source region SR2 has a higher impurity concentration than the n-type semiconductor region 10B. The drain region DR2 has a higher impurity concentration than the n-type well NW2.

[0096] Furthermore, by using photolithography and ion implantation techniques, a body contact region BC1 is formed within the p-type well PW1 in region 1A, and a body contact region BC2 is formed within the p-type well PW2 in region 1B. Body contact region BC1 has a higher impurity concentration than p-type well PW1. Body contact region BC2 has a higher impurity concentration than p-type well PW2.

[0097] As shown in Figure 11, the n-type semiconductor region 10A is in contact with both the source region SR1 and the insulating region STI1. In contrast, the n-type semiconductor region 10B is in contact with the source region SR2, but is separated from the n-type offset drain region OD2.

[0098] In this case, the length of the portion of the gate electrode GE2 located between the n-type offset drain region OD2 and the n-type semiconductor region 10B in the gate length direction (X direction) is less than or equal to the length of the n-type semiconductor region 10B in the gate length direction of the gate electrode GE2.

[0099] Furthermore, the length of the n-type semiconductor region 10A in the gate length direction of the gate gate electrode GE1 is greater than the length of the n-type semiconductor region 10B in the gate length direction of the gate gate electrode GE2.

[0100] Next, as shown in Figure 12, in region 1A, an interlayer insulating film IL is formed on the drain region DR1, a portion of the insulating region STI1, the gate electrode GE1, the source region SR1, and the body contact region BC1. In region 1B, an interlayer insulating film IL is formed on the drain region DR2, a portion of the insulating region STI2, the gate electrode GE2, the source region SR2, and the body contact region BC2.

[0101] Then, in region 1A, plugs PLG1A and PLG2A are formed, penetrating the interlayer insulating film IL. Plug PLG1A is connected to the source region SR1 and the body contact region BC1. Plug PLG2A is connected to the drain region DR1.

[0102] In region 1B, plugs PLG1B and PLG2B are formed, penetrating the interlayer insulating film IL. Plug PLG1B is connected to the source region SR2 and the body contact region BC2. Plug PLG2B is connected to the drain region DR2.

[0103] Subsequently, in region 1A, source wiring WL1A and drain wiring WL2A are formed on the interlayer insulating film IL. Source wiring WL1A is connected to plug PLG1A. Drain wiring WL2A is connected to plug PLG2A.

[0104] In region 1B, source wiring WL1B and drain wiring WL2B are formed on the interlayer insulating film IL. Source wiring WL1B is connected to plug PLG1B. Drain wiring WL2B is connected to plug PLG2B.

[0105] As described above, semiconductor devices including low-Vth LDMOSFETs and depletion-type LDMOSFETs can be manufactured.

[0106] <<Characteristics of the manufacturing process of semiconductor devices>> According to the embodiment, wells can be formed in the same ion implantation process for LDMOSFETs, low-Vth LDMOSFETs, and depletion-type LDMOSFETs, and the upper surface region of the wells (p-type semiconductor region) can also be formed in the same ion implantation process. Therefore, according to the embodiment, there is no need to add an ion implantation process to form wells and upper surface regions of the wells that are specific to low-Vth LDMOSFETs (first feature).

[0107] As shown in Figure 7, the n-type semiconductor region 10B of the low-Vth LDMOSFET can be formed in the same ion implantation process as the n-type semiconductor region 10A of the depletion-type LDMOSFET. Here, the layout of the n-type semiconductor region 10B of the low-Vth LDMOSFET and the layout of the n-type semiconductor region 10A of the depletion-type LDMOSFET can be changed by using a mask (patterned resist film PR) used in the same ion implantation process (second feature).

[0108] Based on the above, according to this embodiment, by adopting the structure shown in Figure 2 as the structure of the low-Vth LDMOSFET, the manufacturing process of semiconductor devices, including not only LDMOSFETs but also low-Vth LDMOSFETs and depletion-type LDMOSFETs, can be simplified. As a result, according to this embodiment, the manufacturing cost of semiconductor devices can be reduced.

[0109] The present inventors have described the invention in detail based on its embodiments, but it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0110] 1A area 1B area 10 n-type semiconductor region 10A n-type semiconductor region 10B n-type semiconductor region 20 p-type semiconductor region 100 Semiconductor Equipment BC1 Body Contact Area BC2 Body Contact Area CD1 p-type semiconductor region CD2 p-type semiconductor region CH channel formation region DR1 Drain Area DR2 drain area EPI p-type epitaxial layer GE Terminal GE1 🙏 GE2 gate GOX gate insulating film GOX1 gate insulating film GOX2 gate insulating film HPW1 p-type resurfacing layer HPW2 p-type resurfacing layer IL interlayer film NBL n-type embedding layer NW1 n-type well NW2 n-type well OD n-type offset drain region OD1 n-type offset drain region OD2 n-type offset drain region PLG1A Plug PLG1B Plug PLG2A plug PLG2B Plug PR resist film PW1 p-type well PW2 p-type well SR Source Area SR1 Source Area SR2 Source Area STI isolation area STI1 Insulation Area STI2 Insulation Area SUB p-type semiconductor substrate WL1A Source Wiring WL1B Source Wiring WL2A drain wiring WL2B drain wiring

Claims

1. A first-conductivity epitaxial layer, The first well of the first conductivity type formed in the epitaxial layer, A first offset drain region of a second conductivity type is formed within the epitaxial layer and is located apart from the first well, The first source region of the second conductivity type formed in the first well, A first semiconductor region of a second conductivity type formed within the first well, in contact with the first source region, and separated from the first offset drain region, and having a lower impurity concentration than the first source region, A first gate electrode formed on a portion of the first offset drain region, on a portion of the epitaxial layer located between the first offset drain region and the first semiconductor region, and on the first semiconductor region via a first gate insulating film, Equipped with, A semiconductor device wherein the length of the portion of the first gate electrode located between the first offset drain region and the first semiconductor region in the gate length direction is less than or equal to the length of the first semiconductor region of the first gate electrode in the gate length direction.

2. In the semiconductor device described in claim 1, The aforementioned semiconductor device is A first trench formed within the first offset drain region, The first insulating film embedded in the first trench, A first drain region of the second conductivity type that is in contact with the first trench and has a higher impurity concentration than the first offset drain region, It has, The first trench is located between the first source region and the first drain region.

3. In the semiconductor device described in claim 1, The first conductivity type is p-type, The second conductivity type is n-type.

4. In the semiconductor device described in claim 1, The epitaxial layer has a first portion and a second portion, The first gate electrode is formed on the first portion via the first gate insulating film, The first well is formed within the first portion, The first offset drain region is formed within the first portion, The first source region is formed within the first portion, The first semiconductor region is formed within the first portion, The aforementioned semiconductor device is The second well of the first conductivity type formed within the second portion, A second offset drain region of a second conductivity type is formed within the second portion and is located apart from the second well, The second source region of the second conductivity type formed in the second well, A second semiconductor region of the second conductivity type formed within the second well, and in contact with the second source region, and in contact with the second offset drain region, and having a lower impurity concentration than the second source region, A second gate insulating film formed on at least the second semiconductor region, A second gate electrode formed on the second gate insulating film, It is equipped with.

5. In the semiconductor device according to claim 4, The length of the second semiconductor region of the second gate electrode in the gate length direction is greater than the length of the first semiconductor region of the first gate electrode in the gate length direction.

6. In the semiconductor device according to claim 4, The second semiconductor region is also formed within a portion of the second offset drain region.

7. In the semiconductor device according to claim 4, The aforementioned semiconductor device is A first trench formed within the first offset drain region, The first insulating film embedded in the first trench, A first drain region of the second conductivity type that is in contact with the first trench and has a higher impurity concentration than the first offset drain region, A second trench formed within the second offset drain region, The second insulating film embedded in the second trench, A second drain region of the second conductivity type that is in contact with the second trench and has a higher impurity concentration than the second offset drain region, It has, The first trench is located between the first source region and the first drain region. The second trench is located between the second source region and the second drain region. The second semiconductor region is in contact with the second trench.

8. In the semiconductor device according to claim 4, The first conductivity type is p-type, The second conductivity type is n-type.

9. (a) A step of forming a first conductive type epitaxial layer having a first portion and a second portion, (b) A step of forming a first well of the first conductivity type in the first portion and a second well of the first conductivity type in the second portion by injecting impurities into the epitaxial layer. (c) A step of forming a first offset drain region of a second conductivity type within the first portion but at a location separate from the first well, (d) A step of forming a second offset drain region of the second conductivity type within the second portion but at a location separate from the second well, (e) A step of forming on the epitaxial layer a mask that covers the first offset drain region and a portion of the first part of the epitaxial layer in contact with the first offset drain region, while exposing at least a portion of the first well, the mask that covers a portion of the second offset drain region while exposing the other part of the second offset drain region, the portion between the second offset drain region and the second well, and the second well. (f) A step of forming a first semiconductor region in the first well by introducing the second conductivity type impurity into the epitaxial layer while the mask is formed, and forming a second semiconductor region in the second well and in a part of the second portion of the epitaxial layer located between the second offset drain region and the second well, A method for manufacturing a semiconductor device, comprising:

10. In the method for manufacturing a semiconductor device according to claim 9, (g) A step of forming a first trench within the first offset drain region, (h) A step of forming a second trench within the second offset drain region, (i) A step of embedding the first insulating film in the first trench, (j) Step of embedding a second insulating film in the second trench, It has.

11. In the method for manufacturing a semiconductor device according to claim 10, (k) A step of forming a first gate electrode via a first gate insulating film on a portion of the first offset drain region, on a portion of the epitaxial layer located between the first offset drain region and the first semiconductor region, and on the first semiconductor region. (l) A step of forming a second gate electrode on a part of the second offset drain region and on the second semiconductor region via a second gate insulating film, (m) A step of forming a first source region of the second conductivity type having a higher impurity concentration than the first semiconductor region in the first well, (n) A step of forming a second source region of the second conductivity type having a higher impurity concentration than the second semiconductor region in the second well, It has, The first semiconductor region is in contact with the first source region, but is separated from the first offset drain region. The second semiconductor region is in contact with the second source region and also in contact with the second trench. The length of the portion of the first gate electrode located between the first offset drain region and the first semiconductor region in the gate length direction is less than or equal to the length of the first semiconductor region in the gate length direction of the first gate electrode.

12. In the method for manufacturing a semiconductor device according to claim 11, The length of the second semiconductor region of the second gate electrode in the gate length direction is greater than the length of the first semiconductor region of the first gate electrode in the gate length direction.

13. In the method for manufacturing a semiconductor device according to claim 9, The first conductivity type is p-type, The second conductivity type is n-type.

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