Image sensor and method for manufacturing the same

Abstract

The present invention provides an image sensor and a method for manufacturing the same, which prevents damage that may occur to the semiconductor layer on the side where the floating diode is formed by forming a plug structure between the floating diode and a metal contact electrically connected to the floating diode. [Solution] The present invention provides an image sensor comprising: a semiconductor layer; a photodiode within the semiconductor layer; a floating diode within the semiconductor layer; a plug structure provided on the semiconductor layer and having a side in contact with the floating diode; and a metal contact connected to the plug structure.

Description

Technical Field

[0001] The present invention relates to an image sensor and a method for manufacturing the same. More specifically, by forming a plug structure between a floating diode and a metal contact electrically connected to the floating diode, damage that may occur in a semiconductor layer on the side where the floating diode is formed is prevented. The present invention relates to an image sensor and a method for manufacturing the same.

Background Art

[0002] An image sensor is a component of an imaging device that generates images in a mobile phone camera, etc., and is classified into a CCD (Charge Coupled Device) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor according to the manufacturing process and application method. Among them, the CMOS image sensor is widely positioned in a general semiconductor chip manufacturing process due to its excellent integration competitiveness, economy, and ease of connection with peripheral chips.

[0003] FIG. 1 is a cross-sectional view of a conventional image sensor of the present invention. Hereinafter, referring to FIG. 1, the structure of the conventional image sensor 9 and the associated problems will be described in detail.

[0004] Referring to FIG. 1, the conventional image sensor 9 can include a photodiode 920 in a semiconductor layer 910 and a floating diode 930 on a side separated from the photodiode 920. Further, an insulating film layer 940 is formed on the semiconductor layer 910, and a metal contact 950 can be formed in a shape penetrating the insulating film layer 940. Such a metal contact 950 is made of, for example, tungsten (W), extends vertically in the insulating film layer 940, its bottom surface is connected to the floating diode 930, and its upper surface can be connected to a metal wiring (not shown).

[0005] Thus, during the reactive ion etching process performed to form the metal contact 950 that contacts the floating diode 930, there is a possibility that damage may occur to the semiconductor layer 910 on the side where the floating diode 930 is formed. In addition, there is a possibility that the metal layer may penetrate and contaminate the floating diode 930 when gap filling of the metal layer within the insulating film layer 940 for the formation of the metal contact 950. In such situations, dark current may be generated in the pixel region, which can be a factor that reduces the reliability of the device.

[0006] To solve the problems described above, the inventors of the present invention present a novel image sensor and a method for manufacturing the same, which will be described in detail later. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] U.S. Patent Registration US9,054,106 B2, "SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME" [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention was devised to solve the problems of the prior art, and its objective is to provide an image sensor and a method for manufacturing the same that prevent damage to the semiconductor layer on the side where the floating diode is formed by forming a plug structure between the floating diode and the metal contact electrically connected to the floating diode.

[0009] Furthermore, the present invention aims to provide an image sensor and a method for manufacturing the same, which prevents contamination of the floating diode with metallic material during the formation of metal contacts by forming a plug structure on the floating diode.

[0010] Furthermore, the present invention aims to provide an image sensor and a method for manufacturing the same, which suppresses leakage current from the surface of a semiconductor layer within a pixel region by forming a pinning layer on the surface side of a floating diode.

[0011] Furthermore, the present invention aims to provide an image sensor and a method for manufacturing the same, wherein the pinning layer is formed only on a portion of the surface of the floating diode, thereby ensuring that the floating diode is in contact with the plug structure.

[0012] Furthermore, the present invention aims to provide an image sensor and a method for manufacturing the same, which improves process convenience by ensuring that the plug structure is directly connected to the drive gate and the polysilicon film.

[0013] Furthermore, the present invention aims to provide an image sensor and a method for manufacturing the same, which prevents damage that may occur in the semiconductor layer on the side where the floating diode is formed, by removing the first insulating film on the floating diode by a wet etching process. [Means for solving the problem]

[0014] The above objectives can be achieved by an embodiment having the following configuration.

[0015] According to one embodiment of the present invention, the image sensor according to the present invention is characterized by including a semiconductor layer, a photodiode in the semiconductor layer, a floating diode in the semiconductor layer, a plug structure provided on the semiconductor layer and having a side in contact with the floating diode, and a metal contact connected to the plug structure.

[0016] According to another embodiment of the present invention, the image sensor according to the present invention further comprises a first pinning layer which is a first conductivity type impurity doping region on the surface side of the photodiode.

[0017] According to another embodiment of the present invention, the image sensor according to the present invention further comprises a second pinning layer which is a first conductivity type impurity doping region on the surface side of the floating diode.

[0018] According to another embodiment of the present invention, the second pinning layer of the image sensor according to the present invention is characterized by having a smaller horizontal width size compared to the floating diode.

[0019] According to another embodiment of the present invention, the plug structure of the image sensor according to the present invention is characterized by being a polysilicon film.

[0020] According to another embodiment of the present invention, the plug structure of the image sensor according to the present invention is characterized in that its bottom surface is in contact with the floating diode.

[0021] According to another embodiment of the present invention, the image sensor according to the present invention further includes a plug insulating film between the plug structure and the floating diode, wherein the plug insulating film is located on the bottom surface of the plug structure on a side adjacent to one side or both sides of the plug structure.

[0022] According to another embodiment of the present invention, the plug structure of the image sensor according to the present invention is characterized by having a stepped portion on the bottom surface.

[0023] According to another embodiment of the present invention, the image sensor according to the present invention further includes a plug spacer on the side wall of the plug structure.

[0024] According to another embodiment of the present invention, the image sensor according to the present invention further includes a drive gate on the semiconductor layer, and the drive gate is physically connected to the plug structure.

[0025] According to another embodiment of the present invention, the image sensor according to the present invention further includes an element isolation film in the semiconductor layer, and the drive gate is connected to the plug structure by a polysilicon film that contacts the element isolation film and extends from above the element isolation film.

[0026] According to another embodiment of the present invention, the image sensor according to the present invention includes a pixel region that is a region for receiving incident light, a logic region in the peripheral portion of the pixel region, a semiconductor layer, a photodiode in the semiconductor layer within the pixel region, a floating diode in the semiconductor layer within the pixel region, a plug structure provided on the semiconductor layer and having a side that contacts the floating diode, a metal contact connected to the plug structure, and a logic gate provided in the logic region and including a first gate and a second gate on the semiconductor layer.

[0027] According to another embodiment of the present invention, the plug structure of the image sensor according to the present invention is formed together in the same process as the logic gate.

[0028] According to another embodiment of the present invention, the image sensor according to the present invention further comprises a drive gate on the semiconductor layer and a polysilicon film on the semiconductor layer that connects the drive gate and the plug structure between the drive gate and the plug structure.

[0029] According to another embodiment of the present invention, the image sensor according to the present invention further includes a first gate insulating film between the first gate and the semiconductor layer, a second gate insulating film between the second gate and the semiconductor layer, and a plug insulating film between the plug structure and the semiconductor layer, wherein the first gate insulating film has a greater vertical thickness than the second gate insulating film.

[0030] According to another embodiment of the present invention, the plug insulating film of the image sensor according to the present invention is characterized in that it has a larger vertical thickness than the second gate insulating film.

[0031] According to another embodiment of the present invention, the floating diode of the image sensor according to the present invention is characterized in that at least one side is surrounded by the photodiode.

[0032] According to one embodiment of the present invention, a method for manufacturing an image sensor according to the present invention is characterized by comprising the steps of: forming a first insulating film having a first thickness on a semiconductor layer; etching one side of the first insulating film to form a first opening on a floating diode; forming a polysilicon film on the first insulating film so as to fill the first opening; etching the polysilicon film to form a plug structure on a logic gate and a floating diode having a side that contacts the floating diode; forming an insulating film layer on the semiconductor layer so as to cover the logic gate and the plug structure; and forming a metal contact that penetrates the insulating film layer so as to be connected to the plug structure.

[0033] According to another embodiment of the present invention, a method for manufacturing an image sensor according to the present invention further includes the steps of etching the other side of the first insulating film to form a second aperture, and forming a second insulating film having a second thickness on the semiconductor layer opened by the second aperture, wherein the first thickness is larger than the second thickness.

[0034] According to another embodiment of the present invention, the method for manufacturing an image sensor according to the present invention further includes the step of forming spacers on the side walls of the logic gate and the plug structure. [Effects of the Invention]

[0035] The present invention has the following effects due to the configuration described above.

[0036] The present invention has the effect of preventing damage that could occur to the semiconductor layer on the side where the floating diode is formed, by forming a plug structure between the floating diode and the metal contact electrically connected to the floating diode.

[0037] Furthermore, the present invention has the effect of preventing contamination of the floating diode with metallic material during the formation of metal contacts by forming a plug structure on the floating diode.

[0038] Furthermore, the present invention provides the effect of suppressing leakage current from the surface of the semiconductor layer within the pixel region by forming a pinning layer on the surface side of the floating diode.

[0039] Furthermore, the present invention demonstrates the effect of ensuring that the floating diode makes contact with the plug structure by forming the pinning layer only on a portion of the surface of the floating diode.

[0040] Furthermore, the present invention demonstrates the effect of improving process convenience by ensuring that the plug structure is directly connected to the drive gate by a polysilicon film.

[0041] Furthermore, the present invention has the effect of preventing damage that could occur in the semiconductor layer on the side where the floating diode is formed, by ensuring that the first insulating film on the floating diode is removed by a wet etching process.

[0042] On the other hand, even effects not explicitly mentioned herein, as well as the effects described below in the specification and their provisional effects that are expected by the technical features of the present invention, shall be treated as described in the specification of the present invention. [Brief explanation of the drawing]

[0043] [Figure 1] This is a cross-sectional view of a conventional image sensor. [Figure 2] This is a plan view of an image sensor according to one embodiment of the present invention. [Figure 3] This is a plan view of an image sensor according to a first embodiment of the present invention. [Figure 4] Figure 3 shows a cross-sectional view of the image sensor along the AA' line. [Figure 5] This is a plan view of an image sensor according to a second embodiment of the present invention. [Figure 6] Figure 5 shows a cross-sectional view of the image sensor along the BB' line. [Figure 7] Figure 5 shows a cross-sectional view of the image sensor along the CC' line. [Figure 8] This is a plan view of an image sensor according to a third embodiment of the present invention. [Figure 9] Figure 8 shows a cross-sectional view of the image sensor along the DD' line. [Figure 10] Figure 8 shows a cross-sectional view of the image sensor along the EE' line. [Figure 11]This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 12] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 13] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 14] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 15] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 16] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Figure 17] This is a cross-sectional view illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. [Modes for carrying out the invention]

[0044] Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Embodiments of the present invention can be modified in various forms, and the scope of the present invention should not be construed as being limited to these embodiments, but rather as being construed in terms of the matters described in the claims. Furthermore, these embodiments are provided only as reference to further fully explain the present invention to those who are ordinary skill in the art.

[0045] In the following, when it is stated that one component (or layer) is placed on another component (or layer), it should be noted that the component may also be placed directly on the other component, or another component or layer may be interposed between them. Also, when it is stated that one component is placed directly on another component, there is no other component located between them. Furthermore, being located "on top," "above," "below," "upper side," "lower side," "one side," or "side" of a component refers to a relative positional relationship.

[0046] Furthermore, terms such as "first," "second," etc., can be used to describe various items such as various elements, domains, and / or parts, but these items are not limited by these terms.

[0047] Furthermore, it should be noted that if a particular embodiment can be realized in a different manner, a particular sequence of steps may be performed in a different order than that described below. For example, two steps described sequentially may be performed substantially simultaneously or in reverse order.

[0048] Furthermore, the conductivity type or doping region of the constituent elements can be defined as "P-type" or "N-type" based on their main carrier characteristics, but this is merely for illustrative purposes and does not limit the technical concept of the present invention to those exemplified. For example, below, "P-type" or "N-type" will be used as the more general terms "first conductivity type" or "second conductivity type," where the first conductivity type means P-type and the second conductivity type means N-type.

[0049] Furthermore, the terms "high concentration" and "low concentration," used to describe doping concentrations in the impurity range, should be understood as referring to the relative doping concentration between one component and other components.

[0050] Furthermore, it should be noted that the image sensor according to the present invention is applicable not only to front-illuminated image sensors but also to back-illuminated image sensors.

[0051] In the following diagram, the x-axis direction will be referred to as the "first direction" and the y-axis direction as the "second direction".

[0052] Figure 2 is a plan view of an image sensor according to one embodiment of the present invention.

[0053] Referring to Figure 2, the image sensor according to the present invention can have a pixel region P and a logic region L. The pixel region P is a region that absorbs light incident from the outside, and the logic region L is a region that forms the periphery of the pixel region. The pixel region P can contain a number of unit pixel regions P1. A pad (not shown) can be formed in the logic region L to be electrically connected to an external terminal.

[0054] Figure 3 is a plan view of an image sensor according to the first embodiment of the present invention, and Figure 4 is a cross-sectional view of the image sensor according to Figure 3 along line AA'.

[0055] The image sensor 1 according to the first embodiment of the present invention will be described in detail below with reference to the attached drawings. The image sensor described below may be a CMOS image sensor as an example.

[0056] Referring to Figures 3 and 4, the present invention relates to an image sensor 1, and more particularly to an image sensor 1 that prevents damage to the semiconductor layer on the side where the floating diode is formed, thereby blocking the generation of dark current in the pixel region P, by forming a plug structure between the floating diode and a metal contact electrically connected to the floating diode.

[0057] To this end, the image sensor 1 according to the first embodiment may include a semiconductor layer 110. The semiconductor layer 110 includes, for example, an epitaxial layer and is formed in common within the pixel region P and the logic region L. The semiconductor layer 110 may also be, as an example, a region doped with a low concentration of first conductivity type impurities. Furthermore, a number of element isolation films 111 can be provided separated from the surface of the semiconductor layer 110 to a predetermined depth. Such element isolation films 111 define an active region and can be formed by performing an STI (Shallow Trench Isolation) process.

[0058] In a unit pixel region P1, a photodiode 121 and a floating diode 123 can be provided within the semiconductor layer 110, spaced apart from each other. For example, the photodiode 121 and the floating diode 123 can be formed on the surface side of the semiconductor layer 110. The photodiode 121 is a region that generates charge in response to incident light, and the floating diode 123 is configured to sequentially read out the charge accumulated in the photodiode 121 according to the readout timing. Both the photodiode 121 and the floating diode 123 may be second conductivity type impurity doping regions.

[0059] Preferably, the photodiode 121 is a pinned photodiode. Such a photodiode 121 can be manufactured by performing an ion implantation process on the semiconductor layer 110 to form a first impurity region 121a of the second conductivity type and a second impurity region 121b of the first conductivity type. In this case, it is preferable that the second impurity region 121b is formed above the first impurity region 121a, the first impurity region 121a is a low-concentration doping region of the second conductivity type impurity, and the second impurity region 121b is a high-concentration doping region of the first conductivity type impurity compared to the epitaxial layer of the semiconductor layer 110. The first impurity region 121a is a region that functions as a photodiode, and the second impurity region 121b is a region corresponding to the pinning layer.

[0060] Furthermore, it is preferable that the floating diode 123 is also a pinned floating diode. Such a floating diode 123, like the photodiode 121, may include a third impurity region 123a of the second conductivity type and a fourth impurity region 123b of the first conductivity type. In this case, it is preferable that the fourth impurity region 123b is formed on the surface side of the semiconductor layer 110 and is formed only in a part of the region such that the plug structure 160, described later, and one side of the floating diode 123 are in contact. For example, it is preferable that the fourth impurity region 123b is not formed on the central side of the floating diode 123, but rather on the edge or border side of the floating diode 123. By configuring it in this way, leakage current from the surface of the semiconductor layer 110 can be suppressed. The third impurity region 123a is a region that functions as a floating diode, and the fourth impurity region 123b is a region corresponding to the pinning layer. In the following, the pinning layer of the second impurity region 121b of the photodiode 121 will be referred to as the "first pinning layer," and the pinning layer of the fourth impurity region 123b of the floating diode 123 will be referred to as the "second pinning layer."

[0061] Furthermore, within the unit pixel region P1 and the logical region L, a number of source / drain regions 125 may be provided spaced apart from each other.

[0062] Furthermore, in a unit pixel region P1, a transfer gate 141, a reset gate 143, a drive gate 145, and a selection gate 147 may be provided on the semiconductor layer 110 at a distance from each other.

[0063] The aforementioned source / drain regions 125 can be formed within the semiconductor layer 110 on either side of each reset gate 143. Therefore, a transfer transistor Tx can be formed on the transfer gate 141 side, a reset transistor Rx on the reset gate 143 side, a drive transistor Dx on the drive gate 145 side, and a selection transistor Sx on the selection gate 147 side.

[0064] For example, the transfer transistor Tx is configured to connect or short-circuit the photodiode 121 and the floating diode 123, and can be formed between the photodiode 121 and the floating diode 123. The reset transistor Rx is configured to be formed between the transfer transistor Tx and the drive transistor Dx, and can reset the voltage of the floating diode 123 to the power supply voltage, thereby resetting the accumulated charge of the floating diode 123.

[0065] Furthermore, the selection transistor Sx is configured to amplify the voltage of the floating diode 123, and the drive transistor Dx is configured to selectively output the amplified voltage according to the selection signal. As an example, the drive transistor Dx can be formed between the reset transistor Rx and the selection transistor Sx.

[0066] Furthermore, in the logic region L, a pair of logic gates 149 can be formed on the semiconductor layer 110. Hereinafter, the pair of logic gates 149 will be referred to as "first gate 149a" and "second gate 149b," respectively. For example, one of the first gate 149a and the second gate 149b may be the gate of a PMOS transistor and the other the gate of an NMOS transistor. Also, a high voltage HV may be applied to one of the first gate 149a and the second gate 149b, and a low voltage LV may be applied to the other. Hereinafter, for the sake of explanation, the gate to which the high voltage (HV) is applied will be referred to as the first gate 149a. On both sides of the first gate 149a and the second gate 149b, a source / drain region 125 can be formed within the semiconductor layer 110.

[0067] For example, source / drain regions 125a, which are highly doped regions of a first conductivity type impurity, can be formed on both sides of the first gate 149a, and source / drain regions 125b, which are highly doped regions of a second conductivity type impurity, can be formed on both sides of the second gate 149b. Then, within the semiconductor layer 110, a first well region 127a, which is a highly doped region of a second conductivity type impurity, can be formed so as to surround the source / drain region 125a, and a second well region 127b, which is a highly doped region of a first conductivity type impurity, can be formed so as to surround the source / drain region 125b. Hereinafter, the first well region 127a and the second well region 127b will be collectively referred to as the well region 127.

[0068] The individual gates 141-149 described above may include polysilicon films. A gate insulating film 151 can be formed between the individual gates 141-149 and the semiconductor layer 110. The gate insulating film 151 may include, for example, a silicon oxide film, a high dielectric film, or a combination thereof. The gate insulating film 151 can be formed by processes such as ALD, CVP, or PVD. Furthermore, the first thickness T1 of the first gate insulating film 151a below the first gate 149a to which a high voltage HV is applied may be greater than the second thickness T2 of the second gate insulating film 151b below the second gate 149b to which a low voltage LV is applied (T1 > T2). In addition, gate spacers 153 may be further formed on the side walls of the individual gates 141-149. Such gate spacers 153 may include, for example, an oxide film or a nitride film, but the scope of the present invention is not limited thereto.

[0069] Furthermore, a plug structure 160 can be formed on the semiconductor layer 110 on the side where the floating diode 123 is formed. The plug structure 160 is formed together with the gates 141 to 149 and can include, for example, a polysilicon film. Moreover, a gate insulating film 151 does not need to be formed between the plug structure 160 and the floating diode 123. That is, since the floating diode 123 must be electrically connected to the metal contact 180 described later, a gate insulating film 151 does not need to be formed between the plug structure 160 and the floating diode 123.

[0070] Alternatively, a plug insulating film 161, identical to the gate insulating film 151, can be formed only in a portion of the area between the plug structure 160 and the floating diode 123. That is, the plug insulating film 161 is formed on the underside of the plug structure 160, but is formed only in a portion of the area so that the floating diode 123 and the metal contact 180 connected to the floating diode 123 are electrically connected to each other, thereby allowing the floating diode 123 to have a side that contacts the plug structure 160.

[0071] Therefore, at least one side of the bottom surface of the plug structure 160 can be in contact with the upper surface of the floating diode 123. For this purpose, the plug insulating film 161 may be formed on one side of the plug structure 160 on the bottom surface of the plug structure 160, or it may be formed on both sides spaced apart from each other. When the plug insulating film 161 is formed in this way, a stepped portion 160a can be formed on the bottom surface of the plug structure 160. The stepped portion 160a is formed in a stepped manner on the bottom surface of the plug structure 160 in correspondence with the plug insulating film 161. In this case, the plug insulating film 161 can have a value substantially the same as the first thickness T1.

[0072] Furthermore, plug spacers 163 may be formed on both side walls of the plug structure 160. The plug spacers 163 have a configuration corresponding to the gate spacers 153 and can be formed together in the same process as the gate spacers 153.

[0073] Furthermore, an insulating film layer 170 can be formed on the semiconductor layer 110 so as to cover the individual gates 141-149 and the plug structure 160. The insulating film layer 170 may include, for example, an oxide film, a nitride film, or an oxidnitride film, but the scope of the present invention is not limited by these specific examples.

[0074] Furthermore, numerous metal contacts 180 are formed along the vertical direction in a structure that penetrates the insulating film layer 170, allowing them to be electrically connected to the source / drain region 125, individual gates 141-149, and plug structure 160, respectively. In addition, the metal contacts 180 connected to the drive gate 145 and the metal contacts 180 connected to the plug structure 160 can be electrically connected to each other by metal wiring (not shown).

[0075] In this case, a silicide film 190 can be formed on the source / drain region 125 and individual gates 141-149 on the side to which the metal contact 180 is connected. Such a silicide film 190 can be formed via a self-aligned silicide (salicide) process using a metal film such as cobalt (Co), nickel (Ni), or titanium (Ti) to improve contact resistance and thermal stability. Furthermore, it is preferable that the silicide film 190 is not formed on the plug structure 160.

[0076] According to the first embodiment of the present invention, the metal contact 180 is connected to the plug structure 160 without being physically directly connected to the floating diode 123. Therefore, damage to the semiconductor layer 110 on the floating diode 123 side can be prevented during the etching process (e.g., reactive ion etching process) for forming the metal contact 180. Furthermore, contamination of the floating diode 123 by the metallic material used to form the metal contact 180 can also be prevented. Consequently, the plug structure 160 can suppress the generation of dark current within the pixel region P. This can have an even greater advantage when applied to a global shutter image sensor, where the time electrons remain in the floating diode 123 is relatively longer than that of a rolling shutter system. However, it should be noted that the image sensor 1 according to the present invention is not limited to a global shutter system.

[0077] Figure 5 is a plan view of the image sensor according to the second embodiment, Figure 6 is a cross-sectional view of the image sensor according to Figure 5 along the BB' line, and Figure 7 is a cross-sectional view of the image sensor according to Figure 5 along the CC' line.

[0078] The image sensor 2 according to the second embodiment of the present invention will be described in detail below with reference to the attached drawings. The image sensor 2 according to the second embodiment differs from the image sensor 1 according to the first embodiment only in the plug structure 260, so only the plug structure 260 will be described in detail below. In addition, for configurations corresponding to the image sensor 1 according to the first embodiment, the starting number of the drawings has been changed from "1" to "2".

[0079] Referring to Figures 5 to 7, the image sensor 2 according to the second embodiment has a plug structure 260. The plug structure 260 can be connected to the drive gate 245. As an example, a single polysilicon film PS can extend on the semiconductor layer 210 from the region where the drive transistor Dx is formed to the region where the floating diode 223 is formed. In this case, the polysilicon film PS can extend across the element isolation film 211 between the region where the drive transistor Dx is formed and the region where the floating diode 223 is formed.

[0080] Furthermore, a gate insulating film 251 and a plug insulating film 261 can be formed between the polysilicon film PS and the semiconductor layer 210. Such a gate insulating film 251 and plug insulating film 261 may have sides that are physically connected to each other. For example, the gate insulating film 251 and the plug insulating film 261 may each consist of a single structure. In this case, it is preferable that the plug insulating film 261 is formed to partially cover the upper surface of the floating diode 223. Alternatively, as another example, a plug insulating film 261 that covers at least a portion of the upper surface of the floating diode 223 may not be formed. That is, the gate insulating film 251 can be formed between the polysilicon film PS and the semiconductor layer 210, extending across the element isolation film 211 to the side adjacent to the floating diode 223, but without a side that covers the floating diode 223.

[0081] Figure 8 is a plan view of an image sensor according to a third embodiment of the present invention, Figure 9 is a cross-sectional view of the image sensor according to Figure 8 along the DD' line, and Figure 10 is a cross-sectional view of the image sensor according to Figure 8 along the EE' line.

[0082] The image sensor 3 according to the third embodiment of the present invention will be described in detail below with reference to the attached drawings. The image sensor 3 according to the third embodiment is, for example, an X-ray sensor, and a transfer transistor may not be formed. Also, for the configuration corresponding to the image sensor 1 according to the first embodiment, the starting number of the drawings has been changed from "1" to "3".

[0083] Referring to Figures 8 to 10, the image sensor 3 according to the third embodiment may include a floating diode 323 within the photodiode 321 in the semiconductor layer 310. A plug structure 360 ​​is formed on the photodiode 321, and this plug structure 360 ​​may be substantially identical to the plug structure 160 according to the first embodiment or the plug structure 260 according to the second embodiment.

[0084] Figures 11 to 17 are cross-sectional views illustrating a method for manufacturing an image sensor according to one embodiment of the present invention. It should be noted that peripheral structures of the floating diode (transfer transistors, photodiodes, etc.) have been omitted from Figures 11 to 17.

[0085] A method for manufacturing an image sensor according to one embodiment of the present invention will be described in detail below with reference to the attached drawings. For the sake of convenience, only the process of forming the plug structure 160 on the semiconductor layer 110 will be described below.

[0086] Referring to Figure 11, first, a first insulating film I1 can be formed on the semiconductor layer 110. The first insulating film I1 can include a silicon oxide film, a high dielectric film, or a combination thereof. For example, the first insulating film I1 may be a silicon oxide film formed by a thermal oxidation process. In this case, the first insulating film I1 may have a first thickness T1 along the vertical direction.

[0087] Referring to Figure 12, the first insulating film I1 on the side where the second gate 149b is formed can then be removed. For example, by forming a mask pattern (not shown) on the first insulating film I1 and then performing an etching process, the first insulating film I1 on the side where the second gate 149b is formed can be removed. This process forms a first opening O1 in the first insulating film I1 on the side where the second gate 149b is formed, thereby exposing the upper surface of the semiconductor layer 110.

[0088] Referring to Figure 13, a second insulating film I2 can be formed on the semiconductor layer 110 on the first opening O1 side in a subsequent step. The second insulating film I2 can include a silicon oxide film, a high dielectric film, or a combination thereof. For example, the second insulating film I2 may be a silicon oxide film formed by a thermal oxidation process. Furthermore, the second insulating film I2 has a second thickness T2 along the vertical direction, and the second thickness T2 can be smaller than the first thickness T1 (T2 <T1)。

[0089] Referring to Figure 14, the first insulating film I1 on the upper surface of the semiconductor layer 110 on which the floating diode 123 is formed can then be removed so that at least one side of the floating diode 123 is opened. This can be done by performing an etching process, such as a wet etching process, using a mask pattern (not shown) on the first insulating film I1. Thus, a second opening O2 can be formed on the upper side of the floating diode 123. Performing a wet etching process in this way prevents damage to the semiconductor layer 110. In the above example, it was explained that the second opening O2 is formed after the first opening O1, but in some cases, the second opening O2 may be formed first, or the pair of openings O1 and O2 may be formed together in the same process, and there are no other restrictions.

[0090] Referring to Figure 15, a polysilicon film PS can then be deposited on the first insulating film I1 and the second insulating film I2 so as to fill the openings O.

[0091] Referring to Figure 16, the polysilicon film PS and, optionally, the first insulating film I1 below the polysilicon film PS can be etched to form individual gates 141-149 and a plug structure 160. A gate insulating film 151 may be formed below the individual gates 141-149, and a plug insulating film 161 may or may not be formed below the plug structure 160. The first gate insulating film 151a below the first gate 149a may have a first thickness T1, and the second gate insulating film 151b below the second gate 149b may have a second thickness T2.

[0092] Subsequently, gate spacers 153 can be formed on the side walls of individual gates 141-149, and plug spacers 163 can be formed on the side wall of the plug structure 160. This process can be carried out by depositing a third insulating film (not shown) to cover the gates 141-149 and the plug structure 160, followed by an etching process. Then, by performing an ion implantation process within the semiconductor layer 110, the source / drain region 125 can be formed.

[0093] Subsequently, a self-aligned silicide process may be performed to form a silicide film 190 on the upper side of the source / drain region 125 and individual gates 141-149.

[0094] Referring to Figure 17, an insulating film layer 170 can then be formed on the semiconductor layer 110 to cover the individual gates 141-149 and the plug structure 160. Subsequently, the insulating film layer 170 can be etched using a mask pattern (not shown), and a metal contact 180 can be formed by a gap-fill process for the metal layer.

[0095] The above detailed description is illustrative of the present invention. Furthermore, the foregoing describes preferred embodiments of the present invention, and the present invention can be used in a variety of different combinations, modifications, and environments. That is, modifications and alterations are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the disclosed content, and / or within the scope of the art or knowledge of the art. The embodiments described herein describe the best possible state for realizing the technical idea of ​​the present invention, and various modifications are possible as required in the specific field of application and use of the present invention. Therefore, the above detailed description of the invention is not intended to limit the present invention to the disclosed embodiments. [Explanation of symbols]

[0096] 1. Image sensor according to the first embodiment 110 Semiconductor layer 111 Element Separation Membrane 121 Photodiode 121a 1st impurity region 121b Second impurity region / first pinning layer 123 Floating Diode 123a Third impurity region 123b Fourth impurity region / second pinning layer 125, 125a, 125b Source / Drain 127-well area 127a First well area 127b Second well area 141 Transfer Gate 143 Reset Gate 145 Drive Gate 147 Selection Gate 149 Logic Gates 149a Gate 1 149b Gate 2 151 Gate Insulator 151a First gate insulating film 151b Second gate insulating film 153 Gate Spacer 160 Plug Structure 160a Step section 161 Plug insulating film 163 Plug Spacer 170 Insulating film layer 180 Metal Contact 190 Silicide membrane P Pixel Region P1 Unit Pixel Area L logical area Tx transfer transistor Rx Reset Transistor Dx drive transistor Sx Select Transistor PS polysilicon film I1 First insulating film I2 Second insulating film T1 First Thread T2 Second thickness O1 First opening O2 2nd opening

Claims

1. Semiconductor layer, The photodiode in the semiconductor layer, The floating diode in the semiconductor layer, A plug structure provided on the semiconductor layer and having a side that contacts the floating diode, An image sensor characterized by including a metal contact connected to the plug structure.

2. The image sensor according to claim 1, further comprising a first pinning layer which is a first conductivity type impurity doping region on the surface side of the photodiode.

3. The image sensor according to claim 1, further comprising a second pinning layer which is a first conductivity type impurity doping region on the surface side of the floating diode.

4. The image sensor according to claim 3, characterized in that the second pinning layer has a smaller horizontal width size compared to the floating diode.

5. The image sensor according to claim 1, characterized in that the plug structure is a polysilicon film.

6. The image sensor according to claim 1, characterized in that the plug structure has a bottom surface that contacts the floating diode.

7. The plug insulating film between the plug structure and the floating diode further comprises The plug insulating film is The image sensor according to claim 1, characterized in that it is located on the bottom surface of the plug structure on a side adjacent to one side or both sides of the plug structure.

8. The image sensor according to claim 7, characterized in that the plug structure has a stepped portion on its bottom surface.

9. The image sensor according to claim 1, further comprising a plug spacer on the side wall of the plug structure.

10. Further comprising a drive gate on the semiconductor layer, The aforementioned drive gate is The image sensor according to claim 1, characterized in that it is physically connected to the plug structure.

11. The semiconductor layer further includes an element isolation film, The aforementioned drive gate is The image sensor according to claim 10, characterized in that it is connected to the plug structure by a polysilicon film that is in contact with the element isolation film and extends from the element isolation film.

12. The pixel region is the area that receives incident light, The logical region of the peripheral part of the aforementioned pixel region, Semiconductor layer, A photodiode in the semiconductor layer within the pixel region, A floating diode in the semiconductor layer within the pixel region, A plug structure provided on the semiconductor layer and having a side that contacts the floating diode, A metal contact connected to the plug structure, An image sensor characterized by including a logic gate within the logic region, which includes a first gate and a second gate on the semiconductor layer.

13. The aforementioned plug structure is The image sensor according to claim 12, characterized in that it is formed together with the logic gate in the same process.

14. The drive gate on the semiconductor layer, The image sensor according to claim 12, further comprising a polysilicon film on a semiconductor layer that connects the drive gate and the plug structure between the drive gate and the plug structure.

15. The first gate insulating film between the first gate and the semiconductor layer, The second gate insulating film between the second gate and the semiconductor layer, The plug insulating film between the plug structure and the semiconductor layer further comprises, The first gate insulating film is The image sensor according to claim 12, characterized in that it has a larger vertical thickness than the second gate insulating film.

16. The plug insulating film is The image sensor according to claim 15, characterized in that it has a larger vertical thickness than the second gate insulating film.

17. The image sensor according to claim 12, characterized in that at least one side of the floating diode is surrounded by the photodiode.

18. The steps include forming a first insulating film having a first thickness on a semiconductor layer, The steps include etching one side of the first insulating film to form a first opening on the floating diode, The steps include forming a polysilicon film on the first insulating film so as to fill the first opening, The steps include etching the polysilicon film to form a plug structure on a logic gate and a floating diode, having a side that contacts the floating diode, The steps include forming an insulating film layer on the semiconductor layer so as to cover the logic gate and the plug structure, A method for manufacturing an image sensor, comprising the step of forming a metal contact that penetrates the insulating film layer so as to be connected to the plug structure.

19. The steps include etching the other side of the first insulating film to form a second opening, The method further includes the step of forming a second insulating film having a second thickness on the semiconductor layer opened by the second opening, The first thickness is, The method for manufacturing an image sensor according to claim 18, characterized in that it has a value larger than the second thickness.

20. The method for manufacturing an image sensor according to claim 18, further comprising the step of forming a spacer on the side wall of the logic gate and the plug structure.

Images