Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a power semiconductor structure and a method for manufacturing the same. [Solution] The semiconductor structure 1 includes a substrate 10, a channel layer 110 placed on top of it, electrodes 130, 140, 162 placed on top of the channel layer, and a plurality of field plates 164. The plurality of field plates are electrically connected to the gate electrode and have at least one first field plate 1641 and a second field plate 1642. The first field plate partially overlaps with and connects to the gate electrode. The second field plate partially overlaps with and connects to the first field plate. The gate electrode and the plurality of field plates form a continuous stepped structure. Partially overlapping and connecting means that they are partially directly in contact and connected, with no intermediate structures.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same, and particularly to a power semiconductor structure and a method for manufacturing the same.

Background Art

[0002] In recent years, the demand for high-frequency and high-power products has been increasing day by day. Power semiconductor devices made of gallium nitride, such as aluminum gallium nitride / gallium nitride (AlGaN / GaN), have a wide bandgap and high-speed electron mobility characteristics. Due to these characteristics, the device can achieve a very high switching speed and operate under high-frequency, high-power, and high-temperature working environments. Therefore, such devices are widely applied to high-power semiconductor structures, especially in the fields of high-frequency and power applications. Conventional high electron mobility transistors (HEMTs) employ a stack of group III-V semiconductor materials to form a heterojunction at the material interface. Due to the bending of the energy band in the heterojunction, the conduction band forms a potential well in the bending region. A two-dimensional electron gas (2DEG) is formed within this potential well.

[0003] The device channel resistance of a gallium nitride high electron mobility transistor changes depending on different operating conditions (such as bias and frequency changes), and is particularly significant during switching operations and high-voltage operations. The increase in dynamic resistance causes many problems. This includes an increase in power loss and a decrease in overall efficiency, and this phenomenon is more serious under high-frequency operations. Furthermore, the increase in dynamic resistance causes an increase in the time constant, affects the switching speed of the device, and reduces the advantage of high-speed switching of power devices in high-frequency applications.

[0004] Adding a field plate structure to the gate structure is an important technical means of mitigating dynamic resistance problems. The gate field plate primarily reduces electric field concentration and extends the electric field distribution over a wider area. This structure reduces the peak value of the electric field, thereby mitigating or delaying the dynamic resistance effect. Therefore, after adding the field plate design, the variation in the device's dynamic resistance decreases. This improvement has a significant effect in high-voltage applications, improving the reliability and performance of power devices.

[0005] However, in current power device manufacturing processes, adding a field plate structure requires multiple contact hole (Via) etching and multiple metal deposition processes. As shown in Figure 1, mainstream 650-volt normally-on high electron mobility transistors (D-mode HEMTs) employ a three-layer field plate design. When fabricating a three-layer field plate, the process includes four metal deposition steps (gate metal GM, first field plate FP1, second field plate FP2, third field plate FP3) and three contact hole (V1, V2, V3) etching steps to form a seven-layer stacked structure, without affecting the dielectric layer beneath the gate metal layer. This complex process leads to increased manufacturing time and higher production costs. To overcome this problem, the industry urgently needs an innovative semiconductor structure that can optimize field plate design and reduce production time and costs. [Overview of the project]

[0006] The main objective of this invention is to provide an innovative semiconductor structure. This structure is characterized by the stacking of dielectric layers and block layers with a high etching selectivity ratio. Combined with a patterned etching process, it forms multiple field plates with a continuous step-like structure. This design mitigates the dynamic resistance effect due to electric field concentration in power devices.

[0007] To achieve the above objective, the present invention provides a semiconductor structure comprising a substrate, a channel layer, electrodes, and a plurality of field plates. The channel layer is positioned above the substrate. The electrodes are positioned above the channel layer. The plurality of field plates are electrically connected to the electrodes and have at least one first field plate and a second field plate. The first field plate partially overlaps with and connects to the electrodes. The second field plate partially overlaps with and connects to the first field plate. The electrodes and the plurality of field plates form a continuous stepped structure. Partially overlapping and connected means that they are partially directly in contact and connected, with no intermediate structures.

[0008] In the semiconductor structure of the embodiment of the present invention, the electrode is a gate electrode, a source electrode, or a drain electrode.

[0009] In the semiconductor structure of the embodiment of the present invention, the semiconductor structure further includes a first block layer and a first dielectric layer, the first dielectric layer covers the first block layer, and the first block layer and the first dielectric layer define the shape of the electrode.

[0010] In the semiconductor structure of the embodiment of the present invention, the semiconductor structure further includes a second block layer and a second dielectric layer, the second dielectric layer covers the second block layer, the second block layer covers the first dielectric layer, and the second block layer and the second dielectric layer define the shape of the first field plate.

[0011] In the semiconductor structure of the embodiment of the present invention, the first block layer and the first dielectric layer define a first dimension, the second block layer and the second dielectric layer define a second dimension, the first dimension is smaller than the second dimension, and the first and second dimensions are the maximum lateral dimensions of the electrode and the first field plate, respectively.

[0012] In the semiconductor structure of the embodiment of the present invention, the first block layer and the second block layer are an aluminum nitride (AlN) layer, a gallium oxide (Ga2O3) layer, or an aluminum oxide (Al2O3) layer.

[0013] In the semiconductor structure of the embodiment of the present invention, the first dielectric layer and the second dielectric layer are silicon nitride (SiN) layer, silicon oxide (SiO2) layer, silicon oxide nitride (SiON) layer, or silicon carbide (SiC).

[0014] In the semiconductor structure of the embodiment of the present invention, the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a diamond substrate, or a gallium nitride substrate.

[0015] To achieve the above objective, the present invention provides a method for manufacturing a semiconductor structure, comprising the steps of forming a channel layer on a substrate and forming electrodes and a plurality of field plates simultaneously on the channel layer. The plurality of field plates are electrically connected to the electrodes. The plurality of field plates have at least one first field plate and a second field plate. The first field plate partially overlaps with and connects to the electrodes. The second field plate partially overlaps with and connects to the first field plate. The electrodes and the plurality of field plates form a continuous stepped structure. Partially overlapping and connecting as described above means partially directly in contact with and connected, with no intermediate structure.

[0016] In the method for manufacturing a semiconductor structure according to an embodiment of the present invention, the steps of forming electrodes and a plurality of field plates are: A step of sequentially forming a first block layer and a first dielectric layer above the channel layer, A step of sequentially forming a second block layer and a second dielectric layer above the first dielectric layer, The process involves pattern etching the second dielectric layer, stopping the etching at the second block layer, thereby exposing a portion of the second block layer. The process involves removing the exposed portion of the second block layer, thereby exposing a portion of the first dielectric layer. The process involves pattern etching the first dielectric layer, stopping the etching at the first block layer, thereby exposing a portion of the first block layer, A step of removing the exposed portion of the first block layer, The process includes depositing a metal to cover a portion of the channel layer, a portion of the first dielectric layer, and a portion of the second dielectric layer, thereby simultaneously forming electrodes and multiple field plates. The first block layer and the first dielectric layer define the shape of the electrodes. The second block layer and the second dielectric layer define the shape of the first field plate.

[0017] In the semiconductor structure manufacturing method according to the embodiment of the present invention, a first dimension is defined by the steps of pattern etching a first dielectric layer and removing the exposed portion of the first block layer. A second dimension is defined by the steps of pattern etching a second dielectric layer and removing the exposed portion of the second block layer. The first dimension is smaller than the second dimension. The first and second dimensions are the maximum lateral dimensions of the electrode and the first field plate, respectively.

[0018] In the semiconductor structure manufacturing method according to the embodiment of the present invention, the first block layer and the second block layer are an aluminum nitride (AlN) layer, a gallium oxide (Ga2O3) layer, or an aluminum oxide (Al2O3) layer.

[0019] In the semiconductor structure manufacturing method according to the embodiment of the present invention, the first dielectric layer and the second dielectric layer are silicon nitride (SiN) layer, silicon oxide (SiO2) layer, silicon oxide nitride (SiON) layer, or silicon carbide (SiC).

[0020] In the semiconductor structure manufacturing method according to the embodiment of the present invention, the etching selectivity ratio of the first dielectric layer and the second dielectric layer to the first block layer and the second block layer is greater than 100.

[0021] In the semiconductor structure manufacturing method according to the embodiment of the present invention, the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a diamond substrate, or a gallium nitride substrate.

[0022] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below.

Brief Description of the Drawings

[0023] [Figure 1] Schematic diagram of a conventional normally-on type high electron mobility transistor having a three-layer field plate structure [Figure 2A] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2B] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2C] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2D] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2E] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2F] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2G] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2H] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2I] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2J] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2K] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2L] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2M] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2N] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2O] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 2P]Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Figure 3] Schematic diagram of the manufacturing process of a semiconductor structure in an embodiment of the present invention [Modes for carrying out the invention]

[0024] The present invention will be described below through examples. These examples illustrate the embodiments of the present invention and are not intended to limit the invention to any particular environment, application, or specific configuration described therein. Therefore, while the examples illustrate the present invention, they do not limit it. Components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships of the components in the drawings are for ease of understanding and do not limit the actual dimensions.

[0025] Figures 2A to 2P show the manufacturing process of semiconductor structure 1 in embodiments of the present invention, and more particularly refer to a high electron mobility transistor and a method for manufacturing the same. As shown in Figure 2A, a channel layer 110 and a barrier layer 120 are sequentially formed on a substrate 10. The substrate 10 is a silicon substrate, sapphire substrate, silicon carbide substrate, diamond substrate, gallium nitride substrate, or gallium arsenide substrate. The channel layer 110 is formed on the substrate 10. The cover layer 120 is formed on the channel layer 110. A source electrode 130 and a drain electrode 140 are located on the channel layer 110. The channel layer 110 is connected to the source electrode 130 and the drain electrode 140. In a specific embodiment, there is an additional barrier layer (not shown) between the cover layer 120 and the channel layer 110. The lattice constant of the aforementioned barrier layer is usually smaller than that of the channel layer 110. In this embodiment, the material of the channel layer and the barrier layer includes aluminum indium gallium nitride (AlxInyGa(1-xy)N), with 0≦x<1 and 0≦x+y≦1. In this embodiment, the channel layer 110 is a gallium nitride layer, the barrier layer is an aluminum gallium nitride layer or an indium gallium nitride layer, and the cover layer material includes, but is not limited to, highly doped gallium nitride (GaN). The channel layer 110 forms low-resistance ohmic contact with the direct source and drain electrodes. The channel layer 110 and the barrier layer undergo spontaneous polarization and piezoelectric polarization, thereby forming a two-dimensional electron gas (2DEG) at the heterogeneous junction interface between the channel layer 110 and the barrier layer.

[0026] The source electrode 130 and drain electrode 140 are formed on a barrier layer by a metal deposition process, and ohmic contact is formed by high-temperature treatment. The alloy material is one or a combination selected from the group consisting of titanium, aluminum, nickel, molybdenum, titanium nitride, and gold. Specifically, the source electrode and drain electrode have structures such as titanium / aluminum / nickel / gold, titanium / aluminum / titanium / gold, titanium / aluminum / molybdenum / gold, and titanium / aluminum / titanium / titanium nitride, but are not limited to these. On the other hand, the structural design of the channel layer 110 changes according to the requirements of the device. For example, the semiconductor structure of the present invention is applicable to p-type doped gallium nitride normally-off high electron mobility transistors (pGaN E-mode HEMTs), p-type doped gallium nitride normally-on high electron mobility transistors (pGaN D-mode HEMTs), normally-off HEMT elements with a recess gate structure, normally-off HEMT elements with fluorine ion doping (F Implant), or enhancement and depletion integrated circuits (E / D-mode ICs).

[0027] As shown in Figure 2B, the first block layer 150 is then deposited, covering the channel layer 110, the cover layer 120, the source electrode 130, and the drain electrode 140. The material of this first block layer is, for example, aluminum nitride (AlN), gallium oxide (Ga2O3), or aluminum oxide (Al2O3), but is not limited to these. Subsequently, as shown in Figure 2C, a first dielectric layer 151 is deposited to cover the first block layer 150. The material of this first dielectric layer is, for example, silicon nitride (SiN), silicon oxide (SiO2), silicon oxide nitride (SiON), or silicon carbide (SiC), but is not limited to these. The present invention selects specific compositional materials for the block layer and dielectric layer, so that the first dielectric layer has a high etching selectivity ratio with respect to the first block layer. Preferably, this etching selectivity ratio is greater than 100, which reduces the number of times masks are used in subsequent processes. This design eliminates the need for contact hole structures required for electrical connections between electrodes and field plates and between adjacent field plates. Details are provided below.

[0028] As shown in Figures 2D and 2E, the second block layer 152 is then deposited to cover the first dielectric layer 151, and the second dielectric layer 153 is then deposited to cover the second block layer 152. The compositional materials of the second block layer and the first block layer are the same. Similarly, the compositional materials of the second dielectric layer and the first dielectric layer are also the same. Therefore, the second dielectric layer has a high etching selectivity ratio greater than 100, similar to that of the second block layer. In this embodiment, two sets of composite layer structures are employed. One set consists of the first block layer and the first dielectric layer. The other set consists of the second block layer and the second dielectric layer. However, it is not limited to this. In practice, the number of composite layers composed of block layers and dielectric layers varies depending on the number of layers in the field plate.

[0029] Figures 2F and 2G show the start of the patterned etching process for each layer. First, a patterned first photoresist layer HM1 is formed on the second dielectric layer 153. This patterned first photoresist layer HM1 is used as an etching mask to etch a portion of the second dielectric layer 153. As shown in Figure 2G, due to the high etching selectivity ratio of the dielectric layer and the block layer, this etching stops at the second block layer 152.

[0030] As shown in Figures 2H and 2I, the first photoresist layer HM1 is then removed, and a portion of the second block layer 152 is etched away using the patterned second dielectric layer 153 as an etching mask, thereby exposing a portion of the surface of the first dielectric layer 151. Subsequently, as shown in Figures 2J and 2K, a second patterning etching process is performed in the aforementioned patterned opening region. Specifically, a patterned second photoresist layer HM2 is formed on the patterned second dielectric layer 153 and the exposed portion of the first dielectric layer 151. This patterned second photoresist layer HM2 is used as an etching mask to etch a portion of the first dielectric layer 151. Due to the high etching selectivity of this dielectric layer and block layer, the second patterning etching stops at the first block layer 150, as shown in Figure 2K.

[0031] As shown in Figures 2L and 2M, after removing the second photoresist layer HM2, the patterned first dielectric layer 151 is used as an etching mask to etch away a portion of the first block layer 150, exposing a portion of the surface of the cover layer 120. Then, referring to Figure 2N, a patterned third photoresist layer HM3 is formed on the exposed second dielectric layer 153, thereby defining the shape of the uppermost field plate structure. Figure 2N shows that the first block layer 150 and the first dielectric layer 151 have a first opening with a first dimension CD1 formed by two patterning etching processes. The patterning etching process forms a second opening with a second dimension CD2 in the second block layer 152 and the second dielectric layer 153. The third photoresist layer HM3 has a third opening with a third dimension CD3. These three opening dimensions increase sequentially from bottom to top with each layer. The first dimension CD1 of the first opening is smaller than the second dimension CD2 of the second opening. The second dimension CD2 of the second opening is smaller than the third dimension CD3 of the third opening. The shape of the subsequent gate and field plate structures is based on this three-layer opening structure, which is described in detail below.

[0032] Next, a metal deposition process is carried out to form a thin metal film in the aforementioned three layers of openings at once. As shown in Figure 2O, the thin metal film formed in the aforementioned three layers of openings has a continuous stepped structure 160. A characteristic of this continuous stepped structure 160 is that the "step" structure of each layer "partially overlaps and connects" with the "steps" above and below it. The aforementioned "partially overlapping and connecting" means that they are partially directly in contact and connected, and no intermediate structures such as contact holes (vias) are provided. Specifically, this continuous stepped structure 160 has a gate electrode 162 and a plurality of field plates 164. A portion of the gate electrode 162 forms physical and electrical connections with the plurality of field plates 164.

[0033] More specifically, in this embodiment, as shown in Figure 2P, the first block layer 150 and the first dielectric layer 151 define the shape of the gate electrode 162. Furthermore, the multiple field plates 164 include the first field plate 1641 and the second field plate 1642. The second block layer 152 and the second dielectric layer 153 define the shape of the first field plate 1641. Furthermore, the patterned third photoresist layer HM3 defines the shape of the second field plate 1642. That is, the first dimension CD1, the second dimension CD2, and the third dimension CD3 are the maximum lateral dimensions of the gate electrode 162, the first field plate 1641, and the second field plate 1642, respectively. <CD2<CD3である。

[0034] As described above, the gate electrode 162 and the multiple field plates 164 of the present invention are formed in one step by a metal deposition process. The gate electrode 162 and the first field plate 1641 are "partially overlapping and connected". That is, a portion of the side surface of the gate electrode is directly physically in contact with and connected to the side surface of the upper adjacent first field plate 1641. Similarly, the first field plate 1641 and the second field plate 1642 are "partially overlapping and connected". That is, a portion of the side surface of the first field plate 1641 is directly physically in contact with and connected to the upper adjacent second field plate 1642. Overall, the continuous stepped structure 160 is stepped in shape, extending upward and outward from the bottom layer by layer. This differs from the conventional arrangement of bridging structures such as contact holes in multiple field plate structures. In particular, since the gate and multiple field plates of the present invention form a continuous stepped structure and there are no bridging structures between each layer structure, there is no need to "insert" dielectric layers in between. Therefore, in power elements such as HEMTs that utilize the structure of the present invention, the thickness of the dielectric layer can be reduced, the potential gradient can be controlled to mitigate electric field concentration phenomena, and dynamic resistance changes can be suppressed.

[0035] In the semiconductor structure 1 described above, the continuous stepped structure 160 is explained using the gate electrode and its multiple field plate structures as examples. However, the scope of application of the continuous stepped structure and its manufacturing method disclosed in this invention is not limited thereto. Substantially, depending on the requirement for suppressing the dynamic resistance of the power element, the continuous stepped structure can be applied to other electrode structures, such as source electrodes and / or drain electrodes. By employing a continuous stepped design without contact holes in these electrodes, mask exposure time can be saved and manufacturing costs can be reduced.

[0036] Figure 3 shows a schematic diagram of the manufacturing process of the semiconductor structure of the present invention. First, in step S01, a channel layer is formed on top of the substrate. Next, in step S02, an electrode and a plurality of field plates are formed simultaneously on top of the channel layer. The plurality of field plates are electrically connected to the electrode. The plurality of field plates have at least one first field plate and a second field plate. The first field plate partially overlaps with and is connected to the electrode. The second field plate partially overlaps with and is connected to the first field plate. The electrode and the plurality of field plates form a continuous stepped structure. Partially overlapping and connected means that they are partially directly in contact and connected, with no intermediate structures.

[0037] The above-described embodiments illustrate embodiments of the present invention and describe the characteristic configuration of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the claims. [Explanation of Symbols]

[0038] 1. Semiconductor structure 10 circuit boards 110 channel layer 120 Cover layer 130 Source Electrodes 140 Drain electrode 150 Block Layer 1 151 First Dielectric Layer 152 Second Block Layer 153 Second Dielectric Layer 160 Continuous stepped structure 162 Shuttle gate 164 Multiple field plates 1641 First Field Plate 1642 Field Plate No. 2 CD1 First Dimension CD2 Second Dimension CD3 Third Dimension FP1 1st Field Plate FP2 Second Field Plate FP3 Third Field Plate GM gate metal HM1 First photoresist layer HM2 Second Photoresist Layer HM3 Third photoresist layer V1 Contact Hole V2 Contact Hole V3 Contact Hole

Claims

1. It is a semiconductor structure, circuit board and A channel layer is installed above the aforementioned substrate, An electrode placed above the channel layer, The electrode is electrically connected to a plurality of field plates, each having at least one first field plate and a second field plate, The first field plate partially overlaps with and connects to the electrode, and the second field plate partially overlaps with and connects to the first field plate. The electrodes and the plurality of field plates form a continuous stepped structure. The aforementioned "partially overlapping and connected" refers to a semiconductor structure in which parts are partially directly in contact and connected, without any intermediate structures.

2. The semiconductor structure according to claim 1, characterized in that the electrode is a gate electrode, a source electrode, or a drain electrode.

3. The first block layer and the first dielectric layer are further included. The first dielectric layer covers the first block layer, The semiconductor structure according to claim 1, characterized in that the first block layer and the first dielectric layer define the shape of the electrode.

4. The second block layer and the second dielectric layer are further included. The second dielectric layer covers the second block layer, The second block layer covers the first dielectric layer, The semiconductor structure according to claim 3, characterized in that the second block layer and the second dielectric layer define the shape of the first field plate.

5. The first block layer and the first dielectric layer define a first dimension, The second block layer and the second dielectric layer define a second dimension, The first dimension is smaller than the second dimension. The semiconductor structure according to claim 4, characterized in that the first dimension and the second dimension are the maximum lateral dimensions of the electrode and the first field plate, respectively.

6. The first block layer and the second block layer are made of aluminum nitride (AlN) and gallium oxide (Ga ２ O ３ ) layer, or aluminum oxide (Al ２ O ３ The semiconductor structure according to claim 4, characterized in that it is a layer.

7. The first dielectric layer and the second dielectric layer are silicon nitride (SiN) layer and silicon oxide (SiO ２ The semiconductor structure according to claim 4, characterized in that it is a ) layer, a silicon nitride (SiON) layer, or a silicon carbide (SiC) layer.

8. The semiconductor structure according to claim 1, characterized in that the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a diamond substrate, or a gallium nitride substrate.

9. A method for manufacturing a semiconductor structure, A process of forming a channel layer above the substrate, The process includes a step of forming electrodes and a plurality of field plates simultaneously above the channel layer, The plurality of field plates are electrically connected to the electrodes, The plurality of field plates each have at least one first field plate and a second field plate. The first field plate partially overlaps with and is connected to the electrode. The second field plate partially overlaps and connects with the first field plate. The electrodes and the plurality of field plates form a continuous stepped structure. The aforementioned partial overlap and connection refers to a method for manufacturing semiconductor structures in which the components are partially directly in contact and connected, without any intermediate structures.

10. The step of forming the electrode and the plurality of field plates is: A step of sequentially forming a first block layer and a first dielectric layer above the channel layer, A step of sequentially forming a second block layer and a second dielectric layer above the first dielectric layer, The process involves pattern etching the second dielectric layer, stopping the etching at the second block layer, thereby exposing a portion of the second block layer, A step of removing the exposed portion of the second block layer, thereby exposing a part of the first dielectric layer, The process involves pattern etching the first dielectric layer, stopping the etching at the first block layer, thereby exposing a portion of the first block layer, A step of removing the exposed portion of the first block layer, The process includes depositing a metal to cover a portion of the channel layer, a portion of the first dielectric layer, and a portion of the second dielectric layer, thereby forming the electrode and the plurality of field plates at once. The first block layer and the first dielectric layer define the shape of the electrode, The method for manufacturing a semiconductor structure according to claim 9, characterized in that the second block layer and the second dielectric layer define the shape of the first field plate.

11. The first dimension is defined by the steps of pattern etching the first dielectric layer and removing the exposed portion of the first block layer. The second dimension is defined by the steps of pattern etching the second dielectric layer and removing the exposed portion of the second block layer. The first dimension is smaller than the second dimension. The method for manufacturing a semiconductor structure according to claim 10, characterized in that the first dimension and the second dimension are the maximum lateral dimensions of the electrode and the first field plate, respectively.

12. The first block layer and the second block layer are an aluminum nitride (AlN) layer, a gallium oxide (Ga ２ O ３ ), or an aluminum oxide (Al ２ O ３ ), and the method for manufacturing a semiconductor structure according to claim 10 is characterized in that.

13. The first dielectric layer and the second dielectric layer are silicon nitride (SiN) layer and silicon oxide (SiO ２ A method for manufacturing a semiconductor structure according to claim 10, characterized in that the layer is a silicon nitride (SiON) layer, a silicon carbide (SiC) layer, or a silicon carbide (SiC) layer.

14. The method for manufacturing a semiconductor structure according to claim 10, characterized in that the etching selectivity ratio of the first dielectric layer and the second dielectric layer with respect to the first block layer and the second block layer is greater than 100.

15. The method for manufacturing a semiconductor structure according to claim 9, characterized in that the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a diamond substrate, or a gallium nitride substrate.

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