Semiconductor equipment
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- FUJI ELECTRIC CO LTD
- Filing Date
- 2025-09-29
- Publication Date
- 2026-06-23
Smart Images
Figure 2026102424000001_ABST
Abstract
Claims
1. A semiconductor substrate having an upper surface and a lower surface, A first conductivity type drift region provided on the semiconductor substrate, A gate trench portion having a gate conductive portion provided on the upper surface side of the semiconductor substrate and located inside the semiconductor substrate, and a gate insulating film that insulates the gate conductive portion and the semiconductor substrate, Adjacent trench portions arranged alongside the gate trench portion in the direction of arrangement, A second conductive base region is provided in the mesa region, which is the region sandwiched between the gate trench and the adjacent trench, Equipped with, The first end, which is the lower end of the base region in contact with the gate insulating film, is positioned deeper than the second end, which is the lower end of the central base region in the arrangement direction of the mesa portion. Semiconductor equipment.
2. The distance in the depth direction between the first end and the second end is 0.1 μm or more. The semiconductor device according to claim 1.
3. The distance in the depth direction between the first end and the second end is 1.0 μm or less. The semiconductor device according to claim 1.
4. The mesa portion includes a first conductivity type emitter region provided between the base region and the upper surface of the semiconductor substrate, The distance from the lower end of the emitter region in contact with the gate insulating film to the first end is greater than the distance from the lower end of the central emitter region in the arrangement direction of the mesa to the second end. The semiconductor device according to claim 1.
5. The shape of the lower surface of the base region in the aforementioned arrangement direction is a curved surface that is convex toward the upper surface of the semiconductor substrate. The semiconductor device according to claim 1.
6. It comprises a second conductive trench bottom region provided separately from the base region and in contact with the lower end of the gate trench portion. The semiconductor device according to any one of claims 1 to 5.
7. The upper end of the trench bottom region in contact with the gate insulating film is located on the upper surface side of the semiconductor substrate, more so than the upper end of the central trench bottom region in the arrangement direction of the mesa portion. The semiconductor device according to claim 6.
8. The thickness of the trench bottom region in contact with the gate insulating film is greater than the thickness of the trench bottom region in the center of the mesa portion in the arrangement direction. The semiconductor device according to claim 7.
9. The upper end of the trench bottom region includes a first curved surface that is convex toward the lower surface side of the semiconductor substrate toward the gate insulating film in the arrangement direction. The semiconductor device according to claim 6.
10. The upper end of the trench bottom region includes a second curved surface that is convex toward the upper surface of the semiconductor substrate in the arrangement direction. The semiconductor device according to claim 9.
11. The upper end of the trench bottom region includes, in the arrangement direction, the first curved surface, the second curved surface, and the third curved surface convex toward the lower surface of the semiconductor substrate, in order from the gate insulating film toward the adjacent trench portion. The semiconductor device according to claim 10.
12. The trench bottom region is in contact with the adjacent trench portion, and the upper end of the trench bottom region includes a fourth curved surface that is convex toward the lower surface side of the semiconductor substrate toward the adjacent trench portion in the arrangement direction. The semiconductor device according to claim 9.
13. A second conductive discrete trench bottom region is provided, which is in contact with the lower end of the adjacent trench portion and separated from the base region and the trench bottom region. The upper end of the discrete trench bottom region includes a fourth curved surface that, in the arrangement direction, is convex toward the lower surface side of the semiconductor substrate toward the adjacent trench portion. The semiconductor device according to claim 9.
14. The upper end of the trench bottom region includes the third curved surface in the center of the mesa portion in the direction of arrangement. The semiconductor device according to claim 11.
15. The upper end of the trench bottom region includes the third curved surface on the side of the adjacent trench portion rather than the center of the mesa portion in the direction of arrangement. The semiconductor device according to claim 11.
16. The upper end of the trench bottom region includes the third curved surface below the adjacent trench portion. The semiconductor device according to claim 11.
17. The semiconductor substrate contains antimony as a bulk dopant. The semiconductor device according to any one of claims 1 to 5.
18. The gate insulating film includes the bulk dopant. The semiconductor device according to claim 17.
19. The chemical concentration of the bulk dopant in the gate insulating film at the first position in contact with the semiconductor substrate is higher than the chemical concentration of the bulk dopant in the gate insulating film at the second position, which is further from the semiconductor substrate than the first position. The semiconductor device according to claim 18.
20. In the semiconductor substrate, the chemical concentration of the bulk dopant in the drift region is higher than the chemical concentration of the bulk dopant at the location in contact with the gate insulating film. The semiconductor device according to claim 18.