Semiconductor equipment

Abstract

To provide a semiconductor device with high voltage resistance. [Solution] The semiconductor device includes an oxide insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer on top of the oxide insulating layer, a gate insulating layer in contact with the oxide semiconductor layer on top of the oxide semiconductor layer, and a gate electrode on the gate insulating layer, wherein the thickness of the gate insulating layer is 200 nm or more, the oxide semiconductor layer includes a first region containing impurity elements that does not overlap with the gate electrode in the thickness direction, the gate insulating layer includes a second region containing impurity elements that overlaps with the first region in the thickness direction, the concentration profile of the impurity elements in the thickness direction has a peak in the second region, and the concentration of impurity elements on the oxide insulating layer side surface of the first region is 5 × 10 18 cm -3 The following is true, and the concentration of impurity elements on the gate insulating layer side surface of the first region is 5 × 10 19 cm -3 That's all.

Claims

1. Oxide insulating layer, On the oxide insulating layer, an oxide semiconductor layer in contact with the oxide insulating layer, On the oxide semiconductor layer, a gate insulating layer in contact with the oxide semiconductor layer, The gate electrode on the gate insulating layer, The thickness of the gate insulating layer is 200 nm or more. The oxide semiconductor layer includes a first region containing impurity elements that does not overlap with the gate electrode in the film thickness direction. The gate insulating layer includes a second region containing the impurity element that overlaps with the first region in the film thickness direction. The concentration profile of the impurity element in the film thickness direction has a peak in the second region. The concentration of the impurity element on the surface of the first region on the oxide insulating layer side is 5 × 10 １８ cm －３ The following: The concentration of the impurity element on the gate insulating layer side surface of the first region is 5 × 10 １９ cm －３ That concludes the semiconductor device.

2. The semiconductor device according to claim 1, wherein the peak is located within 50 nm from the interface between the oxide semiconductor layer and the gate insulating layer.

3. The semiconductor device according to claim 1, wherein the thickness of the oxide semiconductor layer is 10 nm or more and 50 nm or less.

4. The sheet resistance of the first region is 1 × 10 ４ The semiconductor device according to claim 3, wherein the Ω / sq. is less than or equal to Ω.

5. Furthermore, it includes a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer, The semiconductor device according to claim 1, wherein when a voltage of 5V is applied to the gate electrode of the semiconductor device having a channel length of 3 μm, the breakdown voltage between the source electrode and the drain electrode is 30V or more.

6. The semiconductor device according to any one of claims 1 to 5, wherein the impurity element is one selected from the group consisting of boron, phosphorus, argon, and nitrogen.

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