Mask, integrated circuit element, and method for adjusting the threshold voltage of the integrated circuit element using the mask.

Abstract

The present invention provides a mask used to adjust the threshold voltage of an integrated circuit element, an integrated circuit element, and a method for adjusting the threshold voltage of the integrated circuit element using the mask. [Solution] The mask according to the present invention comprises a plurality of logic cell regions corresponding to the positions in which a plurality of logic cells of the integrated circuit element to be manufactured are arranged, and a plurality of switch cell regions interposed between the plurality of logic cell regions or arranged to surround at least one logic cell region among the plurality of logic cell regions, wherein each of the plurality of switch cell regions is electrically isolated from each of the plurality of logic cell regions, and the mask, when placed on top of the integrated circuit element to be manufactured, includes a first opening corresponding to a selected logic cell region among the plurality of logic cell regions and a second opening in at least one logic cell region among the plurality of switch cell regions.

Description

Technical Field

[0001] The present invention relates to a mask, an integrated circuit element, and a method for adjusting the threshold voltage (threshold voltage: Vt) of the integrated circuit element using the mask. In particular, the present invention relates to a doping process for adjusting the threshold voltage of an integrated circuit element, a mask and an integrated circuit element used therefor, and a method for adjusting the threshold voltage of the integrated circuit element using the mask.

Background Art

[0002] Integrated circuits are designed based on standard cells. Specifically, by arranging standard cells according to data defining an integrated circuit and routing the arranged standard cells, a layout of the integrated circuit is generated. Such standard cells are pre-designed and stored in a cell library.

[0003] With the miniaturization of the manufacturing process, the size of patterns in standard cells has been reduced, and the size of standard cells has also been reduced. When the size of patterns in standard cells and the size of standard cells are reduced, it becomes difficult to accurately adjust the threshold voltage of a transistor composed of a gate structure and an active region to be adjusted in the doping process for adjusting the threshold voltage, resulting in a problem of reduced reliability.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the problems in the conventional integrated circuit elements described above, and the object of the present invention is to provide a mask used to adjust the threshold voltage of an integrated circuit element, that is, to provide a mask that can adjust the threshold voltage of a target transistor (hereinafter referred to as the "target transistor") with relatively accurate precision, to provide an integrated circuit element in which the threshold voltage has been adjusted using this mask, and to provide a method for adjusting the threshold voltage of an integrated circuit element using this mask. [Means for solving the problem]

[0005] To achieve the above objective, the present invention provides a mask comprising: a plurality of logic cell regions corresponding to the positions where a plurality of logic cells of a manufactured integrated circuit element are arranged; a plurality of switch cell regions interposed between the plurality of logic cell regions or arranged to surround at least one logic cell region among the plurality of logic cell regions, wherein each of the plurality of switch cell regions is electrically isolated from each of the plurality of logic cell regions; and the mask, when placed on top of the manufactured integrated circuit element, includes a first opening corresponding to a selected logic cell region among the plurality of logic cell regions and a second opening in at least one logic cell region among the plurality of switch cell regions.

[0006] To achieve the above objective, the integrated circuit element according to the present invention comprises: a plurality of logic cell regions on which logic cells are formed; a switch cell region interposed between the plurality of logic cell regions or arranged to surround the plurality of logic cell regions; a plurality of power rails extending in a first horizontal direction on the plurality of logic cell regions and the switch cell region to which a power supply voltage is applied; a plurality of first gate structures extending in a second horizontal direction that is spaced apart from each other in the first horizontal direction and intersects the first horizontal direction on any one selected logic cell region among the plurality of logic cell regions; and a plurality of second gate structures extending in the second horizontal direction that is spaced apart from each other in the first horizontal direction on the switch cell region, wherein the switch cell region includes a break region electrically isolated from the logic cell region, and the first transistor controlled by the plurality of first gate structures has a different threshold voltage (Vt) than the second transistor controlled by the plurality of second gate structures.

[0007] A threshold voltage adjustment method according to the present invention, made to achieve the above objective, is a method for controlling the threshold voltage of a plurality of transistors in a manufactured device, wherein the manufactured device comprises a plurality of logic cell regions in which logic cells are formed, an active cell region in which an active cell is formed, and a first dummy cell region adjacent to a first logic cell region among the plurality of logic cell regions and adjacent to the active cell region, wherein the first dummy cell region includes a break region electrically isolated from each of the plurality of logic cell regions, the logic cell has a first width in a first direction, the active cell has a second width smaller than the first width in a first direction, and the first dummy cell region is adjacent to the active cell region in a first direction, and the method for controlling the threshold voltage is: The process is characterized by: placing the device under manufacture, which will be formed as the device to be manufactured, into a process chamber; performing a first doping process on the device under manufacture using a first mask having a device region corresponding to the region of the device to be manufactured, and including an opening that exposes the device region corresponding to the active cell, the device region corresponding to the first dummy cell region, and the device region corresponding to the first logic cell region; and performing a second doping process on the device under manufacture using a second mask including an opening that exposes the device region corresponding to the active cell, the device region corresponding to the first dummy cell region, and covers the device region corresponding to the first logic cell region. [Effects of the Invention]

[0008] According to the mask and integrated circuit element of the present invention, and the method for adjusting the threshold voltage of the integrated circuit element using the mask, in order to adjust the threshold voltage of a standard cell of the integrated circuit element, the first mask includes an opening that exposes adjacent cells, a first standard cell, and a signal tap cell of the device under manufacture and covers the second standard cell, and the second and third masks each include an opening that exposes adjacent cells and a signal tap cell of the device under manufacture and covers the first standard cell and the second standard cell, respectively, and the opening exposes one or more components in the respective cell region corresponding to the cell, thereby sequentially proceeding with the first doping step with the first mask in place, the second doping step with the second mask in place, and the third doping step with the third mask in place, and the first to third doping steps are performed, for example, with different dopant amounts. To embody the desired threshold voltage, a cell requires a mask opening of a specific size. However, even adjacent cells that do not have the required mask opening width can still embody the threshold voltage. This is because the mask is designed to expose both adjacent cells and signal tap cells, allowing for relatively precise adjustment of the threshold voltage of the target transistor. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows a schematic configuration of an integrated circuit element according to an embodiment of the present invention. [Figure 2] This is a diagram illustrating a mask according to an embodiment of the present invention. [Figure 3] This figure shows a schematic configuration of an integrated circuit element according to an embodiment of the present invention. [Figure 4A] This is a cross-sectional view taken along the line A1-A1 in Figure 3. [Figure 4B] This is a cross-sectional view taken along the line A2-A2 in Figure 3. [Figure 5] Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 6]Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 7] Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 8] Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 9] Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 10] Figure 3 illustrates the mask used to adjust the threshold voltage of the integrated circuit element shown in the diagram. [Figure 11] This figure shows a schematic configuration of an integrated circuit element according to another embodiment of the present invention. [Figure 12] This is a cross-sectional view taken along line BB in Figure 11. [Figure 13] Figure 11 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 14] Figure 11 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 15] Figure 11 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 16] This figure shows a schematic configuration of an integrated circuit element according to another embodiment of the present invention. [Figure 17] Figure 16 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 18] Figure 16 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 19] Figure 16 is a diagram illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown. [Figure 20] This figure shows a schematic configuration of an integrated circuit element according to another embodiment of the present invention. [Figure 21]It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 20. [Figure 22] It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 20. [Figure 23] It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 20. [Figure 24] It is a diagram showing a schematic configuration of an integrated circuit element according to another embodiment of the present invention. [Figure 25] It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 24. [Figure 26] It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 24. [Figure 27] It is a diagram for explaining a mask used for threshold voltage adjustment of the integrated circuit element shown in FIG. 24.

Embodiments for Carrying Out the Invention

[0010] Next, specific examples of embodiments for implementing the mask, the integrated circuit element according to the present invention, and the method for adjusting the threshold voltage of the integrated circuit element using the mask will be described with reference to the drawings.

[0011] For the same components on the drawings, the same reference numerals are used, and overlapping explanations thereof are omitted. In this specification, the horizontal direction includes a first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect each other. The direction intersecting the first horizontal direction (X direction) and the second horizontal direction (Y direction) is shown as the vertical direction (Z direction). In this specification, the vertical level refers to the height level along the vertical direction (Z direction) of an arbitrary configuration. A component arranged in the +Z direction relative to other components is shown as being above the other components, and a component arranged in the -Z direction relative to other components is shown as being below the other components. Furthermore, the area of ​​a component may refer to the size occupied by the component on a plane parallel to the horizontal plane, and the width of a component refers to the length in the direction perpendicular to the direction in which the component is extended. Furthermore, when components are coupled or electrically connected, these components are simply referred to as connected.

[0012] For the sake of clarity, only some of the layers are shown in the drawings of this specification. Furthermore, patterns composed of conductive materials, such as wiring layer patterns, are referred to as conductive patterns or simply patterns. In this specification, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "top," "bottom," "front," and "rear" are used as convenient expressions to describe the positional relationships between components, as shown in the drawings, for example. Such spatial relative terminology should be interpreted to include not only the orientation shown in the drawing, but also cases where the device is positioned in various directions.

[0013] In this specification, terms such as "first and / or primary first" and "second and / or secondary first" may be used to describe various components, parts, regions, layers, and / or sections, but these terms do not limit the components, parts, regions, layers, and / or sections in question. These terms are illustrative and not limiting; they are simply used as a naming convention to distinguish one component, part, region, layer, or section from another component, part, region, layer, or section. Accordingly, the “first” and / or “primary first” components, parts, regions, layers, or sections described in certain parts of this specification may be referred to as “second” and / or “secondary” components, etc., in other parts of this specification or in claims, and this does not depart from the technical spirit of the present invention. Furthermore, even if certain components are not explicitly referred to as "first," "second," etc., in this specification, it is clear that these terms are used in the claims to distinguish between different components.

[0014] Figure 1 is a diagram showing the schematic configuration of an integrated circuit element 1 according to an embodiment of the present invention, and Figure 2 is a diagram illustrating the mask M according to an embodiment of the present invention. The mask is, for example, a doping mask corresponding to integrated circuit 1, or a doping mask that allows doping in open regions and prevents doping in closed regions. Throughout this specification, "device to be manufactured" means the final device formed using a mask. Therefore, even if the device is not yet completed at a process stage where a mask is used, such as in the photolithography process, the device will be indicated as "device under manufacture."

[0015] Referring to Figures 1 and 2, the integrated circuit 1 includes logic cell regions 3 in which logic cells are formed or to be formed. Logic cell area 3 contains multiple logic cell areas. Furthermore, the integrated circuit 1 includes a switch cell region 5 that is positioned between a plurality of logic cell regions 3 or that surrounds a plurality of logic cell regions 3, and a switch cell is formed in or is formed in the switch cell region 5. The switch cell region 5 includes multiple switch cell regions and an electrically isolated region (break region, hereinafter referred to as the break region) that is isolated from the logic cell region 3.

[0016] More specifically, a device under manufacture may have multiple logic cell regions 3, and each logic cell region 3 may be an integrated circuit that performs a logic function. Furthermore, the device being manufactured may have multiple switch cell regions 5, and each switch cell region 5 includes a switch cell pattern. In Figures 1 and 2, the logic cell area is labeled "Logic Cell," and the switch cell area is labeled "Switch Cell."

[0017] A logic cell includes various semiconductor elements. In one embodiment, the logic cell is a unit that performs a specific function in a memory area, input / output area, etc., according to the purpose of the integrated circuit element 1. In one embodiment, a switch cell is formed on the switch cell region 5. In one embodiment, a switch cell is a cell used to make the pattern density of the layout uniform overall. In one embodiment, the switch cell includes a signal tap cell, a filler cell, and / or a finishing cell. Signal tap cells are specialized cells used to complement signal transmission and electrical characteristics. They are used to stabilize electrical characteristics (e.g., voltage drop, current flow) in specific signal paths and maintain signal integrity.

[0018] A filler cell is an additional region that helps improve the uniformity and functionality of integrated circuit elements by maintaining uniform process conditions across the entire wafer or substrate. Filler cells are cells used to fill the space on integrated circuit elements in order to ensure spacing between standard cells. Of course, filler cells may be electrically isolated (i.e., insulated) from logic cells, so they are configured not to directly affect the function of the element. Furthermore, filler cells, for example, contribute to the formation of more uniform and functionally improved logic cells in the FEOL (front end of line) process. Therefore, a filler cell may include some or all of the components of an operating cell, but may not include any connections for transmitting signals or voltages between the operating cell and other cells. The filler cells mentioned above are dummy cells.

[0019] A finishing cell is a special cell that is positioned on the outer periphery of multiple logic cells and has a structure that terminates the gate electrodes or the active region. For example, a portion of the gate electrode or active region extends beyond the logic cell and terminates in a region that is not connected to other electrically conductive components. A finishing cell is a cell that corresponds to a portion of the manufactured device in which such a terminal region is formed.

[0020] In other embodiments, the switch cell region 5 includes an active gate region where an active gate is formed and a dummy gate region where a dummy gate is formed. As integrated circuit designs become more sophisticated and complex, a significant amount of time and cost is consumed in the layout design of integrated circuit elements. Therefore, methods are being used that involve preparing standard circuits in advance and performing automated design using these cells. One example is a design method that uses standard cells. When using a method that designs layouts using standard cells, elements such as logic gates that are used repeatedly are defined in advance as standard cells, stored in the computer system, and placed in the necessary locations during layout design, thereby reducing the time required for layout design. Standard cells are pre-designed and verified and registered in a computer. By combining these registered cells using computer-aided design (CAD), logical design, placement, wiring, etc., are performed.

[0021] For example, a standard cell contains one or more basic cells and / or one or more complex cells. For example, a basic cell includes an AND gate, an OR gate, a NOR gate, or an inverter. Furthermore, a composite cell consists of a configuration that combines two or more AND gates, OR gates, NOR gates, and inverters, and includes, for example, an OAI (OR / AND / INVERTER) or AOI (AND / OR / INVERTER) structure. Furthermore, a standard cell may also include storage elements such as a master-slave flip-flop and a latch.

[0022] Each standard cell has a constant cell height (for example, the height measured along the vertical axis when viewed in a plan view), and an integrated circuit can be designed by arranging appropriate standard cells in multiple columns. Specifically, when designing an integrated circuit, if standardized cells (or logic circuit blocks) of a certain scale are already stored in a library, the overall circuit can be designed by taking standard cells suitable for the design purpose from the library, arranging them as multiple cells on the chip, and performing optimal routing that minimizes the wiring length in the wiring space between cells. For example, integrated circuits formed within logic cells are designed using a standard cell scheme.

[0023] In one embodiment, the switch cell includes a dummy pattern having a shape and pattern density similar to the pattern placed in the logic cell. Dummy patterns are formed around logic cells and are not electrically connected to the circuits within the logic cells. As a result, the dummy pattern does not perform any direct electrical function for the circuit. Specifically, in the integrated circuit element 1 of this embodiment, the logic cell is designed and arranged based on a standard cell as described above. Furthermore, for example, a switch cell includes a dummy pattern designed and arranged in a standard cell configuration, where the dummy pattern is substantially identical in form and / or pattern density to the pattern of the integrated circuit of the logic cell. However, the configuration of the switch cell is not limited to this, and the pattern, shape, and / or pattern density of the integrated circuit of the logic cell may differ. On the other hand, while Figures 1 and 2 show a configuration in which multiple logic cell regions 3 and multiple switch cell regions 5 are arranged in rows while intersecting each other, the structure of the integrated circuit element 1 in this embodiment is not limited to this. In other words, depending on the electronic device to be realized, cells including logic cells and switch cells can be arranged in various structures and forms.

[0024] The first power rail PR1 and the second power rail PR2 are, for example, paths to which the power supply voltage and reference voltage (e.g., ground voltage) are supplied, respectively. As shown in the figure, the first and second power rails (PR1 and PR2) extend parallel to each other in the first horizontal direction (X direction) and are spaced apart in the second horizontal direction (Y direction). The width W1 of the first power rail PR1 in the second horizontal direction (Y direction), which is perpendicular to the first horizontal direction (X direction), may be set to be different from the width W2 of the second power rail PR2 in the second horizontal direction (Y direction). For example, to compensate for the voltage drop phenomenon caused by increased resistance due to the reduction in power rail size, the width of these power rails is increased, or reinforcing patterns are added to the filler cells, thereby substantially increasing the area of ​​the path through which the current flows.

[0025] At least one cell is placed between the first and second power rails (PR1 and PR2). As mentioned above, each logic cell is a cell that receives voltage from the power rail and performs a specific function within the device, and is based on a standard cell. For example, each logic cell refers to a logic element that performs a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). In other words, each logic cell includes transistors that constitute a logic element and wiring that connects those transistors to each other. In one embodiment, each switch cell functions as a dummy cell, filling the remaining space after the logic cells have been positioned according to the designed circuit. In other words, the switch cell does not perform any function in terms of the circuit.

[0026] In other embodiments, each switch cell includes an active gate that is activated to electrically constitute a transistor, and a dummy gate that does not electrically constitute a transistor around the active gate. This applies to various switch cells shown in Figures 5 through 27, where one of the dummy gates shown in the switch cell is the active gate. The dummy gate is defined as a deactivated gate because it is not supplied with voltage from the first and second power rails (PR1, PR2). Therefore, although a portion of the switch cell contains an active element, the active element does not function because it is electrically isolated from the larger integrated circuit. As a result, at least some of the switch cells are inoperable and are not configured to perform their logical functions correctly. A switch cell is a dummy cell.

[0027] As shown in Figure 2, the mask M according to this embodiment includes a first opening OP1 and a second opening OP2. The first opening OP1 is an opening formed in the mask region corresponding to the selected logic cell region 3 among the multiple logic cell regions 3, and exposes the selected logic cell region 3. The selected logic cell region 3 contains a target transistor whose threshold voltage is to be controlled. The first aperture OP1 exposes the target transistor or a related portion thereof (e.g., the gate dielectric region, the gate region, or the semiconductor region). The second opening OP2 is an opening formed in the mask region corresponding to the switch cell region 5, exposing a layer or component within the switch cell region 5. The first opening OP1 has a width of at least 3 CCP (contacted poly pitch), and the second opening OP2 has a width of at least 1 CCP. For example, the second opening OP2 has a width of approximately 1 CCP to approximately 3 CCP.

[0028] Here, width refers to the width in a specific direction (for example, the X direction). The threshold voltage of the transistor is calculated using the following equation (1). (Math 1) Vt = φms - (Qox + Qd) / Cox + 2φf ... Formula 1 Here, φms is the potential difference between the work function of the metal constituting the gate and the semiconductor constituting the channel, Qox is the fixed charge on the gate oxide film surface, Qd is the positive charge in the ionic layer, Cox is the capacitance per unit area of ​​the gate, and φf represents the potential difference between the intrinsic or intrinsic Fermi level Ei and the Fermi level Ef of the semiconductor. Vt stands for threshold voltage.

[0029] In order to adjust the threshold voltage according to Equation 1, the following method is performed. The first method is to adjust φms. The second is how to adjust Qox. The third method is to adjust φf. For example, the first method can be implemented by doping a semiconductor with ions or by applying a metal having the work function. In other words, by doping semiconductors with ions to increase or decrease their work function, the difference in work function between semiconductors and metals can be made larger or smaller. Furthermore, by using a metal having the aforementioned work function, the difference in work function between semiconductors and metals can be increased or decreased.

[0030] In the second method, this is achieved by increasing or decreasing the value of Qox. According to Equation 1, when the value of Qox decreases, Vth decreases, and when the value of Qox increases, the threshold voltage increases. Furthermore, it is expressed as "Qox = ε0εR / tox", where εR is the dielectric constant of the gate oxide film and tox is the thickness of the gate oxide film. Therefore, if you want to reduce Qox, you can either increase the thickness of the gate oxide film or use a material with a low dielectric constant. In the third method as well, this is achieved by doping the semiconductor with ions. For example, if the semiconductor layer is made of a p-type substrate, the φf can be increased by doping it with arsenic (As).

[0031] In one embodiment, the first opening OP1 is selectively formed or omitted depending on the threshold voltage set in the selected logic cell region 3 and the doping process conditions for controlling the threshold voltage. On the other hand, the second aperture OP2 is always formed during the doping process to control the threshold voltage (for example, it is always used in all masks during the manufacturing process). The constant formation of the second opening OP2 relatively improves the accuracy of the doping process carried out through the first opening OP1. Examples of such improvements in accuracy will be explained in more detail below, for example, in relation to Figures 5 to 7. The switch cell region 5 and mask M will be explained in more detail below.

[0032] Figure 3 is a schematic diagram showing the configuration of an integrated circuit element 10 according to an embodiment of the present invention, Figure 4A is a cross-sectional view taken along the line A1-A1 in Figure 3, and Figure 4B is a cross-sectional view taken along the line A2-A2 in Figure 3. The integrated circuit element 10 includes an adjacent cell 10A, a standard cell 10B, and a signal tap cell STC.

[0033] Adjacent cell 10A is defined as a cell that interposes between signal tap cell STC and standard cell 10B and is positioned around signal tap cell STC. Standard cell 10B is a logic cell. The adjacent cell 10A is an active cell, such as a logic cell or a single-transistor cell. Furthermore, the integrated circuit element 10 includes a plurality of gate structures GS arranged spaced apart from each other in a first horizontal direction (X direction) and extending in a second horizontal direction (Y direction), and a plurality of single diffusion breaks SDB arranged spaced apart from each other in a first horizontal direction (X direction) and extending in a second horizontal direction (Y direction). Multiple single diffusion breaks (SDBs) or one single diffusion break (SDB) are interposed between multiple gate structures (GS). Components placed between single diffusion breaks are isolated from the circuitry within the cell region. Therefore, the region corresponding to the area between two single diffusion breaks is described as the break region. The adjacent cell 10A, the standard cell 10B, and the signal tap cell STC are formed on the substrate 102.

[0034] The substrate 102 is a silicon substrate or SOI (silicon-on-insulator). In contrast, the substrate 102 contains, but is not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The integrated circuit element 10 includes a field-effect transistor having a gate-all-around structure that includes a nanosheet-shaped active region and a gate surrounding the active region. For example, the integrated circuit element 10 includes a multibridge channel FET (MBCFET) element. However, the technical concept of the present invention is not limited thereto, and the integrated circuit element 10 may also include planar FET elements, fin FET elements, and the like.

[0035] The active region FA is positioned to extend along the first horizontal direction (X direction). In one embodiment, the active region FA is a region where a p-type transistor is formed and includes a well region doped with n-type impurities. In other embodiments, the active region FA is a region in which an n-type transistor is formed, and includes, for example, a well region doped with a p-type impurity. The active region FA is a region defined by deep trenches in the substrate 102. For example, the region on the substrate 102 excluding the active region FA is a region where deep trenches are formed. Each of the multiple nanosheet stacks NSS contains a first nanosheet N1 and a second nanosheet N2 that overlap each other perpendicularly (in the Z direction) on the active region FA. Multiple gate lines 160 surround the first nanosheet N1 and the second nanosheet N2 contained in the nanosheet stack NSS, which overlap in the vertical Z direction. As used herein, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of electric current flow. Nanosheets are understood to include nanowires.

[0036] The first nanosheet N1 and the second nanosheet N2 contained in the nanosheet stack NSS each function as channel regions. In one embodiment, the first nanosheet N1 and the second nanosheet N2 each have a thickness selected in the range of about 4 nm to about 6 nm, but are not limited thereto. Here, the thicknesses of the first nanosheet N1 and the second nanosheet N2 refer to their dimensions along the vertical direction (Z direction). In one embodiment, the first nanosheet N1 and the second nanosheet N2 have substantially the same thickness along the vertical direction (Z direction). In other embodiments, at least portions of the first nanosheet N1 and the second nanosheet N2 have different thicknesses along the vertical Z direction. In one embodiment, the first nanosheet N1 and the second nanosheet N2 contained in the nanosheet stack NSS are each composed of a Si layer, a SiGe layer, or a combination thereof. The first nanosheet N1 and the second nanosheet N2 contained in one nanosheet stack NSS have the same or similar size to each other in the first horizontal direction (X direction). In other embodiments, unlike those shown in Figure 4A, at least portions of the first nanosheet N1 and the second nanosheet N2 contained in a single nanosheet stack NSS may have different sizes from each other in the first horizontal direction (X direction). In this embodiment, we have illustrated a case where each of the multiple nanosheet stacks NSS is composed of two nanosheets, but the technical concept of the present invention is not limited thereto. For example, a nanosheet stack NSS contains at least one nanosheet, but the number of nanosheets that make up the nanosheet stack NSS is not particularly limited.

[0037] Each of the multiple gate lines 160 includes a main gate section 160M and multiple sub-gate sections 160S. The main gate section 160M covers the top surface of the nanosheet stack NSS and extends long in the second horizontal direction (Y direction). Multiple subgate portions 160S are integrally connected to the main gate portion 160M, and one subgate portion is positioned between the first nanosheet N1 and the second nanosheet N2, and one subgate portion is positioned between the first nanosheet N1 and the active region FA. In the vertical direction (Z direction), the thickness of each of the multiple subgate sections 160S is smaller than the thickness of the main gate section 160M. Each of the gate lines 160 is composed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal can be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. The metal nitride is selected from TiN and TaN. The metal carbide is TiAlC. However, the materials that make up the multiple gate lines 160 are not limited to these examples.

[0038] A gate dielectric film 152 is interposed between the nanosheet stack NSS and the gate line 160. In one embodiment, the gate dielectric film 152 is composed of a laminated structure of an interface dielectric film and a high-dielectric film. The interface dielectric film can be composed of a low dielectric material film with a dielectric constant of approximately 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In one embodiment, the interface dielectric film may be omitted. High dielectric films can be made of materials with an even higher dielectric constant than silicon oxide films. For example, high dielectric films have a dielectric constant of approximately 10 to 25. High dielectric films are formed from hafnium oxide, but are not limited to this. The gate dielectric film 152 and the gate line 160 constitute the "gate structure GS" in this specification. In one embodiment, the gate dielectric film 152 and the gate line 160 each include portions that overlap with a plurality of nanosheet stacks NSS.

[0039] In one embodiment, multiple transistors are formed in the region where multiple nanosheet stacks NSS, gate line 160, and gate dielectric film 152 overlap. Multiple transistors are nanosheet transistors. In one embodiment, the plurality of transistors include PMOS transistors and NMOS transistors. For example, each of the multiple transistors consists of at least one nanosheet stack NSS, a gate dielectric film 152 and gate line 160 surrounding at least one nanosheet stack NSS, and multiple source / drain regions 130 facing at least one nanosheet stack NSS in the first horizontal direction (X direction). Multiple source / drain regions 130 are arranged between each of the multiple gate lines 160. Each of the multiple source / drain regions 130 is positioned adjacent to at least one gate line 160 selected from among the multiple gate lines 160. Each of the multiple source / drain regions 130 has a surface facing a first nanosheet N1 and a second nanosheet N2 contained in an adjacent nanosheet stack NSS.

[0040] A capping insulating pattern 168 is placed on the gate dielectric film 152 and the gate line 160. Specifically, the capping insulating pattern 168 covers the upper surface of the main gate portion 160M and the upper surface of the portion of the gate dielectric film 152 that surrounds the main gate portion 160M. The capping insulation pattern 168 is made of a silicon nitride film or a silicon oxide film. The gate line 160 and the capping insulation pattern 168, respectively, have their side walls covered by the outer insulation spacers 118. Specifically, the outer insulating spacer 118 covers both side walls of the main gate section 160M on the upper surface of multiple nanosheet stacks NSS. The outer insulating spacer 118 is separated from the gate line 160 via the gate dielectric film 152. The upper surfaces of the multiple source / drain regions 130, the side walls of the multiple outer insulating spacers 118, and the side walls of the capping insulating pattern 168 are covered by the intergate insulating film 144. The intergate insulating film 144 consists of a silicon oxide film, but is not limited to this.

[0041] The single diffusion break (SDB) is placed on the substrate 102. Single Diffusion Break (SDB) separates the active region (FA) into multiple regions. Considering the manufacturing process for forming a single diffusion break (SDB), after at least a portion of the active region (FA) is removed, insulating material is filled into the area where the active region (FA) was removed. This results in the formation of a single diffusion break (SDB). Therefore, a portion of the sidewall of the single diffusion break (SDB) comes into contact with the active region (FA). A single diffusion break (SDB) includes, for example, an insulating material, and is generally described as an insulating layer or isolation layer. While the single diffusion break (SDB) is shown as being single-layered, it is not limited to this.

[0042] Multiple gate structures GS and multiple single diffusion breaks SDB are arranged adjacent to each other in the first horizontal direction (X direction). Multiple gate structures GS and multiple single diffusion breaks SDB are separated from each other by 1 CPP (contacted poly pitch) in the first horizontal direction (X direction). As an example, multiple gate structures GS are separated by a distance of 1CPP. As another example, adjacent gate structures GS and single diffusion breaks SDB are separated by only 1CPP. As yet another example, multiple adjacent single diffusion break (SDB) devices are separated by only 1 CPP (Combined Point Block).

[0043] For example, assuming there are adjacent first and second gate structures, if the distance between the centerline of the first gate structure extending in the second horizontal direction (Y direction) and the centerline of the second gate structure extending in the second horizontal direction (Y direction) is 1 CPP, it means that no other gate structures or single diffusion breaks are placed between the first and second gate structures. Therefore, 1CPP (contacted poly pitch) is understood as the distance between adjacent gate structures in a semiconductor device. Furthermore, when gate structures and single diffusion breaks are arranged regularly at a constant pitch, 1CPP refers to the distance or pitch between adjacent structures within the gate structures and single diffusion breaks, and generally refers to the pitch between equally spaced line patterns that are repeatedly arranged along a first direction and extended in a second direction perpendicular to the first direction. At least a portion of the single diffusion break (SDB) is positioned at the boundary of a standard cell 10B that extends in the second horizontal direction (Y direction), separating adjacent standard cells 10B. Single diffusion breaks (SDBs) are placed not only at the boundaries of standard cell 10B, but also within standard cell 10B. However, in the following description, the single diffusion break (SDB) is assumed to be located at the boundary of a standard cell 10B that extends in the second horizontal direction (Y direction).

[0044] As shown in Figure 4B, the signal tap cell STC includes at least two single diffusion breaks SDBs adjacent to each other in the first horizontal direction (X direction). For example, at least two single diffusion break SDBs include a first single diffusion break SDB and a second single diffusion break SDB. The first single diffusion break (SDB) and the second single diffusion break (SDB) are separated by a back-through electrode (BTV). The back-through electrode BTV is electrically connected to the contact CAS and to a wiring line (not shown) formed on the front surface of the substrate 102. For example, it is electrically connected to a signal line (not shown). The back-through electrode BTV and signal lines (not shown) serve as a signal distribution network.

[0045] In one embodiment, the first and second power rails (PR1, PR2) shown in Figures 1 and 2 (see Figures 1 and 2) are formed on the back surface of the substrate 102. Furthermore, the formation of signal lines (not shown) and power rails (not shown) on the front and back surfaces of the substrate 102, respectively, allows for greater freedom in pattern placement. However, the present invention is not limited thereto. In one embodiment, the standard cell 10B has a minimum width of 3 CPP, and the adjacent cell 10A has a width of 1 CPP or 2 CPP, which is smaller than 3 CPP.

[0046] Figures 5-7 and 8-10 are diagrams illustrating the masks used to adjust the threshold voltage of the integrated circuit elements shown in Figure 3. Specifically, Figures 5 to 7 illustrate the mask used for adjusting the threshold voltage of the first standard cell (10B_1), and Figures 8 to 10 illustrate the mask used for adjusting the threshold voltage of the second standard cell (10B_2). Figures 5-7 and 8-10 are illustrative diagrams illustrating masks used for threshold voltage adjustment. In addition to the masks disclosed in Figures 5-7 and 8-10, a variety of mask shapes and combinations can be employed within the scope of the technical concept of the present invention.

[0047] Referring to Figures 5 to 7, first, the device under manufacture, including the region corresponding to the integrated circuit device shown in Figures 1, 3, 4A, and / or 4B, is placed inside the process chamber. The first mask M1 includes an opening that exposes the adjacent cell 10A, the first standard cell (10B_1), and the signal tap cell STC of the device under manufacture, and covers the second standard cell (10B_2). The second mask M2 and the third mask M3 each include an opening that exposes the adjacent cell 10A and the signal tap cell STC of the device under manufacture, and covers the first standard cell (10B_1) and the second standard cell (10B_2), respectively. The opening exposes one or more components within each cell region corresponding to the cell.

[0048] To adjust the threshold voltage of the first standard cell (10B_1) (for example, the first threshold voltage), the first doping process is carried out sequentially with the first mask M1 in place, the second doping process with the second mask M2 in place, and the third doping process with the third mask M3 in place. The first to third doping steps may be carried out under different process conditions. For example, the dopant amounts are different. In one embodiment, in order to realize a desired threshold voltage, the cell requires a mask opening of a specific size. For example, in order to realize the first threshold voltage, the minimum width of the mask opening used in manufacturing processes such as ion implantation must be at least approximately 3 CPP. In one embodiment, the adjacent cell 10A does not satisfy the width of 3CPP. For example, adjacent cell 10A has a width of approximately 1 CPP to approximately 2 CPP. Nevertheless, the adjacent cell 10A is still able to embody the first threshold voltage, because the masks (M1-M3) are designed to expose both the adjacent cell 10A and the signal tap cell STC.

[0049] Referring to Figures 8 to 10, the first mask M1 includes an opening that exposes the adjacent cell 10A, the second standard cell (10B_2), and the signal tap cell STC, and covers the first standard cell (10B_1). The second mask M2 and the third mask M3 include openings that expose the adjacent cell 10A and the signal tap cell STC, and cover the first standard cell (10B_1) and the second standard cell (10B_2). To adjust the threshold voltage of the second standard cell (10B_2) (for example, the second threshold voltage), the first doping process is carried out sequentially with the first mask M1 in place, the second doping process with the second mask M2 in place, and the third doping process with the third mask M3 in place. The first to third doping processes are carried out under different process conditions. For example, the amount of doping material injected in each doping process is different from the other. Furthermore, the first to third doping processes are carried out under different process conditions than those described above, as shown in Figures 5 to 7. As a result, the adjacent cell 10A can have a second threshold voltage that is different from the first threshold voltage.

[0050] Similar to the above description with respect to Figures 5 to 7, in one embodiment, in order to realize a desired threshold voltage, the cell requires a mask opening of a specific size. For example, in order to realize a second threshold voltage, the minimum width of the mask opening used in manufacturing processes such as ion implantation must be at least approximately 3 CPP. In one embodiment, the adjacent cell 10A does not satisfy the width of 3CPP. For example, adjacent cell 10A has a width of approximately 1 CPP to approximately 2 CPP. Nevertheless, the adjacent cell 10A can still embody the second threshold voltage because the masks (M1-M3) are designed to expose both the adjacent cell 10A and the signal tap cell STC. Furthermore, if it is assumed that the adjacent cell 10A has multiple different threshold voltages (e.g., a first threshold voltage and a second threshold voltage), then it is assumed that the signal tap cell STC also has multiple different threshold voltages (e.g., a first threshold voltage and a second threshold voltage). Therefore, it is assumed that the signal tap cell STC will be exposed through an opening in a mask used in a doping process to control the threshold voltage of different standard cells.

[0051] As can be seen in Figures 5-7 and 8-10, a method for controlling threshold voltages for multiple transistors in a device under manufacture is disclosed. The device to be manufactured includes multiple logic cell regions where logic cells are formed, an active cell region where an active cell is formed, and a first dummy cell region adjacent to the first logic cell region among the multiple logic cell regions, and also adjacent to the active cell region. The first dummy cell region includes a break region that is electrically isolated from each of the multiple logic cell regions. A logic cell has a first width in the first direction, an active cell has a second width in the first direction that is smaller than the first width, and a first dummy cell region is adjacent to the active cell region in the first direction.

[0052] The above method includes the step of placing a device under manufacture, which is to be formed as a device to be manufactured, into a process chamber, wherein the device under manufacture includes device regions corresponding to each region of the device to be manufactured. The above method also includes the step of performing a first doping step on the device under manufacture using a first mask (for example, mask M1 shown in Figure 5). The first mask includes openings that expose device regions corresponding to the active cell, device regions corresponding to the first dummy cell, and device regions corresponding to the first logic cell. Furthermore, the method includes the step of performing a second doping step on the device under manufacture using a second mask (for example, mask M2 shown in Figure 6), the second mask including openings that expose device regions corresponding to the active cell region and the first dummy cell region and cover the device region corresponding to the first logic cell region.

[0053] Figure 11 is a schematic diagram showing the configuration of an integrated circuit element 20 according to another embodiment of the present invention, and Figure 12 is a cross-sectional view taken along line BB in Figure 11. Since the integrated circuit element 20 is constructed similarly to the integrated circuit element 10 described in Figures 3, 4A, and 4B, the following explanation will focus on the differences.

[0054] Referring to Figures 11 and 12, the integrated circuit element 20 includes a standard cell 20A and a filler cell 20B. The filler cell 20B is interposed between multiple standard cells 20A. Furthermore, the integrated circuit element 20 includes a plurality of gate structures GS arranged spaced apart from each other in a first horizontal direction (X direction) and extending in a second horizontal direction (Y direction), and a plurality of single diffusion breaks SDB arranged spaced apart from each other in a first horizontal direction (X direction) and extending in a second horizontal direction (Y direction). Multiple single diffusion breaks (SDBs) are interposed between multiple gate structures (GS). Multiple single diffusion breaks (SDBs) are positioned at the boundary between the standard cell 20A and the filler cell 20B, which extend in the second horizontal direction (Y direction), separating the standard cell 20A from the filler cell 20B.

[0055] As shown in Figure 12, the filler cell 20B includes two single diffusion breaks (SDBs) adjacent to each other in the first horizontal direction (X direction). Between two adjacent single diffusion breaks (SDBs), there is a source / drain region 130 and an intergate insulating film 144 covering the source / drain region 130. The filler cell 20B shown in Figure 12 is illustrative and includes a dummy pattern designed and arranged in the same manner as the standard cell 20A, the dummy pattern having substantially the same shape and / or pattern density as the integrated circuit pattern of the standard cell 20A. To ensure standard cell spacing, filler cells 20B can employ a variety of structures within the range of cells used to fill space on integrated circuit elements. Filler cell 20B forms a boundary with standard cell 20A through a single diffusion break (SDB). Adjacent standard cell 20A and filler cell 20B share a single diffusion break (SDB) at a common boundary.

[0056] Figures 13 to 15 illustrate the mask used to adjust the threshold voltage of the integrated circuit element shown in Figure 11. Figures 13 to 15 are illustrative diagrams illustrating masks used for threshold voltage adjustment. In addition to the masks disclosed in Figures 13 to 15, a variety of mask shapes and combinations can be employed within the scope of the technical concept of the present invention.

[0057] Referring to Figures 13 to 15, the first mask M1 includes an opening that exposes the first standard cell (20A_1) and filler cell 20B of the device under manufacture and covers the second standard cell (20A_2). Furthermore, the second mask M2 and the third mask M3 each include openings that expose the filler cell 20B of the device under manufacture and cover the first standard cell (20A_1) and the second standard cell (20A_2), respectively. To adjust the threshold voltage of the first standard cell (20A_1) (for example, the first threshold voltage), the first doping process is carried out sequentially with the first mask M1 in place, the second doping process with the second mask M2 in place, and the third doping process with the third mask M3 in place. As a result, the first standard cell (20A_1) has a first threshold voltage, and the filler cell 20B has a second threshold voltage that is different from the first threshold voltage.

[0058] In one embodiment, the filler cell 20B having the structure shown in Figure 12 includes a material having a different dipole characteristic than the first standard cell (20A_1). For example, filler cell 20B contains a low work function dipole (LWD) forming material to reduce the work function, while the first standard cell (20A_1) contains a high work function dipole (HWD) forming material to increase the work function. In other embodiments, unlike the example shown in Figure 12, the filler cell 20B includes a field-effect transistor in a gate-all-around (GAA) structure having an active region in the form of a nanosheet and a gate surrounding the active region, similar to the first standard cell (20A_1) or the second standard cell (20A_2). For example, the filler cell 20B includes a structure in which a source / drain region 130 interposed between multiple single diffusion breaks (SDBs) is connected to a gate structure GS.

[0059] Filler cell 20B contains different materials than the first standard cell (20A_1). Alternatively, even if composed of the same materials, the amount of doping material may differ, or it may have a different threshold voltage than the first standard cell (20A_1). In other words, filler cell 20B may differ from the first standard cell (20A_1) in any combination of these three characteristics (material, doping amount, threshold voltage). This leads to the understanding that filler cell 20B is exposed through an opening in the mask used in the doping process to control the threshold voltage of the first standard cell (20A_1). The filler cell 20B is included in the integrated circuit element and is processed according to a doping process using mask M, which may affect the deposition and / or operation of other operating components of the integrated circuit element.

[0060] Figure 16 shows a schematic configuration of an integrated circuit element 30 according to another embodiment of the present invention. Since the integrated circuit element 30 is constructed similarly to the integrated circuit element 10 described in Figures 3, 4A, and 4B, the following explanation will focus on the differences. Referring to Figure 16, the integrated circuit element 30 includes a plurality of finishing cells 30A and a plurality of standard cells 30B surrounded by the plurality of finishing cells 30A in the second horizontal direction (Y direction). In one embodiment, a plurality of finishing cells 30A include dummy gates DG, and a plurality of standard cells 30B include active gates AG.

[0061] Multiple finishing cells 30A are arranged on the outer edges of multiple standard cells 30B in the second horizontal direction (Y direction) and have a structure that terminates the gate structure GS which extends in the second horizontal direction (Y direction). Multiple gate structures GS and multiple single diffusion breaks SDB are spaced apart by a distance of 1 CPP in the first horizontal direction (X direction), with two gate structures GS arranged in the first horizontal direction (X direction), followed by one single diffusion break SDB. In other words, two gate structures GS are placed between two adjacent single diffusion break SDBs, and the distance between the two adjacent single diffusion break SDBs is 3CPP. The integrated circuit element 30 includes a cell separation film IS that extends in a first horizontal direction (X direction) along the boundaries of a plurality of finishing cells 30A and a plurality of standard cells 30B. The cell separation membrane IS contains insulating material and fills deep trenches that partition the active region FA. The cell separation membrane IS defines a gate structure GS or a single diffusion break SDB at the cell boundary. The cell separation membrane IS is in contact with the gate structure GS and the single diffusion break SDB. The cell separation membrane IS is in contact with one end of the gate structure GS and one end of the single diffusion break SDB, which are extended in the first horizontal direction (X direction).

[0062] Figures 17 to 19 are diagrams illustrating the mask used to adjust the threshold voltage of the integrated circuit element 30 shown in Figure 16. Figures 17 to 19 are illustrative diagrams illustrating masks used for threshold voltage adjustment. In addition to the masks disclosed in Figures 17 to 19, a variety of mask shapes and combinations can be employed within the scope of the technical concept of the present invention. Referring to Figures 17 to 19, the first mask M1 includes openings that expose a plurality of finishing cells 30A and a plurality of standard cells 30B and cover the remaining areas, while the second mask M2 and the third mask M3 also include openings that expose a plurality of finishing cells 30A and cover a plurality of standard cells 30B and the remaining areas.

[0063] To adjust the threshold voltages (e.g., the second threshold voltage) of multiple standard cells 30B, the first doping process is carried out sequentially with the first mask M1 in place, the second doping process with the second mask M2 in place, and the third doping process with the third mask M3 in place. As a result, multiple finishing cells 30A can have a first threshold voltage, and multiple standard cells 30B can have a second threshold voltage that is different from the first threshold voltage. In other words, the multiple finishing cells 30A include materials having different dipole properties or quantities than the multiple standard cells 30B. It can be seen that multiple finishing cells 30A are opened in the opening of a mask used in a doping process to adjust the threshold voltage of standard cells, by having multiple finishing cells 30A have different threshold voltages or containing different materials.

[0064] Figure 20 shows a schematic configuration of an integrated circuit element 30' according to another embodiment of the present invention. Since the integrated circuit element 30' is constructed similarly to the integrated circuit element 30 described in Figure 16, the differences will be the focus of the explanation below. Referring to Figure 20, the integrated circuit element 30' includes a plurality of standard cells 30E and a plurality of finishing cells 30F that surround the plurality of standard cells 30E in the first horizontal direction (X direction). In one embodiment, a plurality of standard cells 30E include an active gate AG, and a plurality of finishing cells 30F include a dummy gate DG. Multiple finishing cells 30F are arranged around the outer periphery of multiple standard cells 30E in the first horizontal direction (X direction) and have a structure that terminates the active region FA which extends in the first horizontal direction (X direction).

[0065] Figures 21 to 23 are diagrams illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown in Figure 20. Figures 21 to 23 are illustrative diagrams illustrating masks used for threshold voltage adjustment. In addition to the masks disclosed in Figures 21 to 23, a variety of mask shapes and combinations can be employed within the scope of the technical concept of the present invention.

[0066] Referring to Figures 21 to 23, the first mask M1 includes openings that expose multiple standard cells 30E and multiple finishing cells 30F and cover the remaining areas, while the second mask M2 and third mask M3 include openings that expose multiple finishing cells 30F and cover multiple standard cells 30E. To adjust the threshold voltages (e.g., the second threshold voltage) of multiple standard cells 30E, the first doping process is carried out sequentially with the first mask M1 in place, the second doping process with the second mask M2 in place, and the third doping process with the third mask M3 in place. As a result, multiple finishing cells 30F can have a first threshold voltage, and multiple standard cells 30E can have a second threshold voltage that is different from the first threshold voltage. In other words, the multiple finishing cells 30F contain materials having different dipole properties or quantities than the multiple standard cells 30E. Multiple finishing cells 30F are opened in the opening of a mask used in a doping process to adjust the threshold voltage of standard cells, by having multiple finishing cells 30F have different threshold voltages or containing different materials.

[0067] Figure 24 is a diagram showing a schematic configuration of an integrated circuit element 40 according to another embodiment of the present invention. Since the integrated circuit element 40 is constructed similarly to the integrated circuit element 10 described in Figures 3, 4A, and 4B, the following explanation will focus on the differences. Referring to Figure 24, the integrated circuit element 40 includes a switch cell 40A. The switch cell 40A includes multiple gate structures GS and single diffusion breaks SDB interposed between the multiple gate structures GS.

[0068] Some of the multiple gate structures GS constitute an active gate AG that is activated to electrically form a transistor, while other parts constitute a dummy gate DG that does not electrically form a transistor. The switch cell 40A includes at least one dummy gate DG and at least one active gate AG. A dummy gate (DG) is defined as an electrically inactive gate. Based on the first and second sides of the dummy gate DG that are opposite each other in the first horizontal direction (X direction), the region within 1 CPP from the first side and the region within 1 CPP from the second side are defined as the dummy gate region DA.

[0069] As shown in Figure 24, based on the first and second sides of each of the multiple dummy gates DG, the region within 1 CPP from the first side and the region within 1 CPP from the second side are defined as the dummy gate region DA. In this case, the region between the two single diffusion breaks SDBs separated between the multiple dummy gates DG is also defined as the dummy gate region DA. Furthermore, based on the first and second sides of the active gate AG that face each other in the first horizontal direction (X direction), the region within 1 CPP from the first side and the region within 1 CPP from the second side are defined as the active gate region AA. As shown in Figure 24, based on the first and second sides of the active gate AG, the region within 1 CPP from the first side and the region within 1 CPP from the second side are defined as the active gate region AA. In this case, the region between the two single diffusion breaks SDBs separated between the active gate AGs is also defined as the active gate region AA.

[0070] Figures 25 to 27 are diagrams illustrating the mask used to adjust the threshold voltage of the integrated circuit element shown in Figure 24. Figures 25 to 27 are illustrative diagrams illustrating masks used for threshold voltage adjustment. In addition to the masks disclosed in Figures 25 to 27, a variety of mask shapes and combinations can be employed within the scope of the technical concept of the present invention. Referring to Figures 25 to 27, the first mask M1 includes an opening that exposes the dummy gate region DA and the active gate region AA and covers the remaining region, while the second mask M2 and the third mask M3 include an opening that exposes the dummy gate region DA and covers the active gate region AA.

[0071] To adjust the threshold voltage of the active gate region AA (for example, the second threshold voltage), the first doping step is performed with the first mask M1 in place, the second doping step is performed with the second mask M2 in place, and the third doping step is performed with the third mask M3 in place, in sequence. As a result, the dummy gate region DA can have a first threshold voltage, and the active gate region AA can have a second threshold voltage that is different from the first threshold voltage. In other words, the dummy gate region DA includes a material that has different dipole properties than the active gate region AA. It can be understood that the dummy gate region DA is opened in the opening of a mask used in a doping process to adjust the threshold voltage of a standard cell, by having a different threshold voltage, containing a different material, or having different doping amounts within the same material.

[0072] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0073] 1. Integrated Circuit Elements 3. Logic Cell Area 5. Switch Cell Region 10 Integrated Circuit Elements 10A Adjacent Cell 10B Standard Cell 102 circuit boards 118 Outer insulating spacer 130 Source / Drain Area 144 Gate-to-gate insulating film 152 Gate Dielectric Film 160 Gate Line 160M Main Gate Section 160S Subgate section 168 Capping Insulation Pattern 160 Gate Line BTV back through electrode CAS Contact FA active region GS Gate Structure M Mask N1, N2 (first, second) nanosheets NSS Nanosheet Stack OP1, OP2 (First, Second) Openings PR1, PR2 (1st and 2nd) Power Rails SDB Single Diffusion Break STC Signal Tap Cell

Claims

1. It is a mask, Multiple logic cell regions corresponding to the locations where multiple logic cells of the manufactured integrated circuit element are arranged, It comprises a plurality of switch cell regions interposed between the plurality of logic cell regions, or arranged to surround at least one logic cell region among the plurality of logic cell regions, Each of the plurality of switch cell regions is electrically isolated from each of the plurality of logic cell regions. When the mask is placed on top of the manufactured integrated circuit element, A first opening corresponding to a selected logic cell region among the plurality of logic cell regions, A mask characterized by including a second opening in at least one logic cell region among the plurality of switch cell regions.

2. The mask according to claim 1, characterized in that the mask is used during a doping process to adjust the threshold voltage (Vt) of each of the plurality of logic cells.

3. Multiple logic cell regions in which logic cells are formed, A switch cell region interposed between the plurality of logic cell regions, or arranged to surround the plurality of logic cell regions, On the plurality of logic cell regions and switch cell regions, there are a plurality of power rails that extend in the first horizontal direction and to which a power supply voltage is applied, On any one selected logic cell region from the plurality of logic cell regions, a plurality of first gate structures are provided, which are spaced apart from each other in the first horizontal direction and extend in a second horizontal direction that intersects the first horizontal direction. The switch cell region includes a plurality of second gate structures that are spaced apart from each other in the first horizontal direction and extend in the second horizontal direction, The switch cell region includes a break region that is electrically isolated from the logic cell region. An integrated circuit element characterized in that the first transistor controlled by the plurality of first gate structures has a different threshold voltage (Vt) than the second transistor controlled by the plurality of second gate structures.

4. The aforementioned switch cell region is Interposed between the plurality of logic cell regions, The first horizontally spaced first single diffusion break and second single diffusion break, A signal tap cell including a back-through electrode penetrating between the first single diffusion break and the second single diffusion break, The signal tap cell and the first horizontally adjacent adjacent cell are included, The integrated circuit element according to claim 3, characterized in that the adjacent cell includes the plurality of second gate structures.

5. The aforementioned switch cell region is Interposed between the plurality of logic cell regions, The filler cell includes a first single diffusion break and a second single diffusion break that are separated from each other by a distance of 1 CPP (contacted poly pitch) in the first horizontal direction, The integrated circuit element according to claim 3, characterized in that the filler cell includes the plurality of second gate structures.

6. The aforementioned switch cell region is The plurality of logic cell regions are surrounded by, The plurality of logic cell regions include a first finishing cell having a structure that terminates a plurality of gate structures that are spaced apart in the first horizontal direction and extended in the second horizontal direction, The integrated circuit element according to claim 3, characterized in that the first finishing cell includes the plurality of second gate structures.

7. The aforementioned switch cell region is The plurality of logic cell regions are surrounded by, The plurality of logic cell regions include a second finishing cell having a structure that terminates a plurality of active regions that extend in the first horizontal direction, The integrated circuit element according to claim 3, characterized in that the second finishing cell includes the plurality of second gate structures.

8. The plurality of second gate structures on the switch cell region are, The active gate that electrically constitutes a transistor, It includes a dummy gate that does not electrically constitute a transistor, The integrated circuit element according to claim 3, characterized in that the dummy gate and the active gate have different threshold voltages (Vt).

9. A method for controlling the threshold voltage of multiple transistors in a manufactured device, The manufactured device comprises a plurality of logic cell regions in which logic cells are formed, an active cell region in which an active cell is formed, and a first dummy cell region adjacent to a first logic cell region among the plurality of logic cell regions and adjacent to the active cell region, wherein the first dummy cell region includes a break region electrically isolated from each of the plurality of logic cell regions, the logic cells have a first width in a first direction, the active cells have a second width smaller than the first width in a first direction, and the first dummy cell region is adjacent to the active cell region in a first direction. The method for controlling the threshold voltage is: The steps include placing the device being manufactured, which will be formed as the manufactured device, into a process chamber, Here, the device being manufactured has a device region corresponding to the region of the device being manufactured, A step of performing a first doping process on the device under manufacture using a first mask that includes openings that expose a device region corresponding to the active cell, a device region corresponding to the first dummy cell, and a device region corresponding to the first logic cell. A threshold voltage adjustment method characterized by comprising the step of performing a second doping step on the device under manufacture using a second mask that includes an opening that exposes a device region corresponding to the active cell, exposes a device region corresponding to the first dummy cell region, and covers a device region corresponding to the first logic cell region.

10. The threshold voltage adjustment method according to claim 9, characterized in that the coupling width in the first direction between the active cell region and the adjacent first dummy cell region is smaller than the width in the first direction of the first logic cell region.

Images