Semiconductor equipment

Abstract

To provide transistors with a fine structure and high yield. Also, the O To provide a semiconductor device that improves performance and enables high-speed response and high-speed drive. [Solution] Oxide semiconductor layer, gate insulating layer, gate electrode layer, insulating layer, conductive film, interlayer insulating The layers are stacked in sequence, and by cutting the conductive film, the gate electrode layer and the insulating layer are connected. The electrode film is removed, and the source electrode layer and drain electrode layer are formed in a self-aligned manner, An electrode layer is provided that is in contact with the oxide semiconductor layer, superimposed on the region in contact with the drain electrode layer and the drain electrode layer. Keru.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] A transistor (thin film transistor) is formed using a semiconductor thin film on a substrate having an insulating surface. The technology that makes up TFTs (also known as Thick-Fiber Telescopes) is attracting attention.

[0003] For example, indium (In), gallium (Ga), and sub-aluminum are used as the active layer of transistors. A transistor using an amorphous oxide containing lead (Zn) has been disclosed (see Patent Document 1). ). [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Overview of the project] [Problems that the invention aims to solve]

[0005] By the way, we have achieved faster transistor operation, lower power consumption, and higher integration. To achieve this, miniaturization of transistors is essential.

[0006] However, with the miniaturization of transistors, there are concerns about a decrease in yield during the manufacturing process. Therefore, one of the objectives is to provide transistors with a fine structure in a high yield.

[0007] Furthermore, with the increasing performance of semiconductor devices including transistors, miniaturized transistors Even so, there is a need to improve the on-characteristics. Therefore, miniaturized transients One of the objectives is to provide a configuration for realizing high-speed response and high-speed driving of a transistor and a manufacturing method thereof.

Means for Solving the Problem

[0008] A semiconductor device according to one aspect of the present invention includes an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, a gate electrode layer on the gate insulating layer, and an insulating layer on the gate electrode layer. On these layers, a conductive film and an interlayer insulating layer are sequentially laminated. By cutting the conductive film to remove the conductive film on the gate electrode layer and the insulating layer and to divide them, a source electrode layer and a drain electrode layer are self-alignedly formed. The oxide semiconductor layer includes a low-resistance region into which an impurity element is introduced to reduce the resistance and a channel formation region. In the low-resistance region, the source electrode layer and the drain electrode layer are in contact. A low-resistance region is provided with an electrode layer made of metal, a conductive metal compound, semiconductor, or the like in contact with the lower part thereof.

[0009] Since an etching process using a resist mask is not used in the formation process of the source electrode layer and the drain electrode layer, precise processing can be accurately performed. Therefore, in the manufacturing process of the semiconductor device, a transistor having a fine structure with small variations in shape and characteristics can be produced with a high yield.

[0010] The low-resistance region of the oxide semiconductor layer is in contact with the source electrode layer and the drain electrode layer and functions as a source region and a drain region. Therefore, the contact resistance between the oxide semiconductor layer and the source electrode layer and the drain electrode layer is reduced. By providing an electrode layer in contact with the lower part of the low-resistance region, the electrode layer also functions as a source region and a drain region, and the source region and the drain region ​This allows for thicker film in the region. By thickening the source and drain regions, the source region can be increased. The resistance of the source and drain regions is reduced, and the electric field of the source and drain electrode layers is weakened. This allows for the provision of semiconductor devices with excellent on-state characteristics.

[0011] Therefore, one aspect of the present invention relates to a pair of electrode layers and a pair of electrode layers in contact with the pair of electrode layers. An oxide semiconductor comprising a pair of low-resistance regions and a channel-forming region sandwiched between the pair of low-resistance regions. A conductive layer, a gate insulating layer on the oxide semiconductor layer, and a channel formation region on the gate insulating layer. A superimposed gate electrode layer, an upper insulating layer on the gate electrode layer, and the sides and top of the gate electrode layer. Sidewall insulating layer covering the sides of the insulating layer, oxide semiconductor layer, sides of the gate insulating layer and sidewall insulating layer A source electrode layer and a drain electrode layer in contact with the side surface, and on the source electrode layer and drain electrode layer The first insulating layer, the upper insulating layer, the side wall insulating layer, and the source electrode layer and drain electrode layer A second insulating layer and a source electrode layer through openings provided in the first insulating layer and the second insulating layer. and a pair of wiring layers in contact with the drain electrode layer, the source electrode layer and the drain electrode layer The height of the upper surface is lower than the height of the upper insulating layer, the side wall insulating layer, and the upper surface of the first insulating layer, The pair of wiring layers are higher than the height of the top surface of the gate electrode layer, and each superimposes itself on the pair of electrode layers. It is a semiconductor device.

[0012] Furthermore, in the above semiconductor device, the electrode layer is in the underlying insulating layer below the oxide semiconductor layer or under It is provided on an insulating layer, and the upper surface of the electrode layer is exposed from the underlying insulating layer or on the underlying insulating layer. The surface and the upper surface of the electrode layer can be configured to be at the same height. In this case, the film of the electrode layer The thickness can be made greater than the film thickness of the oxide semiconductor layer, and the source region and drain region This allows for the creation of thicker films.

[0013] Furthermore, the electrode layer is formed on the underlying insulating layer, and the oxide semiconductor layer is formed on the electrode layer. This is also acceptable. In this case, the number of steps involved in manufacturing semiconductor devices can be reduced.

[0014] Furthermore, the first insulating layer is an aluminum oxide layer in contact with the source electrode layer and the drain electrode layer. It is preferable to include it.

[0015] Furthermore, it is preferable that the surface of the channel-forming region is flat.

[0016] Furthermore, in one aspect of the present invention, a pair of electrode layers are formed, and an oxide semiconductor layer is formed on the pair of electrode layers. This is done, and a gate insulating layer is formed on the oxide semiconductor layer, and the oxide semiconductor layer and the gate insulating layer are superimposed on the gate insulating layer. A gate electrode layer and an upper insulating layer are formed, and the gate electrode layer and the upper insulating layer are used as a mask. By introducing impurity elements into an oxide semiconductor layer, a pair of low-resistance regions and channel-forming regions are self-regulating. Formed together, a sidewall insulating layer is formed on the gate insulating layer to cover the side surface of the gate electrode layer, and an oxide A conductive film is formed on the semiconductor layer, gate electrode layer, side wall insulating layer, and upper insulating layer, and a layer is formed on the conductive film. An interlayer insulating layer is formed, and the interlayer insulating layer and conductive film are chemically and mechanically treated until the upper insulating layer is exposed. The conductive film is separated by abrasion to remove it, and a source electrode layer and a drain electrode layer are formed, and the first Semiconductors forming a second insulating layer on the insulating layer, upper insulating layer, source electrode layer, and drain electrode layer. This is a method for manufacturing a device. Furthermore, the first insulating layer and the second insulating layer are provided with a source electrode layer and a do An opening is formed that reaches the rain electrode layer, and the source electrode layer and drain electrode layer are in contact through the opening. A wiring layer may be formed.

[0017] In this specification, the term "above" means that the relative position of the constituent elements is "directly above". This does not limit it to just that. For example, the expression "gate electrode layer on an insulating layer" means insulating This does not exclude cases that include other components between the layer and the gate electrode layer. The same applies to "below". That is the case.

[0018] Furthermore, in this specification, the terms "electrode layer" and "wiring layer" refer to these components. It is not limited to a specific function. For example, the "electrode layer" can be used as part of the "wiring layer". This can happen, and vice versa. Furthermore, the terms "electrode layer" and "wiring layer" are, This also includes cases where multiple "electrode layers" or "wiring layers" are formed as a single unit.

[0019] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0020] In this specification, etc., "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via ". Here, "something that has some electrical effect" The term "connection" is not particularly limited as long as it enables the exchange of electrical signals between connected objects.

[0021] For example, "things that have some kind of electrical effect" include electrodes and wiring. [Effects of the Invention]

[0022] One aspect of the present invention can provide transistors with a fine structure with high yield. Furthermore, the on-characteristics can be improved even in miniaturized transistors, and miniaturization The present invention provides a configuration and method for manufacturing a transistor that enables high-speed response and high-speed drive. can. [Brief explanation of the drawing]

[0023] [Figure 1] A top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 2] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 3] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 4] A diagram illustrating a method for manufacturing a semiconductor device according to one aspect of the present invention. [Figure 5] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 6] A top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 7] A cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 8] A cross-sectional view, a top view, and a circuit diagram showing one form of a semiconductor device. [Figure 9] A top view and a cross-sectional view showing one form of a semiconductor device. [Figure 10] Circuit diagram and perspective view showing one form of a semiconductor device. [Figure 11] A cross-sectional view showing one form of a semiconductor device. [Figure 12] A top view and a cross-sectional view showing one form of a semiconductor device. [Figure 13] A top view and a cross-sectional view showing one form of a semiconductor device. [Figure 14] A circuit diagram showing one form of a semiconductor device. [Figure 15] A block diagram showing one form of a semiconductor device. [Figure 16] A block diagram showing one form of a semiconductor device. [Figure 17]A block diagram showing one form of a semiconductor device. [Modes for carrying out the invention]

[0024] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... The form and details can be modified in various ways, without being limited to the following description, as any person skilled in the art would know. It is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It is not something that can be done.

[0025] In the embodiments described below, reference numerals indicating the same thing are used in common across different drawings. This may occur. Furthermore, the components shown in the drawing, namely the thickness, width, and relative height of layers, regions, etc. In the description of the embodiment, the relative positions and other details may be exaggerated for clarity. There is a match.

[0026] (Embodiment 1) In this embodiment, the basic configuration and manufacturing method of a semiconductor device according to one aspect of the present invention are shown in Figure This will be explained using a plane. Figure 1 shows a semiconductor device according to one embodiment of the present invention.

[0027] Figure 1(A) shows a top view of a transistor according to one embodiment of the present invention, and Figure 1(B) shows a top view of a transistor according to the present invention. This is a cross-sectional view of 1(A) along the dashed line A1-A2.

[0028] The semiconductor device including the transistor 420 has an underlay insulating layer 436 and an underlay insulating layer on a substrate 400. An electrode layer 405a provided in the edge layer 436, with its upper surface exposed from the underlying insulating layer 436, and Electrode layer 405b and low-resistance regions 40 in contact with electrode layer 405a and electrode layer 405b, respectively. 4a and the low-resistance region 404b, and the area sandwiched between the low-resistance region 404a and the low-resistance region 404b A channel-forming region 403 and an oxide semiconductor layer 409 including a channel-forming region 403 and an oxide semiconductor layer 409 on the oxide semiconductor layer 409 Gate insulating layer 402, gate electrode layer 401 on gate insulating layer 402, gate electrode layer 4 Side wall insulating layers 412a and 412b covering the sides of 01, and gate electrode layer 401 An upper insulating layer 413 covering the top surface, an underlay insulating layer 436, and an oxide semiconductor layer 409, on which side wall insulating Source electrode layer 406a and drain in contact with the side surface of edge layer 412a and side wall insulating layer 412b Electrode layer 406b and insulating layer 415 on source electrode layer 406a and drain electrode layer 406b And, insulating layer 415, source electrode layer 406a, drain electrode layer 406b, side wall insulating layer 412 a. The insulating layer 417 on the side wall insulating layer 412b and the upper insulating layer 413, and the insulating layer 415 and the insulating layer 415. Through the opening provided in the edge layer 417, the source electrode layer 406a and the drain electrode layer 406 It has wiring layers 465a and 465b, which are in contact with b respectively.

[0029] The height of the upper surface of the insulating layer 415 is determined by the side wall insulating layer 412a, the side wall insulating layer 412b and the upper insulating layer 4 The height of the top surface of 13 is approximately the same. Also, the source electrode layer 406a and the drain electrode layer 4 The height of the top surface of 06b is the top surface of the insulating layer 415, the side wall insulating layer 412a, and the side wall insulating layer 412b. It is lower than the height of the gate electrode layer 401 and higher than the height of the upper surface of the gate electrode layer 401. This is the distance from the top surface of the substrate 400.

[0030] The oxide semiconductor layer 409 has a channel formation region 403 that overlaps with the gate electrode layer 401, and Low-resistance regions 404a and 404b, in which resistance is reduced by the introduction of pure elements, The low-resistance region 404a and the low-resistance region 404b mask the gate electrode layer 401. By introducing impurity elements into the oxide semiconductor layer 409, it is formed in a self-aligned manner.

[0031] Furthermore, the source electrode layer 406a and the drain electrode layer 406b are located on top of the oxide semiconductor layer 409. It is provided in contact with the surface and the side wall insulating layer 412a or the side wall insulating layer 412b. The source electrode layer 406a or the drain electrode layer 406b and the oxide semiconductor layer 409 are in contact. The distance (shortest distance) between the region (contact region) and the gate electrode layer 401 is the side wall insulating layer 4 This becomes the width in the channel length direction of 12a or the side wall insulating layer 412b, enabling miniaturization, This allows for control over variations in the shortest distance during the manufacturing process.

[0032] Low-resistance regions 404a and 404b of the oxide semiconductor layer 409 are located in the source electrode layer 4 06a and the drain electrode layer 406b are in contact, respectively, and the source region of transistor 420 and It functions as a drain region. Acid in low resistance region 404a and low resistance region 404b The ionized semiconductor layer 409, the source electrode layer 406a, and the drain electrode layer 406b are in contact with each other. Therefore, the source electrode layer 406a and the drain electrode layer 406b and the oxide semiconductor layer 409 The contact resistance has been reduced.

[0033] Furthermore, the low-resistance regions 404a and 404b are electric fields embedded in the underlying insulating layer 436. It is in contact with the polar layer 405a and the electrode layer 405b, respectively. It is composed of metals, conductive metal compounds, semiconductors, etc. Low resistance region 404a and low resistance Region 404b functions as the source and drain region of transistor 420. By providing electrode layers 405a and 405b at the bottom of the drain region and the so This allows for thicker film in the source and drain regions, and reduces the resistance of the source and drain regions. This can reduce resistance and improve the on-characteristics of the transistor.

[0034] Furthermore, because electrode layers 405a and 405b are embedded in the underlying insulating layer, Even if the film thickness of the electrode layer 405a and electrode layer 405b is increased, the film thickness of the electrode layer 405a and electrode layer 40 The coverage of the oxide semiconductor layer 409 provided on 5b is not affected. Therefore, electrode layer 405 The film thickness of a and electrode layer 405b is the resistance of the source region and drain region of transistor 420. The film can be thickened until the resistance is sufficiently reduced. Also, the channel-forming region 403 Since there is no electrode layer in the lower part, the channel formation region 403 is thinned, and the source region and Only the drain region can be made thicker.

[0035] Next, an example of a method for fabricating the transistor 420 shown in Figure 1 will be explained using Figures 2 to 5. explain.

[0036] First, conductive films that will become electrode layers 405a and 405b are formed on the substrate 400, and the conductive film A resist mask is formed on top, and selective etching is performed to remove the electrode layer 405a and the electrode layer After forming 405b, remove the resist mask.

[0037] There are no major restrictions on the type of substrate that can be used, but at the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. It is necessary to have the following characteristics. For example, barium borosilicate glass or aluminobosilicate glass. Using glass substrates such as acid glass, ceramic substrates, quartz substrates, sapphire substrates, etc. It is possible.

[0038] Also, single-crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, and silicon gel Compound semiconductor substrates such as luminium, SOI substrates, and semiconductor devices on these substrates You can use the facilities that have been set up.

[0039] The conductive films that form electrode layers 405a and 405b are made of materials that can withstand subsequent heat treatment. The film is formed with a thickness of 10 nm to 500 nm by CVD or sputtering. For example, a metal film containing elements selected from Al, Cr, Cu, Ta, Ti, Mo, and W. Alternatively, metal nitride films containing the above-mentioned elements (titanium nitride film, molybdenum nitride film, titanium nitride film) Metals such as Al and Cu can be used. A structure in which a film and a high-melting-point metal such as Ti, Mo, or W are layered may also be used. High-melting-point metals such as W are placed on either the underside, aboveside, or both sides of a metal film such as Al or Cu. The configuration may also be such that the conductive film is formed from an oxide semiconductor material. The substances are indium oxide (In2O3), tin oxide (SnO2), and zinc oxide (ZnO2). ), indium tin oxide (In2O3-SnO2), indium zinc oxide (In Use 2O3-ZnO or these metal oxide materials containing silicon oxide. It is possible.

[0040] When using an oxide semiconductor for the conductive film, even if the oxide semiconductor material is the same as that used for the oxide semiconductor layer 409... Different oxide semiconductor materials may be used. In particular, the same oxide may be used for the conductive film and the oxide semiconductor layer 409. When semiconductor materials are used, the electrode layer 405a and electrode layer 405b and the oxide semiconductor layer 409 Because contact resistance can be further reduced, transistors with good electrical characteristics can be fabricated. This is possible. For example, as an oxide semiconductor material, In-Ga-Zn-based oxide (IGZ When using (also denoted as O), IGZO is also used for electrode layer 405a and electrode layer 405b. It would be good to do so.

[0041] In this embodiment, the conductive film is produced using the sputtering method, with an atomic ratio of In:Ga:Z After depositing a 30nm n=1:1:1 IGZO film, etching is performed using a resist mask. This process is used to form electrode layers 405a and 405b.

[0042] Next, an underlayer insulating film 435 is applied to cover the substrate 400, electrode layer 405a and electrode layer 405b. This forms (see Figure 2(A)). The undercoat insulating film 435 is formed by sputtering, MBE, C VD method, pulsed laser deposition method, ALD method, etc., can be used as appropriate. When 435 is formed using the sputtering method, impurity elements such as hydrogen can be reduced. Cut.

[0043] The underlying insulating film 435 includes silicon oxide, gallium oxide, aluminum oxide, and nitridation. Oxide insulating layer such as silicon, silicon nitride, hafnium oxide, or tantalum oxide. It is preferable to use these compounds in a single-layer structure or a multilayer structure of two or more layers. It can be formed and used. When forming a laminated structure, for example, C can be used as the underlying insulating layer that comes into contact with the substrate. A silicon oxide film formed by the VD method is used as the underlying insulating film in contact with the oxide semiconductor layer 409. A configuration using a silicon oxide film formed by sputtering as the layer is also possible. By making the insulating layer in contact with the semiconductor layer an oxide insulating layer with reduced hydrogen concentration, In addition to suppressing hydrogen diffusion in the semiconductor layer 409, it also provides undercurrent insulation to oxygen vacancies in the oxide semiconductor layer 409. Because oxygen is supplied from the oxide insulating layer which becomes the edge layer 436, the electrical characteristics of the transistor 420 It can improve sexual performance.

[0044] Note that silicon oxidnitride, in this context, refers to a material whose composition contains more oxygen than nitrogen. This indicates, for example, that oxygen is at least 50 atomic% to 70 atomic%, and nitrogen is 0.5 atomic%. Materials containing between 15% and 15% of silicon, and between 25% and 35% of silicon. However, the above range refers to Rutherford backscattering (RBS). Forward scattering spectrometry (HFS) and hydrogen forward scattering spectrometry (HFS) When measured using Hydrogen Forward Scattering) Furthermore, the content ratio of the constituent elements shall not exceed 100 atomic percent in total. .

[0045] Since the underlying insulating film 435 is in contact with the oxide semiconductor layer 409, at least the amount in the layer (bulk) It is preferable that an amount of oxygen exceeding the stoichiometric composition is present. For example, the underlayer insulating film 43 5. When using a silicon oxide layer, SiO (2+α) (However, α > 0) ru.

[0046] Furthermore, before forming the underlying insulating film 435, the electrode layer 405a and electrode layer 405b were subjected to nitrogen plasma treatment. The procedure may be performed. By performing nitrogen plasma treatment, the electrode layer 405a and electrode layer 40 The contact resistance between 5b and the oxide semiconductor layer 409 that is formed later can be further reduced. can.

[0047] Next, the substrate insulating film 435 is subjected to polishing treatment (for example, chemical mechanical polishing). Mechanical Polishing (CMP) and etching processes This exposes the upper surfaces of electrode layer 405a and electrode layer 405b from the underlying insulating film 435, and the electrodes A base insulating layer 436 is formed that is the same height as the upper surface of layer 405a and electrode layer 405b. See Figure 2(B). Polishing or etching may be performed multiple times, and these can be combined. They may be done together. When done together, the order of the processes is not particularly limited. Substrate insulating layer In order to improve the crystallinity of the oxide semiconductor layer provided on 436, the underlying insulating layer 436 It is preferable to keep the surface as flat as possible.

[0048] In this embodiment, after the electrode layer 405a and electrode layer 405b are provided, the base insulating layer is applied. Although a method for forming 436 is shown, the electrode layer 405a, electrode layer 405b and base insulating layer 43 The method of manufacturing 6 is not limited to this. For example, after providing the base insulating layer 436 on the substrate 400, An opening is formed in the underlying insulating layer 436 using an etching process or the like, and a conductive material is filled into the opening. The electrode layer 405a and electrode layer 405b may be formed by filling the gaps.

[0049] In this embodiment, electrode layers 405a and 405b are embedded in the underlying insulating layer 436. Therefore, even if the film thickness of electrode layer 405a and electrode layer 405b is increased, the acid that is later applied It does not affect the coverage of the ion semiconductor layer. Therefore, electrode layer 405a and electrode layer 405 b may be made thick enough to sufficiently reduce the resistance of the source and drain regions. For example, , source electrode layer 406a and drain electrode layer 405a and electrode layer 405b are provided later. It is preferable that the thickness be greater than that of the polar layer 406b or the oxide semiconductor layer 409.

[0050] Next, an oxide semiconductor film is formed on the base insulating layer 436, electrode layer 405a, and electrode layer 405b. Oxide semiconductor films are produced by sputtering, evaporation, and pulsed laser deposition (Puls Laser Deposition (PLD), ALD, or MBE, etc. A film can be formed using this method.

[0051] After applying a resist mask to the oxide semiconductor film and etching the oxide semiconductor film in an island-like pattern Then, the resist mask is removed to form the oxide semiconductor layer 409. The oxide semiconductor layer 409 is The configuration may completely cover electrode layer 405a and electrode layer 405b, or an oxide semiconductor layer The end of 409 overlaps with electrode layer 405a and electrode layer 405b, and electrode layer 405a and electrode layer A portion of the upper surface of 405b may be exposed.

[0052] When a portion of the upper surface of electrode layer 405a and electrode layer 405b is exposed, electrode layer 405a and The electrode layer 405b is formed later with the source electrode layer 406a and the drain electrode layer 406b. They may be in contact. For example, Figure 5(A) shows electrode layer 405a and electrode layer 405b and source electric The diagram shows a configuration in which the polar layer 406a and the drain electrode layer 406b are in contact with each other.

[0053] The oxide semiconductor used in the oxide semiconductor layer 409 is at least indium (In), Alternatively, it is preferable to include zinc (Zn). In particular, it is preferable to include in and Zn. Furthermore, a stabilizer to reduce variations in the electrical characteristics of transistors using the oxide semiconductor. It is preferable to have gallium (Ga) in addition to those as a riser. Other materials used include tin (Sn), hafnium (Hf), and aluminum (Al). It is preferable to do so.

[0054] Additionally, other stabilizers include the lanthanoids lanthanum (La) and cerium (C). e) Praseodymium (Pr), Neodymium (Nd), Samarium (Sm), Europium ( Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hormone Um (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lute It may contain one or more of thium (Lu) and zirconium (Zr).

[0055] For example, oxide semiconductors include indium oxide, tin oxide, and acid, which are oxides of monometallic compounds. Zinc oxide, an oxide of a binary metal, such as In-Zn oxides, Sn-Zn oxides, and Al-Z n-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-G α-type oxides, ternary metal oxides such as In-Ga-Zn oxides and In-Al-Zn oxides Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn acids oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides Materials, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, I n-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides which are oxides of quaternary metals, I n-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al- Using Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides It is possible to be there.

[0056] In this context, for example, an In-Ga-Zn oxide is defined as an oxide whose main components are In, Ga, and Zn. It means an oxide containing In, and the ratio of In, Ga, and Zn is not specified. Also, In and It is acceptable for metals other than Ga and Zn to be present.

[0057] In addition, as an oxide semiconductor, InMO3(ZnO) m (m > 0, and m is not an integer) Materials represented by may also be used. Note that M is selected from Ga, Fe, Mn, and Co. It represents one or more metallic elements. Also, as an oxide semiconductor, In2SnO5 (ZnO) n Materials expressed as (n>0 and n is an integer) may also be used.

[0058] For example, In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxidation with atomic ratio a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Oxides with a similar composition to the substance can be used. Alternatively, In:Sn:Zn=1: 1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8) It is advisable to use In-Sn-Zn oxides with a specific ratio or oxides with a similar composition.

[0059] For example, if the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of an oxide with c=1 is such that the atomic ratio is In:Ga:Zn=A:B:C(A+B+C The composition of the oxide in the vicinity of (aA) = 1) means that a, b, and c are in the vicinity of (aA)2 +(bB) 2 + (cC) 2 ≤r 2 This means satisfying the following condition. For example, r can be set to 0.05. The same applies to other oxides.

[0060] However, this is not limited to these, and depends on the required electrical characteristics (mobility, threshold, variability, etc.). You should use one with an appropriate composition. Also, in order to obtain the required electrical characteristics, A concentration, impurity element concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to make it appropriate.

[0061] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, Furthermore, even with In-Ga-Zn oxides, mobility can be increased by reducing the bulk defect density. It is possible.

[0062] The oxide semiconductor film may have an amorphous structure or a crystalline structure. A preferred embodiment of the oxide semiconductor film is a CAAC oxide semiconductor (CAAC-OS:C Axis Aligned Crystalline Oxide Semicondu There is a ctor film. The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous material. The CAAC-OS film has a crystalline-amorphous multiphase structure in which the amorphous phase has both crystalline and amorphous parts. This is an oxide semiconductor film. The crystalline portion is contained within a cube with sides less than 100 nm long. They are often of a certain size. Transmission electron microscope (TEM) Observation using an lectron microscope shows that the CAAC-OS film contains The boundary between the amorphous and crystalline parts is not always clear. Furthermore, TEM reveals that CAAC- No grain boundaries (also called grain boundaries) can be observed in the OS film. Therefore, CAA The C-OS film suppresses the decrease in mobility caused by grain boundaries.

[0063] The crystalline portion contained in the CAAC-OS film has a c-axis that is the normal vector to the surface on which the CAAC-OS film is formed. Aligned in a direction parallel to the normal vector of the plane or surface, and triangular when viewed from a direction perpendicular to the ab plane. Having a shape or hexagonal atomic arrangement, the metal atoms are layered or when viewed from a direction perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. Furthermore, the a-axis and between different crystalline regions are as follows: The orientation of the b-axis may be different. In this specification, when it is simply described as vertical, 85 The range of ° to 95° is also included. Furthermore, when simply described as parallel, -5° is used. The range of 5° or less is also included. It may be replaced with nitrogen.

[0064] Furthermore, the distribution of crystalline regions in the CAAC-OS film does not need to be uniform. For example, CAA In the formation process of a C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, the shape The proportion of crystalline material may be higher near the surface compared to near the surface of the material. Also, CA By adding impurities to the AC-OS film, the crystalline region in the impurity-added area becomes amorphous. It can also become qualitative.

[0065] The c-axis of the crystalline portion contained in the CAAC-OS film is the normal vector to the surface on which the CAAC-OS film is formed. Because it aligns in a direction parallel to the normal vector of the surface or the material, the shape of the CAAC-OS film (formed Depending on the cross-sectional shape of the surface or face, they may face in different directions. Oh, the direction of the c-axis of the crystalline portion is the normal vector to the surface on which the CAAC-OS film was formed. The direction is parallel to the normal vector of the crystalline or surface. The crystalline portion is formed by deposition, and It is formed by performing crystallization treatments such as heat treatment after film formation.

[0066] Transistors using CAAC-OS film exhibit changes in electrical properties due to irradiation with visible light and ultraviolet light. Its value is small. Therefore, this transistor is highly reliable.

[0067] Furthermore, when the oxide semiconductor layer 409 is in a stacked structure, the first oxide semiconductor film to the third acid A single-crystal acid oxide semiconductor film may also be applied to the oxide semiconductor film. Iridescent semiconductor film, polycrystalline oxide semiconductor film, amorphous oxide semiconductor film, or CAAC-OS film A configuration in which these are appropriately combined may also be used. In addition, the first oxide semiconductor film to the third oxide semiconductor film When an amorphous oxide semiconductor film is applied to any one of the conductive films, the internal stress of the oxide semiconductor film and External stress is relieved, and variations in transistor characteristics are reduced, and the transistor This will further enhance its reliability.

[0068] Furthermore, some of the oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

[0069] For example, when forming an oxide semiconductor layer using an In-Zn-based metal oxide, The target composition is expressed in atomic ratio as In / Zn = 1 to 100, preferably In / Zn = 1 to 20, more preferably In / Zn = 1 to 10. The atomic ratio of Zn is within a preferred range. By doing so, mobility can be improved. Here, in order to include an excess of oxygen, It is preferable to set the atomic ratio of metal oxides, In:Zn:O=X:Y:Z, to Z > 1.5X + Y. It seems so.

[0070] When depositing an In-Ga-Zn oxide as an oxide semiconductor layer using the sputtering method, Specifically, the atomic ratios are In:Ga:Zn = 1:1:1, 4:2:3, 3:1:2, 1:1 Using an In-Ga-Zn-O target represented as :2, 2:1:3, or 3:1:4 Using an In-Ga-Zn-O target having the aforementioned atomic ratio, an oxide semiconductor film is formed. Deposition of the film facilitates the formation of polycrystalline semiconductor films or CAAC-OS films.

[0071] Furthermore, when depositing an In-Sn-Zn oxide as an oxide semiconductor layer using the sputtering method... Preferably, the atomic ratios are In:Sn:Zn = 1:1:1, 2:1:3, 1:2:2. Alternatively, use the In-Sn-Zn-O target shown at 20:45:35. Deposition of an oxide semiconductor layer using an In-Sn-Zn-O target with a specific atom ratio. This makes it easier for polycrystalline semiconductor films or CAAC-OS films to form.

[0072] In this case, the relative density of the target is 90% to 100%, preferably 95% or more. It should be 99.9% or less. By increasing the target packing density, the oxide that is formed... This allows for the semiconductor layer to be made denser.

[0073] Furthermore, metal oxides that can be applied to oxide semiconductor layers have an energy gap of 2e It is preferably V or higher, more preferably 2.5 eV or higher, and even more preferably 3 eV or higher. Therefore, using metal oxides with a wide bandgap reduces the off-current of the transistor. It can be done.

[0074] In addition, it is preferable to reduce the alkali metals and alkaline earth metals in the oxide semiconductor layer. These concentrations are preferably 1×10 18 atoms / cm 3 or less, and more preferably 2×10 16 atoms / cm 3 or less. Alkali metals and alkaline earth metals may generate carriers when combined with the oxide semiconductor, which may cause an increase in the off-current of the transistor.

[0075] Also, the oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are laminated. For example, the oxide semiconductor film may be a laminate of a first oxide semiconductor film and a second oxide semiconductor film, and metal oxides with different compositions may be used for the first oxide semiconductor film and the second oxide semiconductor film. For example, one of a binary metal oxide to a quaternary metal oxide may be used for the first oxide semiconductor film, and a binary metal oxide to a quaternary metal oxide different from the first oxide semiconductor film may be used for the second oxide semiconductor film.

[0076] Also, the constituent elements of the first oxide semiconductor film and the second oxide semiconductor film may be the same, and their compositions may be different. For example, the atomic ratio of the first oxide semiconductor film may be In:Ga:Zn = 1 :1:1 or in the vicinity thereof, and the second oxide semiconductor film may be In:Ga:Zn = 3:1:2 or in the vicinity thereof. Also, the atomic ratio of the first oxide semiconductor film may be In:Ga:Zn =1:3:2 or in the vicinity thereof, and the atomic ratio of the second oxide semiconductor film may be In:Ga:Zn =2:1:3 or in the vicinity thereof.

[0077] At this time, of the first oxide semiconductor film and the second oxide semiconductor film, the gate electrode layer to be added later... The content of In and Ga in the oxide semiconductor film on the side closer to 401 (channel side) is set to In > Ga. It would be good to do so. Also, the In and G of the oxide semiconductor film on the side furthest from the gate electrode (back channel side) It is recommended to set the content of a to In ≤ Ga.

[0078] Furthermore, the oxide semiconductor film has a three-layer structure, with the first oxide semiconductor film to the third oxide semiconductor film... The constituent elements may be the same, but their respective compositions may differ. For example, the first oxide semi The atomic ratio of the conductive film is In:Ga:Zn=1:3:2, and the atomic number of the second oxide semiconductor film is... The ratio is set to In:Ga:Zn = 3:1:2, and the atomic ratio of the third oxide semiconductor film is set to In:Ga :Zn=1:1:1 is also acceptable.

[0079] Oxide semiconductor films in which the atomic ratio of In is smaller than that of Ga and Zn; typically, the atomic ratio of In is: The first oxide semiconductor film with Ga:Zn=1:3:2 has more In atoms than Ga and Zn. Oxide semiconductor films with a large ratio, typically the second oxide semiconductor film, and Ga, Zn, Compared to oxide semiconductor films with the same atomic ratio of In, typically the third oxide semiconductor film, It has high affinity. Also, it is the first oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:3:2. If the film has an amorphous structure, its insulating properties are further enhanced.

[0080] Furthermore, since the constituent elements of the first oxide semiconductor film to the third oxide semiconductor film are the same, The oxide semiconductor film has fewer trap levels at the interface with the second oxide semiconductor film. Therefore, by using the above structure for the oxide semiconductor film, the aging of the transistor and the optical BT signal are improved. This can reduce the amount of fluctuation in threshold voltage caused by the resuscitation test.

[0081] In oxide semiconductors, the s orbitals of heavy metals primarily contribute to carrier conduction, and the In content... By increasing the amount of s orbitals, more s orbitals overlap, resulting in an oxide composition where In > Ga. It exhibits higher mobility compared to oxides with a composition of In ≤ Ga. Also, Ga is relative to In. In comparison, the energy required for oxygen vacancies is higher, making oxygen vacancies less likely to occur, therefore, the composition of In ≤ Ga Oxides with this composition exhibit more stable properties compared to oxides with a composition where In > Ga.

[0082] An oxide semiconductor with a composition of In > Ga is applied to the channel side, and In ≤ Ga is applied to the back channel side. By applying an oxide semiconductor with a Ga composition, the field-effect mobility and signal strength of the transistor can be improved. This will make it possible to further enhance reliability.

[0083] The thickness of the oxide semiconductor layer 409 is 1 nm or more and 100 nm or less, preferably 1 nm or more and 20 nm or less. The size shall be less than nm. Transistor 420 consists of an oxide semiconductor layer 409, an electrode layer 405a and an electrode In the region where polar layer 405b is superimposed, it is in contact with wiring layer 465a and wiring layer 465b, respectively. Therefore, even if the oxide semiconductor layer is made thinner due to the miniaturization of transistors, oxidation The electrode layers 405a and 405b, which are superimposed on the semiconductor layer 409, allow acid to To ensure electrical connection between the ion semiconductor layer 409 and the wiring layers 465a and 465b. It is possible.

[0084] The oxide semiconductor layer 409 is preferably formed by sputtering, with the substrate heating temperature set to 100°C. Above 600°C or below, preferably 150°C to 550°C, and more preferably 200°C or below. The film is deposited at a temperature of 500°C or lower in an oxygen gas atmosphere. The higher the substrate heating temperature during film deposition, the better the result. The concentration of impurity elements in the oxide semiconductor layer 409 becomes lower. Also, in the oxide semiconductor layer 409 The atomic arrangement becomes more organized and denser, making it easier to form polycrystalline or CAAC-OS films. .

[0085] When forming the CAAC-OS film, for example, a polycrystalline oxide semiconductor sputtering process is used. The film is deposited by sputtering using a sputtering target. When ions collide with the target, the crystalline region contained in the sputtering target becomes a- Sputtering in the form of a flat plate or pellet, cleaved from surface b and having a surface parallel to surface ab. The particles may detach. In this case, the flat sputtered particles may become crystalline. By maintaining its state while reaching the substrate, the CAAC-OS film can be deposited.

[0086] Furthermore, it is preferable to apply the following conditions for forming the CAAC-OS film.

[0087] By reducing the inclusion of impurities during film formation, it is possible to suppress the disruption of the crystalline state due to impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present in the deposition chamber. It should be reduced. Also, the concentration of impurities in the film-forming gas should be reduced. Specifically, the dew point A film-forming gas with a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0088] Furthermore, by increasing the substrate heating temperature during film deposition, the sputtering particles can be prevented from migrating after reaching the substrate. A reaction occurs. Specifically, the substrate heating temperature is preferably between 100°C and 740°C. The film is deposited at a temperature between 200°C and 500°C. By increasing the substrate heating temperature during film deposition, the flat When plate-shaped sputtering particles reach the substrate, migration occurs on the substrate. The flat surface of the sputtered particles adheres to the substrate.

[0089] Furthermore, by increasing the oxygen content in the deposition gas and optimizing the power, plasma damage during film deposition can be reduced. It is preferable to reduce this. The oxygen content in the film-forming gas is 30% by volume or more, preferably 100% by volume. Let the product be %.

[0090] As an example of a target for sputtering, an In-Ga-Zn oxide target is used. The following is shown.

[0091] InO X powder, GaO Y Powder and ZnO Z The powder is mixed in a predetermined number of moles and then subjected to pressure treatment. By heat treatment at temperatures between 1000°C and 1500°C, polycrystalline In-Ga - A Zn-based oxide target is used. X, Y, and Z are arbitrary positive numbers. Here, A given molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z The powder is 2: The ratios are 2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, or 3:1:2. Oh, the type of powder and the molar ratio in which they are mixed are important for the sputtering target being prepared. You can change it as needed depending on the situation.

[0092] Furthermore, by forming the film under an oxygen gas atmosphere, extra atoms such as noble gases are not included. Therefore, polycrystalline semiconductor films or CAAC-OS films are more easily formed. However, oxygen gas and A mixed atmosphere of noble gases is also acceptable, in which case the proportion of oxygen gas should preferably be 30% by volume or more. The amount is 50% by volume or more, more preferably 80% by volume or more. It is preferable that the argon and oxygen used in film formation do not contain water, hydrogen, etc. For example, The purity of the argon is 9N (dew point -121°C, water 0.1 ppb, hydrogen 0.5 ppb), and the oxygen is A purity of 8N (dew point -112°C, water 1 ppb, hydrogen 1 ppb) is preferred.

[0093] In this embodiment, sputtering is performed in an atmosphere with an argon-to-oxygen flow rate ratio of 2:1. Using the IGZO method, a 10nm thin film of IGZO with an atomic ratio of In:Ga:Zn=3:1:2 was deposited. ru.

[0094] Amorphous oxide semiconductors can be made relatively easily to obtain a flat surface, Transistors using this technology can reduce interfacial scattering of carriers (electrons) during operation, and are relatively easy to operate. It is easy to achieve a relatively high degree of mobility.

[0095] Furthermore, in crystalline oxide semiconductors, bulk defects can be reduced even further, and surface By improving the flatness, it is possible to obtain mobility higher than that of an amorphous oxide semiconductor. To improve surface flatness, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Alternatively, it is preferable to form it on a surface with a nm or smaller.

[0096] Note that Ra is defined in JIS B601:2001 (ISO4287:1997) This is an extension of the arithmetic mean roughness that can be applied to curved surfaces in three dimensions, and is called a "reference surface." It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface," and is defined by the following formula.

[0097]

number

[0098] Here, the specified surface is the surface to be measured for roughness, and the coordinates are (x1, y1, f(x1, y 1))(x1,y2,f(x1,y2))(x2,y1,f(x2,y1))(x2,y Let the region be a quadrilateral represented by the four points 2,f(x2,y2), and project the specified plane onto the xy-plane. Let S0 be the area of ​​the rectangle, and Z0 be the height of the reference plane (average height of the specified plane). Ra is an atom. Measurement is possible using an atomic force microscope (AFM). That is the case.

[0099] Furthermore, the reference plane is the plane parallel to the XY plane at the average height of the specified plane. When the average height of a fixed surface is denoted as Z0, the height of the reference surface can also be represented by Z0.

[0100] Thus, in the region where channels are formed in the oxide semiconductor layer, the average surface of the underlying insulating layer To reduce the roughness to 0.3 nm or less, a planarization treatment should be performed. Planarization is performed using an oxide semiconductor. This should be done before the conductive film is formed.

[0101] For example, a planarization process such as dry etching can be performed. Here, etching gas Examples include chlorine, boron chloride, silicon chloride, or carbon tetrachloride, and tetrachloride-based gases. Fluorine-based gases such as carbon dioxide, sulfur fluoride, or nitrogen fluoride can be used.

[0102] Furthermore, it is preferable that the amount of hydrogen contained in the oxide semiconductor layer be as low as possible. In addition to atoms, hydrogen may also be present as hydrogen molecules, water, hydroxyl groups, or other hydrides. Therefore, excess hydrogen (including water and hydroxyl groups) contained in the oxide semiconductor layer is removed (dehydrated). It is preferable to perform heat treatment (or dehydrogenation). The heat treatment temperature should be 300°C or higher. The temperature should be below 0°C or below the substrate's strain point. Heat treatment should be performed under reduced pressure or in a nitrogen atmosphere. This can be done. Furthermore, the heat treatment is performed after the formation of the oxide semiconductor film but before processing it into island shapes. Alternatively, it may be done after processing into island shapes. Furthermore, heat treatment for dehydration and dehydrogenation may be performed. This process may be performed multiple times and may be combined with other heat treatments.

[0103] The heat treatment is performed in a reduced pressure atmosphere or an inert atmosphere, followed by maintaining the temperature while removing oxidation. It is preferable to switch to a different atmosphere and perform further heat treatment. This is a reduced-pressure atmosphere or an inert atmosphere. When heat treatment is performed, the concentration of impurities (e.g., hydrogen) in the oxide semiconductor layer is reduced. This is possible, but at the same time, there is a risk of oxygen deficiency occurring, and in this case, the oxygen deficiency that occurs is This can be reduced by heat treatment in an oxidizing atmosphere.

[0104] By heat treatment, the oxide semiconductor layer can be made to have an extremely low concentration of impurity elements such as hydrogen within the layer. This makes it possible to achieve an ideal field-effect mobility for the transistor. It becomes possible to increase the motion level to near its maximum.

[0105] Furthermore, it is preferable to include an excess of oxygen in the oxide semiconductor layer 409 relative to its stoichiometric composition. It seems that if an excess of oxygen is included, oxygen vacancies will form in the oxide semiconductor layer 409. Carrier formation can be suppressed. In order to include an excess of oxygen, oxygen must be present during film formation. The film may be formed under conditions where a large amount is present, or after the formation of the oxide semiconductor film, oxygen (at least) By introducing oxygen (which includes either an oxygen radical, an oxygen atom, or an oxygen ion) into the membrane, oxygen is passed through it. It may be included in excess. Methods for introducing oxygen include ion implantation, ion doping, and Methods such as rasmimmerion ion implantation and plasma treatment can be used. Cut.

[0106] Furthermore, when an oxide insulating layer is used as the base insulating layer, the oxide semiconductor layer is placed on top of the oxide insulating layer. By heating in the provided state, oxygen can be supplied to the oxide semiconductor layer. Oxygen vacancies in oxide semiconductor layers can be reduced, improving their electrical properties. By performing the heating process with at least a portion of the layer and the oxide insulating layer in contact, oxidation Oxygen may be supplied to the material semiconductor layer. The heat treatment adds the oxide semiconductor film in an island-like manner. It can be done before construction, or after processing into an island shape. However, processing into an island shape By performing the heat treatment earlier, the amount of oxygen released to the outside from the underlying insulating layer is reduced. Therefore, it is preferable because it can supply more oxygen to the oxide semiconductor layer.

[0107] Next, a gate insulating film 452 is formed on the oxide semiconductor layer 409 (see Figure 2(C)).

[0108] The gate insulating film 452 is made of hafnium oxide, yttrium oxide, and hafnium silicate. (HfSi x O y (x>0, y>0), nitrogen-added hafnium silicate (H fSi x O y (x>0, y>0), hafnium aluminate (HfAl x O y x>0, By using high-k materials such as y>0 and lanthanum oxide, the gate leakage current can be reduced. It can be reduced. Furthermore, the gate insulating film 452 may be a single layer structure or a multilayer structure. good.

[0109] The thickness of the gate insulating film 452 shall be between 1 nm and 20 nm, and the method of sputtering or MBE shall be used. Methods such as CVD, PLD, and ALD can be used as appropriate. Also, the gate insulating film 4 52 is a configuration in which multiple substrate surfaces are set approximately perpendicular to the sputtering target surface. The film may also be deposited using a sputtering apparatus that performs film deposition under specific conditions.

[0110] In this embodiment, silicon oxidnitride is deposited as a 20 nm film by CVD.

[0111] Furthermore, since the gate insulating film 452 is in contact with the oxide semiconductor layer, similar to the underlying insulating layer 436, It is preferable that the amount of oxygen present in the layer (bulk) exceeds at least the stoichiometric composition. stomach.

[0112] Furthermore, in order to improve the coverage of the gate insulating film 452, the upper surface of the oxide semiconductor layer 409 is also Planarization treatment may be performed. In particular, a thin insulating layer may be used as the gate insulating film 452. In this case, it is preferable that the surface of the oxide semiconductor layer 409 has good flatness.

[0113] Next, the conductive film and insulating film are laminated on the gate insulating film 452 and the oxide semiconductor layer 409. The conductive film and the insulating film are formed and etched to form electrode layer 405a and electrode layer 405b. A gate electrode layer 401 and an upper insulating layer 413 are formed in the region that overlaps with the sandwiched region (Figure (See 2(D)).

[0114] The materials for the gate electrode layer 401 are molybdenum, titanium, tantalum, tungsten, and aluminum. Metal materials such as um, copper, chromium, neodymium, scandium, or compounds mainly composed of these materials. It can be formed using gold material. Furthermore, impurities such as phosphorus can be used as the gate electrode layer 401. Semiconductor films, such as polycrystalline silicon films doped with elements, and nickel silicides. A silicide film may also be used. Furthermore, it may contain indium tin oxide and tungsten oxide. Indium oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, acid Conductive materials such as indium tin oxide with added silicon dioxide can also be used. Alternatively, a laminated structure of the above-mentioned conductive material and the above-mentioned metal material can be used.

[0115] Furthermore, a nitrogen-containing metal acid is used as one layer of the gate electrode layer 401 that is in contact with the gate insulating film 452. These are phosphates, specifically In-Ga-Zn-O films containing nitrogen, and In-Sn-O films containing nitrogen. , In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn-O film containing nitrogen Films, nitrogen-containing In-O films, and metal nitride films (InN, SnN, etc.) can be used. These films have a work function of 5 eV or more, preferably 5.5 eV or more, and gate electrodes. When used in this way, the threshold voltage of the transistor's electrical characteristics can be made positive.

[0116] In this embodiment, a tungsten film with a thickness of 100 nm is deposited using the sputtering method. ru.

[0117] The upper insulating layer 413 typically consists of silicon oxide, silicon oxide nitride, and aluminum oxide. Aluminum oxide nitride, silicon nitride, aluminum nitride, silicon oxide nitride, nitride Inorganic insulating materials such as aluminum oxide can be used. Also, the upper insulating layer 413 can be formed by using a CVD method, a sputtering method, or the like.

[0118] In this embodiment, as the upper insulating layer 413, silicon oxynitride is formed to a thickness of 20 0 nm by a CVD method. Thereafter, the upper insulating layer 413 and the gate electrode layer 4 01 are processed into an island shape by a dry etching method. At this time, the gate insulating layer 402 may also be etched together. That's fine.

[0119] Subsequently, using the gate electrode layer 401 and the upper insulating layer 413 as masks, an impurity element 421 is introduced into the oxide semiconductor layer 40 9, and self-aligned low-resistance regions 404a and 404b are formed in a region that does not overlap with the gate electrode layer 401 of the oxide semiconductor layer 409. (Refer to FIG. 3( A)). Note that the region where the impurity element 421 is not introduced becomes the channel formation region 403. That's right.

[0120] Therefore, in the oxide semiconductor layer 409, a channel formation region 403 that overlaps with the gate electrode layer 401 and, sandwiching the channel formation region 403, low-resistance regions 404a and 404b that have a lower resistance than the channel formation region 403 are formed. As a method for introducing the impurity element 421, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

[0121] For the impurity element to be introduced, phosphorus, boron, nitrogen, arsenic, argon, aluminum, or molecular ions containing these can be used. The dose amount of these elements is 1×10 13 ~5×10 ions / cm

[0122] 13 ~5×10 16 ions / cm2 It is preferable to do so. Also, phosphorus as an impurity element. When introducing this system, it is preferable to set the acceleration voltage to 0.5 to 80 kV.

[0122] In this embodiment, phosphorus is introduced as an impurity element.

[0123] The process of introducing impurity elements into the oxide semiconductor layer 409 may be performed multiple times. When the process of introducing impurity elements into the semiconductor layer 409 is performed multiple times, the impurity elements are introduced multiple times. It may be the same throughout, or it may be changed for each processing step.

[0124] By introducing impurity elements, the resistance is reduced in low-resistance regions 404a and 404b. By including an oxide semiconductor layer, the oxide semiconductor layer 409 and the source electrode layer 406a And the resistance of the drain electrode layer 406b becomes smaller. Therefore, the source electrode layer 406a and The electric field near the drain electrode layer 406b is relaxed, and transistor 420 has high ON characteristics. This allows for the creation of a semiconductor device with excellent electrical characteristics, enabling high-speed operation and fast response.

[0125] Furthermore, the introduction of impurity elements may alter the crystal structure of the oxide semiconductor layer. The semiconductor device in this form may use an oxide semiconductor layer with different crystallinity depending on the region. For example, the channel formation region 403 is higher than the low-resistance regions 404a and 404b. It may have crystalline properties. Specifically, the oxide semiconductor of the channel formation region 403 is C The AAC-OS film consists of an electrode layer 405a in the low-resistance region 404a and a low-resistance region 404b and The region in contact with the electrode layer 405b can also be an amorphous film.

[0126] Furthermore, in the case where electrode layer 405a and electrode layer 405b are formed of an oxide semiconductor material In addition, when introducing impurity elements into the oxide semiconductor layer 409, the electrode layer 405a and By introducing impurity elements into 405b, the resistance of both electrode layer 405a and electrode layer 405b is also reduced. This is possible. In the region where the electrode layer 405a and electrode layer 405b have reduced resistance, the oxide Because it is in contact with the semiconductor layer 409, it has low contact resistance and excellent on-characteristics, resulting in a semiconductor device. It is possible.

[0127] Next, an insulating film is formed on the gate electrode layer 401 and the upper insulating layer 413, and the insulating film is etched. This process forms the side wall insulating layer 412a and the side wall insulating layer 412b. Furthermore, the gate electrode layer Using 401 and the side wall insulating layers 412a and 412b as a mask, the gate insulating film 452 is etched. This process forms the gate insulating layer 402 (see Figure 3(B)).

[0128] The side wall insulating layer 412a and the side wall insulating layer 412b are made of the same materials and methods as the upper insulating layer 413. It can be formed using the following. In this embodiment, a silicon oxidnitride film is formed by the CVD method. It is formed to a film thickness of 70 nm.

[0129] Next, oxide semiconductor layer 409, gate insulating layer 402, gate electrode layer 401, side wall insulating layer On 412a, the side wall insulating layer 412b, and the upper insulating layer 413, the source electrode layer and the drain electrode A conductive film is formed that will form polar layers (including wiring etc. formed from the same layers).

[0130] The conductive film can be formed using the same materials and methods as the gate electrode layer 401. In this embodiment, a tungsten film with a thickness of 30 nm is formed by sputtering.

[0131] A resist mask is formed on the conductive film by a photolithography process, and selective etching is performed to form an island-shaped conductive film 406, and then the resist mask is removed (see Fig. 3(C)). In the etching process, the conductive film 406 in the region overlapping with the gate electrode layer 401 is not removed.

[0132] An insulating layer 415 is formed on the island-shaped conductive film 406 (see Fig. 3(D)).

[0133] The insulating layer 415 can be formed using the same materials and methods as the upper insulating layer 413. The insulating layer 415 is formed with a film thickness that can planarize the unevenness caused by the transistor 420. In this embodiment, 500 nm of silicon oxynitride formed by the CVD method is formed.

[0134] Also, the insulating layer 415 may be a single layer or a laminate of different insulating layers. By forming the insulating layer 415 into a laminated structure, as in the transistor 430 shown in Fig. 5(A), a configuration in which an insulating layer 415 and an insulating layer 416 are provided on the source electrode layer 40 6a and the drain electrode layer 406b can be achieved. For example, the insulating layer 416 can be an aluminum oxide layer and the insulating layer 415 can be a silicon oxide layer.

[0135] Next, chemical mechanical polishing is performed on the insulating layer 415 and the conductive film 406, and a part of the insulating layer 415 and the conductive film 406 is removed so that the upper insulating layer 413 is exposed (see Fig. 4(A)).

[0136] By this polishing process, the conductive film 406 overlapping with the gate electrode layer 401 is removed, and the conductive film 4 06 becomes the source electrode layer 406a and the drain electrode layer 406b.

[0137] ​​ The source electrode layer 406a and the drain electrode layer 406b are located on the upper surface of the oxide semiconductor layer 409, and It is provided in contact with the side wall insulating layer 412a or the side wall insulating layer 412b. The region where the drain electrode layer 406a and the drain electrode layer 406b are in contact with the oxide semiconductor layer 409 ( The distance (shortest distance) between the contact region and the gate electrode layer 401 is the distance between the side wall insulating layer 412a and This becomes the width of the channel length direction of the side wall insulating layer 412b, which allows for further miniaturization, as well as the manufacturing process. This allows for better control over the variation in the shortest distance.

[0138] In this embodiment, a chemical-mechanical polishing method was used to remove the insulating layer 415 and the conductive film 406. However, other cutting (grinding, polishing) methods may be used. Also, superimposed on the gate electrode layer 401 In the process of removing the conductive film 406, cutting (grinding, polishing) methods such as chemical mechanical polishing are used. In addition, etching methods (dry etching, wet etching) and plasma treatment are also used. They can be combined. For example, after a removal process by chemical mechanical polishing, dry etching can be performed. The flatness of the treated surface may be improved by applying a cutting or plasma treatment. When the process is carried out in combination with etching, plasma treatment, etc., the order of the processes is not particularly limited. Furthermore, the insulating layer 415 and the conductive film 406 are appropriately configured according to the material, film thickness, and surface irregularities. Just set it.

[0139] In this embodiment, the source electrode layer 406a and the drain electrode layer 406b are Sides of the side wall insulating layer 412a and side wall insulating layer 412b provided on the side surface of the electrode layer 401 It is provided so as to be in contact with the side wall insulating layer 412a and the side wall insulating layer 412b It covers up to a position slightly below the edge. Source electrode layer 406a and drain electrode layer 40 The shape of 6b varies depending on the conditions of the polishing process to remove the conductive film 406, as shown in this embodiment. To that end, the side wall insulating layer 412a, the side wall insulating layer 412b, and the upper insulating layer 413 are polished. In some cases, the shape may be recessed in the film thickness direction from the polished upper surface. However, depending on the polishing treatment conditions... In this case, the upper ends of the source electrode layer 406a and the drain electrode layer 406b are roughly coincided. There are also others.

[0140] Furthermore, in the step of removing the conductive film 406, for example, as shown in Figure 5(B), the upper insulating film A transistor 440 in which the entire marginal layer 413 has been removed, exposing the gate electrode layer 401. This may also be done. Furthermore, a portion of the gate electrode layer 401 may also be removed. Transis In configurations like transistor 440, where the gate electrode layer 401 is exposed, other components are present on transistor 440. It can be used in integrated circuits that stack wiring and semiconductor elements.

[0141] Next, the insulating layer 415, the source electrode layer 406a, the drain electrode layer 406b and the upper insulating layer An insulating layer 417 is formed on 413 (see Figure 4(B)). The insulating layer 417 is the upper insulating layer 4 It can be formed using the same materials and methods as in 13. As the insulating layer 417, dense When a high inorganic insulating layer (typically an aluminum oxide film, etc.) is used, transistor 420 It functions as a protective insulating film.

[0142] In this embodiment, the insulating layer 417 is made of an oxide formed by sputtering. The product of a 50nm luminium film and a 350nm silicon oxidizride film formed by CVD. A layered structure is used.

[0143] Furthermore, after forming the aluminum oxide film, heat treatment may be performed. This provides a function to prevent water or hydrogen from entering the oxide semiconductor layer and to remove oxygen from the oxide semiconductor layer. It has a separation prevention function. Therefore, the oxide semiconductor layer 409, or the insulating layer in contact with it, is the film. It has a region where oxygen exists in excess of the stoichiometric composition (also referred to as the oxygen-rich region). Then, by performing heat treatment with the aluminum oxide film in place, the oxide semiconductor layer In the film, or at the interface between the insulating layer and the oxide semiconductor layer, at least one oxygen-rich region exists. It is possible to provide this.

[0144] Next, in the regions that overlap with electrode layer 405a and electrode layer 405b, respectively, insulating layer 41 7 penetrates the insulating layer 415 and reaches the source electrode layer 406a and the drain electrode layer 406b. Openings 455a and 455b are provided (see Figure 4(C)). The openings are formed using a mask, etc. This is performed by selective etching using [a specific method]. Etching can be done by dry etching or by [another specific method]. The opening may be formed by etching, or by combining both methods. It is sufficient for the electrode to reach the drain electrode layer 406a and the drain electrode layer 406b, and the shape is not particularly limited. However, by making it tapered as shown in Figure 4(C), the wiring that is formed later will be This method is suitable because it allows for the formation of layers without interruption. In this embodiment, the dry etching method is used. To form a larger opening.

[0145] In the process of forming openings 455a and 455b, the insulating layer 417 and insulating layer 415 By cutting, the source electrode layer 406a, the drain electrode layer 406b, or the oxide semiconductor The body layer 409 may also be etched, resulting in a decrease in film thickness. (Transistor of this embodiment) The region overlapping with electrode layer 405a and electrode layer 405b has openings 455a and 455b To form the oxide semiconductor layer 409 and wiring, even if the film thickness decreases due to etching, This allows for electrical connection with the layer.

[0146] Next, a wiring layer 4 is constructed using a conductive material on the openings 455a, 455b and the insulating layer 417. Forms 65a and 465b (see Figure 4(D)). The wiring layers 465a and 465b are as described above. The same material used for the gate electrode layer 401 can be used. This involves sputtering a 50nm titanium film, a 100nm aluminum film, and a titanium film. A 50nm film is formed sequentially.

[0147] The transistor 420 can be manufactured using the above process.

[0148] In the manufacturing process of the transistor shown in this embodiment, the gate electrode layer 401 and the upper insulating layer Conductive film 406 provided on edge layer 413, and side wall insulating layer 412a, and side wall insulating layer 412b By removing it through chemical and mechanical polishing and breaking up the conductive film 406, the source An electrode layer 406a and a drain electrode layer 406b are formed.

[0149] Furthermore, the source electrode layer 406a and the drain electrode layer 406b are located on top of the oxide semiconductor layer 409. It is provided in contact with the surface and the side wall insulating layer 412a or the side wall insulating layer 412b. , the area where the source electrode layer 406a and the drain electrode layer 406b and the oxide semiconductor layer 409 are in contact The distance (shortest distance) between the contact area and the gate electrode layer 401 is the distance between the side wall insulating layer 41 This becomes the width in the channel length direction of 2a and the side wall insulating layer 412b, and further miniaturization can be achieved. This allows for better control over variations in the shortest distance during the manufacturing process.

[0150] Thus, the source electrode layer 406a or the drain electrode layer 406b and the oxide semiconductor layer 40 Because the distance between the region where 9 is in contact and the gate electrode layer 401 can be shortened, the source The region in contact with the electrode layer 406a or the drain electrode layer 406b and the oxide semiconductor layer 409 and The resistance between the gate electrode layers 401 is reduced, improving the on-characteristics of the transistor 420. It is possible.

[0151] Furthermore, in the process of forming the source electrode layer 406a and the drain electrode layer 406b, the gate electrode In the process of removing the conductive film 406 on layer 401, etching using a resist mask is performed. Because no processes are used, precise machining can be performed accurately. Therefore, semiconductor equipment can be manufactured. In the process, transistors with a fine structure that exhibits small variations in shape and characteristics are produced in the yield. It can be manufactured more efficiently.

[0152] Furthermore, the semiconductor device shown in this embodiment involves introducing impurity elements into the oxide semiconductor layer. This forms a low-resistance region, and the source electrode layer and drain electrode layer are in contact with this low-resistance region. This refers to the source electrode layer and the drain region. Therefore, the source electrode layer and the drain electrode layer and the oxide semiconductor The contact resistance of the conductor layer can be reduced. Also, the source region and drain region By providing electrode layers 405a and 405b at the bottom, the source region and drain region This allows for thicker film construction, reducing the resistance of the source and drain regions, and improving the transistor's performance. This can improve the on-characteristics.

[0153] Furthermore, although not shown in the diagram, an insulating layer may be provided on the transistor 420. Typical examples include silicon oxide films, silicon oxide nitride films, aluminum oxide films, and nitrile oxide films. Aluminum oxide film, hafnium oxide film, gallium oxide film, silicon nitride film, aluminum nitride A single layer or Lamination can be used.

[0154] After the formation of the insulating layer, a further heating process may be performed. For example, in air at a temperature of 100°C or higher and 200°C or higher. A heating process may be carried out at a temperature of ℃ or below for a period of 1 hour to 30 hours. This heating process is performed at a constant temperature. You can heat it while maintaining the temperature, or you can heat it from room temperature to a temperature between 100°C and 200°C. The process of raising the temperature and then lowering it from the heating temperature back to room temperature may be repeated multiple times.

[0155] Furthermore, even if a planarizing insulating film is formed to reduce surface irregularities caused by transistor 420 Good. As a planarizing insulating film, there are polyimide, acrylic, benzocyclobutene resins, etc. Materials can be used. In addition to the above organic materials, low-dielectric materials (low-k materials) can also be used. ) etc. can be used. Furthermore, multiple insulating films formed from these materials can be stacked. A planar insulating film may be formed in this manner.

[0156] This embodiment can be combined with other embodiments as appropriate.

[0157] (Embodiment 2) This embodiment describes a semiconductor device according to one aspect of the present invention, which differs from Embodiment 1. In this embodiment, only the differences from Embodiment 1 will be described. Figure 6 shows the differences in this embodiment. Figure 6(A) shows a top view of a semiconductor device in its form. Figure 6(B) is a cross-sectional view of Figure 6(A) along the dashed line B1-B2.

[0158] The semiconductor device including transistor 520 has a substrate 400 with an underlay insulating layer 536 and an underlay insulating layer Electrode layer 505a and electrode layer 505b on edge layer 536, and electrode layer 505a and electrode layer 505 Low-resistance regions 404a and 404b that are in contact with b respectively, and low-resistance region 404a And sandwiched between the low-resistance region 404b, the channel-forming region 403 on the underlying insulating layer 536, The oxide semiconductor layer 409 contains, the gate insulating layer 402 on the oxide semiconductor layer 409, and the gate A gate electrode layer 401 on an insulating layer 402, and a side wall insulating layer 4 covering the side of the gate electrode layer 401. 12a and the side wall insulating layer 412b, and the upper insulating layer 413 that covers the upper surface of the gate electrode layer 401 On the base insulating layer 536 and oxide semiconductor layer 409, there are side wall insulating layers 412a and side wall insulating layers 4 The source electrode layer 406a and drain electrode layer 406b are in contact with the side surface of 12b, and the source electrode Insulating layer 415 on layer 406a and drain electrode layer 406b, insulating layer 415, source electrode Layer 406a, drain electrode layer 406b, side wall insulating layer 412a, side wall insulating layer 412b and above The insulating layer 417 on the insulating layer 413 and the openings provided in the insulating layer 415 and the insulating layer 417 The wiring layers 46 are in contact with the source electrode layer 406a and the drain electrode layer 406b, respectively. It has 5a and wiring layer 465b.

[0159] Low-resistance regions 404a and 404b are electrode layers 505a and 505b and They come into contact with each other. Electrode layer 505a and electrode layer 505b are made of metal, metal compound, and conductive metallized material. It is composed of composites, semiconductors, etc. Low resistance region 404a and low resistance region 404b are transistors It functions as the source and drain regions of the TA520. By providing electrode layers 505a and 505b at the bottom, the source region and drain region This allows for thicker film construction, reducing the resistance of the source and drain regions, and improving the transistor's performance. This can improve the on-characteristics.

[0160] The transistor 520 shown in this embodiment is compared to the transistor 420 shown in Embodiment 1. In comparison, the difference is that electrode layers 505a and 505b are provided on the underlying insulating layer. Since electrode layers 505a and 505b are not embedded in the underlying insulating layer, the transistor The 520 can be manufactured with fewer steps than the 420 transistor.

[0161] This section explains how to manufacture transistor 520.

[0162] First, a base insulating layer 536 is formed on the substrate 400. The base insulating layer 536 is as in Embodiment 1 It can be manufactured using the same materials and manufacturing method as the underlayment insulating layer 436 shown.

[0163] Next, conductive films that will become electrode layers 505a and 505b are fabricated and photolithographed. The electrode layer 505a and electrode layer 505b are formed by selective etching during the process.

[0164] The conductive film that forms electrode layer 505a and electrode layer 505b is electrode layer 405a as shown in Embodiment 1. Furthermore, it can be formed using the same materials and manufacturing methods as the electrode layer 405b. Considering the coverage of the oxide semiconductor layer 409 formed thereon, electrode layer 505a and electrode layer 505 It is preferable that both ends of b be tapered. Also, electrode layer 505a and electrode layer 50 The film thickness of 5b is such that the oxide semiconductor layer 409 that is formed later is electrode layer 505a and electrode layer 505 It is preferable to use a film thickness that is sufficient to adequately cover b.

[0165] Furthermore, after the conductive film is formed, the island-shaped electrode layers 505a and 505b are etched. Before processing, the conductive film may be treated with nitrogen plasma. As a result, electrode layer 505a and electrode layer 505b and the oxide semiconductor layer 409 which is formed later This can reduce the contact resistance.

[0166] Next, oxide semiconductor films are formed on the base insulating layer 536, electrode layer 505a, and electrode layer 505b. The oxide semiconductor film is then processed into island-shaped oxide semiconductor layers 409 by etching. The oxide semiconductor layer 409 is the electrode layer 505a, as shown in the transistor 520 in Figure 6(B). And without covering all of electrode layer 505b, at least a portion of electrode layer 505a and electrode layer 50 The configuration may be such that it is in contact with 5b, or as shown in the transistor 530 in Figure 7, the electrode layer 50 The configuration may also cover all of 5a and the electrode layer 505b.

[0167] The contact area between the oxide semiconductor layer 409 and the electrode layers 505a and 505b is adjusted as appropriate. This allows contact between the oxide semiconductor layer 409 and the electrode layer 505a and electrode layer 505b. The resistance can be set as appropriate. Also, the oxide of electrode layer 505a and electrode layer 505b The region not covered by the semiconductor layer 409 is later formed by the source electrode layer 406a and Drain Each of them may be in contact with the in electrode layer 406b.

[0168] The oxide semiconductor layer 409 is formed by the same method as the materials and manufacturing method shown in Embodiment 1. This can be achieved. Furthermore, the thickness of the oxide semiconductor layer is the electrode layer 505a and electrode layer 505b It is preferable to make it sufficiently thick so that no stepped breaks occur due to this.

[0169] Furthermore, the gate electrode layer 401, upper insulating layer 413, side wall insulating layer 412a, and side wall insulating layer 4 12b, source electrode layer 406a, drain electrode layer 406b, insulating layer 415, insulating layer 417 The method for fabricating wiring layers 465a and 465b is the same as the transistor shown in Embodiment 1. It is manufactured using a similar manufacturing method, and for details, please refer to the description in Embodiment 1. I will omit the explanation.

[0170] In the manufacturing process of the transistor shown in this embodiment, the gate electrode layer 401 and the upper insulating layer Conductive film 406 provided on edge layer 413, and side wall insulating layer 412a, and side wall insulating layer 412b By removing it through chemical and mechanical polishing and breaking up the conductive film 406, the source An electrode layer 406a and a drain electrode layer 406b are formed.

[0171] Furthermore, the source electrode layer 406a and the drain electrode layer 406b are located on top of the oxide semiconductor layer 409. It is provided in contact with the surface and the side wall insulating layer 412a or the side wall insulating layer 412b. , the area where the source electrode layer 406a and the drain electrode layer 406b and the oxide semiconductor layer 409 are in contact The distance (shortest distance) between the contact area and the gate electrode layer 401 is the distance between the side wall insulating layer 41 This becomes the width in the channel length direction of 2a and the side wall insulating layer 412b, and further miniaturization can be achieved. This allows for better control over variations in the shortest distance during the manufacturing process.

[0172] Thus, the source electrode layer 406a or the drain electrode layer 406b and the oxide semiconductor layer 40 Because the distance between the region where 9 is in contact and the gate electrode layer 401 can be shortened, the source The region in contact with the electrode layer 406a or the drain electrode layer 406b and the oxide semiconductor layer 409 and The resistance between the channel formation regions 403 is reduced, improving the on-characteristics of transistor 520. It is possible.

[0173] Furthermore, in the process of forming the source electrode layer 406a and the drain electrode layer 406b, the gate electrode In the process of removing the conductive film 406 on layer 401, etching using a resist mask is performed. Because no processes are used, precise machining can be performed accurately. Therefore, semiconductor equipment can be manufactured. In the process, transistors with a fine structure that exhibits small variations in shape and characteristics are produced in the yield. It can be manufactured more efficiently.

[0174] Furthermore, the semiconductor device shown in this embodiment has a source region and a drain region of an oxide semiconductor layer. By providing electrode layers 405a and 405b at the bottom of the region, the source region and drain This allows for thicker film in the region, reducing the resistance of the source and drain regions, and transitions This can improve the on-performance characteristics of the studs.

[0175] This embodiment can be combined with other embodiments as appropriate.

[0176] (Embodiment 3) In this embodiment, the transistors shown in Embodiment 1 and Embodiment 2 are used, and the power is Semiconductors can retain stored data even when power is unavailable, and have no limitations on the number of write cycles. An example of a device will be described using the drawings. Note that the semiconductor device of this embodiment is a transient The transistor described in Embodiment 1 and Embodiment 2 is used as st162. The transistor 162 is the transistor shown in Embodiment 1 and Embodiment 2. Any of these structures can be applied.

[0177] Figure 8 shows an example of the configuration of a semiconductor device. Figure 8(A) shows a cross-sectional view of the semiconductor device, and Figure 8(B) shows a cross-sectional view of the semiconductor device. Figure 8(C) shows a top view of the semiconductor device, and Figure 8(C) shows a circuit diagram of the semiconductor device. Here, Figure 8(A) corresponds to the cross-sections at C1-C2 and D1-D2 in Figure 8(B). In Figure 8(B), for clarity, a portion of the configuration of the semiconductor device shown in Figure 8(A) is shown. Some elements have been omitted.

[0178] The semiconductor device shown in Figures 8(A) and 8(B) has a transistor made of the first semiconductor material at the bottom. A device having a zista 160 and a transistor 162 on top of which is made of a second semiconductor material. The transistor 162 has the same configuration as shown in Embodiment 1 and Embodiment 2. It can be considered a success.

[0179] Here, the first semiconductor material and the second semiconductor material are materials with different band gaps. Desirable. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistor used is easy to operate at high speed. On the other hand, the transistor using oxide semiconductors Due to its properties, the sta allows for long-term charge retention.

[0180] The above explanation assumes that all transistors are n-channel transistors. However, p-channel transistors can also be used. Furthermore, the technical aspects of the disclosed invention The essence lies in the use of oxide semiconductors in transistor 162 to retain information. This section describes the specific configuration of semiconductor devices, including the materials used and the structure of the semiconductor device. It is not necessary to limit the scope to what is shown here.

[0181] The transistor 160 in Figure 8(A) includes a semiconductor material (e.g., silicon). A channel formation region 116 provided on the substrate 185, and sandwiching the channel formation region 116 An impurity element region 120 is provided therein, and an intermetallic compound region is in contact with the impurity element region 120. 124, a gate insulating layer 108 provided on the channel forming region 116, and a gate insulating layer It has a gate electrode layer 110 provided on 108. Note that in the figure, explicitly, In some cases, the source electrode layer and drain electrode layer may be absent, but for convenience, this condition is included. It is sometimes called a transistor. In this case, the connection relationships of the transistors are explained. Therefore, the source region and drain region are included and referred to as the source electrode layer and drain electrode layer. In other words, in this specification, the term "source electrode layer" includes the source region. Shut up.

[0182] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. Furthermore, an insulating layer 130 is provided so as to cover the transistor 160. To achieve this, as shown in Figure 8(A), transistor 160 is located on the sidewall insulating layer. It is desirable to have a configuration that does not have [this]. On the other hand, in situations where the characteristics of transistor 160 are important In this case, a sidewall insulating layer is provided on the side surface of the gate electrode layer 110, and the concentration of impurity elements differs. The region 120 may include the region of impurities containing such elements.

[0183] The transistor 162 shown in Figure 8(A) is a transistor that uses an oxide semiconductor in the channel formation region. It is a transistor. Here, the oxide semiconductor layer 144 contained in the transistor 162 is high purity It is desirable that it be purified. By using highly purified oxide semiconductors, For the first time, a transistor 162 with excellent off-mode characteristics can be obtained. Transistor 162 is The transistors shown in Embodiment 1 and Embodiment 2 can be applied.

[0184] Transistor 162 has a low off-current, so by using it, it can be used for long-term recording. It is possible to retain the stored content. In other words, it does not require a refresh operation, or This makes it possible to create a semiconductor memory device with an extremely low refresh frequency, Power consumption can be significantly reduced.

[0185] The transistor 162 has an electrode layer 1 that is in contact with the gate electrode layer 110, and is in contact with the insulating layer 130. 43a, electrode layer 143b, and an insulating layer in which electrode layer 143a and electrode layer 143b are embedded. It has layer 145 and

[0186] CMP treatment when exposing the upper surfaces of electrode layer 143a and electrode layer 143b from the insulating layer 145 This allows the oxide semiconductor layer 144 to undergo planarization treatment. The surface to be formed on the body layer 144 is sufficiently flattened (preferably the electrode layer and the underlying insulation layer). The average surface roughness of the upper surface of the margin layer is 0.15 nm or less, and the oxide semiconductor layer 144 has excellent crystallinity. This can be achieved, and the characteristics of transistor 162 can be improved.

[0187] In the manufacturing process, transistor 162 has a gate insulating layer 146 and a gate electrode layer 148. Conductive film provided on the upper insulating layer 137, the side wall insulating layer 136a, and the side wall insulating layer 136b The material is removed by chemical and mechanical polishing to form electrode layer 142a and electrode layer 142b. .

[0188] Therefore, transistor 162 functions as either a source electrode layer or a drain electrode layer. The region where the polar layer 142a and electrode layer 142b and the oxide semiconductor layer 144 are in contact (contact region) ) and the distance between the electrode layer 142a and the gate electrode layer 148 can be shortened, so the electrode layer 142a and the electrode The region where the polar layer 142b and the oxide semiconductor layer 144 are in contact (contact region), and the channel The resistance between the formed regions 144c is reduced, improving the on-characteristics of the transistor 162. It becomes possible.

[0189] In the process of forming electrode layers 142a and 142b, the electrode superimposed on the gate electrode layer 148 In the process of removing the film, an etching process using a resist mask is not used, Precise machining can be performed accurately. Therefore, in the manufacturing process of semiconductor devices, the shape and To manufacture transistors with a fine structure that exhibits small variations in characteristics with high yield. can.

[0190] An insulating layer 135 and an insulating layer 140 are provided on electrode layers 142a and 142b. Furthermore, through the openings provided in the insulating layer 135 and the insulating layer 140, the source electrode layer... or electrode layers 142a and 142b, which function as drain electrode layers, are in contact with each other. Wiring layer 157a and wiring layer 157b are provided. 157b is provided superimposed on electrode layer 143a and electrode layer 143b, respectively.

[0191] The oxide semiconductor layer 144 and the source electrode layer are superimposed on electrode layers 143a and 143b. Or, the electrode layer 142a and electrode layer 142b, which function as a drain electrode layer, are in contact. Therefore, the source and drain regions of the transistor can be made thicker, and oxide semiconductors The contact resistance between layer 144 and the source electrode layer and drain electrode layer can be reduced. This allows for improved on-characteristics of transistor 162.

[0192] Furthermore, the oxide semiconductor layer 144 is subjected to a process that introduces impurity elements, and the gate electricity Using the polar layer 148 as a mask, a process is performed to introduce impurity elements into the oxide semiconductor layer 144. As a result, the oxide semiconductor layer 144 is self-aligned with low-resistance region 144a and low-resistance region 144b. And it forms a channel-forming region 144c.

[0193] Low-resistance regions 144a and 144b have more impurities than channel-forming region 144c. The elemental degree is increasing. By increasing the elemental degree of impurities, the oxide semiconductor layer 144 The carrier density increases, and the electrode layer 142a and electrode layer 142b and oxide semiconductor layer 144 Because the contact resistance between the contacts is reduced, the on-current and mobility are improved, enabling a fast response. .

[0194] An insulating layer 150 is provided on the transistor 162. An electrode layer 156 is provided in the region that overlaps with the wire layer 157a. Electrode layer 156, insulating layer The capacitor element 164 is formed by 150 and the wiring layer 157a. The wiring layer 157a of the zista 162 functions as one electrode of the capacitive element 164, and electrode layer 1 56 functions as the other electrode of the capacitive element 164. Note that if capacitance is not required, It is also possible to omit the capacitance element 164. Alternatively, the capacitance element 164 can be replaced with a separate transistor. It may be installed above the radiator 162.

[0195] In Figures 8(A) and 8(B), transistor 160 and transistor 162 are, At least a portion of it is arranged to overlap, and the source region of transistor 160 and It is preferable that the drain region and a portion of the oxide semiconductor layer 144 overlap. Furthermore, transistor 162 and capacitive element 164 are at least as efficient as transistor 160. It is also provided so as to overlap with a part of it. By adopting this planar layout, Therefore, it is possible to reduce the occupied area of ​​semiconductor devices, thereby enabling higher integration. .

[0196] Next, Figure 8(C) shows an example of a circuit configuration corresponding to Figures 8(A) and 8(B).

[0197] In Figure 8(C), the first wiring (1st Line) and the source power of transistor 160 The polar layer is electrically connected to the second line and transistor 160. The drain electrode layer is electrically connected. Also, the third wiring (3rd Line) The source electrode layer or drain electrode layer of transistor 162 is electrically connected to it. The fourth wire (4th Line) and the gate electrode layer of transistor 162 are electrically connected. They are precisely connected. And the gate electrode layer of transistor 160 and transistor 16 The other of the source electrode layer or drain electrode layer of 2 is electrically connected to one of the electrodes of the capacitive element 164. It is connected to the fifth line and the other electrode of the capacitive element 164 is electrically Connected.

[0198] In the semiconductor device shown in Figure 8(C), the potential of the gate electrode layer of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: .

[0199] This section explains how to write and retain information. First, the potential of the fourth wire is set to transistor 1. The potential is set so that 62 is ON, and transistor 162 is turned ON. This allows, The potential of the third wiring is applied to the gate electrode layer of transistor 160 and the capacitive element 164. In other words, a predetermined charge is applied to the gate electrode layer of transistor 160. (Input). Here, a charge that gives two different potential levels (hereinafter referred to as Low-level charge, H) Let's assume that one of the following is given (referred to as a igh-level charge). Then, the power of the fourth wiring... The voltage is set to a level where transistor 162 is in the off state, and transistor 162 is turned off. By doing so, the charge applied to the gate electrode layer of transistor 160 is retained. retention).

[0200] Because the off-current of transistor 162 is extremely small, the gate electrode layer of transistor 160 The charge is retained for a long time.

[0201] Next, we will explain how to read the information. The first wiring is under the condition that a predetermined potential (constant potential) is applied. Then, when the appropriate potential (readout potential) is applied to the fifth wire, the gate of transistor 160 Depending on the amount of charge held in the electrode layer, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then the gate electrode layer of transistor 160 will have a high level Apparent threshold V when a charge is given th_H This is the gate of transistor 160. Apparent threshold V when a low level charge is applied to the electrode layer th_L twist This is because it becomes lower. Here, the apparent threshold voltage is the voltage at which transistor 160 is turned "on". This refers to the potential of the fifth wiring necessary to achieve the "state". Therefore, the fifth wiring The potential of V th_H and V th_L By setting the potential V0 between these points, transistor 160 The charge applied to the gate electrode layer can be determined. For example, in writing, High-Re If a Bell charge is given, the potential of the fifth wire is V0 (>V th_H ) Transistor 160 turns "on" when a low-level charge is applied. The potential of the fifth wire is V0( <V th_L Even if this happens, transistor 160 will remain "off". The state remains the same. Therefore, by looking at the potential of the second wire, the information that is being held can be determined. It can be read.

[0202] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output the information. In the case of a memory cell that does not read out information, the state of the gate electrode layer Regardless of the state, the potential at which transistor 160 is in the "off state" is, that is, V th_ H A smaller potential can be applied to the fifth wire. Alternatively, regardless of the state of the gate electrode layer, The potential at which transistor 160 is in the "on state" is, V th_L bigger We just need to apply potential to the fifth wire.

[0203] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0204] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0205] Figure 9 also shows another example of the configuration of a semiconductor device. Figure 9(A) is a top view of the semiconductor device. Figure 9(B) is a cross-sectional view of the semiconductor device. Here, Figure 9(B) is E1- This corresponds to the cross-section at E2. Note that in Figure 9(A), for clarity, Figure 9( Some components of the semiconductor device shown in B) have been omitted.

[0206] The semiconductor device shown in Figure 9 has a transistor 162 in which a channel is formed in the oxide semiconductor layer and Channels are formed in layers of semiconductor materials other than oxide semiconductors (e.g., silicon). It has a transistor 160 and a capacitive element 164. Note that transistor 162 and The configuration of the converter 160 is the same as that of the semiconductor device shown in Figure 8, so a detailed explanation is omitted. To abbreviate.

[0207] In Figure 9, the capacitive element 164 consists of an electrode layer 143b, an oxide semiconductor layer 144, and an insulating layer 173 It consists of a gate electrode layer 148 and a conductive layer 174. The conductive layer 174 is manufactured in the same process as the gate electrode layer 148. It is manufactured and its top surface is covered with an insulating film 176, and its sides are covered with side wall insulating layers 175a and 175b.

[0208] The oxide semiconductor layer 144 uses the gate electrode layer 148 and the conductive layer 174 as a mask to filter out impurities. By introducing this element, in the region that does not overlap with the gate electrode layer 148 and the conductive layer 174, It forms a self-aligned low-resistance region. The electrodes function as source electrode layer and drain electrode layer. The polar layer 142a and electrode layer 142b are in contact with the low-resistance region of the oxide semiconductor layer 144 and transition Since it functions as the source and drain regions of sta 162, the oxide semiconductor layer 144 and The contact resistance between the source electrode layer and the drain electrode layer is reduced.

[0209] Furthermore, the electrode layer 14 is in contact with the lower part of the low-resistance region which functions as the source region and drain region. 3a and electrode layer 143b are provided. Therefore, the source region and drain region are The film is made thicker, and the resistance between the oxide semiconductor layer 144 and the source electrode layer and drain electrode layer is reduced. It can be done.

[0210] The electrode layer 142b of transistor 162 is an electrode layer formed on the insulating layer 135 and insulating layer 150. At the opening reaching 142b, it is electrically connected to the electrode layer 156. Also, the electrode layer 143 A conductive layer 172 is provided in contact with the bottom of a, and extends to the source electrode layer of transistor 160. Alternatively, the drain electrode layer and the source electrode layer or drain electrode layer of transistor 162 are connected. They are connected by energy.

[0211] As shown in Figure 9, transistor 160, transistor 162, and capacitive element 164 are superimposed. By densely stacking them in this manner, the occupied area of ​​the semiconductor device can be further reduced. Therefore, it is possible to achieve high integration.

[0212] In this embodiment, the transistor 162 is formed with the electrode layer in contact with the lower part of the oxide semiconductor layer. Furthermore, by using the gate electrode layer as a mask to introduce impurity elements into the oxide semiconductor layer, Such transistors exhibit good electrical characteristics and can sufficiently reduce off-current. By using a zista, a semiconductor device can retain its memory contents for an extremely long period of time. You can obtain this.

[0213] Transistors like the ones described above have high on-characteristics (e.g., on-current), enabling high-speed operation and high-speed response. The answer is possible. Furthermore, miniaturization can also be achieved. Therefore, by using this transistor, high We can provide high-performance and highly reliable semiconductor devices.

[0214] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0215] (Embodiment 4) In this embodiment, the transistors shown in Embodiment 1 and Embodiment 2 are used. It can retain stored data even when power is not supplied, and there is no limit to the number of write cycles. Regarding the semiconductor device, a configuration different from the one shown in Embodiment 3 is shown in Figures 10 to 10. The explanation will be given using 13. Note that the semiconductor device in this embodiment is a transistor 162. Therefore, either transistor structure shown in Embodiment 1 and Embodiment 2 can be applied. can.

[0216] Figure 10(A) shows an example of a semiconductor device circuit configuration, and Figure 10(B) shows an example of a semiconductor device. This is a conceptual diagram illustrating the concept. First, we will explain the semiconductor device shown in Figure 10(A), and then... The semiconductor device shown in Figure 10(B) will be described below.

[0217] In the semiconductor device shown in Figure 10(A), the bit line BL and the source power of transistor 162 The polar layer or drain electrode layer is electrically connected to the word line WL and transistor 162. It is electrically connected to the gate electrode layer and is the source electrode layer or drain of transistor 162. The electrode layer and the first terminal of the capacitive element 254 are electrically connected.

[0218] The oxide semiconductor transistor 162 has the characteristic of having an extremely low off-current. Therefore, by turning off transistor 162, the first capacitive element 254 The potential of the terminal (or the charge accumulated in the capacitive element 254) over an extremely long period of time It is possible to hold it.

[0219] Next, information is written to and stored in the semiconductor device (memory cell 250) shown in Figure 10(A). This explains how to perform this action.

[0220] First, the potential of the word line WL is set to the potential at which transistor 162 turns ON. Turn on the zistor 162. This will change the potential of the bit line BL to that of the capacitive element 254. The first terminal is supplied (written). Then, the potential of the word line WL is set to transistor 1. By setting transistor 162 to the OFF state, which is the potential at which 62 is OFF, The potential of the first terminal of the quantitative element 254 is maintained (held).

[0221] Since the off-current of transistor 162 is extremely small, the potential of the first terminal of capacitive element 254 (Or the charge stored in a capacitive element) can be retained for a long period of time.

[0222] Next, we will explain how to read the information. When transistor 162 is turned on, floating In this state, the bit line BL and the capacitive element 254 are conductive, and the bit line BL and the capacitive element 254 Charge is redistributed between them. As a result, the potential of bit line BL changes. The change in position is the potential of the first terminal of the capacitive element 254 (or the potential stored in the capacitive element 254). It takes on different values ​​depending on the charge.

[0223] For example, let V be the potential of the first terminal of the capacitive element 254, C be the capacitance of the capacitive element 254, and let C be the bit line The capacitance component of BL (hereinafter also called bit line capacitance) is called CB, and the capacitance before charge redistribution. If the potential of bit line BL is VB0, then the potential of bit line BL after charge redistribution is: The formula becomes (CB × VB0 + C × V) / (CB + C). Therefore, the memory cell state is 250. And, assuming that the potential of the first terminal of the capacitive element 254 takes two states, V1 and V0 (V1 > V0) Then, the potential of the bit line BL when the potential V1 is maintained is (=CB × VB0 + C × V1) / (CB+C) is the potential of the bit line BL when the potential V0 is maintained (=CB×VB0 It can be seen that this is higher than (+C × V0) / (CB + C)).

[0224] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. ru.

[0225] Thus, in the semiconductor device shown in Figure 10(A), the off-current of transistor 162 is extremely low. Due to its small size, the charge stored in the capacitive element 254 can be retained for a long time. This means that refresh operations become unnecessary, or the frequency of refresh operations decreases. Because the temperature can be reduced to an extremely low level, power consumption can be significantly reduced. Furthermore, it is possible to retain the stored data for a long period of time even without a power supply. be.

[0226] Next, we will explain the semiconductor device shown in Figure 10(B).

[0227] The semiconductor device shown in Figure 10(B) has a memory circuit at the top, as shown in Figure 10(A). The memory cell array 251a and memory cell array 251b each have multiple units 250. At the bottom, memory cell array 251 (memory cell array 251a and memory cell array 25 It has peripheral circuits 253 necessary to operate 1b). Note that peripheral circuits 253 are It is electrically connected to the Morisel array 251.

[0228] By using the configuration shown in Figure 10(B), the peripheral circuit 253 is connected to the memory cell array 251. It can be installed directly below (memory cell array 251a and memory cell array 251b). Therefore, it is possible to miniaturize semiconductor devices.

[0229] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material than transistor 162. It is preferable to use silicon, germanium, silicon germanium, Silicon carbide or gallium arsenide can be used, and single-crystal semiconductors can be used. Preferred. Alternatively, organic semiconductor materials may be used. The transistor is capable of high-speed operation. Therefore, the transistor enables high It is possible to suitably realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation. be.

[0230] In the semiconductor device shown in Figure 10(B), there are two memory cell arrays 251 (memory cells Although a configuration in which a memory cell array 251a and a memory cell array 251b are stacked was illustrated, The number of memory cells is not limited to this. That's good too.

[0231] Next, the specific configuration of the semiconductor device shown in Figure 10 will be explained using Figure 11.

[0232] Figure 11 is a cross-sectional view of a semiconductor device. The semiconductor device shown in Figure 11 has multiple layers formed on the top. It has multiple memory cell arrays 251 and peripheral circuits 253 at the bottom. I251 and peripheral circuit 253 are electrically connected. Figure 11 shows multiple memory cells. Of the arrays, there is memory cell array 251a, memory cell array 251b, and peripheral circuit 253 These are representative examples.

[0233] The transistor 162a and the capacitive element 254a included in the memory cell array 251a, The electrode layer 343c of the Moricell array 251a, which connects to other memory cells, is shown as a representative example. The transistor 162a is a transistor in which a channel is formed in the oxide semiconductor layer. The transistor 162a is adapted to the transistor described in Embodiment 1 and Embodiment 2. Since it can be used, the explanation will be omitted. Capacitive element 254a is transistor 162a It is formed using the source electrode layer and electrodes formed in the same layer as the wiring layer. Electrode layer 3 43c is formed in the same layer as electrode layers 143a and 143b of transistor 162a. It will be accomplished.

[0234] The transistor 162b and the capacitive element 254b included in the memory cell array 251b, The Molycell array 251b has an electrode layer 343b that connects to other memory cells, and the memory cell array A typical example shows the electrode layer 343a connecting I251b and the peripheral circuit 253. Transistor 162b is a transistor in which a channel is formed in the oxide semiconductor layer. Transistor 1 62b applies the transistors described in Embodiment 1 and Embodiment 2. Since this can be done, the explanation will be omitted. Capacitive element 254b is the source power of transistor 162b It is formed using electrodes formed in the same layer as the polar layer and the wiring layer. The electrode layer 343b is It is formed in the same layer as wiring layers 157a and 157b of the transistor 162b. The electrode layer 343a is connected to the electrode layer 143a and electrode layer 143b of the transistor 162b. They are formed in the same layer.

[0235] The peripheral circuit 253 uses a semiconductor material other than the oxide semiconductor layer as the channel formation region. It has a transistor 301. The transistor 301 is made of a semiconductor material (e.g., silicon). A substrate 300 containing the element is provided with an element isolation insulating layer, and the region surrounded by the element isolation insulating layer 306 is provided with A transistor can be obtained by forming a region that will become a channel.

[0236] Furthermore, transistor 301 has a semiconductor layer such as a silicon layer formed on an insulating surface, and SO It may also be a transistor in which a channel is formed in the silicon layer of the substrate. For the configuration of 301, known configurations can be used.

[0237] A wiring layer 310a is formed between the peripheral circuit 253 and the memory cell array 251b. An insulating layer 341a is provided between the peripheral circuit 253 and the wiring layer 310a, and the wiring layer 3 An insulating layer 341b is provided between 10a and the memory cell array 251b. Layer 341a contains a wiring layer 355a which electrically connects the peripheral circuit 253 and the wiring layer 310a. A wiring layer 310a and a memory cell array 25 are provided in the insulating layer 341b. A wiring layer 355b is provided that electrically connects to 1b.

[0238] Furthermore, the peripheral circuit 253 and the memory cell array 251b are electrically connected via the wiring layer 310a. Although the configuration was designed for connection, the method of connecting the peripheral circuit 253 and the memory cell array 251b is as follows: Not limited to. The peripheral circuit 253 and the memory cell array 251b include transistor 301 and Although it is electrically connected to transistor 162b in a region that does not overlap, this is not limited to this. No. For example, the electrode layer 143a and electrode layer 143b of transistor 162b and the surrounding area The circuit 253 may be configured to be in direct contact with the other circuit.

[0239] A wiring layer 310b is located between the memory cell array 251a and the memory cell array 251b. It is formed. The wiring layer 310b is an insulating layer provided within the memory cell array 251b. It is located on layer 341c. Between wiring layer 310b and memory cell array 251a An insulating layer 341d is provided. The insulating layer 341c contains the wiring layer 310b and the memory cell A wiring layer 355c is provided to electrically connect to the layer 251b. The wiring layer 355d electrically connects the wiring layer 310b and the memory cell array 251a. It is provided.

[0240] By adopting the layout shown in Figure 11, the occupied area of ​​the semiconductor device can be reduced. This allows for higher integration.

[0241] Furthermore, Figures 12 and 13 show the structure of a semiconductor device that can be applied to the memory cell 250 shown in Figure 10. Another example of the configuration is shown. Figure 12(A) is a top view of a semiconductor device, and Figure 12(B) is a semiconductor device. This is a cross-sectional view. Here, Figure 12(B) shows the cross-section at F1-F2 in Figure 12(A) This applies. Note that in Figure 12(A), for clarity, the semiconductor shown in Figure 12(B) is used. Some components of the device have been omitted.

[0242] The memory cell shown in Figure 12 is a transistor 162 in which a channel is formed in the oxide semiconductor layer. It also has a capacitive element 254. The configuration of the transistor 162 is as shown in Figure 8. Since it is similar to transistor 162 in the device, a detailed explanation will be omitted.

[0243] In Figure 12, the capacitive element 254 consists of an electrode layer 143b, an oxide semiconductor layer 144, and an insulating layer 17 3 and a conductive layer 174 are formed in the same process as the gate electrode layer 148. The fabricated surface is coated with an insulating film 176 on the top surface, and sidewall insulating layers 175a and 175b on the sides. It is covered.

[0244] The oxide semiconductor layer 144 uses the gate electrode layer 148 and the conductive layer 174 as a mask to filter out impurities. By introducing this element, in the region that does not overlap with the gate electrode layer 148 and the conductive layer 174, It forms a self-aligned low-resistance region. The electrodes function as source electrode layer and drain electrode layer. The polar layer 142a and electrode layer 142b are in contact with the low-resistance region of the oxide semiconductor layer 144 and transition Since it functions as the source and drain regions of sta 162, the oxide semiconductor layer 144 and The contact resistance between the source electrode layer and the drain electrode layer is reduced.

[0245] The electrode layer 142b of transistor 162 is an electrode layer formed on the insulating layer 135 and insulating layer 150. At the opening reaching 142b, it is electrically connected to the wiring 260.

[0246] Figure 13(A) is a top view of the semiconductor device, and Figure 13(B) is a cross-sectional view of the semiconductor device. Therefore, Figure 13(B) corresponds to the cross-section at G1-G2 in Figure 13(A). Note that Figure 13 In (A), for clarity of the diagram, some of the components of the semiconductor device shown in Figure 13(B) are shown. It has been omitted.

[0247] The memory cell shown in Figure 13 is a transistor 162 in which a channel is formed in the oxide semiconductor layer. It also has a capacitive element 254. The configuration of the transistor 162 is shown in Figure 8. Since it is the same as Sta162, a detailed explanation will be omitted.

[0248] In Figures 13(A) and (B), the capacitive element 254 consists of a conductive layer 192, an insulating layer 193, and a conductive layer. It is composed of layer 194 and formed in insulating film 196. The insulating layer 193 has a dielectric constant It is preferable to use a highly insulating material. The capacitive element 254 and the transistor 162 are insulated from each other. Electrode layer 1 of transistor 162 formed on layer 135, insulating layer 150, and insulating layer 195 They are electrically connected via a conductive layer 191 provided in the opening that reaches 42b.

[0249] The oxide semiconductor layer 144 introduces impurity elements using the gate electrode layer 148 as a mask. Then, in the region that does not overlap with the gate electrode layer 148, a self-aligned low-resistance region is formed. Electrode layers 142a and 142b, which function as the source electrode layer and drain electrode layer, The low-resistance region of the oxide semiconductor layer 144 is in contact with the source region and drain region of the transistor 162. In order to function as a region, the oxide semiconductor layer 144, the source electrode layer and the drain electrode layer The contact resistance is reduced.

[0250] As shown in Figures 12 and 13, the transistor 162 and the capacitive element 254 are densely superimposed. By stacking them, the occupied area of ​​the semiconductor device can be further reduced, thus enabling high It is possible to integrate the resources.

[0251] As described above, the multiple memory cells formed in multiple layers on top use an oxide semiconductor. Formed by a transistor. A transistor using a highly purified and intrinsically purified oxide semiconductor. Because the inverter has a low off-current, it can be used to preserve stored data over a long period of time. It is possible to maintain this. In other words, it is possible to make the frequency of refresh operations extremely low. Therefore, power consumption can be significantly reduced.

[0252] Thus, transistors using materials other than oxide semiconductors (in other words, sufficiently high-speed operation) A peripheral circuit using transistors capable of operation, and a transistor using oxide semiconductors ( In a broader sense, it integrates a memory circuit using a transistor with a sufficiently low off-current. This makes it possible to realize a semiconductor device with unprecedented features. By using a stacked structure for the paths and memory circuits, it is possible to integrate semiconductor devices.

[0253] In this embodiment, the transistor 162 is formed with the electrode layer in contact with the lower part of the oxide semiconductor layer. Furthermore, by using the gate electrode layer as a mask to introduce impurity elements into the oxide semiconductor layer, Such transistors exhibit good electrical characteristics and can sufficiently reduce off-current. By using a zista, a semiconductor device can retain its memory contents for an extremely long period of time. You can obtain this.

[0254] Transistors like the ones described above have high on-characteristics (e.g., on-current), enabling high-speed operation and high-speed response. The answer is possible. Furthermore, miniaturization can also be achieved. Therefore, by using this transistor, high We can provide high-performance and highly reliable semiconductor devices.

[0255] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. That is the case.

[0256] (Embodiment 5) In this embodiment, the semiconductor device shown in the previous embodiment is used in a mobile phone, smartphone, and other electronic devices. Examples of applications to portable devices such as children's books will be explained using Figures 14 to 17.

[0257] In mobile devices such as cell phones, smartphones, and e-readers, temporary storage of image data SRAM or DRAM is used in these applications. The reason is that flash memory has a slow response time and is unsuitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics apply: ru.

[0258] In a typical SRAM, as shown in Figure 14(A), one memory cell is located in transistor 801~ It consists of six 806 transistors, which are used for the X decoder 807 and the Y decoder. It is driven by transistors 803, 805, and 808. 04 and transistor 806 form an inverter, enabling high-speed drive. However, 1 Because each memory cell is composed of 6 transistors, it has the disadvantage of having a large cell area. Yes. When the minimum dimension of the design rule is F, the memory cell area of ​​SRAM is usually 10 0-150F 2 Therefore, SRAM has a high cost per bit.

[0259] In contrast, DRAM has a memory cell, as shown in Figure 14(B), transistor 811, It is composed of a holding capacity 812, which is then used by the X decoder 813 and the Y decoder 814. It is in operation. Each cell has a configuration of 1 transistor and 1 capacitance, resulting in a small area. The memory cell area of ​​DRAM is typically 10F 2 The following applies. However, DRAM is always refreshed. A shutdown is required, and power is consumed even if no rewriting is performed.

[0260] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Front and back Furthermore, frequent refreshing is unnecessary. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0261] Figure 15 shows a block diagram of the portable device. The portable device shown in Figure 15 has an RF circuit 901, analog Baseband circuit 902, digital baseband circuit 903, battery 904, power supply Circuit 905, application processor 906, flash memory 910, display Controller 911, memory circuit 912, display 913, touch sensor 919, It consists of an audio circuit 917, a keyboard 918, etc. The display 913 displays It consists of part 914, source driver 915, and gate driver 916. The Revision Processor 906 consists of CPU 907, DSP 908, and Interface (IF) ) has 909. Generally, the memory circuit 912 is composed of SRAM or DRAM. Furthermore, by employing the semiconductor device described in the previous embodiment in this part, information It offers high-speed writing and reading, long-term memory retention, and significantly reduced power consumption. We can provide the mobile devices that have been modified.

[0262] Figure 16 shows that the semiconductor device described in the previous embodiment is used in the memory circuit 950 of the display. An example of its use is shown. The memory circuit 950 shown in Figure 16 includes memory 952, memory 953, and switch It consists of a switch 954, a switch 955, and a memory controller 951. The memory circuit 950 receives image data (input image data) from the signal line, and the memory 9 The data (storage image data) stored in 52 and memory 953 is read and controlled. The display controller 956 and the signals from the display controller 956 A display 957 is connected to show the display.

[0263] First, some image data is formed by an application processor (not shown). (Input image data A). Input image data A is sent to memory 952 via switch 954. It is stored. And the image data stored in memory 952 (stored image data A) is... The signal is sent to the display 957 via the switch 955 and the display controller 956. , it will be displayed.

[0264] If there are no changes to the input image data A, the stored image data A is typically stored at a frequency of about 30-60 Hz. During this period, the memory 952 is read from the display controller 956 via the switch 955. To be revealed.

[0265] Next, for example, when a user performs an operation to rewrite the screen (i.e., input image data A If there are any changes, the application processor will use the new image data (input image data). Form B). Input image data B is stored in memory 953 via switch 954. During this time, the stored image data A was periodically read from memory 952 via switch 955. It is being done. When the new image data (storage image data B) has finished being stored in memory 953, From the next frame on display 957, stored image data B is read out, and switch 95 5. The stored image data is sent to the display 957 via the display controller 956. Data B is sent and displayed. This read then memos new image data. This continues until it is stored in RI952.

[0266] In this way, memory 952 and memory 953 alternately write image data, and image data By reading from this, the display 957 will display the information. Note that memory 9 Memory 52 and memory 953 are not limited to separate memory locations, but can be used by dividing a single memory location. It may be used. The semiconductor device described in the previous embodiment can be used in memory 952 and memory 953. By adopting this method, information can be written and read at high speed, and long-term memory retention is possible. Furthermore, power consumption can be significantly reduced.

[0267] Figure 17 shows a block diagram of the e-book. Figure 17 shows battery 1001 and power supply circuit 1002. Microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard Code 1006, memory circuit 1007, touch panel 1008, display 1009, It is comprised of a display controller 1010.

[0268] Here, the memory circuit 1007 in Figure 17 uses the semiconductor device described in the previous embodiment. It is possible. The memory circuit 1007 has the function of temporarily holding the contents of the book. For example If the user uses the highlight function, the memory circuit 1007 will specify It remembers and retains information about the highlighted sections. The highlighting function allows the user to read ebooks... When you're doing this, you can mark specific areas, for example, by changing the display color or underlining. Marking can be done by drawing lines, making the letters bold, or changing the font to make it stand out from the surroundings. The goal is to demonstrate that the memory circuit 1007 is used for storing short-term information and long-term information. To store the data, copy the data held by the memory circuit 1007 to the flash memory 1004. It is also possible to use the semiconductor device described in the previous embodiment. This allows for high-speed writing and reading of information, long-term memory retention, and This allows for a significant reduction in power consumption.

[0269] As described above, the portable device shown in this embodiment is equipped with the semiconductor device according to the previous embodiment. It is listed. Therefore, it has high read speed, can retain data for long periods, and consumes low power. Portable devices with reduced noise levels will be realized.

[0270] The configurations and methods shown in this embodiment can be appropriately combined with the configurations and methods shown in other embodiments. They can be used together. [Explanation of symbols]

[0271] 106 Element isolation insulating layer 108 Gate Insulation Layer 110 Grid Layer 116 Channel formation region 120 Impurity element area 124 Intermetallic compound area 130 Insulating layer 135 Insulating layer 136a Sidewall insulation layer 136b Sidewall insulating layer 137 Upper insulating layer 140 Insulating layer 142a Electrode layer 142b Electrode layer 143a Electrode layer 143b Electrode layer 144 Oxide semiconductor layer 144a Low resistance area 144b Low resistance region 144c channel formation region 145 Insulating layer 146 Gate Insulation Layer 148 Guard Layer 150 Insulating layer 156 Electrode layer 157a wiring layer 157b Wiring layer 160 transistors 162 transistors 162a Transistor 162b Transistor 164 Capacitive elements 172 Conductive layer 173 Insulating layer 174 Conductive layer 175a Sidewall insulation layer 175b Sidewall insulation layer 176 Insulating film 185 circuit boards 191 Conductive layer 192 Conductive layer 193 Insulating layer 194 Conductive layer 195 Insulating layer 196 Insulating film 250 memory cells 251 memory cell array 251a Memory Cell Array 251b Memory Cell Array 253 Peripheral Circuits 254 Capacitive elements 254a Capacitive element 254b Capacitive element 260 Wiring 300 circuit boards 301 Transistors 306 Element Isolation Insulating Layer 310a wiring layer 310b wiring layer 341a Insulating layer 341b Insulating layer 341c insulating layer 341d insulating layer 343a Electrode layer 343b Electrode layer 343c electrode layer 355a wiring layer 355b wiring layer 355c wiring layer 355d wiring layer 400 circuit boards 401 Guard Layer 402 Gate Insulation Layer 403 Channel formation region 404a Low resistance area 404b Low resistance region 405a Electrode layer 405b Electrode layer 406 Conductive film 406a Source electrode layer 406b Drain electrode layer 409 Oxide semiconductor layer 412a Sidewall insulation layer 412b Sidewall insulation layer 413 Upper insulating layer 415 Insulating layer 416 Insulating layer 417 Insulating layer 420 transistors 421 Impurity elements 430 transistors 435 Undercoat Insulating Film 436 Underlayment Insulation Layer 440 transistors 452 Gate Insulator 455a aperture 455b aperture 465a Wiring layer 465b Wiring layer 505a Electrode layer 505b Electrode layer 520 transistors 530 transistors 536 Underlayment Insulation Layer 801 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistors 807 X Decoder 808 Y Decoder 811 Transistors 812 holding capacity 813 X Decoder 814 Y Decoder 901 RF circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power supply circuit 906 Application Processor 907 CPU 908 DSP 910 Flash Memory 911 Display Controller 912 memory circuit 913 Display 914 Display section 915 Source Driver 916 Gate Driver 917 Audio Circuit 918 Keyboard 919 Touch Sensor 950 memory circuit 951 Memory Controller 952 memory 953 memory 954 Switch 955 Switch 956 Display Controller 957 displays 1001 Battery 1002 Power supply circuit 1003 Microprocessor 1004 Flash Memory 1005 Audio Circuit 1006 Keyboard 1007 Memory Circuit 1008 Touch Panel 1009 Display 1010 Display Controller

Claims

[Claim 1] A pair of electrode layers, An oxide semiconductor layer comprising a pair of low-resistance regions on the pair of electrode layers that are in contact with the pair of electrode layers, and a channel-forming region sandwiched between the pair of low-resistance regions, The gate insulating layer on the oxide semiconductor layer, A gate electrode layer superimposed on the channel formation region on the gate insulating layer, The upper insulating layer on the gate electrode layer, A side wall insulating layer covering the side surface of the gate electrode layer and the side surface of the upper insulating layer, The oxide semiconductor layer, the source electrode layer and drain electrode layer in contact with the side surface of the gate insulating layer and the side surface of the side wall insulating layer, The first insulating layer on the source electrode layer and the drain electrode layer, The upper insulating layer, the side wall insulating layer, the source electrode layer, and the second insulating layer on the drain electrode layer, The first insulating layer and the second insulating layer have a pair of wiring layers that are in contact with the source electrode layer or the drain electrode layer through openings provided in the first insulating layer and the second insulating layer, The height of the upper surfaces of the source electrode layer and the drain electrode layer is lower than the height of the upper insulating layer, the side wall insulating layer, and the first insulating layer, and higher than the height of the upper surface of the gate electrode layer. The pair of wiring layers are superimposed on the pair of electrode layers in a semiconductor device.

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