Semiconductor equipment

Abstract

To provide a semiconductor device that prevents electrical connection failures and crack formation. [Solution] The semiconductor device S100 comprises a semiconductor chip 10, a wiring board 50 on which the semiconductor chip 10 is mounted, and a conductive columnar structure 20 disposed between the electrode portion of the semiconductor chip 10 and the wiring board 50, wherein the columnar structure 20 and the wiring board 50 are fixed together by a dissimilar material bonding material having an intermetallic bond.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In recent years, in order to cope with the miniaturization of electrode pads, a structure in which Cu pillars are formed on an electrode pad and the Cu pillars and the electrode pad are connected by solder has been put into practical use. For example, in Patent Document 1, in order to prevent the solder from being disconnected by voids formed in the solder, a configuration in which the thickness of the solder layer (SnAg) is 20 μm or less has been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the solder layer is relatively thin as in the configuration of Patent Document 1, there are problems such as poor electrical connection and cracks in the solder layer due to the warping of the substrate and the influence of coplanarity.

[0005] Therefore, the present invention has been made in view of these points, and an object thereof is to provide a semiconductor device that prevents the occurrence of poor electrical connection and cracks.

Means for Solving the Problems

[0006] A semiconductor device according to an aspect of the present invention includes a semiconductor chip, a wiring substrate on which the semiconductor chip is mounted, and a conductive columnar structure disposed between an electrode portion of the semiconductor chip and the wiring substrate, the columnar structure having a height of 40 μm or less, and the columnar structure and the wiring substrate are fixed by a joining material for joining different materials having an intermetallic bond.

[0007] The dissimilar material bonding material is formed to connect the electrode portion of the semiconductor chip and the electrode portion of the wiring substrate, and the thickness of the dissimilar material bonding material may be 5 μm or more and 40 μm or less.

[0008] The aforementioned dissimilar material bonding material may be a material having an intermetallic compound in a matrix containing a Sn-Cu alloy, or sintered Ag.

[0009] The material of the columnar structure is Cu, and a Ni layer may be formed on one or both ends of the columnar structure.

[0010] The material of the columnar structure is Cu, and a Pd film may be formed at the interface between the columnar structure and the dissimilar material bonding material.

[0011] The wiring substrate further comprises an insulating resin layer filled between the semiconductor chip and the wiring substrate, the wiring substrate being formed below the semiconductor chip and having a heat dissipation path for releasing heat from the resin layer to the outside.

[0012] The wiring board, in a plan view of the semiconductor device as seen from the side on which the semiconductor chip is mounted, has electrodes electrically connected to the semiconductor chip and located outside the semiconductor chip, and vias extending from the electrodes in the thickness direction of the wiring board, wherein a plating with a thickness of 1 / 4 or more of the via's hole diameter is formed inside the via, and a conductive resin paste may be filled in the center. [Effects of the Invention]

[0013] The present invention provides a semiconductor device that prevents electrical connection failures and crack formation. [Brief explanation of the drawing]

[0014] [Figure 1] This is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. [Figure 2]This is a schematic diagram showing an example of a columnar structure. [Figure 3] This figure shows an example of the manufacturing process for semiconductor devices. [Figure 4] This figure shows a modified example of a semiconductor device. [Figure 5] This figure shows other variations of a semiconductor device. [Modes for carrying out the invention]

[0015] Embodiments of the present invention will be described below with reference to the drawings. Figure 1 is a cross-sectional view showing the configuration of the semiconductor device of this embodiment. Figure 2 is a schematic diagram showing an example of a columnar structure.

[0016] As shown in Figure 1, the semiconductor device S100 comprises a semiconductor chip 10, a wiring board 50, a columnar structure 20, a bonding material 30, and a filler resin 40. The columnar structure 20 and the bonding material 30 are provided at multiple locations on the semiconductor device S100, but since they all have similar connection structures, only one connection structure will be described below as an example.

[0017] The semiconductor chip 10 is a device mounted as a flip chip on a wiring board 50. The semiconductor chip 10 has a silicon substrate 11 and is provided with a polyimide layer 12 and an Al layer 13. The polyimide layer 12 is a layer formed on the lower surface of the silicon substrate 11 and is formed on the circuit surface of the chip. The polyimide layer 12 may be single-phase or multiple layers. The Al layer 13 is an electrode portion formed on the semiconductor chip 10.

[0018] The wiring board 50 is a board on which the semiconductor chip 10 is mounted. In this example, the wiring board 50 is a ceramic board or a resin board. A resist 51 and an electrode portion 52 are formed on the wiring board 50. The resist 51 is a protective layer having electrical insulation formed on the upper surface of the wiring board 50. The electrode portion 52 is formed on the upper surface of the wiring board 50 so as to be exposed from a part of the resist 51. In this example, a Ni plating 53 is formed on the surface of the electrode portion 52. An electrode Au plating 55 is formed on the lower surface (back surface) of the wiring board 50.

[0019] The columnar structure 20 is a conductive member. The columnar structure 20 is, for example, a Cu pillar. The columnar structure 20 may be a cylindrical shape as shown in Fig. 2(a) or a cylindrical shape with a step as shown in Fig. 2(b). The columnar structure 20 is disposed between the Al layer 13 which is an electrode portion of the semiconductor chip 10 and the wiring board 50. One end of the columnar structure 20 is formed so as to contact the Al layer 13. The columnar structure 20 extends from the semiconductor chip 10 toward the wiring board 50 side, and its tip is formed so as to protrude from the polyimide layer 12. A Ni plating 21 is formed on the surface of the columnar structure 20. The height of the columnar structure 20 is preferably, for example, 40 μm or less, and more preferably 20 μm or less. In one example, the height of the columnar structure 20 may be 10 μm or more and 20 μm or less. As an effect of the columnar structure 20 having the above-described height, the semiconductor device S100 can be made thinner, and heat from the semiconductor chip 10 can be favorably transmitted to the wiring board 50 to improve heat dissipation.

[0020] The bonding material 30 is a member for fixing the columnar structure 20 and the wiring board 50. The bonding material 30 is a bonding material between dissimilar materials having an intermetallic bond. The thickness of the bonding material 30 is 5 μm or more and 40 μm or less. The thickness of the bonding material 30 is preferably 20 μm or more and 40 μm or less. The bonding material 30 is formed so as to contact the Ni plating 53 and is electrically connected to the electrode portion 52 of the wiring board 50. Thereby, the semiconductor chip 10 is electrically connected to the circuit of the wiring board 50.

[0021] The bonding material 30 is, as an example, a material having an intermetallic compound in a matrix phase containing a Sn-Cu alloy. Specifically, the bonding material 30 is an IMC (Inter Metallic Compound). The IMC is, for example, a material manufactured by a manufacturing technique called the nanomizing method based on Sn-Cu. As a specific example, the IMC is a bonding material having a homogeneous fine grain structure (Cu6Sn5 compound). The IMC has, in addition to good electrical conductivity, a uniform and homogeneous fine grain structure.

[0022] The melting point temperature of the bonding material 30 is, as an example, higher than the temperature (for example, 120°C to 150°C) at the time of filling the filling resin when manufacturing the package. The melting point temperature of the bonding material 30 is also higher than the temperature (for example, 220°C) at the time of the secondary mounting reflow of the package. The melting point temperature of the bonding material 30 is preferably 250°C or higher, and more preferably 300°C or higher. When the bonding material is a general solder, for example, the solder melts during the secondary mounting reflow, and the bonding between the columnar structure 20 and the wiring board 50 cannot be maintained, and there is a risk of warping of the member and poor electrical connection. On the other hand, according to the configuration of the present embodiment, since the melting temperature of the bonding material 30 is sufficiently high, the bonding material 30 does not melt, and the occurrence of the above problems is prevented.

[0023] In this specification, when referring to a metal, it may include not only a single metal element but also an alloy containing a plurality of metal elements, a composite structure of an intermetallic compound, or a combination thereof. Nano refers to a size of 1 μm or less. The metal matrix phase refers to a metal or alloy that becomes a base material supporting them when bulked using other components. The endo-taxial bonding structure is a structure in which another (intermetallic compound) substance exists in a substance that becomes a metal or alloy, and the crystal grains are formed in a bonding state at the crystal lattice level between the target substances (for example, between alloys, between metals, between intermetallic compounds).

[0024] The bonding material 30 may, for example, include an intermetallic compound and a metal matrix, wherein the intermetallic compound includes Sn and Cu, and the metal matrix includes a Sn-Cu alloy and voids, and the intermetallic compound and the metal matrix are endotaxially bonded.

[0025] In conventional technology, the thinness of the SnAg bonding material leads to problems such as crack formation due to the influence of substrate warping and coplanarity, preventing stress relaxation in unbonded electrode areas and differences in thermal expansion coefficients. In contrast, the configuration of this embodiment prevents such problems because the bonding material 30 is a dissimilar material bonding material with intermetallic bonding. In particular, a configuration in which the bonding material 30 thickness is 5 μm to 40 μm is advantageous for reducing ON resistance, reducing height, and improving heat dissipation of the semiconductor device S100. Furthermore, if a Cu6Sn5 compound metal tube compound is pre-included in the paste, solder decomposition is suppressed even if the bonding material 30 is relatively thick (e.g., more than 20 μm).

[0026] The bonding material 30 may be nano-sintered Ag. Since the melting point of nano-sintered Ag is 961.8°C, the bonding material 30 does not decompose.

[0027] The filler resin 40 is a sealing resin that fills the space between the semiconductor chip 10 and the wiring board 50. It is preferable that the filler resin 40 before curing is a relatively fluid material so that it can flow well into the space between the semiconductor chip 10 and the wiring board 50. As an example, the filler resin 40 may be a material that does not contain fillers, or a material in which the average particle size of the fillers is 10 μm or less.

[0028] (Manufacturing of semiconductor device S100) Figure 3 shows an example of the manufacturing process for a semiconductor device. In the state shown in Figure 3(a), an Au plating 54 is formed on the surface of the Ni plating 53 of the wiring board 50. A bonding material 30 is formed on the end of the columnar structure 20 of the semiconductor chip 10 before melting.

[0029] From the state shown in Figure 3(a), the semiconductor chip 10 is placed on the wiring board 50, and sintering is performed in this state. In the state shown in Figure 3(b), the Au plating 54 diffuses into the Sn of the bonding material 30.

[0030] Next, as shown in Figure 3(c), filler resin 40 is injected into the space between the semiconductor chip 10 and the wiring substrate 50 and cured. Through this series of steps, the semiconductor device S100 is manufactured.

[0031] (Effects of semiconductor device S100) As described above, the semiconductor device S100 is fixed to the columnar structure and the wiring board by a dissimilar material bonding material having an intermetallic bond, thus preventing cracks from occurring in the bonding material 30 or electrical connection failures from occurring during sintering. In particular, when the thickness of the bonding material 30 is 5 μm or more and 40 μm or less, it is advantageous for reducing the ON resistance, reducing the height, and improving the heat dissipation of the semiconductor device S100.

[0032] (modified version) Figure 4 shows a modified example of a semiconductor device. The semiconductor device S101 in Figure 4 has a heat dissipation path 58. The heat dissipation path 58 is formed below the semiconductor chip 10 and penetrates the wiring substrate 50. The heat dissipation path 58 is filled with, for example, a resin paste. The resin paste may contain, for example, a metallic material such as copper. With a configuration like that in Figure 4, since the heat dissipation path 58 is formed in the wiring substrate 50, heat from the resin layer, which is the filling resin 40, can be dissipated to the outside via the heat dissipation path 58.

[0033] In particular, a configuration in which the thickness of the bonding material 30 is 40 μm or less, and the heat dissipation path 58 is located directly beneath the chip, achieves excellent heat dissipation and a low profile.

[0034] Figure 5 shows another modified example of a semiconductor device. Figure 5(b) is a plan view of the semiconductor device as seen from the side on which the semiconductor chip is mounted, and Figure 5(a) is a cross-sectional view along line AA. The semiconductor device S102 in Figure 5 comprises a semiconductor chip 10 and a wiring board 50, similar to the embodiment described above. Note that in Figure 5, not all of the wiring pattern extending from the device operating electrode 57 to the lower surface of the semiconductor chip 10 is shown; only a portion is illustrated.

[0035] The semiconductor chip 10 includes a first heat dissipation path 58-1, a second heat dissipation path 58-2, and a side via 59.

[0036] The first heat dissipation path 58-1 is located below the semiconductor chip 10 and is formed to penetrate the wiring board 50. The second heat dissipation path 58-2 is formed to penetrate the wiring board 50 at a position where a wiring pattern drawn out from the device operating electrode 57 is connected to a predetermined electrode portion of the semiconductor chip 10. Both the first heat dissipation path 58-1 and the second heat dissipation path 58-2 are provided outside the chip, at locations other than the device operating electrode 57.

[0037] The side via 59 is located below the electrode 62 on the upper surface of the wiring board 50 (towards the back of the page in Figure 5(b); the electrode 62 is not shown in Figure 5(a)). The electrode 62 is electrically connected to the semiconductor chip 10 and is located outside the semiconductor chip 10.

[0038] The side via 59 is formed to extend from the electrode 62 in the thickness direction of the wiring board 50. A plated member 63a and a resin member 63b are provided inside the side via 59.

[0039] The plated member 63a is a so-called thick plated material, formed to a thickness of at least 1 / 4 of the via hole diameter. The resin member 63b is provided in the center of the plated member 63a. Specifically, the resin member 63b is formed from a conductive resin paste filled in the center of the plated member 63a. The inside of the side via 59 may be filled only with the plating material, but in the configuration as in this embodiment, since the resin paste is provided in the center, it prevents cracks from forming in the material inside the via due to heat, for example, compared to a configuration in which the via is filled only with the plating material.

[0040] In one embodiment of the present invention, Ni plating 21 (see Figure 1) may be formed on both ends of the columnar structure 20. Alternatively, Ni plating may not be formed on both ends of the columnar structure 20. In the above description, the wiring board 50 is exemplified as being a ceramic or organic substrate, but the semiconductor chip 10 may be mounted on a Cu substrate. The mounted device may be sealed with resin. A Pd film may be formed at the interface between the bonding material 30 and the Ni plating 21 or the columnar structure 20. The material of the columnar structure 20 is Cu, and a Pd film may be formed at the interface between the columnar structure 20 and the bonding material 30. In this case, diffusion and Kirkendall of the bonding material 30 are suppressed, and interface cracks are less likely to occur. A Cu layer of 3 μm or more may be formed at the interface between the bump, which is the columnar structure 20, and the Al layer 13.

[0041] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of its gist. For example, all or part of the apparatus can be configured by functionally or physically distributing and integrating in any unit. Furthermore, new embodiments resulting from any combination of multiple embodiments are also included in the embodiments of the present invention. The effects of the new embodiments resulting from the combinations are combined with the effects of the original embodiments. [Explanation of Symbols]

[0042] 10 Semiconductor Chips 11 Silicon substrate 12 Polyimide layer 13 Al layer 20 Columnar structure 21 Ni plating 30 Bonding material 40 Filling resin 40μm or more 50 Wiring boards 51 Resist 52 Electrode section 53 Ni plating 54 Au plating 55 Electrode Au plating 57 Device Operating Electrodes 58 Heat dissipation path 58-1 First heat dissipation path 58-2 Second heat dissipation path 59 Side vias 62 electrodes 63a Plated material 63b Resin component S100 Semiconductor Device

Claims

1. Semiconductor chips and A wiring board on which the aforementioned semiconductor chip is mounted, A conductive columnar structure disposed between the electrode portion of the semiconductor chip and the wiring substrate, the columnar structure having a height of 40 μm or less, Equipped with, The columnar structure and the wiring board are fixed together by a dissimilar material bonding material having a metal-to-metal connection. Semiconductor equipment.

2. The aforementioned dissimilar material bonding material is formed to connect the electrode portion of the semiconductor chip and the electrode portion of the wiring substrate, The thickness of the aforementioned dissimilar material bonding material is 5 μm or more and 40 μm or less. The semiconductor device according to claim 1.

3. The aforementioned dissimilar material bonding material is a material having an intermetallic compound in a matrix containing a Sn-Cu alloy, or sintered Ag. The semiconductor device according to claim 1 or 2.

4. The material of the columnar structure is Cu. Ni layers are formed at one or both ends of the columnar structure. The semiconductor device according to claim 1 or 2.

5. The material of the columnar structure is Cu. A Pd film is formed at the interface between the columnar structure and the dissimilar material bonding material. The semiconductor device according to claim 1 or 2.

6. The semiconductor chip and the wiring substrate are further provided with an insulating resin layer filled between them. The aforementioned wiring board is It is formed below the semiconductor chip and has a heat dissipation path that releases heat from the resin layer to the outside. The semiconductor device according to claim 1 or 2.

7. The aforementioned wiring board is In a plan view of the semiconductor device as seen from the side on which the semiconductor chip is mounted, the electrodes electrically connected to the semiconductor chip and located on the outside of the semiconductor chip, vias extending from the electrode in the thickness direction of the wiring board, It has, The via is plated to a thickness of at least one-quarter of the via's pore diameter, and its center is filled with conductive resin paste. The semiconductor device according to claim 1 or 2.

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