Data decoder and memory system

Abstract

To realize a data decoding device that can improve throughput. [Solution] According to the embodiment, the data decoding device comprises a first storage unit, a second storage unit, a decoding unit, a first selection unit, and a second selection unit. The first storage unit stores a data stream that includes one or more first blocks, each containing a first type data unit and a second type data unit. The second storage unit is capable of storing the second type data unit. The decoding unit decodes the second type data unit. The first selection unit switches the destination to which the second type data unit is transferred from the first storage unit. The second selection unit switches the source to which the second type data unit is transferred to the decoding unit. If the second block among the one or more first blocks is the last block in the data stream, the first selection unit transfers the second data unit of the second type contained in the second block from the first storage unit to the second storage unit, and the second selection unit transfers the second data unit stored in the second storage unit to the decoding unit.

Description

Technical Field

[0001] Embodiments of the present invention relate to a technique for decrypting data.

Background Art

[0002] Entropy encoding is a variable-length encoding method that generates an encoding table based on the occurrence frequency of each symbol in a symbol sequence to be encoded. The encoding table shows the correspondence between a symbol and the code word assigned to the symbol. In entropy encoding, a short code word is assigned to a symbol with a high occurrence frequency, and a long code word is assigned to a symbol with a low occurrence frequency. Therefore, each symbol to be encoded is converted into a variable-length code using the encoding table.

[0003] The compressed data (compressed stream) obtained by entropy encoding includes one or more compression units (CUs). Each of the one or more compression units includes one or more blocks. Each of the one or more blocks includes a header and a payload. The header includes data for restoring the encoding table. The payload part includes one or more variable-length codes. Each of the one or more variable-length codes is decoded using the restored encoding table. Therefore, the compressed data can be decompressed by decoding the variable-length code using the restored encoding table for each block.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0005] One embodiment of the present invention aims to provide a data decoding device and a memory system that can improve the throughput of data decoding. [Means for solving the problem]

[0006] According to the embodiment, the data decoding device comprises a first storage unit, a first decoding unit, a second storage unit, a second decoding unit, a first selection unit, and a second selection unit. The first storage unit stores a first data stream including one or more first blocks, each containing a first type data unit and a second type data unit. The first decoding unit decodes the first type data unit. The second storage unit is capable of storing the second type data unit. The second decoding unit decodes the second type data unit. The first selection unit switches the destination to which the second type data unit is transferred from the first storage unit. The second selection unit switches the source to which the second type data unit is transferred to the second decoding unit. If the second block among the one or more first blocks is the last block in the first data stream, the first selection unit transfers the second type data unit contained in the second block from the first storage unit to the second storage unit, and the second selection unit transfers the second data unit stored in the second storage unit to the second decoding unit. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing an example configuration of an information processing system including a data decoding device according to the embodiment. [Figure 2] A diagram showing an example of the data structure of a compressed stream input to a data decoding device according to an embodiment, and its relationship to the LAST signal. [Figure 3] A block diagram showing the configuration of the data decoding device related to the comparative example. [Figure 4] A timing chart showing the execution times of the header decoding process and the payload decoding process in a data decoding device relating to a comparative example. [Figure 5]A block diagram showing an example configuration of a data decoding device according to the embodiment. [Figure 6] A flowchart showing an example of the procedure for the first processing performed in the data decoding device according to the embodiment. [Figure 7] A flowchart showing an example of the procedure for the second processing performed in the data decoding device according to the embodiment. [Figure 8] A flowchart showing an example of the procedure for the third process performed in the data decoding device according to the embodiment. [Figure 9] A timing chart showing an example of the execution time of the header decoding process and the payload decoding process in a data decoding device according to the embodiment. [Modes for carrying out the invention]

[0008] The embodiments will be described below with reference to the drawings.

[0009] Figure 1 shows an example configuration of an information processing system including a data decoding device according to an embodiment. The information processing system 1 includes a host device 2 and a memory system 3.

[0010] Host device 2 is an information processing device that stores data in memory system 3. Host device 2 is, for example, a storage server or personal computer that stores large amounts of diverse data in memory system 3. Hereinafter, host device 2 will be referred to as host 2.

[0011] Memory system 3 is a semiconductor storage device configured to write data to non-volatile memory and read data from non-volatile memory. The non-volatile memory is, for example, NAND flash memory 4. Memory system 3 can be implemented, for example, as a solid-state drive (SSD). The following example illustrates the case where memory system 3 is implemented as an SSD equipped with NAND flash memory 4. Note that memory system 3 may also be implemented as other types of storage devices, such as a hard disk drive (HDD).

[0012] Memory system 3 can be used as the storage of host 2. Memory system 3 may be built into host 2 or connected to host 2 via a cable or network.

[0013] The interface for connecting host 2 and memory system 3 complies with standards such as SCSI, Serial Attached SCSI (SAS), ATA (AT Attachment), Serial ATA (SATA), PCI Express TM (PCIe TM ), Ethernet TM , Fibre channel, NVM Express TM (NVMe TM ), etc.

[0014] Memory system 3 includes, for example, NAND flash memory 4, dynamic random access memory (DRAM) 5, and controller 6.

[0015] NAND flash memory 4 includes one or more memory chips. Each memory chip includes a plurality of blocks. The plurality of blocks each function as the minimum unit of the data erasure operation. A block is also referred to as an erase block or a physical block. Each of the plurality of blocks includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells connected to a single word line. The plurality of pages each function as the unit of the data write operation and the data read operation. Note that the word line may function as the unit of the data write operation and the data read operation.

[0016] There is an upper limit to the number of program / erase cycles (P / E cycles) for each block, which is referred to as the maximum P / E cycle number. One P / E cycle of a certain block includes an erase operation to set all the memory cells in this block to the erased state and a write operation to write data to each page of this block.

[0017] DRAM5 is a volatile memory. The memory area of DRAM5 is allocated, for example, as a storage area for firmware (FW), a cache area for a logical physical address translation table, and a buffer area for user data. User data is data requested to be stored in the memory system 3 by the host 2 and transmitted from the host 2. The user data stored in the buffer area includes, for example, user data to be written to the NAND flash memory 4 and user data read from the NAND flash memory 4. The user data to be written to the NAND flash memory 4 can be written to the NAND flash memory 4 after being compressed. Also, the user data read from the NAND flash memory 4 is compressed user data and can be decompressed.

[0018] The interface for connecting DRAM5 and an external element (for example, the data decoding device 15) conforms to, for example, the Advanced eXtensible Interface 4-Stream (AXI4-Stream) standard. In an interface conforming to AXI4-Stream, for example, signals for controlling the start of data transfer (VALID signal and READY signal), a signal for transferring data (DATA signal), and a signal indicating that it is the last data (LAST signal) are used. Each of these signals is provided with, for example, its own signal line.

[0019] The controller 6 is a memory controller that controls the NAND flash memory 4 and DRAM5. The controller 6 is realized by a circuit such as, for example, a System-on-a-chip (SoC).

[0020] The controller 6 functions as a flash translation layer (FTL), configured to perform data management and block management of the NAND flash memory 4, for example. The data management performed by this FTL includes (1) managing mapping information that shows the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing to conceal the difference between page-level data read / write operations and block-level data erase operations. Block management includes bad block management, wear leveling, and garbage collection.

[0021] Logical addresses are used by host 2 to address memory areas in memory system 3. A logical address is, for example, a logical block address (LBA).

[0022] The mapping between each logical address and each physical address is managed, for example, using a logical-physical address translation table. The controller 6 uses the logical-physical address translation table to manage the mapping information between each logical address and each physical address in units of a specific management size. The physical address corresponding to a given logical address indicates the physical storage location in the NAND flash memory 4 where the user data for that logical address is written. The logical-physical address translation table may be loaded from the NAND flash memory 4 into the DRAM 5 when the memory system 3 is started.

[0023] Data can only be written to a single page once per P / E cycle. Therefore, the controller 6 writes the updated user data corresponding to a certain logical address to a different physical memory location, rather than to the physical memory location where the previous user data corresponding to that logical address is stored. The controller 6 then invalidates the previous user data by updating the logical-physical address translation table to associate this logical address with this different physical memory location.

[0024] The controller 6 includes, for example, a CPU 11, a NAND interface (NAND I / F) 12, a DRAM interface (DRAM I / F) 13, a host interface (Host I / F) 14, and a data decoding device 15. These components, the CPU 11, NAND I / F 12, DRAM I / F 13, Host I / F 14, and data decoding device 15, are connected, for example, via a bus 10.

[0025] The controller 6 may also have built-in static random access memory (SRAM) or DRAM. In this case, an external DRAM 5 is not required for the controller 6.

[0026] SRAM is a volatile memory. The storage area of ​​SRAM can be allocated as, for example, a storage area for firmware, a cache area for logical-physical address translation tables, and a buffer area for user data.

[0027] The CPU 11 is a processor configured to control the NAND I / F 12, DRAM I / F 13, host I / F 14, and data decoding device 15. The CPU 11 performs various processes by executing firmware (FW) loaded from the NAND flash memory 4 into the DRAM 5. FW is a control program containing a set of instructions for the CPU 11 to perform various processes. In addition to the FTL processing described above, the CPU 11 also performs command processing to handle various commands from the host 2. The operation of the CPU 11 is controlled by the FW executed by the CPU 11. Note that some or all of the FTL processing and command processing may be performed by dedicated hardware within the controller 6.

[0028] The NAND I / F12 electrically connects the controller 6 and the NAND flash memory 4. The NAND I / F12 supports interface standards such as Toggle DDR and Open NAND Flash Interface (ONFI).

[0029] The NAND I / F 12 functions as a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F 12 may be connected to multiple memory chips within the NAND flash memory 4 via multiple channels. By driving multiple memory chips in parallel, the access bandwidth between the NAND flash memory 4 and the controller 6 can be increased.

[0030] The DRAM I / F13 functions as a DRAM control circuit configured to control access to DRAM5.

[0031] The host interface 14 is a circuit that functions as an interface for communication between the memory system 3 and the host 2. The host interface 14 includes circuitry that receives various commands (e.g., input / output (I / O) commands and control commands) and data from the host 2. I / O commands are, for example, read commands or write commands. Control commands are, for example, unmap commands (trim commands) or format commands. The host interface 11 includes circuitry that transmits responses and data corresponding to commands to the host 2.

[0032] The data decoding device 15 is a decompressor that decompresses (decodes) a compressed stream. A compressed stream is also called compressed data. A compressed stream is, for example, data transmitted from the host 2 to the memory system 3, or data read from the NAND flash memory 4. The CPU 11 stores the compressed stream read from the NAND flash memory 4 in the DRAM 5 in response to receiving a read command from the host 2, for example. The Direct Memory Access Controller (DMAC) inputs the data stored in the DRAM 5 to the data decoding device 15 via DMA data transfer. The DMAC is provided, for example, within the controller 6 and controls data transfer between components within the controller 6 (for example, data transfer from the DRAM 5 to the data decoding device 15). Alternatively, the CPU 11 may read the compressed stream stored in the DRAM 5 and input the read compressed stream to the data decoding device 15. Alternatively, the data decoding device 15 may read the compressed stream stored in the DRAM 5. The data decoding device 15 then decompresses the input (read) compressed stream to generate decompressed data (decoded data). More specifically, the data decoding device 15 decompresses the compressed stream unit by unit (CU). A CU is a single unit of data that is compressed at one time.

[0033] When a compressed stream is stored in the NAND flash memory 4, predetermined processes such as error correction and randomization may be performed. In this case, the CPU 11 writes the data on which the predetermined processes have been performed to the compressed stream to the NAND flash memory 4 via the NAND I / F 12. That is, the CPU 11 writes data based on the compressed stream to the NAND flash memory 4. Here, the controller 6 may be equipped with a compression circuit, and the compressed stream may be data compressed by the compression circuit of the controller 6. Also in this case, when the CPU 11 reads the compressed stream from the NAND flash memory 4, it reads data based on a read command from the host 2 via the NAND I / F 12. After predetermined processes such as error correction and randomization de-processing are performed on the data read from the NAND flash memory 4, the CPU 11 stores it in the DRAM 5 as a compressed stream. The compressed stream stored in the DRAM 5 is input to the data decoding device 15 by the CPU 11. The data decoding device 15 decompresses the input compressed stream to generate decompressed data (decoded data). In other words, the data decoding device 15 decompresses the compressed stream based on the data read from the NAND flash memory 4 to generate decompressed data (decoded data).

[0034] When the data decoding device 15 reads a compressed stream from the DRAM 5, the DRAM 5 outputs a compressed stream of a compression unit to the data decoding device 15 as a DATA signal via the DRAM I / F 13, for example, using a VALID signal and a READY signal, in response to the fact that data transfer to the data decoding device 15 has begun. Then, at the timing when the last data in the compressed stream of the compression unit is output, the DRAM 5 outputs a LAST signal indicating the end of the transfer of the compressed stream of the compression unit. In other words, the LAST signal represents the end of the compressed stream of the compression unit. This allows the data decoding device 15 to read the compressed stream from the DRAM 5 unit by unit.

[0035] Figure 2 shows an example of the data structure of the compressed stream input to the data decoding device 15 and the LAST signal.

[0036] The compressed stream 7 is, for example, a data stream transferred from a specific memory area to the data decoding device 15. The specific memory area is, for example, DRAM 5. The compressed stream 7 includes, for example, data compressed using entropy coding. The compressed stream 7 may also be data that has been compressed by entropy coding after any processing such as dictionary compression has been performed. In other words, the data subject to entropy coding may be data that has been instructed to be written from the host 2, or data on which any processing such as dictionary compression has been performed. Specifically, the compressed stream 7 includes, in order from the beginning, one or more compressed streams 70, 71, ... of compression units (CUs). Each of the compressed streams 70, 71, ... of a compression unit is data in which the uncompressed data of the compression unit has been compressed using entropy coding (for example, data that has been compressed by entropy coding after dictionary compression). The compressed stream of a compression unit is also simply referred to as a compression unit.

[0037] Dictionary-style compression is an encoding method that uses a history buffer, which holds previously input data (i.e., symbol sequences), to convert the data to be compressed into a pointer. Dictionary-style compression is also called dictionary coding. A pointer includes, for example, a match distance and a match length. In dictionary-style compression, the history buffer is searched to retrieve past data that matches the data to be compressed in at least part, and the match distance and match length are obtained. The match distance is the distance in the history buffer from the location where the data to be compressed is stored to the location where the retrieved past data is stored. The match length is the length of the portion that matches the retrieved past data and the data to be compressed. In dictionary-style compression, data can be compressed by converting the data to be compressed into a pointer (i.e., a symbol containing the match distance and match length).

[0038] Each of the compression units 70, 71, ... consists of, for example, one or more blocks. Specifically, compression unit 70 consists of, for example, one or more blocks 70-1, 70-2, ..., and 70-N. Compression unit 71 consists of, for example, one or more blocks 71-1, 71-2, ..., and 71-N.

[0039] Each block contains a header and a payload. Within a block, the header and payload are arranged in order.

[0040] The header is a first type of data section containing data (information) for decoding the payload. Specifically, the header includes the final block information and data for reconstructing the coding table.

[0041] The final block information is a flag that indicates whether the corresponding block is the final block in the compression unit. The final block information corresponds to, for example, the BFINAL field defined in the DEFLATE standard. If the corresponding block is the final block in the compression unit, the final block information will show, for example, "1". If the corresponding block is not the final block in the compression unit, the final block information will show, for example, "0". Note that the values ​​indicating whether the corresponding block is the final block in the compression unit and whether the corresponding block is not the final block in the compression unit can be set arbitrarily.

[0042] An encoding table is information that shows the correspondence between one or more symbols and one or more codewords (variable-length codes) assigned to each of those symbols. By using the reconstructed encoding table, codewords are converted back into symbols (decoded). The reconstructed encoding table is also called a decoded table.

[0043] The payload is a second type of data section containing the data to be decoded (encoded data). The data to be decoded includes, for example, a codeword converted from a symbol by entropy coding.

[0044] In the example shown in Figure 2, the first block 70-1 of the compression unit contains the header 80 and the payload 81. For example, the final block information 80F is placed at the beginning of the header 80. The final block information 80F corresponds to the first block 70-1. Therefore, the final block information 80F is set to a value (for example, 0) that indicates that block 70-1 is not the final block.

[0045] Furthermore, the last block 70-N of the compression unit 70 includes the header 85 and the payload 86. For example, the final block information 85F is placed at the beginning of the header 85. The final block information 85F corresponds to the last block 70-N. Therefore, the final block information 85F is set to a value (for example, 1) that indicates that block 70-N is the final block.

[0046] Furthermore, at the timing when the last data of each compression unit 70, 71, ... is transferred (i.e., when the transfer of each compression unit is completed), a LAST signal 9, indicating the end of each compression unit, is input to the data decoding device 15. In the example shown in Figure 2, the LAST signal 90 is input to the data decoding device 15 at the timing when the last data of compression unit 70 is transferred. Also, the LAST signal 91 is input to the data decoding device 15 at the timing when the last data of compression unit 71 is transferred. The input of the LAST signal 9 allows the data decoding device 15 to detect the end of the transfer of the corresponding compression unit.

[0047] Based on the data structure of the compressed stream 7 and the LAST signal 9 described above, the data decoder 15 decompresses the compressed stream 7. Note that the data structure of the compressed stream 7 and the LAST signal 9 shown in Figure 2 are examples. The data structure of the compressed stream 7 and the LAST signal 9 may be replaced with any configuration that the data decoder 15 can detect, such as the end of each of one or more compression units and the final block in each compression unit. Hereinafter, one of the compressed streams 70, 71, ... of the compression units, without specifying which one it is, will also be referred to as the compressed stream 7 of the compression unit.

[0048] Here, with reference to Figures 3 and 4, the data decoding device 15C related to the comparative example will be described.

[0049] Figure 3 is a block diagram showing the configuration of a data decoding device 15C according to a comparative example. The data decoding device 15C is a device that decodes a compressed stream 7C input from an external source and outputs decoded data 43C obtained by the decoding. The data decoding device 15C comprises a header decoding unit 32C and a payload decoding unit 36C.

[0050] The header decoding unit 32C includes a shift register 31C. The shift register 31 stores the compressed stream 7C.

[0051] The header decoding unit 32C reads the compressed stream 7C sequentially from the shift register 31, starting from the beginning. The header decoding unit 32C obtains the header of the current block from the read data. The header decoding unit 32C reconstructs the coding table 42C using the data contained in the header. The header decoding unit 32C outputs the coding table 42C to the payload decoding unit 36C. The header decoding unit 32C also sequentially outputs the data stream following the header in the compressed stream 7C to the payload decoding unit 36C via a pipeline (decoding pipeline) from the header decoding unit 32C to the payload decoding unit 36C.

[0052] The payload decoding unit 36C generates one or more symbols by decoding the data stream received via the decoding pipeline using the coding table 42C. The payload decoding unit 36C then outputs decoded data 43C containing one or more symbols.

[0053] More specifically, the payload decoding unit 36C uses the coding table 42C to convert the data stream received via the decoding pipeline into symbols sequentially from the beginning. Then, based on the fact that the symbols obtained by the conversion are End of Block (EOB) symbols, the payload decoding unit 36C detects the boundary between the current block and the next block. An EOB symbol is a symbol that indicates the end of the corresponding block.

[0054] Thus, the boundaries between blocks in the compressed stream 7C are detected in response to the generation of EOB symbols by the payload decoding unit 36C. Therefore, the data stream output from the header decoding unit 32C to the payload decoding unit 36C via the decoding pipeline may contain the header of the next block.

[0055] If the payload decoding unit 36C has received a data stream that follows the payload of the current block, it re-inputs that data stream to the header decoding unit 32C via the recycle path 40C (recycle input). This allows the header decoding unit 32C and the payload decoding unit 36C to start decoding the next block.

[0056] In the decoding process of the data decoding device 15C in this comparative example, for example, when decoding the compressed stream 7C unit by unit, the decoding process of the payload detects the boundary (i.e., the EOB symbol) between the last block of the current compression unit and the first block of the next compression unit, and then starts decoding the header of the first block. Therefore, in the data decoding device 15C, the decoding process of the header of the first block of the next compression unit is not performed while the decoding process of the payload of the last block of the current compression unit is being performed. In other words, the data decoding device 15C cannot perform the decoding process of the payload of the last block of the current compression unit and the decoding process of the header of the first block of the next compression unit in parallel. Consequently, the data decoding throughput (decoding efficiency) of the data decoding device 15C is reduced.

[0057] Figure 4 is a timing chart showing the execution times of the header decoding process and the payload decoding process in the data decoding device 15C according to the comparative example. In the timing chart 51C, the horizontal axis represents time. Here, one compression unit (CU) is assumed to consist of one block. In the timing chart 51C, the period during which the header of each compression unit is decoded by the header decoding unit 32C and the period during which the payload of each compression unit is decoded by the payload decoding unit 36C are shown along with the passage of time.

[0058] In the data decoding device 15C, the header decoding process by the header decoding unit 32C and the payload decoding process by the payload decoding unit 36C are executed alternately. Specifically, in the data decoding device 15C, the following processes are executed sequentially: decoding of the header of compression unit CU0, decoding of the payload of compression unit CU0, decoding of the header of compression unit CU1, decoding of the payload of compression unit CU1, decoding of the header of compression unit CU2, decoding of the payload of compression unit CU2, decoding of the header of compression unit CU3, and decoding of the payload of compression unit CU3.

[0059] Thus, in the data decoding device 15C, the decoding process of the payload of the current compression unit (for example, the decoding process of the payload of compression unit CU0) and the decoding process of the header of the next compression unit (for example, the decoding process of the header of compression unit CU1) are not executed at overlapping times (i.e., in parallel). In other words, in the data decoding device 15C, the decoding process of the header of each compression unit is executed intermittently, and the decoding process of the payload of each compression unit is also executed intermittently. Therefore, the decoding throughput of the compressed stream 7C in the data decoding device 15C is low.

[0060] In contrast, the data decoding device 15 according to this embodiment is configured to perform at least a portion of the decoding process for the payload of the block included in the current compression unit (e.g., the last block) and the decoding process for the header of the block included in the next compression unit (e.g., the first block) in overlapping operations. Specifically, for example, when the data decoding device 15 is to decode the payload of the last block of the current compression unit, it transfers that payload from the first storage unit, where the compressed stream 7 of the compression unit is stored, to the second storage unit. As a result, the compressed stream 7 of the next compression unit is written to the first storage unit.

[0061] The configuration of this data decoding device 15 is based on the premise that (a) the boundary between the last block of the current compression unit and the first block of the next input compression unit can be determined by an external signal (e.g., LAST signal 9), and (b) since the payload of the last block in a compression unit is not followed by a header of the same compression unit, it is not necessary to precisely cut out the beginning of the header from the compression stream 7. Based on these premises (a) and (b), the decoding of the payload of the last block does not require a shift operation of the compression stream 7 corresponding to the amount of code consumed corresponding to the generated symbols. The amount of code consumed corresponding to a symbol is the amount of data of the codeword used to generate the symbol. Therefore, the data decoding device 15 decodes the payload of the last block before storing it in the second storage unit. In response to storing the payload of this last block in the second storage unit, the data decoding device 15 stores the next compression unit in the first storage unit. This allows the data decoding device 15 to start decoding the header of the first block of the next compression unit.

[0062] Therefore, the data decoding device 15 can, for example, duplicate at least part of the process of decoding the payload of the last block of the current compression unit, which has been read from the second storage unit, and the process of decoding the header of the first block of the next compression unit, which has been read from the first storage unit. Consequently, the data decoding device 15 can improve the throughput of decoding (decompression) of the compressed stream 7 compared to the data decoding device 15C of the comparative example.

[0063] Figure 5 is a block diagram showing an example configuration of the data decoding device 15. The data decoding device 15 receives, for example, a compressed stream 7 and a LAST signal 9 that indicates the end of a compressed unit of the compressed stream 7. The data decoding device 15 decodes the compressed stream 7 and outputs decoded data 43.

[0064] The data decoding device 15 includes, for example, an input data receiving unit 30, a shift register 31, a header decoding unit 32, a demultiplexer (DEMUX) 33, a multiplexer (MUX) 34, a data buffer 35, and a payload decoding unit 36.

[0065] Components within the data decoding device 15, such as the input data receiving unit 30, shift register 31, header decoding unit 32, DEMUX 33, MUX 34, data buffer 35, and payload decoding unit 36, are implemented by, for example, at least one of registers, memory, adders, multipliers, selectors, and other arithmetic units. Registers are implemented by sequential circuits such as flip-flops. Memory is implemented by memory elements such as SRAM or DRAM. Adders, multipliers, selectors, and other arithmetic units are implemented by combinational logic circuits.

[0066] The input data receiving unit 30 receives data input (supplied) from an external source. The received data includes, for example, a compressed stream 7 and a LAST signal 9. Specifically, the input data receiving unit 30 receives a compressed stream 7 in a compressed unit until it receives a LAST signal 9 indicating the end of that compressed stream 7. Alternatively, the input data receiving unit 30 may receive an uncompressed data stream in a specific unit until it receives a LAST signal 9 indicating the end of that data stream. The input data receiving unit 30 sequentially stores the received compressed stream 7 (or uncompressed data stream in a specific unit) in the shift register 31. The following description will mainly focus on the case where the data input from an external source consists of a compressed stream 7 in a compressed unit and a LAST signal 9 indicating the end of that compressed stream 7.

[0067] The input data receiving unit 30 prohibits (stops) writing data to the shift register 31 when it has stored the compressed stream 7 of the compression unit to the end in the shift register 31. Specifically, the input data receiving unit 30 determines that it has stored the compressed stream 7 of the compression unit to the end in the shift register 31 based on the reception of the LAST signal 9. Then, the input data receiving unit 30 sets the write permission / prohibition state of the shift register 31 to prohibited (i.e., changes it from permitted to prohibited). The write permission / prohibition state of the shift register 31 indicates whether data writing to the shift register 31 is permitted or prohibited.

[0068] Furthermore, the input data receiving unit 30 resumes writing data to the shift register 31 when the payload 41 belonging to the final block of the compressed stream 7 of the compression unit is stored in the data buffer 35. Specifically, the input data receiving unit 30 resumes writing data to the shift register 31 when the write permission / prohibition state of the shift register 31 is set to permission. This allows the input data receiving unit 30 to start processing to store the next compressed stream 7 of the compression unit in the shift register 31.

[0069] The shift register 31 is a data storage unit. The shift register 31 is, for example, a sequential circuit including a plurality of sequentially connected flip-flops. The data capacity of the shift register 31 is, for example, smaller than the data size of a compression unit. The shift register 31 stores at least a portion of the compressed stream 7 of the compression unit received by the input data receiving unit 30 by performing a shift operation that shifts the data stored in each flip-flop and stores new data. In other words, the shift register 31 discards previously stored old data and stores new data by performing a shift operation.

[0070] The header decoding unit 32 decodes the header 40 of each block contained in the compressed stream 7. Specifically, the header decoding unit 32 reads the header 40 of one block (hereinafter also referred to as the current block) contained in the compressed stream 7 from the shift register 31. The header decoding unit 32 restores the coding table 42 by decoding the read header 40. The header decoding unit 32 outputs the restored coding table 42 to the payload decoding unit 36. The coding table 42 is used to decode the payload 41 contained in the current block.

[0071] Here, we will specifically describe the operation by which the header decoding unit 32 reads the header 40 from the shift register 31. The header decoding unit 32 sequentially reads data (data stream) from the shift register 31. The data read is at least a part of the header 40. The header decoding unit 32 dynamically determines the total size of the header 40 to be read by referring to one or more fields in the read data that indicate the structure of the header 40. The header decoding unit 32 reads data of the determined size, including the data already read, from the shift register 31. Alternatively, the header decoding unit 32 reads from the shift register 31 until it detects the end of the data used to reconstruct the encoding table 42. By reading data from the shift register 31 in this way, the header decoding unit 32 obtains the data portion corresponding to the header 40. This allows the header decoding unit 32 to decode the header 40 of the current block.

[0072] The header decoding unit 32 notifies the shift register 31 of the size 46 of the data read as the header 40 (hereinafter also referred to as the header code consumption amount 46). The header decoding unit 32 may also sequentially notify the shift register 31 of the size of the data that has been confirmed to be part of the header 40 and read from the shift register 31. In the shift register 31, a shift operation is performed based on the notified header code consumption amount 46 while the current compression unit's compression stream 7 is input from an external source. As a result, the shift register 31 discards previously stored old data and stores new data.

[0073] Furthermore, the header decoding unit 32 includes a final block determination unit 321.

[0074] The final block determination unit 321 obtains final block information 44 from the header 40. The final block information 44 indicates whether the current block to which the header 40 belongs is the final block in the current compression unit's compression stream 7. Based on the obtained final block information 44, the final block determination unit 321 determines whether the current block is the final block in the current compression unit's compression stream 7. The final block determination unit 321 also outputs the final block information of a block to the shift register 31, DEMUX 33, and MUX 34, for example, until the transfer of the payload 41 belonging to the block from the shift register 31 to the transfer destination is completed. In the following description, the final block information will show "1" if the corresponding block is the final block, and "0" if the corresponding block is not the final block.

[0075] The header decoding unit 32, if the current block is the last block in the current compression unit's compression stream 7, starts processing to decode the header 40 of the first block in the next compression unit's compression stream 7 when the header 40 of that block has been written to the shift register 31.

[0076] DEMUX33 is a selection circuit that switches the destination for transferring the payload 41 from the shift register 31 according to the final block information 44 output by the final block determination unit 321.

[0077] If the final block information indicates that the current block is not the final block (0 in Figure 5), DEMUX33 selects MUX34 as the destination for the payload 41. In other words, DEMUX33 outputs (transfers) the payload 41 read from the shift register 31 to MUX34.

[0078] If the final block information indicates that the current block is the final block ("1" in Figure 5), DEMUX33 selects the data buffer 35 as the destination for the payload 41. In other words, DEMUX33 stores (transfers) the payload 41 read from the shift register 31 to the data buffer 35. Specifically, DEMUX33 reads the data up to the end of the compressed stream 7 of the compression unit stored in the shift register 31 as the payload 41 belonging to the current block. Then, DEMUX33 writes the read payload to the data buffer 35. As a result, the payload 41 of the final block is saved in the data buffer 35. Note that the payload 41 of the final block may contain data other than the codeword to be decoded.

[0079] MUX34 is a selection circuit that switches the source from which the payload 41 is transferred to the payload decoding unit 36, according to the final block information 44 output by the final block determination unit 321.

[0080] If the final block information indicates that the current block is not the final block (0 in Figure 5), MUX34 selects DEMUX33 as the source for transferring payload 41. Then, MUX34 outputs the payload 41 output by DEMUX34 to the payload decoding unit 36. In other words, if the final block information indicates that the current block is not the final block, the payload decoding unit 36 ​​reads the payload 41 from the shift register 31 via DEMUX33 and MUX34.

[0081] If the final block information indicates that the current block is the final block ("1" in Figure 5), the MUX34 selects the data buffer 35 as the source for transferring the payload 41. The MUX34 then outputs the payload 41 stored in the data buffer 35 to the payload decoding unit 36. In other words, if the final block information indicates that the current block is the final block, the payload decoding unit 36 ​​reads the payload 41 from the data buffer 35 via the MUX34.

[0082] Thus, if the final block information indicates that the current block is not the final block, the path from DEMUX33 to MUX34 becomes valid. On the other hand, if the final block information indicates that the current block is the final block, the path from DEMUX33 to MUX34 via data buffer 35 becomes valid.

[0083] The data buffer 35 is a memory unit capable of temporarily storing the payload 41. The data buffer 35 is a volatile memory, such as a first-in first-out (FIFO) memory. Specifically, the data buffer 35 is read from the shift register 31 by the DEMUX 33 and stores the payload 41 of the final block written to the data buffer 35. The payload 41 of the final block stored in the data buffer 35 is read by the MUX 34 and output to the payload decoding unit 36.

[0084] The payload decoding unit 36 ​​decodes the payload 41 of each block contained in the compressed stream 7. Specifically, the payload decoding unit 36 ​​receives an encoding table 42 corresponding to the current block from the header decoding unit 32. The payload decoding unit 36 ​​also receives the payload 41 belonging to the current block from the MUX 34. Using the encoding table 42, the payload decoding unit 36 ​​decodes (converts) one or more codewords contained in the payload 41 into one or more symbols. The payload decoding unit 36 ​​then outputs decoded data 43 containing the one or more symbols obtained by decoding.

[0085] Furthermore, the payload decoding unit 36 ​​outputs one or more symbols obtained by decoding to the header decoding unit 32. If the symbols received by the payload decoding unit 36 ​​are EOB symbols 45, the header decoding unit 32 starts processing to decode the header 40 of the next block. In this case, the next block is the block that follows the current block in the compressed stream 7 of the current compression unit.

[0086] Furthermore, if the payload decoding unit 36 ​​receives a payload contained in an uncompressed data stream instead of the payload 41 contained in the compressed stream 7, it outputs the symbols contained in that data stream as decoded data 43. The payload decoding unit 36 ​​also outputs the symbols contained in that data stream as they are to the header decoding unit 32. The header decoding unit 32 detects the end of a block of symbols decoded by the payload decoding unit 36 ​​based on the symbol count information contained in the header 40.

[0087] Here, we will explain in more detail how the payload decoding unit 36 ​​receives the payload 41.

[0088] If the current block is not the last block, the payload decoding unit 36 ​​sequentially receives data (data stream) read from the shift register 31 via DEMUX 33 and MUX 34. The received data is at least a part of the payload 41. The payload decoding unit 36 ​​uses the coding table 42 to decode the codewords contained in the received data into symbols. If the symbol obtained by decoding is the EOB symbol 45, the payload decoding unit 36 ​​terminates receiving the payload 41 belonging to the current block. In other words, by reading data from the shift register 31 until the EOB symbol 45 is obtained, the payload decoding unit 36 ​​obtains the data portion corresponding to the payload 41 of the current block. This allows the payload decoding unit 36 ​​to decode the payload 41 of the current block.

[0089] If the current block is the final block, the payload decoding unit 36 ​​receives the payload 41 of the final block read from the data buffer 35 via the MUX 34. The payload decoding unit 36 ​​may also receive the data (data stream) constituting the payload 41 of the final block sequentially from the beginning. The payload decoding unit 36 ​​uses the coding table 42 to decode the codewords contained in the received payload 41 into symbols. This allows the payload decoding unit 36 ​​to decode the payload 41 of the final block. After the payload decoding unit 36 ​​has received the entire payload 41 of the final block, the data stored in the data buffer 35 may be discarded.

[0090] Furthermore, if the current block is not the final block, the payload decoding unit 36 ​​notifies the shift register 31 of the size 47 of the data read out as payload 41 (hereinafter also referred to as payload consumption code amount 47). The payload decoding unit 36 ​​may also sequentially notify the shift register 31 of the size of a portion of the decoded payload 41. While the compressed stream 7 of the current compression unit is being input from an external source, the shift register 31 performs a shift operation based on the notified payload consumption code amount 47. As a result, the shift register 31 discards previously stored old data and stores new data.

[0091] The payload decoding unit 36 ​​does not need to notify the shift register 31 of the payload consumption code amount 47 if the current block is the last block. This is because the boundary between the last block of the current compression unit and the first block of the next compression unit can be determined by an external signal (for example, the LAST signal 9). In other words, the shift register 31 can perform a shift operation, for example, based on the LAST signal 9, to discard the data of the current compression unit and store the data of the next compression unit.

[0092] With the above configuration, the data decoding device 15 decodes the header 40 and payload 41 belonging to each block contained in the compressed stream 7 and decompresses the compressed stream 7. Specifically, the header decoding unit 32 analyzes the header 40 to restore the coding table 42 and obtain the final block information 44. The payload decoding unit 36 ​​uses the coding table 42 to decode the codewords contained in the payload 41 into symbols.

[0093] Furthermore, DEMUX33 stores the payload 41 of the final block of the current compression unit's compressed stream 7 in the data buffer 35. As a result, the shift register 31 stores the compressed stream 7 of the next compression unit. Then, the header decoding unit 32 starts processing to decode the header 40 of the first block of the next compression unit's compressed stream 7, in response to the fact that the header 40 of the first block of the next compression unit's compressed stream 7 has been written to the shift register 31.

[0094] Therefore, in the data decoding device 15, the process of the payload decoding unit 36 ​​decoding the payload 41 of the last block of the compressed stream 7 of the current compression unit and the process of the header decoding unit 32 decoding the header 40 of the first block of the compressed stream 7 of the next compression unit can be executed at least partially in overlap (in parallel). Consequently, compared to the comparative example data decoding device 15C, in which the header decoding unit 32C starts decoding the first block of the compressed stream 7C of the next compression unit only after the payload decoding unit 36C has completed decoding the payload of the last block of the compressed stream 7C of the current compression unit, the data decoding device 15 can improve the decoding throughput.

[0095] Next, referring to Figures 6 to 8, the processes performed in the data decoding device 15 will be described.

[0096] Figure 6 is a flowchart showing an example of the procedure for the first processing performed in the data decoding device 15. The first processing is the process of controlling the writing (storage) of data to the shift register 31. The input data receiving unit 30 executes the first processing, for example, when there is a compressed stream 7 to be decoded. The compressed stream 7 to be decoded is stored in the DRAM 5, for example.

[0097] First, the input data receiving unit 30 receives input data (step S101). The input data is, for example, at least a portion of the compressed stream 7 transferred from the DRAM 5 to the data decoding device 15. The input data receiving unit 30 writes the received input data to the shift register 31 (step S102).

[0098] The input data receiving unit 30 determines whether or not it has stored the compressed stream 7 of the compression unit to the end in the shift register 31 (step S103). Specifically, the input data receiving unit 30 determines whether or not it has stored the compressed stream 7 of the compression unit to the end in the shift register 31 based on, for example, the LAST signal 9 defined in the AXI-4 Stream interface standard. The input data receiving unit 30 determines, for example, that it has stored the compressed stream 7 of the compression unit to the end in the shift register 31 based on the LAST signal 9 becoming "1". Alternatively, the input data receiving unit 30 determines, for example, that it has not stored the compressed stream 7 of the compression unit to the end in the shift register 31 based on the LAST signal being "0".

[0099] If the compressed stream 7 of the compression unit has not been stored to the end in the shift register 31 (No. in step S103), the input data receiving unit 30 returns to step S101. In other words, the input data receiving unit 30 continues to receive input data and write it to the shift register 31.

[0100] When the compressed stream 7 of the compression unit is stored in the shift register 31 to the end (Yes in step S103), the input data receiving unit 30 prohibits writing data to the shift register 31 (step S104). In other words, the input data receiving unit 30 sets the write permission / prohibition state of the shift register 31 to prohibited. As a result, no new input data (for example, the compressed stream 7 of the next compression unit) is written to the shift register 31.

[0101] Next, the input data receiving unit 30 checks the write permission / prohibition status of the shift register 31 (step S105). The write permission / prohibition status of the shift register 31 is changed from prohibited to permitted, for example, in response to a notification of write permission from the header decoding unit 32 (more specifically, the final block determination unit 321). The write permission / prohibition status of the shift register 31 may also be changed to permitted in response to the final block information 44 indicating the final block in the current compression unit's compression stream 7 being input to the shift register 31 from the header decoding unit 32, and the payload 41 of that final block being read from the shift register 31 (i.e., being transferred to the data buffer 35). Then, the input data receiving unit 30 determines whether or not data writing to the shift register 31 is permitted (step S106).

[0102] If writing data to the shift register 31 is prohibited (No. in step S106), the input data receiving unit 30 returns to step S105. In other words, the input data receiving unit 30 repeatedly performs steps S105 and S106 until writing data to the shift register 31 is permitted.

[0103] If writing data to the shift register 31 is permitted (Yes in step S106), the input data receiving unit 30 returns to step S101. That is, the input data receiving unit 30 receives the input data that constitutes the next compression unit of the compressed stream 7 and writes it to the shift register 31.

[0104] Through the above first process, the input data receiving unit 30 can control the reception of the compressed stream 7 from outside and its writing to the shift register 31 for each compression unit. Specifically, the input data receiving unit 30 can prohibit the writing of new input data to the shift register 31 from the time the compressed stream 7 of a compression unit is stored in the shift register 31 to the end until the payload 41 of the final block in the compressed stream 7 of that compression unit is transferred from the shift register 31 to the data buffer 35.

[0105] Figure 7 is a flowchart showing an example of the procedure for the second processing performed in the data decoding device 15. The second processing is the process for decoding the block headers 40 contained in the compressed stream 7. The header decoding unit 32 and DEMUX 33 execute the second processing, for example, if at least a portion of the compressed stream 7 of the compression unit is stored in the shift register 31 and is unprocessed.

[0106] First, the header decoding unit 32 determines whether the header 40 of the next block (hereinafter also referred to as the target block) has been written to the shift register 31 (step S201). The target block is either (A) the block that follows the block from which the header decoding unit 32 immediately restored the encoding table 42 in the current compression unit's compression stream 7, or (B) the first block in the next compression unit's compression stream 7 after the compression unit's compression stream 7 in which the block from which the header decoding unit 32 immediately restored the encoding table 42 is the last block. The header decoding unit 32 determines whether the header 40 of the target block has been written, for example, based on the amount of data stored in the shift register 31.

[0107] If the header 40 of the target block has not been written to the shift register 31 (No. in step S201), the header decoding unit 32 returns to step S201. In other words, the header decoding unit 32 waits until the header 40 of the target block is written to the shift register 31.

[0108] If the header 40 of the target block is written to the shift register 31 (Yes in step S201), the header decoding unit 32 reads the header 40 of the target block from the shift register 31 (step S202). The header decoding unit 32 uses the read header 40 to reconstruct the encoding table 42 corresponding to the target block (step S203). The header decoding unit 32 outputs the reconstructed encoding table 42 to the payload decoding unit 36 ​​(step S204). The header decoding unit 32 (more specifically, the final block determination unit 321) also obtains the final block information 44 from the read header 40 (step S205). The header decoding unit 32 outputs the obtained final block information 44 to the shift register 31, DEMUX 33, and MUX 34 (step S206). Note that the execution order of steps S203 and S204 and steps S205 and S206 may be reversed, or they may be executed in parallel.

[0109] Next, the header decoding unit 32 uses the acquired final block information 44 to determine whether the target block is the final block in the current compression unit's compression stream 7 (step S207). The final block information indicates, for example, "1" if the target block is the final block, and "0" if the target block is not the final block. In this case, the header decoding unit 32 determines whether the final block information indicates "1" (final block) or "0" (non-final block).

[0110] If the target block is not the last block (No. in step S207), the header decoding unit 32 receives a symbol from the payload decoding unit 36 ​​(step S208). The header decoding unit 32 then determines whether the received symbol is the EOB symbol 45 (step S209).

[0111] If the received symbol is not the EOB symbol 45 (No. in step S209), the header decoding unit 32 returns to step S208. In other words, the header decoding unit 32 waits until it receives the EOB symbol 45 from the payload decoding unit 36.

[0112] If the received symbol is the EOB symbol 45 (Yes in step S209), the header decoding unit 32 returns to step S201. In other words, the header decoding unit 32 has obtained the EOB symbol 45, which indicates the end of the current block, through the decoding of the payload 41 by the payload decoding unit 36, and therefore performs further processing to decode the header 40 of the next block.

[0113] Furthermore, if the target block is the last block (Yes in step S207), DEMUX33 reads the data up to the end of the current compression unit's compressed stream 7 from the shift register 31 as the payload 41 of the target block (step S210). DEMUX33 stores the read payload 41 in the data buffer 35 (step S211). Then, the header decoding unit 32 notifies the shift register 31 of write permission (step S212) and returns to step S201. In other words, the header decoding unit 32 notifies the shift register 31 of write permission because the payload 41 of the last block in the current compression unit's compressed stream 7 has been stored (saved) in the data buffer 35. As a result, the shift register 31 can start writing to the next compression unit's compressed stream 7. The header decoding unit 32 can also start processing to decode the header 40 of the first block in the next compression unit's compressed stream 7 (i.e., the second processing).

[0114] Through the second process described above, the header decoding unit 32 can decode the header 40 for each block contained in the compressed stream 7 and obtain the encoding table 42 and the final block information 44. Also, if the target block is the final block, DEMUX 33 stores the payload 41 of the final block in the current compression unit's compressed stream 7 in the data buffer 35. This makes the next compression unit's compressed stream 7 writable to the shift register 31. Therefore, the data decoding device 15 can, for example, perform at least part of the decoding of the payload 41 of the final block in the current compression unit's compressed stream 7 and the decoding of the header 40 of the first block in the next compression unit's compressed stream 7 in parallel.

[0115] Figure 8 is a flowchart showing an example of the procedure for the third processing performed in the data decoding device 15. The third processing is the process for decoding the block-by-block payload 41 contained in the compressed stream 7. The payload decoding unit 36, DEMUX 33, and MUX 34 execute the third processing, for example, if at least a portion of the compressed stream 7 of the compression unit is stored in the shift register 31 and is unprocessed.

[0116] First, the payload decoding unit 36 ​​receives the encoding table 42 of the next block (target block) from the header decoding unit 32 (step S301). The payload decoding unit 36 ​​also receives the final block information 44 from the header decoding unit 32 (step S302). The execution order of the processes in step S301 and step S302 may be reversed. Using the received final block information 44, the payload decoding unit 36 ​​determines whether the target block is the final block in the current compression unit's compression stream 7 (step S303).

[0117] If the target block is not the last block (No. in step S303), DEMUX33 reads the payload 41 of the target block from the shift register 31 (step S304). DEMUX33 outputs the read payload 41 to MUX34 (step S305). MUX34 outputs the payload 41 received from DEMUX33 to the payload decoding unit 36 ​​(step S306). The payload decoding unit 36 ​​generates symbols by decoding the payload 41 received from MUX34 using the encoding table 42 (step S307). The payload decoding unit 36 ​​outputs the generated symbols as decoded data 43 and also outputs them to the header decoding unit 32 (step S308), and proceeds to step S313.

[0118] On the other hand, if the target block is the final block (Yes in step S303), the MUX34 reads the payload 41 of the target block (i.e., the final block) from the data buffer 35 (step S309). The MUX34 outputs the payload 41 read from the data buffer 35 to the payload decoding unit 36 ​​(step S310). The payload decoding unit 36 ​​generates symbols by decoding the payload 41 received from the MUX34 using the coding table 42 (step S311). The payload decoding unit 36 ​​outputs the generated symbols as decoded data 43 (step S312) and proceeds to step S313.

[0119] Next, the payload decoding unit 36 ​​determines whether the generated symbol is the EOB symbol 45 (step S313).

[0120] If the generated symbol is not the EOB symbol 45 (No. in step S313), the payload decoding unit 36 ​​returns to step S303. That is, the payload decoding unit 36 ​​either obtains the payload 41 from the shift register 31 via DEMUX 33 and MUX 34, or obtains the payload 41 from the data buffer 35 via MUX 34, and continues processing to decode the obtained payload 41.

[0121] If the generated symbol is the EOB symbol 45 (Yes in step S313), the payload decoding unit 36 ​​returns to step S301. That is, the payload decoding unit 36 ​​further processes the decoder of the payload 41 of the next block. In this case, the next block is (A) the block that follows the target block in the current compression unit's compression stream 7 if the target block is not the last block, and (B) the first block in the compression stream 7 of the compression unit that follows the current compression unit's compression stream 7 if the target block is the last block.

[0122] As a result of the third process described above, the payload decoding unit 36 ​​can decode either the payload 41 obtained from the shift register 31 via DEMUX 33 and MUX 34, or the payload 41 obtained from the data buffer 35 via MUX 34. The payload decoding unit 36 ​​obtains the payload 41 of the final block in the compressed stream 7 of the compression unit from the data buffer 35, not from the shift register 31. This is because the payload 41 of the final block has been moved from the shift register 31 to the data buffer 35 in response to the header decoding unit 32 determining that the target block is the final block. This makes the shift register 31 writable for the compressed stream 7 of the next compression unit. The data decoding device 15 can then perform, for example, at least part of the decoding of the payload 41 of the final block in the compressed stream 7 of the current compression unit (i.e., the payload 41 stored in the data buffer 35) and the decoding of the header 40 of the first block in the compressed stream 7 of the next compression unit (i.e., the header 40 stored in the shift register 31) in parallel. Therefore, the data decoding device 15 can improve the decoding throughput of the compressed stream 7.

[0123] Figure 9 is a timing chart showing an example of the execution time for the decoding process of the header 40 and the decoding process of the payload 41 in the data decoding device 15. In the timing chart 51, the horizontal axis represents time. Here, it is assumed that one compressed stream 7 of one compressed unit consists of one block. In the timing chart 51, the period during which the header 40 of each compressed unit is decoded by the header decoding unit 32 and the period during which the payload 41 of each compressed unit is decoded by the payload decoding unit 36 ​​are shown along with the passage of time.

[0124] In the data decoding device 15, at least a portion of the decoding of the header 40 by the header decoding unit 32 and the decoding of the payload 41 by the payload decoding unit 36 ​​are performed in overlapping mode. Specifically, in the data decoding device 15, after the header 40 of the compression unit CU0 is decoded, at least a portion of the decoding of the payload 41 of the compression unit CU0 and the decoding of the header 40 of the compression unit CU1 are performed in overlapping mode. Next, at least a portion of the decoding of the payload 41 of the compression unit CU1 and the decoding of the header 40 of the compression unit CU2 are performed in overlapping mode. Then, at least a portion of the decoding of the payload 41 of the compression unit CU2 and the decoding of the header 40 of the compression unit CU3 are performed in overlapping mode.

[0125] In other words, the header decoding unit 32 sequentially executes the decoding of the headers 40 of compression unit CU0, CU1, CU2, and CU3. Similarly, the payload decoding unit 36 ​​sequentially executes the decoding of the payloads 41 of compression unit CU0, CU1, CU2, and CU3. At least a portion of the processing by the header decoding unit 32 and the payload decoding unit 36 ​​is performed in parallel. The decoding process by the payload decoding unit 36 ​​for the payload 41 belonging to a block (final block) of a certain compression unit and the decoding process by the header decoding unit 32 for the header 40 belonging to the block (first block) of the next compression unit may start first or they may start simultaneously. For example, the decoding process by the payload decoding unit 36 ​​for a payload 41 belonging to the final block of a compression unit starts before the decoding process by the header decoding unit 32 for a header 40 belonging to the first block of the next compression unit.

[0126] In this way, the data decoding device 15 performs the decoding of the payload 41 of a certain compression unit (for example, the decoding of the payload 41 of compression unit CU0) and the decoding of the header 40 of the next compression unit (for example, the decoding of the header 40 of compression unit CU1) in overlapping time (i.e., in parallel). As a result, the data decoding device 15 can improve the throughput of decoding (decompression) of the compressed stream 7 compared to the decoding of the compressed stream 7C by the data decoding device 15C of the comparative example.

[0127] As described above, the data decoding device 15 of this embodiment can improve the throughput of data decoding.

[0128] The shift register 31 stores a first data stream (for example, a compressed stream 7 of a compression unit) which contains one or more first blocks, each containing a header 40 and a payload 41. The header decoding unit 32 decodes the header 40. The data buffer 35 can store the payload 41. The payload decoding unit 36 ​​decodes the payload 41. The DEMUX 33 switches the destination to which the payload 41 is transferred from the shift register 31. The MUX 34 switches the source from which the payload 41 is transferred to the payload decoding unit 36. If the second block of the one or more first blocks is the last block in the first data stream, the DEMUX 33 transfers the payload 41 contained in the second block from the shift register 31 to the data buffer 35, and the MUX 34 transfers the payload 41 stored in the data buffer 35 to the payload decoding unit 36.

[0129] As a result, for example, the next second data stream (for example, the compressed stream 7 of the next compression unit) is written to the shift register 31. The data decoder 15 can then perform at least part of the process of decoding the payload 41 of the last block of the first data stream, which is read from the data buffer 35, and the process of decoding the header 40 of the first block of the second data stream, which is read from the shift register 31, in overlapping operation. Therefore, the data decoder 15 can improve the throughput of decoding the compressed stream 7 compared to the data decoder 15C of the comparative example.

[0130] Each of the various functions described in this embodiment may be implemented by a circuit (processing circuit). Examples of processing circuits include a programmed processor, such as a central processing unit (CPU). This processor performs each of the described functions by executing computer programs (sets of instructions) stored in memory. This processor may be a microprocessor including electrical circuits. Examples of processing circuits also include digital signal processors (DSPs), application-specific integrated circuits (ASICs), microcontrollers, controllers, and other electrical circuit components. Each of the components other than the CPU described in this embodiment may also be implemented by a processing circuit.

[0131] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0132] 1... Information processing system, 2... Host, 3... Memory system, 4... NAND flash memory, 5... DRAM, 6... Controller, 7... Compressed stream, 9... LAST signal, 11... CPU, 12... NAND I / F, 13... DRAM I / F, 14... Host I / F, 15... Data decoding device, 30... Input data receiving unit, 31... Shift register, 32... Header decoding unit, 321... Final block determination unit, 33... DEMUX, 34... MUX, 35... Data buffer, 36... Payload decoding unit, 40... Header, 41... Payload, 42... Encoding table, 43... Decoded data, 44... Final block information, 45... EOB symbol, 46... Header code consumption, 47... Payload code consumption.

Claims

1. A first storage unit that stores a first data stream which includes one or more first blocks, each containing a first type data section and a second type data section, A first decoding unit that decodes the first type of data unit, A second storage unit capable of storing the second type of data unit, A second decoding unit that decodes the second type of data unit, A first selection unit that switches the destination to which the second type of data unit is transferred from the first storage unit, The system comprises a second selection unit that switches the source from which the second type of data unit is transferred to the second decoding unit, If the second block among the one or more first blocks is the last block in the first data stream, The first selection unit transfers the second data unit of the second type included in the second block from the first storage unit to the second storage unit. The second selection unit transfers the second data unit stored in the second storage unit to the second decoding unit. Data decoding device.

2. If the second block is the last block in the first data stream, The first storage unit stores a second data stream which includes one or more third blocks, each containing a first type data section and a second type data section. The decoding of the second data portion included in the second block by the second decoding unit and the decoding of the first type data portion included in the first block of the one or more third blocks by the first decoding unit are performed in parallel. The data decoding device according to claim 1.

3. The data decoding device receives the first data stream and first information representing the end of the first data stream, and then receives the second data stream. The data decoding device according to claim 2.

4. The system further comprises a receiving unit that, upon receiving the first information, detects that the data subsequently input to the data decoding device is the second data stream. The data decoding device according to claim 3.

5. The first storage unit stores the second data stream after the second data unit has been transferred from the first storage unit to the second storage unit. The data decoding device according to claim 2.

6. The first data stream and the second data stream are each compressed streams of a compression unit. The data decoding device according to claim 2.

7. The compressed stream is a compressed stream obtained using entropy coding. The data decoding device according to claim 6.

8. The first data unit of the first type included in the second block includes second information indicating whether or not the second block is the final block. The first decoding unit acquires the second information from the first data unit. The data decoding device according to claim 1.

9. The first decoding unit outputs the second information to the first selection unit and the second selection unit. If the second information indicates that the second block is the final block, The first selection unit transfers the second data unit included in the second block from the first storage unit to the second storage unit. The second selection unit transfers the second data unit stored in the second storage unit to the second decoding unit. The data decoding device according to claim 8.

10. The first selection unit and the second selection unit transfer the second data portion included in the second block from the first storage unit to the second decoding unit if the second information indicates that the second block is not the final block. The data decoding device according to claim 9.

11. The aforementioned first data stream is a compressed stream obtained using entropy coding, The first decoding unit uses the first data unit of the first type included in the second block to reconstruct an encoding table showing the correspondence between a plurality of symbols and a plurality of codes assigned to each of the plurality of symbols. The second decoding unit uses the coding table to convert each of the one or more codes contained in the second data unit into a symbol. The data decoding device according to claim 1.

12. The first decoding unit outputs the encoding table to the second decoding unit, The second decoding unit receives the coding table from the first decoding unit and the second data unit transferred from either the first storage unit or the second storage unit. The data decoding device according to claim 11.

13. The second decoding unit outputs the symbol to the first decoding unit, The first decoding unit decodes the first type of data portion included in the fourth block that follows the second block if the second block is not the final block and the symbol is a block end symbol indicating the end of the first block. The data decoding device according to claim 11.

14. The first memory unit is a shift register, The second storage unit is a data buffer, The data decoding device according to claim 1.

15. The system further includes a data receiving unit that receives the first data stream and stores the first data stream in the first storage unit, The second type of data unit is input to the data receiving unit following the first type of data unit. The data decoding device according to claim 1.

16. Non-volatile memory and Random access memory and A controller comprising a data decoding device according to any one of claims 1 to 14, which is capable of accessing the non-volatile memory and the random access memory, The aforementioned controller, The first data stream is read from the non-volatile memory. The read first data stream is stored in the random access memory, The first data stream stored in the random access memory is configured to be input to the data decoding device. Memory system.

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