A three-dimensional vertical non-volatile memory device including a memory cell string, a method for driving the same, and an electronic device including the same.

Abstract

The present invention provides a three-dimensional vertical non-volatile memory device including a memory cell string, a method for driving the same, and an electronic device including the same. [Solution] A three-dimensional vertical non-volatile memory device includes a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers; wherein the electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer by a voltage applied to the plurality of gate electrodes, and the blocking layer may include a charge trapping layer extending along the first direction and configured to trap charges by a voltage applied to the plurality of gate electrodes.

Description

[Technical Field]

[0001] The present invention relates to a three-dimensional vertical non-volatile memory device including a memory cell string, a method for driving the same, and an electronic device including the same. [Background technology]

[0002] Non-volatile memory devices, as semiconductor memory devices, include multiple memory cells that retain information even when the power is off and allow the stored information to be used again when power is supplied. Non-volatile memory devices can be used in mobile phones, digital cameras, personal digital assistants (PDAs), mobile computer devices, fixed computer devices, and other devices.

[0003] One example of a non-volatile memory device is vertical NAND (VNAND). VNAND is a memory device that increases integration density by vertically stacking a large number of memory cells. Various technologies have been proposed to increase the number of stacked VNANDs and achieve high capacity in the same area. For example, various technologies have been proposed to realize VNAND, such as methods using charge traps, methods using phase-shift materials, methods using resistance-changing materials, and methods using ferroelectrics. In addition, various materials are being researched to improve the performance of non-volatile memory devices, such as improving data reliability, increasing drive speed, reducing power consumption, and increasing integration density. [Overview of the project] [Problems that the invention aims to solve]

[0004] The problem that this invention aims to solve is to provide a three-dimensional vertical non-volatile memory device including a memory cell string.

[0005] Furthermore, the problem that the present invention aims to solve is to provide a three-dimensional vertical non-volatile memory device having a relatively low drive voltage and an improved memory window.

[0006] Furthermore, the problem that the present invention aims to solve is to provide a method for driving a three-dimensional vertical non-volatile memory device and an electronic device including a three-dimensional vertical non-volatile memory device. [Means for solving the problem]

[0007] A three-dimensional vertical non-volatile memory device according to one embodiment includes: a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers; wherein the electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer by a voltage applied to the plurality of gate electrodes, and the blocking layer may include a charge trapping layer extending along the first direction and configured to trap charges by a voltage applied to the plurality of gate electrodes.

[0008] The charge trapping layer may include, for example, at least one material from among silicon nitride, aluminum nitride, hafnium nitride, silicon oxynitride, aluminum oxynitride, hafnium oxynitride, hafnium oxide, zirconium oxide, tantalum oxide, and titanium oxide.

[0009] The charge trapping layer may include a metal oxide material doped with silicon (Si) or aluminum (Al).

[0010] The blocking layer may further include at least one of a first barrier layer extending in a first direction between the charge trapping layer and the plurality of gate electrodes and between the charge trapping layer and the plurality of spacers, and a second barrier layer extending in a first direction between the electrochemical layer and the charge trapping layer.

[0011] The first barrier layer and the second barrier layer may include at least one material selected from aluminum oxide, silicon oxide, hafnium oxide, and zirconium oxide.

[0012] The thickness of the blocking layer in the second direction is 5 nm to 15 nm, and the thickness of the charge trapping layer in the second direction is 1 nm to 10 nm.

[0013] The blocking layer includes both the first barrier layer and the second barrier layer, and the thickness of the first barrier layer in the second direction is thinner than the thickness of the second barrier layer in the second direction.

[0014] The electrochemical layer may include an oxide of at least one metal selected from scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0015] When the electrochemical layer includes an oxide of at least one metal selected from scandium (Sc), yttrium (Y), and lanthanum (La), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.35 or less. When the electrochemical layer includes an oxide of at least one metal selected from titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), and cerium (Ce), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.8 or less. When the electrochemical layer includes an oxide of at least one metal selected from vanadium (V), niobium (Nb), and tantalum (Ta), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 2.25 or less. When the electrochemical layer includes an oxide of at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W), the ratio of oxygen atoms to metal atoms in the electrochemical layer may be 2.7 or less.

[0016] The electrochemical layer may include an ion storage layer extending in a first direction adjacent to the blocking layer and an electrolyte layer extending in a first direction adjacent to the channel layer.

[0017] The ion storage layer and the electrolyte layer contain an oxide of at least one metal selected from scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and the ratio of oxygen to the total material in the ion storage layer is smaller than the ratio of oxygen to the total material in the electrolyte layer.

[0018] The thickness of the electrolyte layer in the second direction is thinner than the thickness of the ion storage layer in the second direction. The electrochemical layer may have a composition in which the proportion of oxygen gradually or continuously increases along a second direction toward the channel layer within the electrochemical layer.

[0019] The channel layer may include, for example, at least one oxide semiconductor material from among IGZO (indium-gallium-zinc oxide), IZO (indium-zinc oxide), GZO (gallium-zinc oxide), ZTO (zinc-tin oxide), and IWO (indium tungsten oxide).

[0020] A method for driving a three-dimensional vertical non-volatile memory device, comprising: a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction intersecting the first direction and arranged alternately in the first direction; an electrochemical layer extending in a first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending in a first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, and comprising a charge trapping layer configured to trap charges by a voltage applied to the plurality of gate electrodes; the method may also include the steps of: applying a negative (-) program voltage to any one of the plurality of gate electrodes; moving and trapping electrons in a portion of the charge trapping layer adjacent in a second direction to the gate electrode to which the program voltage has been applied; and moving ions in a portion of the channel layer adjacent in a second direction to the gate electrode to which the program voltage has been applied to a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the program voltage has been applied, so that the portion of the channel layer has a first resistance.

[0021] Furthermore, the driving method for a three-dimensional vertical non-volatile memory device may further include the steps of: applying a positive (+) erase voltage to one of the plurality of gate electrodes; moving electrons from a portion of the charge trapping layer adjacent in a second direction to the gate electrode to which the erase voltage is applied to the gate electrode to which the erase voltage is applied; and moving ions in a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the erase voltage is applied to a portion of the channel layer adjacent in a second direction to the gate electrode to which the erase voltage is applied, so that the portion of the channel layer has a second resistance lower than the first resistance.

[0022] Of the plurality of gate electrodes, the gate electrode to which the program voltage or the erase voltage is not applied is in a floating state, and no ions move between the region of the electrochemical layer adjacent to the floating gate electrode in the second direction and the region of the channel layer.

[0023] Furthermore, the driving method for a three-dimensional vertical non-volatile memory device further includes the step of applying a positive (+) read voltage only to the gate electrode of the selected memory cell from among the plurality of gate electrodes from which data is read, and applying a positive (+) pass voltage to the remaining gate electrodes, wherein the read voltage is higher than the program voltage and lower than the erase voltage, and the pass voltage is higher than the read voltage and lower than the erase voltage.

[0024] If a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a first resistance, a first current flows through the channel layer. If a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a second resistance, a second current larger than the first current flows through the channel layer.

[0025] Further embodiments of the electronic device include a processing circuit and a three-dimensional vertical non-volatile memory device, the three-dimensional vertical non-volatile memory device including: a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, wherein the electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer by a voltage applied to the plurality of gate electrodes, and the blocking layer may include a charge trapping layer extending along the first direction and configured to trap charges by a voltage applied to the plurality of gate electrodes. [Effects of the Invention]

[0026] The three-dimensional vertical non-volatile memory device according to this embodiment can record information by changing the resistance of the channel layer through ion exchange between the ion storage layer and the channel layer. Such a three-dimensional vertical non-volatile memory device can operate at a lower drive voltage compared to the charge trap flash method. Therefore, since the spacing between adjacent gate electrodes can be reduced compared to the charge trap flash method, the three-dimensional vertical non-volatile memory device according to this embodiment can have an even higher integration density.

[0027] Furthermore, the three-dimensional vertical non-volatile memory device according to the embodiment may further include a charge trapping layer disposed between the gate electrode and the ion storage layer. According to the embodiment, the charge trapped in the charge trapping layer can shift a low threshold voltage to an even lower value, and a high threshold voltage to an even higher value, thereby increasing the memory window. Therefore, the operational reliability of the three-dimensional vertical non-volatile memory device according to the embodiment can be improved. [Brief explanation of the drawing]

[0028] [Figure 1] Block diagram showing a memory system according to one embodiment. [Figure 2] This is a block diagram showing one example of a memory device implementation shown in Figure 1. [Figure 3] This is a block diagram showing the memory cell array shown in Figure 1. [Figure 4] This is a diagram showing an equivalent circuit corresponding to a memory block according to one embodiment. [Figure 5] This is a vertical cross-sectional view schematically showing the structure of a memory cell string according to an embodiment. [Figure 6] This is a horizontal cross-sectional view schematically showing the structure of a memory cell string according to an embodiment. [Figure 7] This is a schematic vertical cross-sectional view showing the structure of a memory cell string according to another embodiment. [Figure 8A] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8B] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8C] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8D] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8E] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8F] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 8G] Figure 7 is an illustrative diagram showing a method for manufacturing the memory cell string shown. [Figure 9] This diagram illustrates the programmed operation of a memory cell string according to an embodiment. [Figure 10] This diagram illustrates the erasure operation of a memory cell string according to an embodiment. [Figure 11] This diagram illustrates the read operation for a selected memory cell of a memory cell string according to the embodiment after the program has run. [Figure 12] This diagram illustrates the read operation for a selected memory cell in a memory cell string according to the embodiment after the erase operation. [Figure 13] This graph illustrates the principle of memory window increase due to the charge trapping layer. [Figure 14] This graph exemplifies the voltage-current characteristics of a single memory cell in a memory cell string, as illustrated by a comparative example. [Figure 15] This graph exemplifies the voltage-current characteristics of a single memory cell in a memory cell string, as illustrated by a comparative example. [Figure 16] This graph exemplifies the voltage-current characteristics of one memory cell in a memory cell string according to an embodiment. [Figure 17]This graph exemplifies the voltage-current characteristics of one memory cell in a memory cell string according to an embodiment. [Figure 18] This graph exemplifies the voltage-current characteristics of one memory cell in a memory cell string according to another embodiment. [Figure 19] This graph exemplifies the voltage-current characteristics of one memory cell in a memory cell string according to another embodiment. [Figure 20] Furthermore, this is a schematic vertical cross-sectional view showing the structure of a memory cell string according to another embodiment. [Figure 21] Furthermore, this is a schematic vertical cross-sectional view showing the structure of a memory cell string according to another embodiment. [Figure 22] Furthermore, this is a schematic vertical cross-sectional view showing the structure of a memory cell string according to another embodiment. [Figure 23] This is a conceptual diagram illustrating a schematic element architecture that may be applied to an exemplary electronic device, including a memory device, according to the embodiment. [Figure 24] This is a schematic diagram showing a neuromorphic device including a memory device according to an embodiment. [Modes for carrying out the invention]

[0029] A three-dimensional vertical non-volatile memory device including a memory cell string will be described in detail below with reference to the attached drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings is exaggerated for clarity and convenience of explanation. Furthermore, the embodiments described below are merely illustrative, and various modifications are possible from such embodiments.

[0030] In the following, the terms "upper / lower" and "up / down" may include not only those directly above / below in contact, but also those above / below without contact. Furthermore, spatially relative expressions such as "up" or "down" are indicated based on the direction shown in the drawing, and may be expressed differently if the orientation of the object changes. In other words, spatially relative expressions encompass not only the direction shown in the drawing but also different orientations of the element during use or operation, and therefore, if elements are arranged in different directions, the spatially relative expressions may be interpreted accordingly. A singular expression includes multiple expressions unless the context clearly indicates otherwise. Also, when a part "includes" a component, this means that it includes other components, not excludes them, unless otherwise stated.

[0031] The use of the term "the foregoing" and similar referential terms can be singular or plural. Unless otherwise explicitly stated, the steps constituting a method are performed in any order, but are not necessarily limited to the order stated.

[0032] Furthermore, terms such as "...part" and "module" as used in the specification refer to a unit that processes at least one function or operation, which may be implemented by hardware or software, or by a combination of hardware and software.

[0033] The lines or connecting members between components shown in the drawings exemplify functional and / or physical or circuit connections, and in actual devices, they may be substituted or represent a variety of additional functional, physical, or circuit connections.

[0034] All use of examples or illustrative terms is solely for the purpose of illustrating the technical idea in detail, and the scope of the invention is not limited by these examples or illustrative terms unless otherwise specified in the claims.

[0035] While the terms “identical,” “equivalent,” or “same” are used in the description of exemplary embodiments, it should be understood that there may be some degree of inaccuracy. Therefore, when one element is referred to as identical to another, it should be understood that the element or numerical value is identical to the other element within the desired manufacturing or operational tolerance range (e.g., ±10%). Also, expressions such as “approximately” or “substantially” used with numerical and / or geometric terms mean the numerical value including the manufacturing tolerance (e.g., ±10%) in the vicinity of the numerical value. Furthermore, regardless of expressions such as “approximately” or “substantially,” numerical values ​​should be understood to include the manufacturing or operational tolerance (e.g., ±10%) in the vicinity of that numerical value.

[0036] Figure 1 is a block diagram illustrating a memory system according to one embodiment. Referring to Figure 1, the memory system 10 according to one embodiment may include a memory controller 100 and a memory device 200. The memory controller 100 performs control operations on the memory device 200. For example, the memory controller 100 can perform program (or write), read (readout), and erase operations on the memory device 200 by providing addresses (ADD) and commands (CMD) to the memory device 200. In addition, data for program operations and read data can be transmitted and received between the memory controller 100 and the memory device 200. The memory device 200 provides the memory controller 100 with a pass / fail signal based on the read result of the read data, and the memory controller 100 can control the write / read operations of the memory cell array 210 by referring to the pass / fail signal.

[0037] The memory device 200 may include a memory cell array 210 and a voltage generating unit 220. The memory cell array 210 may include a plurality of memory cells arranged in a region where a plurality of word lines and a plurality of bit lines intersect. The memory cell array 210 includes non-volatile memory cells that store data in a non-volatile manner, and as non-volatile memory cells, the memory cell array 210 may include flash memory cells such as a NAND flash memory cell array 210 or a NOR flash memory cell array 210. Hereinafter, embodiments of the present disclosure will be described assuming that the memory cell array 210 includes a flash memory cell array 210, and that the memory device 200 is thus a non-volatile memory device.

[0038] The memory controller 100 may include a write / read control unit 110, a voltage control unit 120, and a data discrimination unit 130.

[0039] The write / read control unit 110 can generate addresses (ADD) and commands (CMD) for performing program / read and erase operations on the memory cell array 210. The voltage control unit 120 can also generate voltage control signals to control at least one voltage level used within the non-volatile memory device 200. For example, the voltage control unit 120 can generate voltage control signals to control the voltage level of a word line for reading data from or programming data into the memory cell array 210.

[0040] The data discrimination unit 130 can perform discrimination operations on data read from the memory device 200. For example, it can discriminate data read from memory cells and determine the number of on-cell and / or off-cell cells among the memory cells. As an example of operation, if a program is executed on multiple memory cells, it can determine whether the program has been successfully completed for all cells by using a predetermined read voltage to determine the data state of the memory cells.

[0041] As mentioned above, the memory cell array 210 includes non-volatile memory cells, and for example, the memory cell array 210 may include flash memory cells. Furthermore, flash memory cells can be implemented in various forms, and for example, the memory cell array 210 may include three-dimensional (or vertical) NAND (VNAND) memory cells.

[0042] Figure 2 is a block diagram showing one implementation example of the memory device 200 shown in Figure 1. Referring to Figure 2, the memory device 200 may further include a row decoder 230, an input / output circuit 240, and a control logic 250.

[0043] The memory cell array 210 may be connected to one or more string selection lines SSL, multiple word lines WL1 to WLm, and one or more common source lines CSLs, and may also be connected to multiple bit lines BL1 to BLn. The voltage generator 220 generates one or more word line voltages V1 to Vi, which may be provided by the row decoder 230. Signals for program / read / erase operations may be applied to the memory cell array 210 via the bit lines BL1 to BLn.

[0044] Furthermore, the programmed data is provided to the memory cell array 210 via the input / output circuit 240, and the read data can be provided to an external source (e.g., a memory controller 100) via the input / output circuit 240. The control logic 250 can provide various control signals related to memory operation to the row decoder 230 and the voltage generator 220.

[0045] The decoding operation of the raw decoder 230 may provide word line voltages V1 to Vi to various lines SSLs, WL1 to WLm, and CSLs. For example, the word line voltages V1 to Vi may include string selection voltages, word line voltages, and ground selection voltages, where string selection voltages are provided to one or more string selection lines SSLs, word line voltages are provided to one or more word lines WL1 to WLm, and ground selection voltages are provided to one or more common source lines CSLs.

[0046] Figure 3 is a block diagram of the memory cell array shown in Figure 1. Referring to Figure 3, the memory cell array 210 includes multiple memory blocks BLK1 to BLKz. Each memory block BLK has a three-dimensional structure (or vertical structure). For example, each memory block BLK may include structures extending along a first to third direction. For example, each memory block BLK may include multiple memory cell strings extending along a first direction (Z direction). Therefore, multiple memory cell strings may have a three-dimensional vertical structure. In this respect, the memory device 200 is also a three-dimensional vertical non-volatile memory device. Each memory cell string is connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL. Therefore, each memory block BLK1 to BLKz is connected to multiple bit lines BL, multiple string selection lines SSLs, multiple word lines WL, and multiple common source lines CSL. Such memory blocks BLK1 to BLKz will be described in more detail with reference to Figure 4.

[0047] Figure 4 is a diagram showing an equivalent circuit corresponding to a memory block according to one embodiment. Exemplarily, one of the memory blocks BLK1 to BLKz of the memory cell array 210 in Figure 3 is shown in Figure 4. Referring to Figures 3 and 4, each memory block BLK1 to BLKz contains multiple memory cell strings CS11 to CSkn. These memory cell strings CS11 to CSkn can be arranged two-dimensionally along the row and column directions to form rows and columns. Each memory cell string CS11 to CSkn contains multiple memory cell MCs and multiple string selection transistors SSTs. The memory cell MCs and string selection transistors SSTs of each memory cell string CS11 to CSkn can be stacked in the height direction.

[0048] Each row of memory cell strings CS11 to CSkn is connected to a different string selection line SSL1 to SSLk. For example, the string selection transistors SST of memory cell strings CS11 to CS1n are commonly connected to string selection line SSL1. The string selection transistors SST of memory cell strings CSk1 to CSkn are commonly connected to string selection line SSLk.

[0049] Furthermore, each of the multiple memory cell strings CS11 to CSkn is connected to a different bit line BL1 to BLn. For example, the memory cell MC and string selection transistor SST of memory cell strings CS11 to CSk1 may be commonly connected to bit line BL1, while the memory cell MC and string selection transistor SST of memory cell strings CS1n to CSkn may be commonly connected to bit line BLn.

[0050] Furthermore, each row of multiple memory cell strings CS11 to CSkn can be connected to different common source lines CSL1 to CSLk. For example, the string selection transistors SSTs of multiple memory cell strings CS11 to CS1n can be commonly connected to the common source line CSL1, and the string selection transistors SSTs of multiple memory cell strings CSK1 to CSkn can be commonly connected to the common source line CSLk.

[0051] Memory cells MC located at the same height from the substrate (or string selection transistor SST) are commonly connected to a single word line WL, while memory cells MC located at different heights may be connected to different word lines WL1 to WLm, respectively.

[0052] The memory block shown in Figure 4 is illustrative. The technical concepts of this disclosure are not limited to the memory block shown in Figure 4. For example, the number of rows of multiple memory cell strings CS11~CSkn may increase or decrease. Changing the number of rows of multiple memory cell strings CS11~CSkn may also change the number of string selection lines SSL1~SSLk connected to the rows of memory cell strings CS11~CSkn, and the number of memory cell strings CS11~CSkn connected to a single bit line. Changing the number of rows of memory cell strings CS11~CSkn may also change the number of common source lines CSL1~CSLk connected to the rows of memory cell strings CS11~CSkn. In addition, the number of columns of memory cell strings CS11~CSkn may increase or decrease. By changing the number of columns in the memory cell string CS11~CSkn, the number of bit lines BL1~BLn connected to the memory cell string CS11~CSkn, and the number of memory cell strings CS11~CSkn connected to a single string selection line SSL may also change.

[0053] The height of each memory cell string CS11~CSkn can be increased or decreased. For example, the number of memory cells MC stacked in each memory cell string CS11~CSkn can be increased or decreased. Changing the number of memory cells MC stacked in each memory cell string CS11~CSkn can also change the number of word lines WL. For example, the number of string selection transistors provided to each memory cell string CS11~CSkn can be increased. Changing the number of string selection transistors provided to each memory cell string CS11~CSkn can also change the number of string selection lines or common source lines. If the number of string selection transistors increases, the string selection transistors can be stacked in a form similar to memory cells MC.

[0054] Exemplary, write and read operations can be performed row by row of memory cell strings CS11-CSkn. Memory cell strings CS11-CSkn can be selected row by row by common source lines CSLs, and memory cell strings CS11-CSkn can be selected row by row by string selection lines SSLs. Then, within the selected rows of memory cell strings CS11-CSkn, write and read operations can be performed page by page. For example, a page is also a row of memory cell MC linked to a word line WL. Within the selected rows of memory cell strings CS11-CSkn, memory cell MC can be selected page by page by the word line WL.

[0055] On the other hand, each memory cell MC within each memory cell string CS11~CSkn may correspond to a circuit in which a transistor and a resistor are connected in parallel. For example, Figure 5 is a schematic vertical cross-sectional view showing the structure of each memory cell string according to one embodiment. Referring to Figure 5, the memory cell string CS may include a plurality of insulating spacers 311 and a plurality of gate electrodes 312 alternately stacked along a vertical direction, i.e., a first direction (Z direction), that intersects the second direction (X direction) orthogonally. The plurality of insulating spacers 311 and the plurality of gate electrodes 312 extend along a horizontal direction, i.e., the second direction. Each gate electrode 312 is connected to a word line WL or is a word line WL itself.

[0056] The insulating spacer 311 may, but is not limited to, include any one of a variety of insulating dielectric materials, such as silicon oxide, aluminum oxide, or silicon nitride. The gate electrode 312 may include, for example, at least one conductive material or a combination thereof from among tungsten (W), molybdenum (Mo), ruthenium (Ru), polysilicon, TiN, and metallic two-dimensional materials. The metallic two-dimensional materials may include, for example, at least one material from among graphene, TaS2, TaSe2, NbS2, NbSe2, PdTe2, PtTe2, NbTe2, TiSe2, VSe2, AuSe, and MoTe2.

[0057] Furthermore, the memory cell string CS may include a channel hole that penetrates a plurality of insulating spacers 311 and a plurality of gate electrodes 312 in a first direction. Multiple layers for forming channels and resistors may be provided within the channel hole. For example, the memory cell string CS may include an insulating support 321 located at the center of the channel hole and extending in a first direction, a channel layer 322 surrounding the insulating support 321 and extending in a first direction, an electrochemical layer 323 surrounding the channel layer 322 and extending in a first direction, and a blocking layer 324 surrounding the electrochemical layer 323 and extending in a first direction. The electrochemical layer 323 may be located between the channel layer 322 and the plurality of gate electrodes 312 and between the channel layer 322 and the plurality of insulating spacers 311. The blocking layer 324 may be located between the electrochemical layer 323 and the multiple gate electrodes 312, and between the electrochemical layer 323 and the multiple insulating spacers 311.

[0058] The blocking layer 324 may have a multilayer structure including a charge trap layer 324a. For example, the blocking layer 324 may include a first barrier layer 324b extending in a first direction, a charge trap layer 324a extending in a first direction, and a second barrier layer 324c extending in a first direction. Both sides of the charge trap layer 324a are surrounded by the first barrier layer 324b and the second barrier layer 324c. The first barrier layer 324b is provided between the charge trap layer 324a and a plurality of gate electrodes 312 and between the charge trap layer 324a and a plurality of insulating spacers 311, and the second barrier layer 324c may be provided between the electrochemical layer 323 and the charge trap layer 324a.

[0059] Figure 6 is a schematic horizontal cross-sectional view showing the structure of a memory cell string CS according to an embodiment. Referring to Figure 6, an insulating support 321, a channel layer 322, an electrochemical layer 323, a second barrier layer 324c, a charge trapping layer 324a, and a first barrier layer 324b can be arranged concentrically from the center outwards. Therefore, the first barrier layer 324b may have a cylindrical shape surrounding the charge trapping layer 324a. The charge trapping layer 324a may have a cylindrical shape surrounding the second barrier layer 324c. The second barrier layer 324c may have a cylindrical shape surrounding the electrochemical layer 323. The electrochemical layer 323 may have a cylindrical shape surrounding the channel layer 322. The channel layer 322 may have a cylindrical shape surrounding the insulating support 321. Although not shown in Figure 6, a plurality of insulating spacers 311 and a plurality of gate electrodes 312 may be stacked alternately in the first direction while surrounding the blocking layer 324.

[0060] For this purpose, the blocking layer 324 may be conformally deposited on a plurality of insulating spacers 311 and a plurality of gate electrodes 312 and extend along the first direction. The electrochemical layer 323 may be conformally deposited along the surface of the blocking layer 324 and extend along the vertical direction. The channel layer 322 may be conformally deposited along the surface of the electrochemical layer 323 and extend along the vertical direction. The insulating support 321 may be provided to fill the remaining space in the center of the channel hole and extend along the vertical direction.

[0061] As a result, the channel layer 322 has a configuration that extends in a first direction opposite to the plurality of insulating spacers 311 and the plurality of gate electrodes 312, the electrochemical layer 323 has a configuration that extends in a first direction between the channel layer 322 and the plurality of gate electrodes 312, and the blocking layer 324 has a configuration that extends in a first direction between the electrochemical layer 323 and the plurality of gate electrodes 312.

[0062] Although not shown, a drain may be provided on the uppermost surface of the memory cell string CS so as to cover at least the upper surface of the channel layer 322. The drain may contain doped semiconductor material. The drain may be electrically connected to the upper part of the channel layer 322. A bit line BL may also be connected to such a drain. A source may be provided on the lower surface of the channel layer 322. The source may contain doped semiconductor material. The source may be electrically connected to the lower part of the channel layer 322. A common source line CSL may also be connected to such a source.

[0063] According to the embodiment, ion exchange can occur between the channel layer 322 and the electrochemical layer 323 due to a program voltage (i.e., write voltage) or erase voltage applied to the gate electrode 312. For example, when a negative (-) write voltage is applied to the gate electrode 312, ions may move from the channel layer 322 to the electrochemical layer 323, decreasing the ion concentration in the channel layer 322. In this case, the resistance of the channel layer 322 increases. Conversely, when a positive (+) erase voltage is applied to the gate electrode 312, ions may move from the electrochemical layer 323 to the channel layer 322, increasing the ion concentration in the channel layer 322. In this case, the resistance of the channel layer 322 decreases. Therefore, the channel layer 322 can have both the function of a current flow path and the function of a resistance changing layer.

[0064] In embodiments, ions are also donor ions that function as electron donors. For example, a donor ion is also an oxygen vacancy. The electrochemical layer 323 may contain a relatively large amount of donor ions, such as oxygen vacancies, or may contain a metal oxide material that readily accommodates / ejects donor ions. For example, the electrochemical layer 323 may contain an oxide of at least one metal from among the following: Group 3 metals such as scandium (Sc), yttrium (Y), and lanthanum (La); Group 4 metals such as titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), and cerium (Ce); Group 5 metals such as vanadium (V), niobium (Nb), and tantalum (Ta); and Group 6 metals such as chromium (Cr), molybdenum (Mo), and tungsten (W).

[0065] The electrochemical layer 323 may have a stoichiometrically oxygen-deficient composition, such that it contains a relatively high concentration of donor ions (e.g., oxygen vacancies). For example, if the electrochemical layer 323 contains an oxide of a group 3 metal, the ratio of oxygen atoms to metal atoms within the electrochemical layer 323 is approximately 1.35 or less. If the electrochemical layer 323 contains an oxide of a group 4 metal, the ratio of oxygen atoms to metal atoms within the electrochemical layer 323 is approximately 1.8 or less. If the electrochemical layer 323 contains an oxide of a group 5 metal, the ratio of oxygen atoms to metal atoms within the electrochemical layer 323 is approximately 2.25 or less. If the electrochemical layer 323 contains an oxide of a group 6 metal, the ratio of oxygen atoms to metal atoms within the electrochemical layer 323 is approximately 2.7 or less.

[0066] The channel layer 322 may contain a material that readily accommodates / expels ions (e.g., oxygen vacancies) and whose electrical resistance changes depending on the ion concentration. For this reason, the channel layer 322 may contain an oxide semiconductor material. For example, the channel layer 322 may contain at least one oxide semiconductor material from among IGZO (indium-gallium-zinc oxide), IZO (indium-zinc oxide), GZO (gallium-zinc oxide), ZTO (zinc-tin oxide), and IWO (indium tungsten oxide). In addition, the channel layer 322 may contain a variety of other oxide semiconductor materials besides IGZO, IZO, GZO, ZTO, and IWO.

[0067] Furthermore, according to the embodiment, charges can be trapped in the charge trapping layer 324a of the blocking layer 324 by a program voltage (i.e., write voltage) or erase voltage applied to the gate electrode 312. For example, when a negative (-) write voltage is applied to the gate electrode 312, electrons can move from the gate electrode 312 to the charge trapping layer 324a and be trapped in the charge trapping layer 324a. Electrons trapped in the charge trapping layer 324a can increase the threshold voltage. Conversely, when a positive (+) erase voltage is applied to the gate electrode 312, electrons trapped in the charge trapping layer 324a can move to the gate electrode 312. In this case, holes exist in the charge trapping layer 324a, which lowers the threshold voltage.

[0068] The charge trapping layer 324a may include a metal nitride material or a metal oxide material that can trap or provide charge by a voltage applied to the gate electrode 312. For example, the charge trapping layer 324a may include at least one of the following: metal nitride materials such as silicon nitride (SiN), aluminum nitride (AlN), hafnium nitride (HfN), silicon oxynitride (SiON), aluminum oxynitride (AlON), hafnium oxynitride (HfON), or metal oxide materials such as hafnium oxide (HfO), zirconium oxide (ZrO), tantalum oxide (TaO), or titanium oxide (TiO). If the charge trapping layer 324a includes a metal oxide material such as hafnium oxide (HfO), zirconium oxide (ZrO), tantalum oxide (TaO), or titanium oxide (TiO), the metal oxide material may be doped with silicon (Si) or aluminum (Al) to have sufficient charge trapping sites.

[0069] The first barrier layer 324b can function to prevent or reduce the leakage of charge trapped in the charge trapping layer 324a to the gate electrode 312. The second barrier layer 324c can function to prevent or reduce ion exchange between the charge trapping layer 324a and the electrochemical layer 323, thereby preventing or reducing the leakage of charge trapped in the charge trapping layer 324a to the electrochemical layer 323. The first barrier layer 324b and the second barrier layer 324c may include at least one metal oxide material from among, for example, aluminum oxide (AlO), silicon oxide (SiO), hafnium oxide (HfO), and zirconium oxide (ZrO). The metal oxide materials of the first barrier layer 324b and the second barrier layer 324c may have a composition that is undoped and stoichiometrically oxygen-free.

[0070] Furthermore, referring to Figure 5, as shown by the dotted box, any one gate electrode 312 and a portion of the blocking layer 324, a portion of the electrochemical layer 323, and a portion of the channel layer 322 adjacent to that gate electrode 312 in the horizontal direction, i.e., the second direction, can form a single memory cell MC. For example, one gate electrode 312 and a portion of the blocking layer 324, a portion of the electrochemical layer 323, and a portion of the channel layer 322 adjacent to it in the horizontal direction can form a transistor. Also, a portion of the channel layer 322 can form a resistor. In this respect, the channel layer 322 can perform both the role of a transistor channel and the role of a resistive switching layer. Therefore, each memory cell MC can correspond to a circuit in which a transistor and a resistor are connected in parallel. Multiple such memory cell MCs can be arranged in a vertical stacked structure to form each memory cell string CS. According to the embodiment, since an oxide semiconductor material having a relatively high electrical conductivity compared to polysilicon (p-Si) is used as the channel layer 322, the number of memory cell MCs that can be stacked in the memory cell string CS can be increased.

[0071] The thickness of one memory cell MC is determined by the first-direction height t1 of one gate electrode 312, and the spacing between two adjacent memory cell MCs in the first direction may be determined by the first-direction height t2 of one insulating spacer 311. The integration density of memory cell MCs can be increased by reducing the first-direction height t2 of one insulating spacer 311 or the spacing between two adjacent gate electrodes 312 in the first direction. For example, the first-direction height t1 of one gate electrode 312 may be about 20 nm or less. According to the embodiment, the first-direction height t2 of one insulating spacer 311 can be reduced because the drive voltage applied to each gate electrode 312 is relatively low. For example, the first-direction height t2 of one insulating spacer 311 may be about 15 nm or less, about 10 nm or less, or about 8 nm or less.

[0072] The thickness d1 of the blocking layer 324 in the second direction is, for example, about 5 nm to about 15 nm. The thickness d2 of the charge trapping layer 324a in the second direction is also about 10% to 60% of the thickness d1 of the blocking layer 324 in the second direction. For example, the thickness d2 of the charge trapping layer 324a in the second direction is also about 1 nm to about 10 nm. The first barrier layer 324b and the second barrier layer 324c may, but are not limited to, have the same thickness in the second direction. If the charge leakage from the charge trapping layer 324a to the gate electrode 312 is sufficiently small, the thickness of the first barrier layer 324b between the charge trapping layer 324a and the gate electrode 312 in the second direction is thinner than the thickness of the second barrier layer 324c between the charge trapping layer 324a and the electrochemical layer 323 in the second direction. Also, the thickness d3 of the electrochemical layer 323 in the second direction is, for example, about 2 nm to about 20 nm. The thickness d4 of the channel layer 322 in the second direction is, for example, approximately 2 nm to approximately 10 nm.

[0073] Figure 7 is a schematic vertical cross-sectional view showing the structure of a memory cell string CS according to another embodiment. Referring to Figure 7, the electrochemical layer 323 may have a multilayer structure. For example, the electrochemical layer 323 may include an ion reservoir layer 323a extending along a first direction and an electrolyte layer 323b extending along the first direction. The ion reservoir layer 323a may be provided adjacent to the blocking layer 324, and the electrolyte layer 323b may be provided adjacent to the channel layer 322. That is, the electrolyte layer 323b may be provided between the ion reservoir layer 323a and the channel layer 322. When a write voltage or erase voltage is applied to the gate electrode 312, the electrolyte layer 323b may function as an ion transfer path between the channel layer 322 and the ion reservoir layer 323a, and when no write voltage or erase voltage is applied to the gate electrode 312, it may function as a barrier layer that prevents or reduces ion exchange between the channel layer 322 and the ion reservoir layer 323a.

[0074] The ion storage layer 323a and the electrolyte layer 323b may contain oxides of at least one metal from among the following: Group 3 metals such as scandium (Sc), yttrium (Y), and lanthanum (La); Group 4 metals such as titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), and cerium (Ce); Group 5 metals such as vanadium (V), niobium (Nb), and tantalum (Ta); and Group 6 metals such as chromium (Cr), molybdenum (Mo), and tungsten (W). The ratio of oxygen to the total material in the ion storage layer 323a is smaller than the ratio of oxygen to the total material in the electrolyte layer 323b, so that the ion storage layer 323a contains a relatively high concentration of donor ions (e.g., oxygen vacancies). For example, the ion storage layer 323a may have a stoichiometrically oxygen-deficient composition, while the electrolyte layer 323b may have a stoichiometrically oxygen-free composition. In other words, the concentration of donor ions in the ion storage layer 323a is higher than the concentration of donor ions in the electrolyte layer 323b. Hereafter, donor ions can be simply referred to as ions.

[0075] The thickness d5 of the ion storage layer 323a in the second direction is, for example, about 2 nm to about 10 nm. The thickness d6 of the electrolyte layer 323b in the second direction is, for example, about 1 nm to 10 nm. To facilitate ion transfer between the ion storage layer 323a and the channel layer 322, the thickness d6 of the electrolyte layer 323b in the second direction is smaller than the thickness d5 of the ion storage layer 323a in the second direction. For example, the thickness d6 of the electrolyte layer 323b in the second direction is about 1 nm to 5 nm. By providing an electrolyte layer 323b between the channel layer 322 and the ion storage layer 323a that prevents or reduces ion exchange between the channel layer 322 and the ion storage layer 323a, the ion storage layer 323a can contain ions at an even higher concentration. For example, the ion storage layer 323a can contain ions at a higher concentration than the single-layer electrochemical layer 323 shown in Figure 5.

[0076] Figures 8A to 8G illustrate the method for manufacturing the memory cell string CS shown in Figure 7.

[0077] Referring to Figure 8A, multiple insulating spacers 311 and multiple gate electrodes 312 can be stacked alternately along the first direction.

[0078] Referring to Figure 8B, the centers of multiple insulating spacers 311 and multiple gate electrodes 312 can be etched to form a channel hole CH. Then, referring to Figure 8C, for example, an atomic layer deposition (ALD) method can be used to conformally deposit a first barrier layer 324b along the side walls of the multiple insulating spacers 311 and the multiple gate electrodes 312 within the channel hole CH.

[0079] Subsequently, as shown in Figures 8D to 8G, a charge trapping layer 324a may be conformally deposited along the sidewall of the first barrier layer 324b using an atomic layer deposition method, a second barrier layer 324c may be conformally deposited along the sidewall of the charge trapping layer 324a, an ion storage layer 323a may be conformally deposited along the sidewall of the second barrier layer 324c, an electrolyte layer 323b may be conformally deposited along the sidewall of the ion storage layer 323a, and a channel layer 322 may be conformally deposited along the sidewall of the electrolyte layer 323b. The center of the remaining channel hole CH may be left as a cavity, or an insulating support 321 may be deposited to fill the remaining space in the center of the channel hole CH.

[0080] According to the embodiment, programming and erasing operations in a memory cell string CS can be performed independently for each memory cell MC in the memory cell string CS. Figure 9 illustrates the programming operation of a memory cell string CS according to the embodiment, and Figure 10 illustrates the erasing operation of a memory cell string CS according to the embodiment. In Figures 9 and 10, for convenience, the insulating support 321 and the symmetrical portions of the remaining layers shown in Figure 5 have been omitted.

[0081] Referring to Figure 9, among the multiple gate electrodes 312, the gate electrode 312 of the memory cell where the programmed operation is performed has a negative (-) programmed voltage V PRcan be applied via the word line WL. As a result, a negative (-) program voltage V PR ions (e.g., oxygen vacancies) in a partial region of the channel layer 322 adjacent to the gate electrode 312 to which the negative (-) program voltage V PR is applied can move to a partial region of the electrochemical layer 323 adjacent to the gate electrode 312 to which the negative (-) program voltage V PR is applied in the second direction. When the electrochemical layer 323 includes an ion storage layer 323a and an electrolyte layer 323b as shown in FIG. 7, the ions in a partial region of the channel layer 322 adjacent to the gate electrode 312 to which the negative (-) program voltage V PR is applied can pass through the electrolyte layer 323b and move to a partial region of the ion storage layer 323a adjacent to the gate electrode 312 to which the negative (-) program voltage V

[0082] As a result, the concentration of donor ions such as oxygen vacancies in the channel layer 322 decreases. For example, when a partial region of the channel layer 322 has a relatively low first ion concentration, the partial region of the channel layer 322 has a relatively high first resistance or a relatively low first electrical conductivity. In this case, the transistor including the gate electrode 312 to which the negative (-) program voltage V PR is applied and a part of the electrochemical layer 323 and a part of the channel layer 322 adjacent to the gate electrode 312 in the second direction may have a relatively high first threshold voltage.

[0083] Also, if a negative (-) program voltage V PR is applied to the gate electrode 312, electrons can move in a partial region of the charge trapping layer 324a adjacent to the gate electrode 312 to which the negative (-) program voltage V PR is applied from the gate electrode 312 to which the negative (-) program voltage V PR is applied in the second direction. As a result, electrons can be trapped in a partial region of the charge trapping layer 324a adjacent to the gate electrode 312 to which the negative (-) program voltage V PR is applied. The electrons trapped in the charge trapping layer 3a can shift the first threshold voltage in the positive direction and further increase the first threshold voltage.

[0084] On the other hand, referring to Figure 10, the gate electrode 312 of the memory cell on which the erase operation is performed has a positive erase voltage V ER This can be applied through the word line WL. This allows for a positive (+) elimination voltage V ER When the gate electrode 312 to which the voltage is applied has a positive (+) elimination voltage V applied to a portion of the electrochemical layer 323 adjacent to it in the second direction, the ions in that region have a positive (+) elimination voltage V ER The voltage applied to the gate electrode 312 can move to a portion of the channel layer 322 adjacent in the second direction. When the electrochemical layer 323 includes an ion storage layer 323a and an electrolyte layer 323b as shown in Figure 7, the positive (+) elimination voltage V ER Ions in a portion of the ion storage layer 323a adjacent to the gate electrode 312 in the second direction, to which the voltage V is applied, pass through the electrolyte layer 323b and undergo a positive (+) elimination voltage V ER The applied electrode 312 may move to a portion of the channel layer 322 adjacent in the second direction.

[0085] This increases the concentration of donor ions, such as oxygen vacancies, within the channel layer 322. For example, if a portion of the channel layer 322 has a second ion concentration higher than the first ion concentration, then that portion of the channel layer 322 has a second resistance lower than the first resistance or a second electrical conductivity higher than the first electrical conductivity. In this case, the positive (+) elimination voltage V ER A transistor including a gate electrode 312 to which a voltage is applied, and a portion of the electrochemical layer 323 and a portion of the channel layer 322 adjacent to the gate electrode 312 in the second direction, may have a relatively low second threshold voltage. Here, the second threshold voltage is the negative (-) program voltage V PR The first threshold voltage is higher than the second threshold voltage and is positive (+) and has a positive (+) elimination voltage V ER This is higher than the first threshold voltage.

[0086] Additionally, a positive (+) cancellation voltage V is applied to the gate electrode 312. ERWhen a positive (+) elimination voltage V is applied, electrons can move from a portion of the charge trapping layer 324a adjacent to the gate electrode 312 in the second direction to the gate electrode 312. ER In the charge trapping layer 324a adjacent to the gate electrode 312 to which the voltage is applied in the second direction, the amount of electrons may decrease and the amount of holes may increase. This may cause the second threshold voltage to shift in the negative direction and become even lower.

[0087] On the other hand, among the multiple gate electrodes 312, the gate electrodes 312 of the remaining memory cells that are not subjected to program or erase operations are in a floating state where no voltage is applied. Ions do not move between the region of the electrochemical layer 323 and the region of the channel layer 322 adjacent to the floating gate electrode 312 in the second direction. Therefore, the threshold voltage does not change in the remaining memory cells among the multiple gate electrodes 312 that are not subjected to program or erase operations.

[0088] Although Figures 9 and 10 illustrate only one memory cell, multiple memory cells within a single memory cell string CS can be programmed or erased independently at the same time. For example, a positive erase voltage V can be applied to the gate electrode 312 of one memory cell. ER While the voltage is applied, a negative (-) programmed voltage V is applied to the gate electrode 312 of other adjacent memory cells. PR It may be applied.

[0089] Figure 11 illustrates the read operation on the selected memory cell of the memory cell string CS after the program operation according to the embodiment, and Figure 12 illustrates the read operation on the selected memory cell of the memory cell string CS after the erase operation according to the embodiment. The read operation involves applying a positive (+) read voltage V only to the gate electrode 312 of the selected memory cell sMC from which data is read within the memory cell string CS. RD By applying this voltage, a positive (+) path voltage V is applied to the gate electrodes 312 of all remaining non-selected memory cells nMC. PS With the applied current, the current I flows along the channel layer 322.D This can be performed using a method that measures the readout voltage V. RD The program voltage V PR Higher, erase voltage V ER Lower. In particular, the read voltage V RD The reading voltage V is higher than the second threshold voltage when the ion concentration in the channel layer 322 is relatively high (for example, when the channel layer 322 has a second ion concentration), and lower than the first threshold voltage when the ion concentration in the channel layer 322 is relatively low (for example, when the channel layer 322 has a first ion concentration). RD Also, the pass voltage V PS It can be lower. Path voltage V PS This refers to the first threshold voltage, the second threshold voltage, and the readout voltage V RD Higher erase voltage V ER It can be lower. That is, the read voltage V RD This is also the voltage that turns off the transistor of the memory cell nMC when the channel layer 322 has a first ion concentration, and turns on the transistor of the memory cell nMC when the channel layer 322 has a second ion concentration. (Path voltage V) PS This voltage is also the voltage that turns on the transistors of the memory cell nMC while preventing movement between the channel layer 322 and the electrochemical layer 323, regardless of the ion concentration, resistance, or electrical conductivity within the channel layer 322.

[0090] Referring to Figure 11, the path voltage V PS When the voltage is applied to the transistor of the non-selected memory cell nMC, it turns on. When the channel layer 322 of the selected memory cell sMC has a first ion concentration, the read voltage V RD The transistor of the selected memory cell sMC to which the current is applied turns off. That is, the channel layer 322 of the selected memory cell sMC has a relatively high first resistance. Therefore, almost no current flows through the channel layer 322 of the selected memory cell sMC, and as a result, current I flows through the channel layer 322 between the source and drain. DThe current almost completely stops flowing. In other words, a relatively low first current flows between the source and the drain through the channel layer 322.

[0091] On the other hand, referring to Figure 12, when the channel layer 322 of the selected memory cell sMC has a second ion concentration, the read voltage V RD The transistors of the selected memory cell sMC to which the current is applied turn on. Therefore, all transistors in the memory cell string CS turn on, and current I flows through the channel layer 322 between the source and drain along the channel layer 322. D A current I can flow between the source and drain. That is, a second current greater than the first current flows through the channel layer 322 between the source and drain. In this manner, the current I between the source and drain of the memory cell string CS D The data recorded in the selected memory cells (sMC) can be read through the intensity of the signal.

[0092] According to the embodiment, the aforementioned program voltage V PR or erase voltage V ER The absolute value of such a drive voltage is relatively low compared to, for example, the drive voltage of a charge trap flash (CTF) type memory device. For example, the absolute value of the drive voltage of a memory cell string CS according to the embodiment is about 70% or less, or about 60% or less, or about 50% or less, of the absolute value of the drive voltage of a charge trap flash type memory cell string. Therefore, interference with adjacent memory cells is reduced by the relatively low drive voltage during program or erase operations on any of the memory cells, thus reducing the spacing between adjacent memory cells and increasing the integration density of the memory cell string CS according to the embodiment. For example, the spacing between adjacent memory cells in a memory cell string CS according to the embodiment is about 70% or less, or about 60% or less, or about 50% or less, of the spacing between adjacent memory cells in a charge trap flash type memory cell string.

[0093] Furthermore, according to the embodiment, the memory window, which is the difference between the first threshold voltage and the second threshold voltage, can be further increased by further including a charge trapping layer 324a in the memory cell string CS. Figure 13 is a graph illustrating the principle of memory window increase due to the charge trapping layer. In Figure 13, the thin solid line exemplifies the voltage-current characteristics of a memory cell without the charge trapping layer 324a, and the thick solid line exemplifies the voltage-current characteristics of a memory cell with the charge trapping layer 324a. Referring to Figure 13, the width of the hysteresis curve in a memory cell with the charge trapping layer 324a is wider than the width of the hysteresis curve in a memory cell without the charge trapping layer 324a. That is, by further including the charge trapping layer 324a, the second threshold voltage can be further shifted in the negative direction, and the first threshold voltage can be further shifted in the positive direction. Therefore, the memory window of a memory cell with the charge trapping layer 324a is further larger than that of a memory cell without the charge trapping layer 324a.

[0094] Figures 14 and 15 are illustrative graphs showing the voltage-current characteristics of a single memory cell in the comparative example memory cell string. The blocking layer 324 of the comparative example memory cell string may include only a barrier layer and not a charge trapping layer. In the comparative example, the barrier layer contains aluminum oxide (AlO) and has a thickness of approximately 10 nm in the second direction. The graph in Figure 14 shows the result of sweeping the voltage applied to the gate electrode 312 between -5V and +5V, and the graph in Figure 15 shows the result of sweeping the voltage applied to the gate electrode 312 between -10V and +10V. Referring to Figure 14, when a voltage between -5V and +5V is applied to the gate electrode 312, the first threshold voltage and the second threshold voltage are not clearly distinguished. Therefore, the comparative example memory cell string has difficulty performing memory functions at drive voltages between -5V and +5V. Referring to Figure 15, when a voltage between -10V and +10V is applied to the gate electrode 312, the memory window, which is the difference between the first threshold voltage and the second threshold voltage, is approximately 6V. Here, the threshold voltage is the applied voltage at which the memory cell is reliably turned on, and in the graphs of Figures 14 and 15, the threshold voltage can be defined as the applied voltage when the source-drain current is approximately 1E-10A.

[0095] Figures 16 and 17 are illustrative graphs showing the voltage-current characteristics of one memory cell in a memory cell string according to an embodiment. In Figures 16 and 17, the first barrier layer 324b of the memory cell string CS according to the embodiment comprises aluminum oxide (AlO) with a thickness of 2 nm in the second direction, the charge trapping layer 324a comprises silicon nitride (SiN) with a thickness of 2 nm in the second direction, and the second barrier layer 324c comprises aluminum oxide (AlO) with a thickness of 6 nm in the second direction. The graph in Figure 16 shows the result of sweeping the voltage applied to the gate electrode 312 from -5V to +5V, and the graph in Figure 17 shows the result of sweeping the voltage applied to the gate electrode 312 from -10V to +10V. Referring to Figure 16, the memory cell string according to the embodiment can operate as a memory even with a relatively low drive voltage of 5V. This is interpreted as the hysteresis effect occurring first in the charge trapping layer 324a because the voltage for injecting charge into the charge trapping layer 324a is lower than the voltage for ion exchange between the channel layer 322 and the electrochemical layer 323. Also, referring to Figure 17, when a voltage between -10V and +10V is applied to the gate electrode 312, the memory window, which is the difference between the first threshold voltage and the second threshold voltage, is approximately 7V or more.

[0096] Figures 18 and 19 are illustrative graphs showing the voltage-current characteristics of one memory cell in a memory cell string according to another embodiment. In Figures 18 and 19, the first barrier layer 324b of the memory cell string CS according to another embodiment contains silicon oxide (SiO) with a thickness of 2 nm in the second direction, the charge trapping layer 324a contains silicon nitride (SiN) with a thickness of 2 nm in the second direction, and the second barrier layer 324c contains silicon oxide (SiO) with a thickness of 6 nm in the second direction. The graph in Figure 18 shows the result of sweeping the voltage applied to the gate electrode 312 from -5V to +5V, and the graph in Figure 19 shows the result of sweeping the voltage applied to the gate electrode 312 from -10V to +10V. Referring to Figures 18 and 19, the memory window when the first and second barrier layers 324b and 324c contain silicon oxide (SiO) is even larger than the memory window when they contain aluminum oxide (AlO). For example, when a voltage between -10V and +10V is applied to the gate electrode 312, the memory window in embodiments in which the first and second barrier layers 324b and 324c are silicon oxide (SiO) is approximately 8V or greater. This can be interpreted as the threshold voltage shift effect being even greater because silicon oxide (SiO) has an even lower dielectric constant than aluminum oxide (AlO). Therefore, it is advantageous to use oxide materials with relatively low dielectric constants as the first and second barrier layers 324b and 324c.

[0097] Figures 20 and 21 are schematic vertical cross-sectional views showing the structure of a memory cell string according to yet another embodiment. Up to this point, it has been explained that the blocking layer 324 includes both a first barrier layer 324b and a second barrier layer 324c, but one of the first barrier layer 324b and the second barrier layer 324c may be omitted. For example, if there is little possibility that the charge trapped in the charge trapping layer 324a will leak to the gate electrode 312, the first barrier layer 324b may be omitted, and if there is little possibility that the charge trapped in the charge trapping layer 324a will leak to the electrochemical layer 323 and that ions from the electrochemical layer 323 will move to the charge trapping layer 324a, the second barrier layer 324c may be omitted.

[0098] Referring to Figure 20, the blocking layer 324 of the memory cell string may consist only of a first barrier layer 324b and a charge trapping layer 324a. In this case, the charge trapping layer 324a may be in direct contact with the electrochemical layer 323. Also, referring to Figure 21, the blocking layer 324 of the memory cell string may consist only of a charge trapping layer 324a and a second barrier layer 324c. In this case, the charge trapping layer 324a may be in direct contact with the gate electrode 312 and the insulating spacer 311.

[0099] Figure 22 is a schematic vertical cross-sectional view showing the structure of a memory cell string according to yet another embodiment. Referring to Figure 22, the electrochemical layer 323' may have a composition that gradually changes along a second direction. For example, the electrochemical layer 323' may have the highest oxygen composition at a first surface adjacent to the channel layer 322 and the lowest oxygen composition at a second surface adjacent to the blocking layer 324. For this reason, the proportion of oxygen may gradually or continuously increase along the second direction toward the channel layer 322 within the electrochemical layer 323'. In this case, the concentration of ions such as oxygen vacancies in the electrochemical layer 323' may gradually or continuously decrease along the second direction toward the channel layer 322 and gradually or continuously increase along the second direction toward the blocking layer 324. Thus, the region adjacent to the channel layer 322 within the electrochemical layer 323' may act as an electrolyte layer, and the region adjacent to the blocking layer 324 may act as an ion storage layer.

[0100] The aforementioned memory device 200 can be used for data storage in various electronic devices. Figure 23 is a conceptual diagram schematically showing an element architecture that may be applied to an electronic device according to an exemplary embodiment. Referring to Figure 23, the electronic device 400 may include a main memory 410, auxiliary storage 420, a CPU (central processing unit) 430, and an input / output device 440. The CPU 430 may include a cache memory 431, an ALU (arithmetic logic unit) 432, and a control unit 433. The cache memory 431 consists of SRAM (Static Random Access Memory). The main memory 410 includes DRAM elements, and the auxiliary storage 420 may include the memory device 200 according to the embodiment. Alternatively, the cache memory 431, main memory 410, and auxiliary storage 420 may all include the memory devices 100 and 200 according to the embodiment. Depending on the circumstances, the electronic device 400 may be implemented in a configuration where computer unit elements and memory unit elements are adjacent to each other on a single chip, without the aforementioned subunit divisions.

[0101] Furthermore, the memory device 200 can be used as a neuromorphic computer platform. For example, Figure 24 schematically shows a neuromorphic device including the memory device 200 according to an embodiment. Referring to Figure 24, the neuromorphic device 1000 may include a processing circuit 1010 and / or memory 1020. The memory 1020 of the neuromorphic device 1000 may include the memory device 200 according to an embodiment.

[0102] The processing circuit 1010 may be configured to control functions for driving the neuromorphic device 1000. For example, the processing circuit 1010 may control the neuromorphic device 1000 by executing a program stored in the neuromorphic device 1020. The processing circuit 1010 may include hardware such as logic circuits, a combination of hardware and software such as a processor that executes software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) within the neuromorphic device 1000, an arithmetic logic unit (ALU), a digital processor, a microcomputer, an FPGA (field programmable gate array), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like. Furthermore, the processing circuit 1010 can read and write various data to the external device 1030 and use that data to run the neuromorphic device 1000. The external device 1030 may include a sensor array equipped with external memory and / or an image sensor (e.g., a CMOS image sensor circuit).

[0103] The neuromorphic device 1000 shown in Figure 24 can be applied to a machine learning system. The machine learning system can utilize a variety of artificial neural network structures and processing models, including, for example, convolutional neural networks (CNNs), deconvolutional neural networks, recurrent neural networks (RNNs) that selectively include long short-term memory (LSTMs) and / or gated recurrent units (GRUs), stacked neural networks (SNNs), state-space dynamic neural networks (SSDNNs), deep belief networks (DBNs), generative adversarial networks (GANs), and / or restricted Boltzmann machines (RBMs).

[0104] Such machine learning systems may include, for example, combinations of machine learning models such as linear regression and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and expert systems, and / or ensemble techniques such as random forests. Such machine learning models can be used to provide a variety of services, such as video classification services, user authentication services based on biometric information or biometric data, advanced driver assistance systems (ADAS), voice assistant services, and automatic speech recognition (ASR) services, and may be mounted on and run in other electronic devices.

[0105] The embodiments described above can be summarized as follows: (1) In one embodiment, a three-dimensional vertical non-volatile memory device includes a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers; wherein the electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer by a voltage applied to the plurality of gate electrodes, and the blocking layer may include a charge trapping layer extending along the first direction and configured to trap charges by a voltage applied to the plurality of gate electrodes.

[0106] (2) In one example, the charge trapping layer may include at least one material from among silicon nitride, aluminum nitride, hafnium nitride, silicon oxynitride, aluminum oxynitride, hafnium oxynitride, hafnium oxide, zirconium oxide, tantalum oxide, and titanium oxide.

[0107] (3) In other examples, the charge trapping layer may include a metal oxide material doped with silicon (Si) or aluminum (Al).

[0108] (4) The blocking layer may further include at least one of a first barrier layer extending in a first direction between the charge trapping layer and the plurality of gate electrodes and between the charge trapping layer and the plurality of insulating spacers, and a second barrier layer extending in a first direction between the electrochemical layer and the charge trapping layer.

[0109] (5) The first barrier layer and the second barrier layer may each contain at least one material selected from aluminum oxide, silicon oxide, hafnium oxide, and zirconium oxide.

[0110] (6) For example, the thickness of the blocking layer in the second direction is 5 nm to 15 nm, and the thickness of the charge trapping layer in the second direction is 1 nm to 10 nm.

[0111] (7) In one example, the blocking layer includes both the first barrier layer and the second barrier layer, wherein the thickness of the first barrier layer in the second direction is thinner than the thickness of the second barrier layer in the second direction.

[0112] (8) The electrochemical layer may contain an oxide of at least one of the following metals: scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W).

[0113] (9) In one example, if the electrochemical layer contains an oxide of at least one metal from scandium (Sc), yttrium (Y), and lanthanum (La), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.35 or less; if the electrochemical layer contains an oxide of at least one metal from titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), and cerium (Ce), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.8 or less; if the electrochemical layer contains an oxide of at least one metal from vanadium (V), niobium (Nb), and tantalum (Ta), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 2.25 or less; and if the electrochemical layer contains an oxide of at least one metal from chromium (Cr), molybdenum (Mo), and tungsten (W), the ratio of oxygen atoms to metal atoms in the electrochemical layer is also 2.7 or less.

[0114] (10) The electrochemical layer may include an ion storage layer adjacent to the blocking layer and extending in a first direction, and an electrolyte layer adjacent to the channel layer and extending in a first direction.

[0115] (11) The ion storage layer and the electrolyte layer contain an oxide of at least one metal selected from scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W), and the ratio of oxygen to the total material in the ion storage layer may be smaller than the ratio of oxygen to the total material in the electrolyte layer.

[0116] (12) In one example, the thickness of the electrolyte layer in the second direction is thinner than the thickness of the ion storage layer in the second direction.

[0117] (13) The electrochemical layer may have a composition in which the proportion of oxygen gradually or continuously increases along the second direction toward the channel layer within the electrochemical layer.

[0118] (14) The channel layer may include, for example, at least one oxide semiconductor material from among IGZO (indium-gallium-zinc oxide), IZO (indium-zinc oxide), GZO (gallium-zinc oxide), ZTO (zinc-tin oxide), and IWO (indium tungsten oxide).

[0119] (15) A method for driving a three-dimensional vertical non-volatile memory device may also be provided, comprising: a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, and having a charge trapping layer configured to trap charges by a voltage applied to the plurality of gate electrodes.

[0120] For example, a driving method for a three-dimensional vertical non-volatile memory device may include the steps of: applying a negative (-) program voltage to one of the plurality of gate electrodes; moving and trapping electrons in a portion of the charge trapping layer adjacent in a second direction to the gate electrode to which the program voltage is applied; and moving ions in a portion of the channel layer adjacent in a second direction to the gate electrode to which the program voltage is applied to a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the program voltage is applied, so that the portion of the channel layer has a first resistance.

[0121] (16) A method for driving a three-dimensional vertical non-volatile memory device may further include the steps of: applying a positive (+) erase voltage to one of the plurality of gate electrodes; moving electrons from a portion of the charge trapping layer adjacent in a second direction to the gate electrode to which the erase voltage is applied to the gate electrode to which the erase voltage is applied; and moving ions in a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the erase voltage is applied to a portion of the channel layer adjacent in a second direction to the gate electrode to which the erase voltage is applied, so that the portion of the channel layer has a second resistance lower than the first resistance.

[0122] (17) Among the plurality of gate electrodes, the gate electrode to which the program voltage or erase voltage is not applied is in a floating state, and no ions move between the region of the electrochemical layer adjacent to the floating gate electrode in the second direction and the region of the channel layer.

[0123] (18) A method for driving a three-dimensional vertical non-volatile memory device also further includes the step of applying a positive (+) read voltage only to the gate electrodes of the selected memory cells from among the plurality of gate electrodes from which data is to be read, and applying a positive (+) pass voltage to the remaining gate electrodes, wherein the read voltage is higher than the program voltage and lower than the erase voltage, and the pass voltage is higher than the read voltage and lower than the erase voltage.

[0124] (19) If a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a first resistance, a first current flows through the channel layer, and if a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a second resistance, a second current larger than the first current flows through the channel layer.

[0125] (20) An electronic device may also be provided that includes a processing circuit; and a three-dimensional vertical non-volatile memory device. The three-dimensional vertical non-volatile memory device includes: a channel layer extending along a first direction; a plurality of gate electrodes and a plurality of spacers, each extending along a second direction intersecting the first direction and arranged alternately along the first direction; an electrochemical layer extending along the first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers; and a blocking layer extending along the first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers; wherein the electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer or from the channel layer to the electrochemical layer by a voltage applied to the plurality of gate electrodes, and the blocking layer may include a charge trapping layer extending along the first direction and configured to trap charges by a voltage applied to the plurality of gate electrodes.

[0126] All functional blocks illustrated in the diagram and described above can be implemented by processing circuits such as hardware including logic circuits, hardware / software combinations such as processors that perform software, or combinations thereof. For example, processing circuits include, but are not limited to, CPUs (central processing units), APs (application processors), ALUs (arithmetic logic units), GPUs (graphic processing units), digital signal processors, microcomputers, FPGAs (field programmable gate arrays), SoCs (System-on-Chip), PLCs (programmable logic units), microprocessors, or ASICs (application-specific integrated circuits).

[0127] The vertical three-dimensional non-volatile memory device including the memory cell string described above has been described based on the embodiments shown in the drawings, but this is merely an example, and anyone with ordinary skill in the art will understand that a variety of modifications and equivalent other embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in an explanatory rather than restrictive manner. The scope of rights is set forth in the claims, not in the foregoing description, and all differences within an equivalent scope should be construed as being included within the scope of rights. [Explanation of Symbols]

[0128] 10 Memory System 100 memory controllers 110 Write / Read Control Unit 120 Voltage Control Unit 130 Data discrimination unit 200 memory devices 210 memory cell array 220 Voltage generation unit 230 Low Decoder 240 Input / Output Circuits 250 control logic 311 Insulating Spacer 312 Terminal 321 Insulating support 322 channel layer 323 Electrochemical layer 323a Ion storage layer 323b Electrolyte layer 324 blocking layers 324a charge trapping layer 324b, 324c barrier layer

Claims

1. A channel layer extending along the first direction, Multiple gate electrodes and multiple spacers extend along a second direction intersecting the first direction, and are arranged alternately along the first direction, An electrochemical layer extending along a first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers, The electrochemical layer includes a blocking layer extending along a first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, The electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer, or from the channel layer to the electrochemical layer, depending on the voltage applied to each of the plurality of gate electrodes. A three-dimensional vertical non-volatile memory device, wherein the blocking layer includes a charge trapping layer that extends along a first direction and is configured to trap charges by a voltage applied to each of the plurality of gate electrodes.

2. The charge trapping layer comprises at least one material selected from silicon nitride, aluminum nitride, hafnium nitride, silicon oxynitride, aluminum oxynitride, hafnium oxynitride, hafnium oxide, zirconium oxide, tantalum oxide, and titanium oxide, as described in claim 1.

3. The charge trapping layer comprises a metal oxide material doped with silicon (Si) or aluminum (Al), as described in claim 1, for the three-dimensional vertical non-volatile memory device.

4. The three-dimensional vertical non-volatile memory device according to claim 1, wherein the blocking layer further includes at least one of a first barrier layer extending in a first direction between the charge trapping layer and the plurality of gate electrodes and between the charge trapping layer and the plurality of spacers, and a second barrier layer extending in a first direction between the electrochemical layer and the charge trapping layer.

5. The three-dimensional vertical non-volatile memory device according to claim 4, wherein the first barrier layer and the second barrier layer each contain at least one material selected from aluminum oxide, silicon oxide, hafnium oxide, and zirconium oxide.

6. The thickness of the blocking layer in the second direction is 5 nm to 15 nm. The three-dimensional vertical non-volatile memory device according to claim 4, wherein the thickness of the charge trapping layer in the second direction is 1 nm to 10 nm.

7. The three-dimensional vertical non-volatile memory device according to claim 4, wherein the blocking layer includes both the first barrier layer and the second barrier layer, and the thickness of the first barrier layer in the second direction is smaller than the thickness of the second barrier layer in the second direction.

8. The three-dimensional vertical non-volatile memory device according to claim 1, wherein the electrochemical layer comprises an oxide of at least one metal selected from scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W).

9. If the electrochemical layer contains an oxide of at least one metal among scandium (Sc), yttrium (Y), and lanthanum (La), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.35 or less. If the electrochemical layer contains an oxide of at least one metal from titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), and cerium (Ce), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 1.8 or less. If the electrochemical layer contains an oxide of at least one metal from vanadium (V), niobium (Nb), and tantalum (Ta), the ratio of oxygen atoms to metal atoms in the electrochemical layer is 2.25 or less. The three-dimensional vertical non-volatile memory device according to claim 8, wherein the electrochemical layer contains an oxide of at least one metal selected from chromium (Cr), molybdenum (Mo), and tungsten (W), and the ratio of oxygen atoms to metal atoms in the electrochemical layer is 2.7 or less.

10. The three-dimensional vertical non-volatile memory device according to claim 1, wherein the electrochemical layer includes an ion storage layer extending in a first direction adjacent to the blocking layer and an electrolyte layer extending in the first direction adjacent to the channel layer.

11. The ion storage layer and the electrolyte layer contain an oxide of at least one metal selected from scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), rutherfordium (Rf), cerium (Ce), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), and tungsten (W). The three-dimensional vertical non-volatile memory device according to claim 10, wherein the ratio of oxygen to the total material in the ion storage layer is smaller than the ratio of oxygen to the total material in the electrolyte layer.

12. The three-dimensional vertical non-volatile memory device according to claim 11, wherein the thickness of the electrolyte layer in the second direction is smaller than the thickness of the ion storage layer in the second direction.

13. The three-dimensional vertical non-volatile memory device according to claim 1, wherein the electrochemical layer has a composition in which the proportion of oxygen gradually or continuously increases along a second direction toward the channel layer within the electrochemical layer.

14. The three-dimensional vertical non-volatile memory device according to claim 1, wherein the channel layer comprises at least one oxide semiconductor material selected from IGZO (indium-gallium-zinc oxide), IZO (indium-zinc oxide), GZO (gallium-zinc oxide), ZTO (zinc-tin oxide), and IWO (indium tungsten oxide).

15. A channel layer extending along the first direction, Multiple gate electrodes and multiple spacers extend along a second direction intersecting the first direction, and are arranged alternately along the first direction, An electrochemical layer extending along a first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers, A method for driving a three-dimensional vertical non-volatile memory device, comprising: a blocking layer having a charge trapping layer that extends along a first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, and configured to trap charges by a voltage applied to each of the plurality of gate electrodes, The steps include applying a negative (-) program voltage to one of the plurality of gate electrodes, The steps include: an electron moving to a portion of the charge trapping layer adjacent in the second direction to the gate electrode to which the program voltage is applied, and being trapped; A method for driving a three-dimensional vertical non-volatile memory device, comprising the steps of: moving ions in a portion of the channel layer adjacent in a second direction to the gate electrode to which the program voltage is applied to a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the program voltage is applied, and the portion of the channel layer having a first resistance.

16. The steps include applying a positive (+) cancellation voltage to one of the plurality of gate electrodes, A step in which electrons move from a portion of the charge trapping layer adjacent in the second direction to the gate electrode to which the erasure voltage is applied to the gate electrode to which the erasure voltage is applied, A method for driving a three-dimensional vertical non-volatile memory device according to claim 15, further comprising the step of: ions in a portion of the electrochemical layer adjacent in a second direction to the gate electrode to which the erase voltage is applied move to a portion of the channel layer adjacent in a second direction to the gate electrode to which the erase voltage is applied, and the portion of the channel layer having a second resistance lower than the first resistance.

17. A method for driving a three-dimensional vertical non-volatile memory device according to claim 16, wherein, among the plurality of gate electrodes, the gate electrode to which the program voltage or the erase voltage is not applied is in a floating state, and no ions move between the region of the electrochemical layer adjacent to the floating gate electrode in the second direction and the region of the channel layer.

18. The method further includes a step of applying a positive (+) read voltage only to the gate electrode of the selected memory cell from which data is read, and applying a positive (+) pass voltage to the remaining gate electrodes. A method for driving a three-dimensional vertical non-volatile memory device according to claim 16, wherein the read voltage is higher than the program voltage and lower than the erase voltage, and the pass voltage is higher than the read voltage and lower than the erase voltage.

19. If a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a first resistance, then a first current flows through the channel layer. A method for driving a three-dimensional vertical non-volatile memory device according to claim 18, wherein if a portion of the channel layer adjacent in the second direction to the gate electrode to which the read voltage is applied has a second resistance, a second current greater than the first current flows through the channel layer.

20. Processing circuit and Includes a three-dimensional vertical non-volatile memory device, The aforementioned three-dimensional vertical non-volatile memory device is A channel layer extending along the first direction, Multiple gate electrodes and multiple spacers extend along a second direction intersecting the first direction, and are arranged alternately along the first direction, An electrochemical layer extending along a first direction between the channel layer and the plurality of gate electrodes and between the channel layer and the plurality of spacers, The electrochemical layer includes a blocking layer extending along a first direction between the electrochemical layer and the plurality of gate electrodes and between the electrochemical layer and the plurality of spacers, The electrochemical layer and the channel layer are configured such that ions move from the electrochemical layer to the channel layer, or from the channel layer to the electrochemical layer, depending on the voltage applied to each of the plurality of gate electrodes. The blocking layer includes a charge trapping layer that extends along a first direction and is configured to trap charges by a voltage applied to each of the plurality of gate electrodes, in an electronic device.

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