Semiconductor device and method for manufacturing a semiconductor device

Abstract

To easily form a wiring layer on the sealing member. [Solution] The semiconductor device of the embodiment comprises one or more first semiconductor chips, a sealing member containing a plurality of fillers and having a first surface above the one or more first semiconductor chips to seal the one or more first semiconductor chips, electrodes formed on the first surface of the sealing member, a first conductive layer having one end electrically connected to the one or more first semiconductor chips, extending through the sealing member from the side of the one or more first semiconductor chips to the first surface, with the other end exposed on the first surface being an electrode, and a second conductive layer connected to the electrode and extending on the first surface of the sealing member, wherein the plurality of fillers are all located at a depth below the first surface within the sealing member.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device.

Background Art

[0002] There is a semiconductor package in which a semiconductor chip is sealed with a sealing member. In order to electrically lead out the semiconductor chip, a conductive layer extending from the semiconductor chip may be exposed from the sealing member, and a wiring layer may be formed on the exposed surface. At this time, if there are irregularities on the exposed surface, it may be difficult to form the wiring layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0006] [Figure 1] A diagram showing an example of the configuration of a semiconductor device according to Embodiment 1. [Figure 2] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 3] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 4] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 5] A cross-sectional view illustrating, in order, a part of the procedure for manufacturing a semiconductor device according to Embodiment 1. [Figure 6] A cross-sectional view illustrating part of the procedure for manufacturing a semiconductor device according to the comparative example. [Figure 7] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 1 of Embodiment 1. [Figure 8] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 2 of Embodiment 1. [Figure 9] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 2 of Embodiment 1. [Figure 10] A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 3 of Embodiment 1. [Figure 11]A cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 4 of Embodiment 1. [Figure 12A] A diagram showing an example of the configuration of a semiconductor device according to Embodiment 2. [Figure 12B] A diagram showing another example of the configuration of a semiconductor device according to Embodiment 2. [Figure 13] A diagram showing an example of the configuration of a semiconductor device according to Embodiment 3. [Figure 14] A diagram showing another example of the configuration of a semiconductor device according to Embodiment 3. [Figure 15] A diagram showing an example of the configuration of a semiconductor device in a comparative example. [Modes for carrying out the invention]

[0007] Embodiments will be described in detail below with reference to the drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the components in the embodiments described below include those that are easily conceivable by those skilled in the art or that are substantially identical.

[0008] [Embodiment 1] Embodiment 1 will be described in detail below with reference to Figures 1 to 5.

[0009] (Example of semiconductor device configuration) Figure 1 shows an example of the configuration of a semiconductor device according to Embodiment 1. Specifically, Figure 1(a) is a cross-sectional view of the semiconductor device 1 along the X direction, and Figure 1(b) is an enlarged cross-sectional view including the surface 350a of the sealing member 300. However, in Figure 1(a), hatching is omitted for the sake of readability.

[0010] As shown in Figure 1(a), the semiconductor device 1 is configured as a package in which a plurality of semiconductor chips 200a are sealed. Specifically, the semiconductor device 1 comprises a support 100, a plurality of semiconductor chips 200a, a sealing member 300, electrodes 400a, vertical wires 500a, a redistribution layer 600a, and solder balls 700.

[0011] In this embodiment, the side of the support 100 of the semiconductor device 1 is set as the lower side, and the side of the solder balls 700 of the semiconductor device 1 is set as the upper side, and this vertical direction is defined as the Z direction. Also, the direction from the lower side to the upper side of the semiconductor device 1 is referred to as the stacking direction of the semiconductor chips 200a. The X direction and the Y direction are both directions along the orientation of the surface of the semiconductor chip 200a, and the X direction and the Y direction are perpendicular to each other. Also, the direction indicated by the arrows of the X, Y, and Z axes is defined as the positive direction, and the opposite direction of the arrows is defined as the negative direction.

[0012] The support 100 is, for example, a lead frame, and is a thin metal plate containing a metal such as Fe, Cu, Ni, Si, Mg, or an alloy containing at least one of these. A plurality of semiconductor chips 200a are stacked on the upper surface 110 of the support 100.

[0013] Note that the support 100 is not limited to the above, and may be, for example, a flat member such as a Si substrate, glass, or stainless steel, as long as it can serve as a support substrate when stacking the semiconductor chips 200a.

[0014] Each of the plurality of semiconductor chips 200a is a small piece obtained by singulating a Si substrate or the like, and has, for example, a semiconductor element (not shown) on the main surface 210a side. The semiconductor element is, for example, a non-volatile memory such as a NAND flash memory. The semiconductor chip 200a is an example of a first semiconductor chip.

[0015] Note that it is not necessarily required to stack a plurality of semiconductor chips 200a on the upper surface 110 of the support 100, and at least one may be arranged.

[0016] Each of the multiple semiconductor chips 200a is stacked sequentially with its main surface 210a facing upwards, shifting in the negative direction of X. As a result, the positive X-direction edge of the main surface 210a of each semiconductor chip 200a has a portion that does not overlap with the semiconductor chip 200a directly above it. Electrode pads (not shown) are provided in this portion, as well as at the positive X-direction edge of the main surface 210a of the uppermost semiconductor chip 200a. Vertical wires 500a, described later, are connected to these electrode pads.

[0017] An adhesive layer 220 is provided on the surface opposite to the main surface 210a of the semiconductor chip 200a, i.e., the bottom surface. The adhesive layer 220 is also called a die attach film (DAF) and is a thermosetting resin material formed into a film.

[0018] For example, the adhesive layer 220 provided on the underside of the bottom semiconductor chip 200a adheres the top surface 210 of the support 100 to the bottom semiconductor chip 200a. Similarly, the adhesive layer 220 provided on the underside of the second-to-last semiconductor chip 200a adheres the bottom semiconductor chip 200a to the second-to-last semiconductor chip 200a. As a result, the support 100 and each of the multiple semiconductor chips 200a are fixed to one another.

[0019] The sealing member 300 seals multiple semiconductor chips 200a. The sealing member 300 is, for example, a thermosetting resin material such as epoxy resin or acrylic resin. Multiple fillers 310a are unevenly distributed in at least a portion of the sealing member 300.

[0020] More specifically, as shown in Figure 1(b), the sealing member 300 has a two-layer structure including a first layer 320a containing a plurality of fillers 310a and a second layer 330a that does not contain fillers 310a. The first layer 320a is the lower part of the sealing member 300 and covers the upper surface 110 of the support 100, the plurality of semiconductor chips 200a, and the lower part of the vertical wire 500a, which will be described later. The second layer 330a is the part located above the first layer 320a and covers the upper part of the vertical wire 500a. The second layer 330a has a surface 350a on the side opposite to the side where the first layer 320a is located. Surface 350a is an example of a first surface.

[0021] The multiple fillers 310a are, for example, metal oxides such as aluminum oxide and copper oxide, or metal nitrides such as aluminum nitride, and are metal-containing particles with high thermal conductivity. By containing multiple fillers 310a in the sealing member 300, the sealing member 300 as a whole also has high thermal conductivity. This allows the heat generated by the operation of each semiconductor chip 200a to be dissipated more efficiently through the sealing member 300. As a result, a decrease in the operating speed of the semiconductor chip 200a due to heat generation, and malfunctions, are prevented. Furthermore, for example, the multiple fillers 310a may have functions to adjust the viscosity, hardness, and bulk of the sealing member 300. The diameter of the fillers 310a is approximately 20 μm or less.

[0022] As described above, the multiple fillers 310a are selectively contained in the first layer 320a of the sealing member 300. That is, the multiple fillers 310a are located at a depth below the second layer 330a. In other words, all of the multiple fillers 310a are located at a depth below the surface 350a of the second layer 330a.

[0023] In this embodiment, the first layer 320a and the second layer 330a are made of, for example, a resin material. However, the first layer 320a and the second layer 330a may be made of, for example, different resin materials, as long as they can encapsulate multiple semiconductor chips 200a.

[0024] Furthermore, the sealing member 300 does not necessarily have a two-layer structure consisting of a first layer 320a and a second layer 330a. As long as the uppermost layer is a layer that does not contain filler 310a, such as the second layer 330a, the number of layers below the second layer 330a is arbitrary.

[0025] The vertical wire 500a is connected at its lower end to electrode pads (not shown) of the plurality of semiconductor chips 200a, as described above, and extends upward through the first layer 320a and the second layer 330a, with the other end exposed to the surface 350a. This allows the plurality of semiconductor chips 200a to be electrically drawn onto the surface 350a via the vertical wire 500a. That is, the other end of the vertical wire 500a, 520a, which is exposed to the surface 350a, functions as an electrode 400a for electrically drawing the plurality of semiconductor chips 200a. The vertical wire 500a includes, for example, at least one of the metallic materials Au, Cu, Pd, Cu, and Ag. The vertical wire 500a is an example of the first conductive layer.

[0026] A redistribution layer (RDL) 600a is formed on surface 350a. The redistribution layer 600a has an insulating layer 610, wiring layers 621-623, and via layers V0 and V1. The wiring layers 621-623 are arranged at multiple height positions within the insulating layer 610 and have wiring patterns extending along the XY plane at each height position. The via layers V0 and V1 connect these wiring layers 621-623 in the Z direction. The insulating layer 610 contains polyimide resin, epoxy resin, etc., and the wiring layers 621-623 and via layers V0 and V1 contain metallic materials such as Cu.

[0027] Of the wiring layers 621 to 623, wiring layer 621 extends along surface 350a and connects to electrode 400a. Wiring layer 621 is an example of a second conductive layer. Wiring layer 622 extends along the upper surface 611 of insulating layer 610 and connects to solder ball 700, which will be described later. In addition, insulating layer 610 is provided with wiring layer 623 placed between wiring layers 621 and 622, via layer V0 connecting wiring layers 621 and 623, and via layer V1 connecting wiring layers 623 and 622.

[0028] However, the number and arrangement of wiring layers 623 connecting wiring layers 621 and 622, and via layers V0, V1, etc., are arbitrary.

[0029] As described above, the rewiring layer 600a allows the multiple electrodes 400a positioned on the surface 350a of the second layer 330a, which is the lower surface of the rewiring layer 600a, to be further drawn out to the upper surface of the rewiring layer 600a. At this time, the position of each electrode 400a on the surface 350a of the second layer 330a and the position of these electrodes 400a being drawn out to the upper surface of the rewiring layer 600a can be made different. In other words, the electrodes 400a on the surface 350a of the second layer 330a can be rewired on the upper surface of the rewiring layer 600a.

[0030] Multiple solder balls 700 are provided on the upper surface 611 of the insulating layer 610. The multiple solder balls 700 are electrically connected to the wiring layer 622 on which the individual electrodes 400a have been rewired. This electrically connects the multiple semiconductor chips 200a to the multiple solder balls 700. By connecting the multiple solder balls 700 to a motherboard such as a printed circuit board (not shown), the semiconductor device 1 can be mounted on the motherboard.

[0031] (Method of manufacturing semiconductor devices) Next, the manufacturing method of the semiconductor device 1 according to Embodiment 1 will be described using Figures 2 to 5. Figures 2 to 5 are cross-sectional views illustrating, in order, a part of the procedure for manufacturing the semiconductor device according to Embodiment 1.

[0032] As shown in Figure 2(a), multiple semiconductor chips 200a are sequentially stacked on the upper surface 110 of the support 100, shifting them in the negative direction of X. That is, the first semiconductor chip 200a is fixed to the upper surface 110 of the support 100 with an adhesive layer 220. Then, the second, third, and subsequent semiconductor chips 200a are sequentially shifted in the negative direction of X and fixed to the main surface 210a of the lower semiconductor chip 200a with an adhesive layer 220.

[0033] As shown in Figure 2(b), vertical wires 500a extending in the stacking direction of the semiconductor chips 200a are formed from electrode pads (not shown) formed on the main surface 210a of each of the multiple semiconductor chips 200a.

[0034] At this time, the vertical wire 500a is made to reach a position higher than the main surface 210a of the uppermost semiconductor chip 200a, which is the topmost surface. Furthermore, it is desirable that the height positions of the ends 520a of the vertical wire 500a in the stacking direction are approximately equal to each other.

[0035] Next, the multiple semiconductor chips 200a and vertical wires 500a formed in Figure 2(b) are covered with a first layer 320a and a second layer 330a. Specifically, as shown in Figure 2(c), first, the uncured second layer 330a is placed at the bottom of the mold Md, and then the uncured first layer 320a is placed on top of it. As described above, the first layer 320a and the second layer 330a are made of thermosetting resins such as epoxy resin or acrylic resin, with the first layer 320a containing filler 310a and the second layer 330a not containing filler 310a, and are made of the same or different resin materials.

[0036] Furthermore, while the first layer 320a before curing is fluid, it is preferable that the second layer 330a before curing is formed in a sheet shape. For example, by reducing the amount of solvent and incorporating a high concentration of resin material into the solvent, the viscosity of the second layer 330a can be increased, allowing it to be formed in a sheet shape. This suppresses the mixing of the first layer 320a before curing and the second layer 330a before curing within the mold Md. As a result, it becomes possible to selectively include multiple fillers 310a in the first layer 320a.

[0037] However, as long as mixing with the first layer 320a can be suppressed, the second layer 330a does not necessarily have to be formed in a sheet-like form; for example, it may be formed in a fluid state.

[0038] Next, the support 100 is inverted so that its upper surface 110 faces downward. This positions the support 100 on the upper side and the uppermost semiconductor chip 200a and the end 520a of the vertical wire 500a on the lower side. In this state, the support 100 is inserted into the mold Md until the end 520a of the vertical wire 500a reaches the second layer 330a located at the bottom of the mold Md.

[0039] At this time, the insertion depth of the support 100 is adjusted so that the main surface 210a of the uppermost semiconductor chip 200a, that is, the semiconductor chip 200a located at the bottom in Figure 2(c), is positioned above the second layer 330a. At this time, the thicknesses of the first layer 320a and the second layer 330a within the mold Md may be adjusted in advance. This will allow the first layer 320a to later cover the entirety of the multiple semiconductor chips 200a.

[0040] In addition, in order to position the main surface 210a of the semiconductor chip 200a located at the bottom in Figure 2(c) above the second layer 330a, the thicknesses of the first layer 320a and the second layer 330a within the mold Md may be adjusted in advance.

[0041] Next, the first layer 320a and the second layer 330a are heated and cured, and then removed from the mold Md.

[0042] As described above, the entire semiconductor chip 200a, including the vertical wire 500a, is sealed by a sealing member 300 which includes a covering first layer 320a and a second layer 330a. However, at this stage, the sealing member 300 does not have a surface 350a, and the end 520a of the vertical wire 500a is not exposed from the sealing member 300.

[0043] More specifically, as shown in Figure 3(a), of the sealing member 300, the first layer 320a covers the lower portion including the multiple semiconductor chips 200a and the ends 510a of the vertical wires 500a, and the second layer 330a covers the upper portion including the ends 520a of the vertical wires 500a.

[0044] Next, the second layer 330a is ground from above using a method such as CMP (Chemical Mechanical Polishing) to remove a predetermined thickness. As a result, as shown in Figure 3(b), the height of the second layer 330a is reduced to form a surface 350a, and the end 520a of the vertical wire 500a is exposed on this surface 350a.

[0045] At this time, if the end 520a of the vertical wire 500a is exposed on the grinding surface before the second layer 330a is removed by a predetermined thickness, the exposed portion of the vertical wire 500a may be ground together with the second layer 330a. By grinding the exposed portion of the vertical wire 500a together, the height position of the surface 350a of the second layer 330a and the end 520a of the vertical wire 500a can be aligned more precisely.

[0046] As described above, a sealing member 300 having a surface 350a is formed. The end 520a of the vertical wire 500a exposed on the surface 350a of the sealing member 300 becomes an electrode 400a that electrically pulls out the multiple sealed semiconductor chips 200a.

[0047] Next, the process of forming a redistribution layer 600a on the sealing member 300 will be described using Figures 4(a) to 4(d). Figures 4(a) to 4(d) are enlarged cross-sectional views including the surface 350a of the sealing member 300.

[0048] As shown in Figure 4(a), a seed layer Sd is formed covering surface 350a using a sputtering method or the like. The seed layer Sd contains Cu and other materials and serves as a seed crystal for the subsequent electroplating method that forms the plating layer EL on surface 350a.

[0049] Next, as shown in Figure 4(b), a resist pattern PP having, for example, a line width of 2 μm is formed on the surface 350a of the sealing member 300. The resist pattern PP is formed with openings Op that overlap vertically with the electrodes 400 exposed on the surface 350a. The seed layer Sd is exposed in the openings Op. Next, a plating layer EL is formed by electroplating to cover the seed layer Sd exposed in the openings Op. The plating layer EL also contains Cu or the like. At this time, a portion of the plating layer EL may also be formed on the resist pattern PP.

[0050] Next, as shown in Figure 4(c), after removing the resist pattern PP by a lift-off method or the like, the seed layer Sd exposed in the area where the resist pattern PP was removed is removed by etching or the like. As a result, a wiring layer 621 is formed in the region corresponding to the opening Op of the resist pattern PP. The wiring layer 621 includes the seed layer Sd and the plating layer EL. The wiring layer 621 is connected to the electrode 400a in the vertical direction.

[0051] Subsequently, as shown in Figure 4(d), an insulating layer 610 is formed to cover the wiring layer 621, and via layers V0, 623, V1, and 622 are formed, extending through the insulating layer 610 and electrically connected to the wiring layer 621. This completes the formation of the rewiring layer 600a.

[0052] As shown in Figure 5(a), a plurality of solder balls 700 are formed on the upper surface 611 of the insulating layer 610 to connect with the wiring layer 622. The solder balls 700 are formed using, for example, thermocompression bonding technology, ultrasonic bonding technology, or mass reflow technology, which melts a plurality of solder arranged in an array and forms a plurality of solder balls 700 at once.

[0053] As shown in Figure 5(b), the support 100 is cut in the Z direction to separate it into individual pieces. This completes the manufacturing of the semiconductor device 1 of Embodiment 1.

[0054] (Comparative example) Next, a comparative example semiconductor device will be described using Figures 6(a) and 6(b). Figures 6(a) and 6(b) are cross-sectional views illustrating part of the procedure for manufacturing a semiconductor device according to a comparative example of Embodiment 1. More specifically, Figures 6(a) and 6(b) are enlarged cross-sectional views including the end 520a of the vertical wire 500a corresponding to Figures 3(a) and 3(b).

[0055] As shown in Figure 6(a), in the comparative example of semiconductor device manufacturing method, the second layer 330a is not formed. That is, the multiple semiconductor chips 200a and vertical wires 500a are covered only by the first layer 320a which contains multiple fillers 310a.

[0056] This first layer 320a is ground from above, for example, using the CMP method, to expose the end 520a of the vertical wire 500a on the surface 350ax.

[0057] In this case, the CMP method is used to grind various materials with different materials and hardnesses, such as the first layer 320a, multiple fillers 310a, and vertical wire 500a, which can increase the difficulty of grinding. This is because when grinding three different components with different mechanical strengths under the same grinding conditions, the load on each component on the grinding surface may be uneven, and the grinding rate may differ for each material.

[0058] Furthermore, as shown in Figure 6(b), a portion 311x where a part of the filler 310a is missing may be exposed on the surface 350ax, or a crater-like recess 351x, which is the trace of the exposed filler 310a that has fallen off, may be formed on the surface 350ax. The portion 311x is formed when a part of the filler 310a is ground together with the first layer 320a when the filler 310a is at the same height as the ground surface of the first layer 320a. The recess 351x is formed when the portion 311x described above falls off from the ground surface due to the impact of grinding. The maximum diameter of the portion 311x and the recess 351x may be approximately the same as the diameter of the original filler 310a.

[0059] It is difficult to form the wiring layer of the redistribution layer on a surface 350ax where such recesses 351x are formed. This is because when recesses 351x are formed on surface 350ax, the thickness of the resist film applied to surface 350ax becomes uneven, making it difficult to resolve fine resist patterns with a line width of approximately 2 μm by exposure, and making it difficult to uniformly form the plating layer that will become the wiring layer on the uneven surface 350ax.

[0060] In contrast, in the semiconductor device 1 of Embodiment 1, all of the fillers 310a are located at a depth below the surface 350a. That is, the portion 311x of the filler 310a and the recess 351x, which are the traces left by the detached portion 311x, are not exposed on the surface 350a. As a result, the wiring layer 621 can be easily formed on the surface 350a.

[0061] Furthermore, since all of the fillers 310a are located at a depth below the surface 350a, this means that neither the portion 311x of the filler 310a nor the recess 351x, which is the trace left by the detached portion 311x, can be exposed on the grinding surface used to form the surface 350a. In other words, only two types of components are exposed on the grinding surface: the first layer 320a and the vertical wire 500a. For this reason, grinding to form the surface 350a can be performed relatively easily.

[0062] [Example 1] A method for manufacturing a semiconductor device according to Modification 1 of Embodiment 1 will be described using Figures 7(a) and 7(b). In the method for manufacturing a semiconductor device according to Modification 1, the method for forming the first layer 320a and the second layer 330b differs from that of Embodiment 1 described above.

[0063] In the following, components similar to those in Embodiment 1 described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0064] Figure 7 is a cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to Modification 1 of Embodiment 1. Note that the mold is not shown in Figure 7. Also, although the support 100 should normally be shown upside down, in Figure 7 the support 100 is shown facing downwards.

[0065] Prior to Figure 7(a), the semiconductor device manufacturing method of Modified Example 1 also performs the processing up to Figure 2(c) of Embodiment 1 described above. However, in the processing corresponding to Figure 2(c), in Modified Example 1, the first layer 320a containing filler 310b is placed in the mold, out of the filler-containing layer and the filler-free layer. As a result, as shown in Figure 7(a), the multiple semiconductor chips 200a and the vertical wires 500a are completely covered by the first layer 320a before curing.

[0066] The multiple fillers 310b contained in the first layer 320a before curing include, for example, magnetic materials such as nickel and cobalt. The multiple fillers 310b can move within the first layer 320a before curing in accordance with a magnetic field.

[0067] As shown in Figure 7(b), a magnetic field is generated on the side of the support 100 when viewed from the first layer 320a before curing. As a result, the multiple fillers 310b move through the first layer 320a toward the side of the support 100.

[0068] As the multiple fillers 310b move toward the support 100, a second layer 330b is formed in the upper region of the first layer 320a, i.e., the region opposite to the support 100, from which the fillers 310b have been removed. The second layer 330b contains the same resin as the first layer 320a but does not contain the fillers 310b. The second layer 330b is positioned above the first layer 320a and covers the end 520a of the vertical wire 500a.

[0069] Following Figure 7(b), the processes shown in Figures 3 to 5 of Embodiment 1 are carried out. Thus, the semiconductor device of Modified Example 1 is manufactured.

[0070] According to the semiconductor device manufacturing method of Modification 1, a semiconductor device that has the same effects as the semiconductor device 1 of Embodiment 1 can be obtained.

[0071] [Differentiation 2] A method for manufacturing a semiconductor device according to Modification 2 of Embodiment 1 will be described using Figures 8 and 9. The method for manufacturing a semiconductor device according to Modification 2 differs from Embodiment 1 described above in that a release film is used as the second layer 330c.

[0072] In the following, components similar to those in Embodiment 1 described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0073] Figures 8 and 9 are cross-sectional views illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 2 of Embodiment 1.

[0074] Prior to Figure 8(a), the semiconductor device manufacturing method of the modified example 2 also involves the processing up to Figure 2(b) of the above-described embodiment 1.

[0075] As shown in Figure 8(a), a second layer 330c, such as a release film, is placed at the bottom of the mold Md, and the first layer 320a, before curing, is placed on top of it. The first layer 320a and the second layer 330c are thermosetting resins such as epoxy resin or acrylic resin, and each contains the same or different resins.

[0076] The first layer 320a before curing contains multiple fillers 310a. On the other hand, the second layer 330c, which is configured as a release film, does not contain fillers 310a.

[0077] The support 100 is inverted vertically and inserted into the mold Md until the end 520a of the vertical wire 500a reaches the second layer 330c. As a result, the multiple semiconductor chips 200a and the portion of the vertical wire 500a on the end 510a side are covered by the first layer 320a, and the end 520a of the vertical wire 500a protrudes into the second layer 330c.

[0078] Next, the first layer 320a is cured, and the cured first layer 320a and the second layer 330c are removed from the mold Md.

[0079] Next, as shown in Figure 8(b), the second layer 330c is removed by peeling it off from the first layer 320a. With the removal of the second layer 330c, the surface 350b of the first layer 320a is exposed. The end 520a of the vertical wire 500a protrudes from the surface 350b. Thus, in this modified example 2, the first layer 320a having the surface 350b encapsulates a plurality of semiconductor chips 200a as a encapsulating member. Surface 350b is an example of a first surface.

[0080] As shown in Figure 9(a), the portion of the vertical wire 500a protruding from the surface 350b is ground from above, for example, using the CMP method. Specifically, as shown in Figure 9(b), the vertical wire 500a is ground until the height position of the surface 350b and the height position of the end portion 520a of the vertical wire 500a are approximately equal. The end portion 520a of the vertical wire 500a, which is located on the surface 350b of the first layer 320a, which is the sealing member 300, functions as an electrode 400a.

[0081] Following Figure 9(b), the processes shown in Figures 4 and 5 of Embodiment 1 are carried out. Thus, the semiconductor device of Modified Example 2 is manufactured.

[0082] According to the semiconductor device manufacturing method of the modified example 2, a semiconductor device that exhibits the same effects as the semiconductor device 1 of embodiment 1 can be obtained.

[0083] [Difference 3] Using Figure 10, the method for manufacturing a semiconductor device according to Modification 3 of Embodiment 1 will be described. The method for manufacturing a semiconductor device according to Modification 3 is a modification of the method for manufacturing a semiconductor device according to Modification 2.

[0084] In the following, components similar to those in the modified example 2 described above will be denoted by the same reference numerals, and their explanations may be omitted.

[0085] Figure 10 is a cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 3 of Embodiment 1.

[0086] Prior to Figure 10(a), the semiconductor device manufacturing method of Modification 3 also involves the processes up to Figure 8(b) of Modification 2 described above.

[0087] As shown in Figure 10(a), the upper portion including the end 520a of the vertical wire 500a protrudes from the surface 350b of the first layer 320a.

[0088] As shown in Figure 10(b), a second layer 330d covering the end 520a of the vertical wire 500a is formed on the surface 350b, for example, using a spin coating method. The second layer 330d is a thermosetting resin such as epoxy resin or acrylic resin, and contains the same or a different resin as the first layer 320a. The second layer 330d does not contain filler 310a.

[0089] Next, the second layer 330d is ground from above, for example, using the CMP method. As a result, as shown in Figure 10(c), the height of the second layer 330d is reduced and a surface 350c is formed, and the end 520a of the vertical wire 500a is exposed on this surface 350c. Thus, in this modified example 3, the first layer 320a and the second layer 330d having the surface 350c encapsulate a plurality of semiconductor chips 200a as a encapsulating member. Surface 350c is an example of a first surface.

[0090] Following Figure 10(c), the processes shown in Figures 4 and 5 of Embodiment 1 are carried out. Through this process, the semiconductor device of Modified Example 3 is manufactured.

[0091] In the semiconductor device manufacturing method of Modified Example 3, the end 520a of the vertical wire 500a protruding from the first layer 320a is covered with the second layer 330d, and the surface 350c of the second layer 330d is ground to align the height position of the end 520a of the vertical wire 500a with that of the second layer 330d. This makes processing easier compared to, for example, grinding the vertical wire 500a protruding from a sealing member.

[0092] According to the semiconductor device manufacturing method of Modification 3, a semiconductor device that also exhibits the same effects as the semiconductor device 1 of Embodiment 1 can be obtained.

[0093] [Differentiation Example 4] Using Figure 11, the method for manufacturing a semiconductor device according to Modification 4 of Embodiment 1 will be described. The method for manufacturing a semiconductor device according to Modification 4 is another modification of the method for manufacturing a semiconductor device according to Modification 2.

[0094] In the following, components similar to those in the modified example 2 described above will be denoted by the same reference numerals, and their explanations may be omitted.

[0095] Figure 11 is a cross-sectional view illustrating a part of the procedure for manufacturing a semiconductor device according to a modified example 4 of Embodiment 1.

[0096] Prior to Figure 11(a), the semiconductor device manufacturing method of the modified example 4 also involves the processing up to Figure 2(b) of Embodiment 1 described above.

[0097] As shown in Figure 11(a), a second layer 330e is placed at the bottom of the mold Md, and a first layer 320a is placed on top of it. The first layer 320a and the second layer 330e each contain the same or different resins. The second layer 330e is configured as a release film, similar to the second layer 330c in Modification 2. The same release film as the second layer 330c in Modification 2 may be used as the second layer 330e.

[0098] The support 100 is inverted vertically and inserted toward the mold Md until the end 520a of the vertical wire 500a reaches the interface Fa between the second layer 330e and the first layer 320a. At this point, the end 520a of the vertical wire 500a is located at the interface Fa between the second layer 330e and the first layer 320a and is not inserted into the second layer 330e. Several methods can be considered to prevent the end 520a of the vertical wire 500a from hitting the interface Fa between the second layer 330e and the first layer 320a and being inserted into the second layer 330e.

[0099] One possible method for this is to control the thickness of the second layer 330e and the first layer 320a that are filled into the mold Md, and to precisely adjust the position of the interface Fa between the second layer 330e and the first layer 320a within the mold Md. Alternatively, for example, a release film that is harder than the second layer 330c in Modified Example 2 could be used as the second layer 330e. Furthermore, the end 520a of the vertical wire 500a may be pre-polished to blunt it. This is because if the vertical wire 500a has a sharp end 520a, it is more likely to penetrate the interface Fa between the second layer 330e and the first layer 320a and be inserted into the second layer 330e.

[0100] Next, the first layer 320a is cured, and the cured first layer 320a and the second layer 330e are removed from the mold Md.

[0101] As shown in Figure 11(b), the entire semiconductor chip 200a, including the vertical wire 500a, is covered by a first layer 320a. The second layer 330e covers the top of the first layer 320a. The end 520a of the vertical wire 500a extends through the first layer 320a, as described above, and reaches a height approximately equal to the interface Fa.

[0102] Next, the second layer 330e is peeled off from the first layer 320a. As the second layer 330e is peeled off, the surface 350b of the first layer 320a is exposed. On the surface 350b of the first layer 320a, the end 520a of the vertical wire 500a is exposed, as shown in Figure 11(c).

[0103] Following Figure 11(c), the processes shown in Figures 4 and 5 of Embodiment 1 are carried out, respectively. Through this process, the semiconductor device of Modified Example 4 is manufactured.

[0104] According to the semiconductor device manufacturing method of Modified Example 4, multiple semiconductor chips 200a are sealed such that the end 520a of the vertical wire 500a is located at the interface Fa between the second layer 330e and the first layer 320a. This eliminates the need to grind the sealing material after sealing the multiple semiconductor chips 200a, thereby reducing the number of steps and lowering the manufacturing cost of the semiconductor device.

[0105] According to the semiconductor device manufacturing method of Modification 4, a semiconductor device that also exhibits the same effects as the semiconductor device 1 of Embodiment 1 can be obtained.

[0106] [Embodiment 2] The sealing member 300 having the configuration of Embodiment 1 and Modifications 1 to 4 described above can also be applied to various semiconductor devices having configurations different from the semiconductor device 1 described above.

[0107] In the following Embodiment 2, as an example of applying the sealing member 300 having the configuration of Embodiment 1 described above, a semiconductor device having a package-on-package structure will be explained with reference to Figure 12A.

[0108] In the following, components similar to those in Embodiment 1 described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0109] (Example of semiconductor device configuration) Figure 12A is a diagram showing an example of the configuration of the semiconductor device 2 according to Embodiment 2. Figure 12A shows a cross-section of the semiconductor device 2 along the X direction. However, hatching is omitted in Figure 12A for the sake of readability.

[0110] As shown in Figure 12A, the semiconductor device 2 comprises a plurality of semiconductor chips 200b, a semiconductor chip 200c, sealing members 300, 360, electrodes 400b, vertical wires 500b, a redistribution layer 600a, solder balls 700, a wiring board 800, and wires 900a.

[0111] The wiring board 800 is configured as a multilayer substrate in which an insulating layer and a conductive layer (not shown) are alternately laminated multiple times. The insulating layer is made of carbon fiber, glass fiber, or aramid fiber, etc., impregnated with a thermosetting resin such as epoxy resin before curing. The conductive layer is made of a metal such as Cu. The conductive layer has a wiring pattern and is connected to electrodes (not shown) formed on the upper surface 810 and the lower surface 820 of the wiring board 800.

[0112] Multiple semiconductor chips 200b are stacked on the upper surface 810 of the wiring board 800. Each of the multiple semiconductor chips 200b has, for example, a semiconductor element (not shown) on the main surface 210b side. The semiconductor element has multiple memory cells. That is, each of the multiple semiconductor chips 200b is a memory chip such as a NAND flash memory. Semiconductor chip 200b is an example of a first semiconductor chip.

[0113] Multiple semiconductor chips 200b are stacked such that they shift either in the positive or negative direction of X as they move upwards. For example, as shown in Figure 12A, at least some of the semiconductor chips 200b, such as the lower semiconductor chips 200b, are stacked so that they shift in the positive direction of X.

[0114] Furthermore, among the multiple semiconductor chips 200b, the upper semiconductor chip 200b may be stacked so that its shift direction is reversed from that of the lower semiconductor chip 200b, shifting toward the negative X direction. In this way, when there are many semiconductor chips 200b to be stacked, the shift direction in the X direction when stacking the multiple semiconductor chips 200b may be switched.

[0115] As a result, the positive or negative X-direction edge of the main surface 210b of each semiconductor chip 200b has a portion that does not overlap with the semiconductor chip 200b directly above it. Electrode pads (not shown) are provided in this portion, and at the positive or negative X-direction edge of the main surface 210b of the uppermost semiconductor chip 200b. Wires 900a are connected to the electrode pads.

[0116] The wire 900a is made up of at least one metallic material, such as Au, Cu, Pd, and Ag. The wire 900a connects each of the multiple semiconductor chips 200b to electrodes (not shown) provided on the upper surface 810 of the wiring board 800. This electrically connects the wiring board 800 and the multiple semiconductor chips 200b.

[0117] The sealing member 300 seals multiple semiconductor chips 200b. Multiple fillers 310a are unevenly distributed in at least a portion of the sealing member 300.

[0118] More specifically, the sealing member 300 includes, for example, a first layer 320a containing a plurality of fillers and a second layer 330a that does not contain fillers, similar to Embodiment 1 described above. The first layer 320a covers the upper surface 810 of the wiring board 800, the plurality of semiconductor chips 200b, the wires 900a, and the lower portion including the end 510b which is the connection end of the vertical wire 500b to the wiring board 800 (described later). The second layer 330a is positioned above the first layer 320a and covers the upper portion including the end 520c opposite to the end 510b of the vertical wire 500a.

[0119] Electrode 400b is exposed on surface 350d of the second layer 330a. Electrode 400b is also the end 520c of the vertical wire 500b.

[0120] The vertical wire 500b is connected at its end 510b to an electrode (not shown) provided on the upper surface 810 of the wiring board 800, extends upward through the first layer 320a and the second layer 330a, and is exposed on the surface 350d at its other end, end 520c. As a result, multiple semiconductor chips 200b are electrically drawn onto the surface 350d via the wire 900a, the wiring board 800, and the vertical wire 500b. The vertical wire 500b is an example of the first conductive layer.

[0121] A redistribution layer 600a is formed on surface 350d. Similar to Embodiment 1 described above, the redistribution layer 600a has a wiring layer 621, etc., that is connected to the electrode 400b and extends on surface 350d.

[0122] A semiconductor chip 200c is provided on the upper surface 611 of the insulating layer 610 of the redistribution layer 600a. The semiconductor chip 200c is configured as a controller chip that controls NAND flash memory and the like on multiple semiconductor chips 200b. However, it is not limited to this, and the semiconductor chip 200c may also be a logic chip such as an application processor.

[0123] The semiconductor chip 200c is electrically connected to multiple semiconductor chips 200b via a redistribution layer 600a. The semiconductor chip 200c is sealed by a sealing member 360. The semiconductor chip 200c is an example of a second semiconductor chip.

[0124] Multiple solder balls 700 are provided on the lower surface 820 of the wiring board 800. The multiple solder balls 700 are connected to electrodes (not shown) formed on the lower surface 820 of the wiring board 800. As a result, the multiple semiconductor chips 200b and semiconductor chips 200c and the solder balls 700 are electrically connected.

[0125] In addition, the semiconductor device 2 of Embodiment 2 may have a redistribution board 800a instead of the wiring board 800. For example, when using a redistribution board 800a, a redistribution layer is first created on a support substrate, a plurality of semiconductor chips 200b are stacked on the redistribution layer, and then wires 900a are formed to connect to each semiconductor chip 200b. After sealing the plurality of semiconductor chips 200b and wires 900a with a sealing member 300, a redistribution layer 600a is formed on the sealing member 300, the support substrate is peeled off, and the redistribution board 800a is exposed. Of course, a wiring board 800 may also be used as in Figure 12A.

[0126] Furthermore, as shown in Figure 12B, the semiconductor device 2 of Embodiment 2 may have a package PKG on the upper surface of the redistribution layer 600a in which multiple semiconductor chips 200cc are sealed, instead of a single semiconductor chip 200c.

[0127] Figure 12B shows another example of the configuration of the semiconductor device 2 according to Embodiment 2. Figure 12B shows a cross-section of the semiconductor device 2 along the X direction. However, hatching is omitted in Figure 12B for the sake of readability.

[0128] As described above, a package PKG is provided on the upper surface 611 of the redistribution layer 600a. The package PKG has a configuration in which a plurality of semiconductor chips 200cc are sealed on the redistribution layer 600aa by a sealing member 370. The plurality of semiconductor chips 200cc and the redistribution layer 600aa are connected via wires 900b.

[0129] Multiple solder balls 700a are provided on the underside of the redistribution layer 600aa. These solder balls 700a are connected to the wiring layer extending from the upper surface 611 of the redistribution layer 600a. As a result, multiple semiconductor chips 200d and the solder balls 700 are electrically connected via the solder balls 700a.

[0130] In the manufacturing method of the semiconductor device 2 shown in Figure 12B, after each package PKG is formed, the package PKG and the redistribution layer 600a are connected by a plurality of solder balls 700a.

[0131] Furthermore, the semiconductor device 2 in Figure 12B may have a wiring board 60aaa instead of a redistribution layer 600aa. The upper package PKG of the semiconductor device 2 in Figure 12B may have the semiconductor chip 200c shown in Figure 12A inside instead of multiple semiconductor chips 200cc. Both Figure 12A and Figure 12B are examples of the semiconductor device 2. The lower package may have a semiconductor chip 200c, and the upper package PKG may have multiple semiconductor chips 200cc. Alternatively, both the lower package and the upper package PKG may have logic chips such as application processors.

[0132] The semiconductor device 2 of Embodiment 2 provides the same effects as the semiconductor device 1 of Embodiment 1 described above.

[0133] [Embodiment 3] The sealing member 300 having the configuration of Embodiment 1 and Modifications 1 to 4 described above can also be applied to semiconductor devices including a three-dimensional non-volatile memory in which a plurality of memory cells are arranged in three dimensions.

[0134] In the following Embodiment 3, a semiconductor device including a three-dimensional non-volatile memory will be described using Figures 13 and 14 as an example of the application of the sealing member 300 having the configuration of Embodiment 1 described above.

[0135] In the following, components similar to those in Embodiment 1 described above will be denoted by the same reference numerals, and their descriptions may be omitted.

[0136] (Example of semiconductor device configuration) Figure 13 shows an example of the configuration of a semiconductor device 3 according to Embodiment 3. Figure 13 shows a cross-section of the semiconductor device 3 along the X direction. However, hatching is omitted in Figure 13 for the sake of readability.

[0137] As shown in Figure 13, the semiconductor device 3 comprises a semiconductor chip 200d, a sealing member 300, an electrode 400c, a through-hole contact 500c, and a redistribution layer 600b.

[0138] The semiconductor chip 200d comprises a CMOS-side chip 201 and an array-side chip 202 bonded to the upper surface of the CMOS-side chip 201. The CMOS-side chip 201 and the array-side chip 202 are formed and cut individually, and then bonded together.

[0139] The CMOS chip 201 has peripheral circuits CBA provided on the substrate SBa. The array chip 202 has, from bottom to top, a laminate LM in which multiple word lines WL are stacked, and a source line SL. The semiconductor chip 200d is an example of the first semiconductor chip.

[0140] The substrate SBa is, for example, a Si substrate. A peripheral circuit CBA, including transistors TR and wiring, is arranged on the substrate SBa. The peripheral circuit CBA contributes to the operation of the memory cell, which will be described later.

[0141] The peripheral circuit CBA is covered with an insulating layer 40 such as a silicon oxide layer. An array-side chip 202 is positioned on a portion of the upper surface of the insulating layer 40. That is, the chip area of ​​the array-side chip 202 is smaller than the chip area of ​​the CMOS-side chip 201.

[0142] The array-side chip 202's laminated structure LM has a configuration in which multiple word line layers WL are stacked one layer at a time, spaced apart from each other. A memory area MR is located in the center of the laminated structure LM, and stepped areas ER are located at both ends of the laminated structure LM. The word line layers WL are an example of conductive layers.

[0143] Multiple pillars PL are arranged in the memory region MR, penetrating the word line WL in the stacking direction. The upper end of each pillar PL reaches the source line SL. Multiple memory cells are formed at the intersections of the pillars PL and the word line WL. In this way, the semiconductor chip 200d is configured as a three-dimensional non-volatile memory in which memory cells are arranged three-dimensionally within the memory region MR.

[0144] Multiple contacts CC are arranged in the stepped region ER, each connected to a multiple word line WL. From the contacts CC, write voltage, read voltage, etc., are applied to memory cells contained in the memory region MR in the central part of the stacked structure LM, via the word line WL located at the same height as the memory cell. The various voltages applied to the memory cells from the contacts CC are controlled by peripheral circuits CBA that are electrically connected to these contacts CC.

[0145] Multiple word lines WL, pillars PL, and contacts CC are covered with an insulating layer 50 made of silicon oxide or the like. A substrate SBb is placed above the insulating layer 50. The substrate SBb is, for example, a Si substrate. A semiconductor chip 200d is formed with the above configuration.

[0146] The sealing member 300 seals the semiconductor chip 200d. Specifically, the sealing member 300 covers the upper surface of the CMOS-side chip 201 and the peripheral portion of the array-side chip 202.

[0147] More specifically, the sealing member 300 has a two-layer structure including a first layer 320a containing a plurality of fillers and a second layer 330a that does not contain fillers. The first layer 320a covers the portion of the upper surface of the CMOS-side chip 201 where the array-side chip 202 is not located, the lower portion of the array-side chip 202, and the lower portion of the through-hole contact 500c, which will be described later. The second layer 330a is positioned above the first layer 320a and covers the upper portion of the through-hole contact 500c.

[0148] The electrode 400c is exposed on surface 350e of the second layer 330a. The electrode 400c is one end of the conductive layer 530 of the through-hole contact 500c. Surface 350e is an example of the first surface.

[0149] The through-hole contact 500c has a conductive layer 530 and an insulating layer 540 formed in that order from the outside. The conductive layer 530 and insulating layer 540 of the through-hole contact 500c are connected at their lower ends to an electrode pad Pdd exposed on the upper surface of the CMOS chip 201, extend upward through the first layer 320a and the second layer 330a, and are exposed on the surface 350e at the other end. The electrode pad Pdd is connected to the peripheral circuit CBA of the CMOS chip 201. As a result, the semiconductor chip 200d is electrically drawn onto the surface 350e via the through-hole contact 500c. The conductive layer 530 is an example of the first conductive layer.

[0150] A redistribution layer 600b is formed on the surface 350e. Similar to Embodiment 1 described above, the redistribution layer 600b has a wiring layer 621, etc., that is connected to the electrode 400c and extends on the surface 350e.

[0151] A wire 900b is connected to the upper surface of the wiring layer 621. The wire 900b is made up of at least one of the following metallic materials: Au, Cu, Pd, Cu, and Ag. The wire 900b is formed, for example, by a wire bonding method. The wire 900b connects the wiring layer 621 to the wiring layer of other semiconductor devices. This connects the semiconductor device 3 to other semiconductor devices electrically.

[0152] As shown in Figure 14, the semiconductor device 3 of Embodiment 3 may have a vertical wire 500d instead of the through-hole contact 500c described above. Alternatively, it may have a Cu pillar (not shown) instead of the through-hole contact 500c. A Cu pillar to be connected to the electrode pad Pdd is formed in advance before the semiconductor chip 200d is sealed by the sealing member 300, and after sealing with the sealing member 300, the Cu pillar exposed on the surface 350e is ground by the CMP method. As a result, an electrode 400c is formed on the surface 350e.

[0153] As shown in Figure 14, the vertical wire 500d extends vertically through the second layer 330a and the first layer 320a, connecting the wiring layer 621 to the electrode pad Pdd exposed on the upper surface of the CMOS chip 201.

[0154] As described above, by applying the sealing member 300 of any of the above-described embodiment 1 or modifications 1 to 4 to a semiconductor device including, for example, a three-dimensional non-volatile memory, through-hole contacts 500c or vertical wires 500d can be formed in the sealing member 300 that has detached from the semiconductor chip 200d, and these can be easily rewired on the upper surface of the sealing member 300.

[0155] (Comparative example) Next, the semiconductor device of the comparative example will be described using Figure 15. Figure 15 is a diagram showing an example of the configuration of the semiconductor device 3x of the comparative example. However, hatching has been omitted in Figure 15 as well, for the sake of readability.

[0156] In the comparative example, the configuration of Embodiment 1 or Modifications 1-4 described above is not applied when sealing the semiconductor device. In this case, it becomes difficult to place through-hole contacts, etc., in the sealing member and rewire them on the upper surface of the sealing member. For this reason, in the semiconductor device of the comparative example, through-hole contacts, etc., are placed, for example, in the semiconductor chip.

[0157] As a result, in the comparative example semiconductor device 3x, as shown in Figure 15, the chip area of ​​the array-side chip 202x is expanded compared to, for example, the semiconductor chip 200d of Embodiment 3. That is, in the comparative example semiconductor chip 200dx, the area of ​​the insulating layer 50 and the substrate SBbx of the array-side chip 202x is expanded in the XY direction, and a configuration that replaces the through-hole contact 500c of Embodiment 3 is arranged in the expanded portion.

[0158] More specifically, outside the extended portion of the insulating layer 50, i.e., the stepped region ER, a peripheral region PR is located. A conductive layer C3 is formed in the peripheral region PR, extending vertically through the insulating layer 50. At its lower end, the conductive layer C3 is connected to an electrode pad Pddx exposed on the upper surface of the CMOS-side chip 201x. The electrode pad Pddx is connected to the peripheral circuit CBA. The sealing member 300 covers the further outside of the array-side chip 202x, which has an expanded chip area. A polyimide layer PI is also provided on the surface 350e of the sealing member 300.

[0159] Electrode 400cx is exposed on the upper surface of the polyimide layer PI. Electrode 400b is one end of contact 500cx. Contact 500cx is connected at its lower end to the upper end of the conductive layer C3, extends upward over the extended portion of the substrate SBbx, and is exposed on the upper surface of the polyimide layer PI. In other words, electrode 400cx is positioned above the extended portion of the substrate SBbx.

[0160] The electrode 400cx is connected to the wiring layer 621, which is part of the redistribution layer. The wire 900b is connected to the upper surface of the wiring layer 621.

[0161] The wire 900b is formed using the wire bonding method. In the wire bonding method, one end of the wire 900b is crimped onto the wiring layer 621. At this time, a downward force is applied to the wiring layer 621 and the electrode 400cx. This may cause a crack CR to form near the boundary between the stepped region ER and the surrounding region PR, extending in the vertical direction.

[0162] As described above, the insulating layers 40 and 50 are silicon oxide layers, etc., and the substrates Sbax and SBbx are Si substrates, etc. The silicon oxide layers and Si substrates have relatively low elastic moduli. For this reason, when force is applied locally to a part of the silicon oxide layer or Si substrate, cracks CR are easily formed.

[0163] In contrast, in the semiconductor device 3 of Embodiment 3, the areas around the through-hole contact 500c and electrode 400c are covered with a sealing member 300 (first layer 320a, second layer 330a) with a relatively high elastic modulus (see Figure 13). Therefore, even if a downward force is applied to the wiring layer 621 and electrode 400c, cracks CR are unlikely to form.

[0164] Furthermore, in the semiconductor device 3 of Embodiment 3, since the through-hole contact 500c is placed inside the sealing member 300, the chip area of ​​the array-side chip 202 can be kept smaller. As a result, more array-side chips 202 can be cut out from the substrate before it is separated into individual chips, thus reducing production costs.

[0165] The semiconductor device 3 of Embodiment 3 also provides the same effects as the semiconductor device 1 of Embodiment 1 described above.

[0166] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0167] 1,2,3...Semiconductor device, 100...Support, 200a~200d...Semiconductor chip, 300...Sealing material, 310a,310b...Filler, 320a...First layer, 330a~330e...Second layer, 350a~350e...Surface, 400a,400b...Electrode, 500a,500b,500d...Vertical wire, 500c...Through-hole contact, 510a~510b...End, 520a...End, 621...Wiring layer, 800...Wiring board, Md...Mold.

Claims

1. One or more first semiconductor chips, A sealing member containing multiple fillers and having a first surface above the one or more first semiconductor chips to seal the one or more first semiconductor chips, The electrode formed on the first surface of the sealing member, A first conductive layer having one end electrically connected to the one or more first semiconductor chips, extending through the sealing member from the side of the one or more first semiconductor chips to the first surface, with the other end exposed to the first surface serving as the electrode, A second conductive layer is connected to the electrode and extends on the first surface of the sealing member, Equipped with, The aforementioned multiple fillers are, In the sealing member, all of the following are located at a depth position below the first surface: Semiconductor equipment.

2. The sealing member is A first layer containing the filler, A second layer positioned above the first layer, The semiconductor device according to claim 1.

3. The first layer mentioned above, The second layer contains the same resin material, The semiconductor device according to claim 2.

4. The wiring board further comprises one or more of the aforementioned first semiconductor chips mounted on it. The one end of the first conductive layer is Connected to the aforementioned wiring board, The semiconductor device according to claim 1.

5. The system further comprises a second semiconductor chip positioned above the sealing member and electrically connected to the second conductive layer, The semiconductor device according to claim 1.

6. The one or more first semiconductor chips are, It is a memory chip containing multiple memory cells, The second semiconductor chip is A controller chip that contributes to the electrical operation of the aforementioned plurality of memory cells. The semiconductor device according to claim 5.

7. The one or more first semiconductor chips are, A laminate in which multiple conductive layers are stacked one layer at a time, spaced apart from each other, Within the laminate, a pillar extends in the stacking direction of the laminate and forms memory cells at each intersection with the plurality of conductive layers, including, The semiconductor device according to claim 4.

8. One or more first semiconductor chips are stacked on a support, One end of the first semiconductor chip is electrically connected to the one or more first semiconductor chips, and a first conductive layer is formed that extends in the stacking direction of the one or more first semiconductor chips. A resin material containing at least a portion of multiple fillers is used to cover the one or more first semiconductor chips and the first conductive layer. By reducing the height of the resin material covering the one or more first semiconductor chips and the first conductive layer, the other end of the first conductive layer is exposed on the first surface of the reduced-height resin material, thereby forming a sealing member that seals the one or more first semiconductor chips. The other end of the sealing member exposed on the first surface is used as an electrode, and it is connected to the electrode to form a second conductive layer extending on the first surface. Forming the aforementioned resin material The first layer containing the plurality of fillers covers the one or more first semiconductor chips and the first conductive layer, This includes forming a second layer above the first layer, Reducing the height of the aforementioned resin material means The process includes removing the second layer, A method for manufacturing a semiconductor device.

9. The aforementioned plurality of fillers have magnetic material, Forming the second layer above the first layer is, This includes generating a magnetic field to move the plurality of fillers to the lower side of the first layer, thereby forming the second layer above the first layer from which the plurality of fillers have been removed. The method for manufacturing a semiconductor device according to claim 8.

10. Forming the aforementioned resin material The second layer and the first layer are arranged in this order from the bottom inside the mold. The one or more first semiconductor chips and the first conductive layer are arranged in the mold such that the one or more first semiconductor chips are positioned above the second layer, with the side of the support on which the one or more first semiconductor chips are stacked facing downwards. The method for manufacturing a semiconductor device according to claim 8.

11. The second layer is formed in the form of a film, Removing the second layer means This includes peeling the second layer from the first layer. The method for manufacturing a semiconductor device according to claim 8.

Images