Semiconductor devices and electronic equipment

Abstract

To improve the performance of semiconductor devices. [Solution] The multiple external terminals SB arranged on the lower surface 2b of the interposer substrate SUB1 include multiple power supply terminals TVD1 capable of supplying a first power supply potential supplied from the outside to the first circuit. The lower surface 2b includes a terminal arrangement region RSB in which the multiple external terminals SB are arranged, and a peripheral region RPF surrounding the terminal arrangement region RSB. The terminal arrangement region RSB includes a region RVD1 that is closest to and extends along the edge 2s1 of the interposer substrate SUB1. In region RVD1, only the multiple power supply terminals TVD1 among the multiple external terminals SB are arranged adjacent to each other. The power consumption of the above first circuit is the largest among the power consumption of each of the multiple circuits provided by the semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and an electronic device.

Background Art

[0002] There is an electronic device in which each of a plurality of solder balls arranged on the lower surface of a semiconductor device is connected to a terminal on a mounting substrate (see, for example, Patent Document 1 (Japanese Patent Application Laid-Open No. 2015-154062) or Patent Document 2 (International Publication No. 2016 / 046987)).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Among the plurality of circuits included in a semiconductor device, for example, a circuit such as a CPU (Central Processing Unit) needs to process a large amount of data at high speed as it becomes more highly functional, so the power consumption per unit time increases. Therefore, from the viewpoint of realizing a function of processing a large amount of data at high speed, a technology for stably supplying power to a circuit with high power consumption is required.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment includes a semiconductor chip, an interposer substrate, and a plurality of external terminals. The semiconductor chip comprises a plurality of circuits, including a first circuit. The interposer substrate has a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface. The plurality of external terminals are arranged in alignment with the second surface of the interposer substrate. The plurality of external terminals include a plurality of first power supply terminals capable of supplying a first power supply potential supplied from the outside to the first circuit. The second surface includes a terminal arrangement region on which the plurality of external terminals are arranged, and a peripheral region surrounding the terminal arrangement region. The terminal arrangement region includes a first region that is closest to the first edge of the interposer substrate and extends along the first edge. In the first region, only the plurality of first power supply terminals among the plurality of external terminals are arranged adjacent to each other. The power consumption of the first circuit is the largest among the power consumption of each of the plurality of circuits provided in the semiconductor chip.

[0007] Another embodiment of the electronic device includes the semiconductor device described above and a wiring board. The wiring board has a third surface and a fourth surface located opposite the third surface. The semiconductor device is mounted on the third surface of the wiring board. [Effects of the Invention]

[0008] According to the above embodiment, the performance of a semiconductor device or an electronic device having a semiconductor device can be improved. [Brief explanation of the drawing]

[0009] [Figure 1] This is a plan view of the top surface of an electronic device, which is one embodiment of the device. [Figure 2] Figure 1 is a plan view of the underside of the electronic device shown. [Figure 3] This is a cross-sectional view of line AA in Figure 1. [Figure 4]Figure 3 is a plan view showing an example of the power plane and ground plane, which are among the multiple conductor planes present on the mounting board. [Figure 5] Figure 3 is a plan view of the underside of the semiconductor device shown. [Figure 6] Figure 3 is an explanatory diagram showing an example of the layout of multiple circuits contained in the semiconductor chip shown. [Figure 7] This is an explanatory diagram showing an example of the electrical connection state between the multiple circuits shown in Figure 6 and the multiple external terminals shown in Figure 5. [Figure 8] This is a plan view showing an example of the positional relationship between the power terminal, reference potential terminal, and differential signal terminal pair, which are among the multiple external terminals of a semiconductor device. [Figure 9] This is a plan view showing a modified example of a semiconductor device, which is a variation of Figure 8. [Figure 10] This is a plan view showing a semiconductor device, which is another variation of Figure 8. [Figure 11] This is a plan view showing a semiconductor device, which is another variation of Figure 8. [Figure 12] Figure 11 is a plan view showing an example of a circuit layout in a semiconductor chip, which is a modified version of the semiconductor chip shown in Figure 6. [Figure 13] This is an explanatory diagram showing an example of the electrical connection state between the multiple circuits shown in Figure 12 and the multiple external terminals shown in Figure 11. [Figure 14] Figure 11 is a plan view showing an example of the power plane and ground plane, which are among the multiple conductor planes present on the mounting substrate of an electronic device on which a semiconductor device is mounted. [Figure 15] This is a plan view showing a semiconductor device which is a modified example of Figure 11. [Figure 16] This is a plan view showing another modification of Figure 8. [Modes for carrying out the invention]

[0010] (Explanation of format, basic terminology, and usage in this application) In this application, for the sake of convenience, the description of the embodiments is divided into multiple sections and the like. These are not mutually independent and separate. One is a part or detail of the other, or one is a modification example of the other. Also, in principle, repeated explanations of similar parts are omitted. Further, each component in the embodiments is not essential, except when clearly indicated as an essential component, when theoretically limited to that number, and when clearly essential from the context.

[0011] Similarly, in the description of the embodiments and the like, regarding materials, compositions, etc., even when stated as "X consisting of A", etc., those containing elements other than A are not excluded, except when clearly limited and when clearly limited from the context. For example, regarding components, it means "X containing A as the main component". For example, even when referring to a "silicon member", etc., it is not limited to pure silicon, but also includes members containing SiGe (silicon-germanium) alloys, other multi-element alloys with silicon as the main component, and other additives. Also, regarding gold plating, Cu layers, nickel plating, etc., unless otherwise specifically stated, they include not only pure ones but also members with gold, Cu, nickel, etc. as the main components.

[0012] Furthermore, when referring to specific numerical values or quantities, unless clearly limited and clearly limited from the context, the specific numerical values are described as examples.

[0013] Also, in each figure of the embodiments, the same or similar parts are indicated by the same or similar symbols or reference numbers, and the description is not repeated in principle.

[0014] Furthermore, in attached drawings, hatching or similar markings may be omitted even in cross-sections if it would make the drawing unnecessarily complicated or if the distinction from voids is clear. In connection with this, background contour lines may be omitted even for holes that are closed in plan view, if it is clear from the explanation, etc. Moreover, hatching or dot patterns may be added even to areas that are not voids or to indicate the boundaries of an area, even if they are not cross-sections.

[0015] In the following explanation, the terms "power plane," "ground plane," and "conductor plane" may be used. A "plane" refers to a large-area conductor pattern. A "conductor plane" is a general term for both "power planes" and "ground planes," and refers to a large-area conductor pattern to which a fixed potential is supplied. A "power plane" refers to a large-area conductor pattern to which the power potential is supplied. A "ground plane" refers to a large-area conductor pattern to which the reference potential is supplied.

[0016] While there are various examples of the area of ​​a "conductor plane," compared to, for example, the "wiring pattern" that constitutes a signal transmission path, the area of ​​a "conductor plane" is more than 10 times the area of ​​the "wiring pattern."

[0017] <Electronic equipment> First, the electronic device of this embodiment will be described. Figure 1 is a top view of the electronic device of this embodiment. Figure 2 is a bottom view of the electronic device shown in Figure 1. Figure 3 is a cross-sectional view taken along line AA in Figure 1.

[0018] Figures 1 to 3 show either the X direction (see Figures 1 to 3), the Y direction (see Figures 1 and 2), or the Z direction (see Figure 3). The Y direction intersects the X direction, and in the following explanation, the X and Y directions are orthogonal to each other. The Z direction is orthogonal to both the X and Y directions. In other words, the Z direction is the normal direction (or perpendicular direction) to the XY plane, which includes the X and Y directions. In the following explanation, "thickness" generally refers to the length in the Z direction. Also, in the following explanation, "plan view" generally refers to a plan view of the XY plane.

[0019] As shown in Figure 1, the electronic device ED1 includes a mounting substrate (wiring board) MB1 and a semiconductor device PKG1 mounted on the mounting substrate MB1. The mounting substrate MB1 has an upper surface 1t and a lower surface 1b located on the opposite side of the upper surface (see Figure 2). The semiconductor device PKG1 is mounted on the upper surface 1t of the mounting substrate MB1.

[0020] Furthermore, in this embodiment, as shown in Figure 2, a regulator (power supply component) RG1 is mounted on the lower surface 1b of the mounting board MB1. The regulator RG1 is a power supply component capable of supplying potentials of multiple values. For example, the potentials required to operate each of the multiple circuits provided in the semiconductor device PKG1 are supplied from the regulator RG1 via the mounting board MB1.

[0021] The semiconductor device PKG1 comprises an interposer substrate SUB1 and a semiconductor chip CP1 mounted on the interposer substrate SUB1. The detailed structure of the semiconductor device PKG1 will be described later.

[0022] The mounting substrate MB1 and the interposer substrate SUB1 of the semiconductor device PKG1 are both wiring boards. However, the mounting substrate MB1 and the interposer substrate SUB1 differ in the degree of miniaturization of the conductor patterns that constitute the signal transmission path or potential supply path.

[0023] More specifically, the interposer substrate SUB1 is a wiring board that functions as an interposer for electrically connecting the miniaturized semiconductor chip CP1 and the mounting substrate MB1. The signal transmission paths formed on the interposer substrate SUB1 are electrically connected to each of the electrodes of the semiconductor chip CP1, which are arranged at a narrow pitch. For this reason, the conductor patterns constituting the signal transmission paths on the interposer substrate SUB1 need to be miniaturized compared to the conductor patterns constituting the signal transmission paths formed on the mounting substrate MB1.

[0024] The mounting board MB1 is a wiring board on which the semiconductor device PKG1 is mounted. In Figure 1, only the semiconductor device PKG1 is shown as an electronic component mounted on the upper surface 1t of the mounting board MB1. In Figure 2, only the regulator RG1 is shown as an electronic component mounted on the lower surface 1b of the mounting board MB1.

[0025] However, there are various variations in the examples of electronic components mounted on the mounting board MB1. For example, multiple electronic components, including the semiconductor device PKG1, may be mounted on the upper surface 1t of the mounting board MB1. Examples of electronic components other than the semiconductor device PKG1 and regulator RG1 include passive components such as capacitors, resistors, or inductors.

[0026] As shown in Figure 3, the mounting substrate MB1 has multiple wiring layers MWL stacked in the thickness direction (Z direction in Figure 3). The thickness direction of the mounting substrate MB1 is the direction from one of the top surface 1t and the bottom surface 1b of the mounting substrate MB1 to the other. In the example shown in Figure 3, the mounting substrate MB1 has wiring layers MWL1, MWL2, MWL3, MWL4, MWL5, MWL6, MWL7, and MWL8 in that order. Wiring layer MWL1 is the wiring layer closest to the top surface 1t among the multiple wiring layers MWL. Wiring layer MWL8 is the wiring layer closest to the bottom surface 1b among the multiple wiring layers MWL. Note that the 8-layer wiring structure shown in Figure 3 is just one example, and there are various variations in the number of stacked wiring layers MWL other than 8. For example, there may be 7 layers or less, or 9 layers or more.

[0027] Furthermore, the mounting substrate MB1 has multiple through-hole wirings THW formed to penetrate multiple wiring layers MWL. Each of the multiple through-hole wirings THW is formed to penetrate from wiring layer MWL1 to wiring layer MWL8.

[0028] A wiring board in which multiple stacked wiring layers MWL are electrically connected via through-hole wiring THW, such as the MB1 mounting board, is called a through-hole multilayer board. When manufacturing a through-hole multilayer board, after stacking the required total number of wiring layers MWL, holes (through-holes) are formed to penetrate multiple wiring layers MWL. Then, conductors are embedded in the through-holes to form the through-hole wiring THW.

[0029] In the case of the interposer substrate SUB1 shown in Figure 3, among the multiple stacked wiring layers SWL, wiring layers SWL that are adjacent to each other in the thickness direction are connected via wiring. The through-hole wiring THW shown in Figure 3 differs from via wiring in that it is arranged across three or more wiring layers MWL. In Figure 3, a six-layer structure consisting of wiring layers SWL1, SWL2, SWL3, SWL4, SWL5, and SWL6 is shown as an example of wiring layers SWL.

[0030] A wiring board in which multiple wiring layers SWL are electrically connected via vias, such as the interposer board SUB1, is called a build-up board. When manufacturing a build-up board, vias are formed each time a wiring layer SWL is stacked. The method of manufacturing a build-up board is called the build-up method.

[0031] In the case of through-layer multilayer substrates, interlayer conductive paths connecting multiple wiring layers (MWL) can be formed simultaneously, as described above, thereby improving manufacturing efficiency. As a result, the manufacturing cost of the mounted substrate (MB1) can be reduced. On the other hand, each of the multiple wiring layers (MWL) must be designed considering the positions of multiple through-hole wirings (THW). Therefore, constraints are placed on the layout of the conductor patterns in each of the multiple wiring layers (MWL).

[0032] Figure 4 is a plan view showing an example of the power plane and ground plane, among the multiple conductor planes present in the mounting substrate shown in Figure 3. Figure 4 shows an enlarged view of a portion of the wiring layer MWL1 shown in Figure 3. In Figure 4, the contour of the region RPKG, which overlaps with the semiconductor device PKG1 shown in Figure 3, is shown by a dashed line.

[0033] As illustrated in Figure 4, the multiple conductor patterns on the mounting substrate MB1 include a conductor plane 1CP for supplying fixed potentials such as the power supply potential and the reference potential. The conductor plane 1CP is a large-area conductor pattern. By interposing a large-area conductor plane 1CP in the fixed potential supply path, the cross-sectional area of ​​the current path can be increased. As a result, a fixed potential can be stably supplied to the power-consuming circuit.

[0034] Figure 4 illustrates two of the multiple conductor planes on the mounting substrate MB1: power plane 1PVD1, which constitutes the power supply potential supply path, and ground plane 1PVS1, which constitutes the reference potential supply path. Figure 4 also illustrates power plane 1PVD2, which constitutes a power supply potential supply path different from the potential supplied to power plane 1PVD1.

[0035] Furthermore, multiple through-hole wirings THW are arranged in the wiring layer MWL1. Each of the multiple through-hole wirings THW includes a power supply potential through-hole wiring WVD1 for supplying the power supply potential and a reference potential through-hole wiring WVS1 for supplying a reference potential (e.g., ground potential). Additionally, each of the multiple through-hole wirings THW includes a signal through-hole wiring WSG1 for transmitting signals.

[0036] The semiconductor device PKG1 shown in Figure 3 is supplied with various potentials, such as power supply potential, reference potential, or multiple signals. Therefore, as shown in Figure 4, a large number of through-hole wirings THW are densely arranged in the region RPKG that overlaps with the semiconductor device PKG1 (see Figure 3). In other words, the arrangement density of through-hole wirings THW in region RPKG is higher than the arrangement density of through-hole wirings THW in the surrounding region of region RPKG.

[0037] Therefore, within region RPKG, numerous openings H1 are formed in the ground plane 1PVS1. Furthermore, it is difficult to make the area of ​​the power plane 1PVD2, which is located within region RPKG, sufficiently large.

[0038] On the other hand, in a plan view, it is relatively easy to secure space outside the region RPKG where other through-hole wiring THW for potential or signal is not located. For example, in the example shown in Figure 4, of the multiple through-hole wiring THW located in positions overlapping with the power plane 1PVD1, there are two through-hole wiring THW other than the power potential through-hole wiring WVD1. Therefore, there are two openings H1 formed in the power plane 1PVD1.

[0039] From the viewpoint of stably supplying a fixed potential, it is preferable to have fewer openings H1 formed in the power plane 1PVD1. In particular, it is preferable to have fewer openings H1 near the external terminal SB (see Figure 3) where the semiconductor device PKG1 (see Figure 3) and the mounting substrate MB1 are connected. When there are fewer openings H1, the degree of freedom of charge movement within the power plane 1PVD1 is improved. In this case, voltage drops are less likely to occur even when power demand increases instantaneously.

[0040] The electronic device ED1 of this embodiment (see Figure 3) reduces the number of openings H1 formed in the power plane 1PVD1 and increases the area of ​​the power plane 1PVD1. This stabilizes the power supply potential supplied to the semiconductor device PKG1 (see Figure 3) via the power plane 1PVD1.

[0041] For example, in the example shown in Figure 4, a through-hole wiring that is positioned to overlap with the power plane 1PVD1 and is electrically isolated from the power plane 1PVD1 is denoted as through-hole wiring THW1. A through-hole wiring THW that is positioned to overlap with the semiconductor device PKG1 (see Figure 3) is denoted as through-hole wiring THW2. In Figure 4, the number of multiple through-hole wirings THW1 is less than the number of second through-hole wirings THW2.

[0042] Furthermore, as mentioned above, the structure of the semiconductor device PKG1 needs to be modified in order to stabilize the power supply potential. The next section will describe the details of the structure of the semiconductor device PKG1.

[0043] <Semiconductor device> Figure 1 is a top view of the electronic device of this embodiment. Figure 5 is a bottom view of the semiconductor device shown in Figure 3. Although Figure 5 is a plan view, hatching is applied to power terminals TVD1 and TVD2 to make them easier to identify. Figure 6 is an explanatory diagram showing an example of the layout of multiple circuits provided by the semiconductor chip shown in Figure 3. Figure 7 is an explanatory diagram showing an example of the electrical connection state between the multiple circuits shown in Figure 6 and the multiple external terminals shown in Figure 5.

[0044] As shown in Figures 1 and 3, the semiconductor device PKG1 has a semiconductor chip CP1, an interposer substrate SUB1, and a plurality of external terminals SB.

[0045] As shown in Figure 5, the bottom surface 2b of the interposer substrate SUB1 is rectangular. In other words, the shape of the bottom surface 2b when viewed from above is rectangular. The bottom surface 2b has side 2s1, side 2s2 located opposite side 2s1, side 2s3 extending in directions intersecting sides 2s1 and 2s2, and side 2s4 located opposite side 2s3.

[0046] As shown in Figure 1, the upper surface 2t of the interposer substrate SUB1 also has edges 2s1, 2s2, 2s3, and 2s4. Each edge of the lower surface 2b shown in Figure 5 and each edge of the upper surface 2t shown in Figure 1 overlap with each other.

[0047] Furthermore, the semiconductor chip CP1 has edge 3s1, edge 3s2 located opposite edge 3s1, edge 3s3 extending in directions intersecting edges 3s1 and 3s2 respectively, and edge 3s4 located opposite edge 3s3. Edge 3s1 is arranged along edge 2s1. Edge 3s2 is arranged along edge 2s2. Edge 3s3 is arranged along edge 2s3. Edge 3s4 is arranged along edge 2s4. Note that each edge of the semiconductor chip CP1 is also illustrated in Figure 6.

[0048] The lower surface 2b includes a terminal arrangement region RSB in which multiple external terminals SB are arranged, and a peripheral region RPF surrounding the terminal arrangement region RSB. In a plan view, the multiple external terminals SB are arranged in alignment on the lower surface 2b of the interposer substrate SUB1. In the example shown in Figure 5, the multiple external terminals SB are arranged in a matrix. Each of the multiple external terminals SB is a solder ball, for example, made of solder formed into a ball shape.

[0049] As shown in Figure 6, the semiconductor chip CP1 comprises multiple circuits. These multiple circuits include circuits C1 and C2. In the example shown in Figure 6, the multiple circuits of the semiconductor chip CP1 also include circuits C3 and C4.

[0050] The circuit C1 shown in Figure 6 is, for example, a CPU circuit. The CPU circuit is the circuit that reads and executes programs. The CPU circuit is the circuit that performs the main arithmetic operations of the computer. The CPU circuit is electrically connected to peripheral circuits (for example, circuits C3 and C4) via a peripheral bus.

[0051] The multiple circuits C3 are input / output circuits such as DDR SDRAM (Double-Data-Rate Synchronous Dynamic Random Access Memory). DDR SDRAM and similar components are sometimes referred to as main memory, in contrast to the cache memory described later.

[0052] Circuit C4 is a signal input / output circuit. The input / output circuit includes, for example, a SerDes circuit that converts between serial and parallel transmission methods.

[0053] Circuit C2 is the core circuit (also called the core logic circuit). However, the core circuit that makes up circuit C2 is distinct from the CPU circuit shown as circuit C1. Circuit C2 includes a memory control circuit that controls the operation of circuit C3. Circuit C2 also includes an input / output control circuit that controls the operation of circuit C4. Circuit C2 also includes the peripheral bus described above. Furthermore, circuit C2 includes an SRAM (Static Random Access Memory) circuit that can be used as a cache memory circuit.

[0054] Focusing on the power consumption of each of the multiple circuits shown in Figure 6, the power consumption of circuit C1 is the largest among the multiple circuits on the semiconductor chip CP1. Furthermore, the power consumption of circuit C2 is the second largest among the multiple circuits on the semiconductor chip CP1, after circuit C1.

[0055] Although not shown in the diagram, one possible example of consideration for this embodiment is to make the power supply potential supply path to circuit C1, which is the CPU circuit, and the power supply potential supply path to circuit C2, which is the core circuit, common.

[0056] However, from the viewpoint of stably supplying power to circuit C1, which consumes the most power, it is preferable to provide a dedicated path for supplying power potential to circuit C1. For example, by providing a dedicated power supply path to circuit C1, it is possible to prevent momentary power shortages to circuit C1 depending on the operating status of other circuits.

[0057] As shown in Figure 7, in this embodiment, the supply path for power supply potential VD1 and the supply path for power supply potential VD2 are electrically isolated from each other. Power supply potentials VD1 and VD2 are at different potentials. However, as a modification, power supply potentials VD1 and VD2 may be at the same potential. Even when power supply potentials VD1 and VD2 are at the same potential, the supply path for power supply potential VD1 and the supply path for power supply potential VD2 are electrically isolated from each other. For this reason, this embodiment is preferred from the viewpoint of stably supplying power to the circuit C1 with the highest power consumption.

[0058] Note that the power supply paths required to operate each of the multiple circuits C3 and C4 shown in Figure 6 are provided separately from the power supply paths for power supply potential VD1 and power supply potential VD2. However, these are omitted from the illustration in Figure 7.

[0059] As shown in Figure 7, the multiple external terminals SB of the semiconductor device PKG1 include power terminals TVD1 capable of supplying an externally supplied power potential VD1 to circuit C1. Although Figure 7 schematically illustrates one power terminal TVD1, as shown in Figure 5, the semiconductor device PKG1 has multiple power terminals TVD1. Furthermore, in the example shown in Figure 7, the multiple external terminals SB further include power terminals TVD2 capable of supplying an externally supplied power potential VD2 to circuit C2. As shown in Figure 5, the semiconductor device PKG1 has multiple power terminals TVD2.

[0060] As shown in Figure 5, the terminal arrangement region RSB includes region RVD1, which is closest to and extends along edge 2s1 of the interposer substrate SUB1. Furthermore, within region RVD1, only the multiple power supply terminals TVD1 among the multiple external terminals SB are arranged adjacent to each other.

[0061] Here, the power supply potential VD1 is supplied via a power supply plane 1PVD1 formed on the wiring layer MWL1, which is one of the multiple conductor planes 1CP of the mounting substrate MB1 described using Figure 4. In a transparent plan view, the power supply plane 1PVD1 is positioned to straddle side 2s1 of the four sides of the lower surface 2b (see Figure 5) of the interposer substrate SUB1 (see Figure 5) of the semiconductor device PKG1 (see Figure 5).

[0062] As shown in Figure 5, when only multiple power terminals TVD1 are arranged adjacent to each other in region RVD1, no other types of external terminals are placed in region RVD1. For this reason, no opening H1 is formed in the portion of the power plane 1PVD1 shown in Figure 4 that is located in region RPKG, which overlaps with the semiconductor device PKG1 shown in Figure 3. In other words, in this embodiment, no opening H1 (see Figure 4) is formed in the portion of the power plane 1PVD1 (see Figure 4) that is located near multiple power terminals TVD1 (see Figure 5). As a result, the degree of freedom of charge transfer between multiple power terminals TVD1 is improved, and the power potential VD1 can be stably supplied to the circuit C1 shown in Figure 7.

[0063] As described above, circuit C1 is a CPU circuit. The power required for operation of a CPU circuit can change significantly depending on the timing of the calculation process. For example, consider the case where the power required by the CPU circuit increases instantaneously, causing an increase in the current flowing through some of the multiple power supply terminals TVD1.

[0064] When the current flowing through some of the multiple power terminals TVD1 increases, the charge around power terminals TVD1 becomes insufficient. In this case, if a power plane 1PVD1 (see Figure 4) is located near the multiple power terminals TVD1, the insufficient charge is supplied from the area around the power terminal TVD1 through the power plane 1PVD1 where the large current is flowing.

[0065] However, if an opening H1 (see Figure 4) is formed in the power plane 1PVD1 (see Figure 4), the movement of charge may be hindered by the opening H1, causing a momentary voltage drop.

[0066] On the other hand, in this embodiment, as shown in Figure 4, no opening H1 is formed in the power plane 1PVD1 within region RPKG. Therefore, charge movement is not hindered, and the occurrence of voltage drop can be suppressed. That is, the power potential VD1 can be stably supplied to the circuit C1 shown in Figure 7.

[0067] Incidentally, the number of power terminals TVD1 arranged continuously in region RVD1 can be varied in various ways depending on the arrangement pitch of the external terminals SB and the size of the power plane 1PVD1 shown in Figure 4. However, from the viewpoint of stabilizing the power supply potential, at least several power terminals TVD1 must be arranged adjacent to each other. Furthermore, it is preferable that five or more power terminals TVD1 are arranged continuously. In the example shown in Figure 5, ten power terminals TVD1 are arranged continuously.

[0068] Furthermore, as already explained in Figure 6, the multiple circuits of the semiconductor chip CP1 further include circuit C2. As shown in Figures 5 and 7, the multiple external terminals SB further include multiple power terminals TVD2 (see Figure 5) capable of supplying an externally supplied power potential VD2 (see Figure 7) to circuit C2 (see Figure 7). As shown in Figure 5, the terminal array region RSB includes region RVD2, which is further away from region RVD1 when viewed from side 2s1. The multiple power terminals TVD2 are located in region RVD2.

[0069] As shown in Figure 5, the power terminals TVD2 are arranged in a cluster within region RVD2. In other words, the power terminals TVD2 are clustered together within region RVD2. Also, as shown in Figure 4, the power plane 1PVD2, which constitutes the supply path for the power potential VD2 (see Figure 7), is located on the wiring layer MWL1 of the mounting board MB1.

[0070] However, as shown in Figure 5, external terminals SB other than the power terminal TVD2 are arranged around region RVD2. For this reason, as shown in Figure 4, the area of ​​power plane 1PVD2 cannot be made larger than the area of ​​power plane 1PVD1. It is also possible to place power plane 1PVD2 on a wiring layer different from wiring layer MWL1 (for example, any of wiring layers MWL2 to MWL8 shown in Figure 3). However, as shown in Figure 4, numerous through-hole wirings THW are arranged in region RPKG. For this reason, even if power plane 1PVD2 is placed on a wiring layer different from wiring layer MWL1 shown in Figure 4, numerous openings H1 will be formed in power plane 1PVD2.

[0071] Therefore, as described above, from the viewpoint of stably supplying a fixed potential, the power supply potential VD1 supply path shown in Figure 7 is superior to the power supply potential VD2 supply path. In this embodiment, we focus on the power consumption of the multiple circuits in the semiconductor chip CP1 shown in Figure 7, and prioritize countermeasures for the power supply potential supply path connected to circuit C1, which has the highest power consumption. This is because instantaneous voltage drops are less likely to occur in circuit C2, which has lower power consumption compared to circuit C1.

[0072] Furthermore, as shown in Figure 7, which has already been explained, the multiple external terminals SB further include a reference potential terminal TVS1 capable of supplying an externally supplied reference potential VS1 to circuits C1 and C2.

[0073] As shown in Figure 5, the terminal arrangement region RSB further comprises region R3 located between region RVD1 and region RVD2. At least some of the multiple reference potential terminals TVS1 are located within region R3.

[0074] Incidentally, as shown in Figure 6, circuit C1 is located closer to side 3s1 than to side 3s2 of the semiconductor chip CP1. As shown in Figure 1, side 3s1 of semiconductor chip CP1 is aligned with side 2s1 of interposer substrate SUB1. As shown in Figure 5, the multiple power supply terminals TVD1 are located in region RVD1, which is closest to side 2s1. In this case, because circuit C1 is located near side 3s1, the distance of the power supply potential VD1 (see Figure 7) can be shortened.

[0075] <Relationship between signal terminals and power terminals> Next, several embodiments of the positional relationship between the multiple power terminals TVD1 shown in Figure 5 and the external terminals SB for signal transmission will be illustrated and explained. Figure 8 is a plan view showing an example of the positional relationship between the power terminal, the reference potential terminal, and the differential signal terminal pair among the multiple external terminals provided by the semiconductor device. Although Figure 8 is a plan view, some of the multiple external terminals SB are hatched to make it easier to identify the types of external terminals SB. The same applies to Figures 9, 10, 11, 15, and 16, which will be described below.

[0076] The multiple external terminals SB of the semiconductor device PKG2 shown in Figure 8 are arranged as follows: Region RVD1 and region R3 are adjacent without any other regions in between. The multiple external terminals SB further include multiple differential signal terminal pairs TSG1. The differential signal terminal pairs TSG1 constitute a differential pair capable of transmitting the differential signal SG1 (see Figure 7) at a first signal transmission speed.

[0077] Multiple reference potential terminals TVS1 are arranged to surround each of the differential signal terminal pairs TSG1 and to be adjacent to each of the multiple differential signal terminal pairs TSG1. Some of the multiple reference potential terminals TVS1 arranged around each of the multiple differential signal terminal pairs TSG1 are adjacent to one of the multiple power terminals TVD1 located in region RVD1.

[0078] This section compares differential and single-ended signaling as signal transmission methods. One way to increase the speed of signal transmission is to reduce the amplitude of the signal voltage. In recent years, there are also technologies that increase the amount of information contained in the amplitude of the signal voltage, such as PAM4 (4-level Pulse Amplitude Modulation), which speeds up signal transmission.

[0079] In the case of single-ended signals, reducing the amplitude of the signal voltage increases the impact of noise. On the other hand, in the case of differential signals, the potential difference between paired transmission paths is utilized, so if the same noise is applied to each paired transmission path, the noise can be canceled out. In other words, differential signals have higher noise immunity compared to single-ended signals when the amplitude of the signal voltage is reduced. For this reason, differential signals are used as transmission paths for high-speed signals.

[0080] However, in order to improve the transmission quality of differential signals, it is necessary to consider the characteristic impedance of the transmission path. The characteristic impedance of a differential signal transmission path is determined by the distance between transmission paths, the distance between the transmission path and surrounding conductor patterns, and the polarity of the current flowing through the transmission path. To improve the transmission quality of differential signals, it is preferable to avoid creating impedance discontinuities in the transmission path of the differential signal. For this reason, it is preferable to keep the distance between transmission paths constant, and to arrange conductor patterns carrying a fixed potential at a constant distance around the transmission path.

[0081] In the example shown in Figure 8, a reference potential terminal TVS1, for example, to which the ground potential is supplied, is placed between each of the multiple differential signal terminal pairs TSG1 and the power supply terminal TVD1. Therefore, the occurrence of impedance discontinuities in the differential signal transmission path due to the influence of the multiple power supply terminals TVD1 can be suppressed. As a result, the quality of differential signals transmitted at high speed can be improved.

[0082] Incidentally, when considering the layout of signal transmission wiring on the mounting board MB1 (see Figure 1), it is preferable that the signal transmission terminals be located near the outermost edge of the terminal array region RSB shown in Figure 8. In the example shown in Figure 8, the terminal array region RSB includes region R4 extending along edge 2s2, region R5 extending along edge 2s3, and region R6 extending along edge 2s4. Some of the multiple differential signal terminal pairs TSG1 are located in at least one of regions R4, R5, and R6. In the example shown in Figure 8, multiple differential signal terminal pairs TSG1 are located in regions R4 and R5, respectively.

[0083] As mentioned above, from the viewpoint of improving the quality of differential signals, it is preferable that the differential signal terminal pair TSG1 is surrounded by the reference potential terminal TVS1. Therefore, multiple reference potential terminals TSV1 are continuously arranged in the outermost periphery of the terminal arrangement region RSB, i.e., the region closest to side 2s2 and the region closest to side 2s3. The differential signal terminal pair TSG1 is arranged in the second column from the outermost periphery.

[0084] Figure 9 is a plan view showing a semiconductor device that is a modified version of Figure 8. The multiple external terminals SB of the semiconductor device PKG3 shown in Figure 9 differ from those of the semiconductor device PKG2 shown in Figure 8 in the following respects.

[0085] Multiple external terminals SB further include multiple signal terminals TSG2. Signal terminals TSG2 are terminals capable of transmitting signal SG2 (see Figure 7) at a second signal transmission speed. The second signal transmission speed is slower than the first signal transmission speed, which is the transmission speed of signal SG1 shown in Figure 7. Signal SG2 is, for example, a single-ended signal. Signal terminals TSG2 are also illustrated in the example shown in Figure 8. Multiple signal terminals TSG2 are arranged in region R6.

[0086] In the semiconductor device PKG3 shown in Figure 9, multiple signal terminals TSG2 are arranged within region R3. A reference potential terminal TVS1 is interposed between the multiple signal terminals TSG2 and the multiple differential signal terminal pairs TSG1.

[0087] Depending on the layout of the signal transmission terminals, a signal terminal TSG2 may be placed near a differential signal terminal pair TSG1 used for high-speed transmission. In this case, it is necessary to avoid interference between the signal SG2 (see Figure 7) flowing through signal terminal TSG2 and the signal SG1 (see Figure 7) flowing through the differential signal terminal pair TSG1. As in this modified example, if a reference potential terminal TVS1 is interposed between the differential signal terminal pair TSG1 and the signal terminal TSG2, the above-mentioned interference can be suppressed.

[0088] Incidentally, as mentioned above, signal SG2 shown in Figure 7 is a signal that is transmitted at a lower speed compared to signal SG1. Therefore, the effect of noise can be reduced by making the signal voltage sufficiently high. In other words, any external terminal SB can be placed around signal terminal TSG2. In the example shown in Figure 9, some of the multiple signal terminals TSG2 are adjacent to one of the multiple power supply terminals TVD1 located in region RVD1. Although not shown in the illustration, as a modification of the example shown in Figure 9, a reference potential terminal TVS1 may be interposed between the multiple signal terminals TSG2 and the multiple power supply terminals TVD1 located in region RVD1.

[0089] Figure 10 is a plan view showing a semiconductor device that is another modification of Figure 8. The multiple external terminals SB of the semiconductor device PKG4 shown in Figure 10 differ from those of the semiconductor device PKG2 shown in Figure 8 in the following respects.

[0090] The terminal arrangement region RSB further includes region R7, which is closest to and extends along edge 2s3 of the interposer substrate SUB1. In region R7, only multiple power supply terminals TVD1 are arranged adjacent to each other among multiple external terminals SB. In other words, in the case of semiconductor device PKG4, multiple power supply terminals TVD1 are arranged along multiple edges.

[0091] As in this modified example, when power terminals TVD1 are arranged along multiple sides, the area of ​​the power plane 1PVD1 shown in Figure 4 can be further increased in the vicinity of the power terminals TVD1.

[0092] Figure 11 is a plan view showing a semiconductor device that is another modification of Figure 8. Figure 12 is a plan view showing an example of a circuit layout in a semiconductor chip, which is a modification of Figure 6 and is a semiconductor chip having the semiconductor device shown in Figure 11. Figure 13 is an explanatory diagram showing an example of the electrical connection state between the multiple circuits shown in Figure 12 and the multiple external terminals shown in Figure 11. Figure 14 is a plan view showing an example of a power plane and a ground plane among the multiple conductor planes provided on the mounting substrate of an electronic device on which the semiconductor device shown in Figure 11 is mounted. The multiple external terminals SB of the semiconductor device PKG5 shown in Figure 11 differ from those of the semiconductor device PKG2 shown in Figure 8 in the following respects.

[0093] The semiconductor device PKG5 shown in Figure 11 has a semiconductor chip CP2 shown in Figure 12. The semiconductor chip CP2 has multiple circuits, which further include a circuit C5 as shown in Figures 12 and 13. Circuit C5 is, for example, a second CPU circuit that can be turned on and off independently of the CPU circuit C1. Since circuit C5 can be turned on and off independently of circuit C1, there are cases where only circuit C1 is operating, where circuits C1 and C5 are operating simultaneously, and where only circuit C5 is operating.

[0094] If circuits C1 and C5 operate independently on and off, their power supply paths must be separated. Even if they do not operate independently on and off, the power consumption of circuit C5 when it is operating is the same as that of circuit C1, or the second largest among the power consumption of the multiple circuits on the semiconductor chip CP1. Therefore, it is preferable that the power supply paths to these two CPU circuits with high power consumption be separated. This is to prevent the power demand of one CPU circuit from affecting the power supply to the other CPU circuit.

[0095] As shown in Figure 13, the multiple external terminals SB further include multiple power supply terminals TVD3 capable of supplying an externally supplied power supply potential VD3 to circuit C5. The power supply potential VD3 may be the same potential as the power supply potential VD1, or it may be a different potential from the power supply potential VD1. In either case, the power supply terminals TVD3 are electrically isolated from the power supply terminals TVD1.

[0096] As shown in Figure 11, the terminal arrangement region RSB includes region RVD3, which is located at a distance equal to that of region RVD1 from side 2s1 of the interposer substrate SUB1 and extends along side 2s1. In region RVD3, only the multiple power supply terminals TVD3 among the multiple external terminals SB are arranged adjacent to each other.

[0097] In this modified example, each of the multiple power terminals TVD1 and TVD3 is arranged on the outermost periphery of the terminal arrangement region RSB. The multiple power terminals TVD1 are connected to power plane 1PVD1 shown in Figure 14. The multiple power terminals TVD3 are connected to power plane 1PVD3 shown in Figure 14. Furthermore, power planes 1PVD1 and 1PVD3 do not overlap with the through-hole wiring TWH in region RPKG. That is, each of the multiple power terminals TVD1 and TVD3 is connected to a power plane with a large area in the vicinity of the terminal. Therefore, a stable potential can be supplied to each of the multiple power terminals TVD1 and TVD3.

[0098] Incidentally, when using a semiconductor chip equipped with multiple CPU circuits, such as the semiconductor chip CP2 shown in Figure 12, a modified example combining the embodiment shown in Figure 11 and the embodiment shown in Figure 10 is particularly effective. Figure 15 is a plan view showing a semiconductor device that is a modified example of Figure 11.

[0099] The multiple external terminals SB of the semiconductor device PKG6 shown in Figure 15 differ from those of the semiconductor device PKG5 shown in Figure 11 in the following respects.

[0100] In the example shown in Figure 15, the terminal arrangement region RSB further includes regions R7 and R9. Region R7 is closest to and extends along side 2s3 of the interposer substrate SUB1. Region R9 is closest to and extends along side 2s4 of the interposer substrate SUB1. In region R7, only multiple power supply terminals TVD1 are arranged adjacent to each other among multiple external terminals SB. In region R9, only multiple power supply terminals TVD3 are arranged adjacent to each other among multiple external terminals SB.

[0101] In this modified example, multiple power terminals TVD1 and multiple power terminals TVD3 are arranged along two sides. In this case, the number of multiple power terminals TVD1 and multiple power terminals TVD3 can be increased compared to the semiconductor device PKG5 shown in Figure 11.

[0102] Furthermore, in each of the embodiments described above, an embodiment was described in which multiple power terminals TVD1 are arranged only on the outermost periphery of the terminal arrangement region RSB. However, as a modification, there is a case in which some of the multiple power terminals TVD1 are arranged outside the outermost periphery of the terminal arrangement region RSB, as shown in the semiconductor device PKG7 in Figure 16. Figure 16 is a plan view showing another modification of Figure 8.

[0103] The multiple external terminals SB of the semiconductor device PKG7 shown in Figure 16 differ from those of the semiconductor device PKG2 shown in Figure 8 in the following respects: The terminal arrangement region RSB further comprises region R10. Region R10 is adjacent to region RVD1 and is located between region R3 and region RVD1. Region R10 extends along region RVD1. Of the multiple external terminals SB, only the multiple power supply terminals TVD1 are arranged adjacent to each other in region R10.

[0104] In other words, in this modified example, each of the multiple power terminals TVD1 is arranged in two consecutive rows along side 2s1. When only power terminals TVD1 are arranged in each of the adjacent regions RVD1 and R10 in this way, the area of ​​the power plane PVD1 in region RPKG shown in Figure 4 can be further increased.

[0105] In Figure 16, an example is shown of an embodiment in which each of the multiple power terminals TVD1 is arranged in two rows. However, the number of rows may be, for example, three or more.

[0106] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0107] For example, the various modifications described above may be combined with each other.

[0108] Furthermore, Figure 4 illustrates an electronic device ED1 equipped with the semiconductor device PKG1 shown in Figure 5. Figure 14 also illustrates an electronic device ED2 equipped with the semiconductor device PKG5 shown in Figure 11. However, various modifications of the electronic device are possible. For example, although not shown, an electronic device equipped with any of the multiple semiconductor devices described using Figures 8 to 16 can stably supply the power supply potential VD1 (see Figure 7). [Explanation of Symbols]

[0109] 1b,2b Bottom surface 1CP Conductor Plain 1PVD1, 1PVD2, 1PVD3 power plane 1PVS1 Ground Plane 3s1,3s2,3s3,3s4,2s1,2s2,2s3,2s4 sides 1t,2t top surface C1,C2,C3,C4,C5 circuit CP1, CP2 semiconductor chips ED1,ED2 Electronic equipment H1 opening MB1 Mounted board (wiring board) MWL,MWL1,MWL2,MWL3,MWL4,MWL5,MWL6,MWL7,MWL8,SWL,SWL1,SWL2,SWL3,SWL4,SWL5,SWL6 Wiring layer PKG1, PKG2, PKG3, PKG4, PKG5, PKG6, PKG7 Semiconductor R3,R4,R5,R6,R7,R9,R10,RPKG,RVD1,RVD2,RVD3 area RG1 Regulator (Power Supply Component) RPF peripheral region RSB terminal arrangement area SB external terminal SG1,SG2 signal SUB1 Interposer board THW Through-hole wiring TSG1 Differential Signal Terminal Pair TSG2 signal terminal TSV1 Reference Potential Terminal TVD1, TVD2, TVD3 Power Terminals TVS1 Reference Potential Terminal TWH Through-hole wiring VD1,VD2,VD3 Power supply potential VS1 Reference Potential WSG1 signal through-hole wiring WVD1 Through-hole wiring for power potential WVS1 Through-hole wiring for reference potential

Claims

1. A semiconductor chip comprising multiple circuits, including a first circuit, An interposer substrate having a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface, wherein the shape of the second surface when viewed from above is rectangular, A plurality of external terminals arranged in alignment on the second surface of the interposer substrate, It has, The plurality of external terminals include a plurality of first power supply terminals capable of supplying a first power supply potential supplied from the outside to the first circuit. The second surface includes a terminal arrangement region in which the plurality of external terminals are arranged, and a peripheral region surrounding the terminal arrangement region. The terminal arrangement region includes a first region that is closest to the first side of the interposer substrate and extends along the first side. In the first region, of the plurality of external terminals, only the plurality of first power supply terminals are arranged adjacent to each other. The power consumption of circuit C1 is the highest among the power consumption of each of the multiple circuits provided in the semiconductor chip, in the semiconductor device.

2. In the semiconductor device described in claim 1, The plurality of circuits of the semiconductor chip further include a second circuit, The plurality of external terminals further include a plurality of second power supply terminals capable of supplying a second power supply potential supplied from an external source to the second circuit. The terminal arrangement region includes a second region that is further away from the first region when viewed from the first side. The plurality of second power supply terminals are located in the second region of the semiconductor device.

3. In the semiconductor device described in claim 2, The terminal arrangement region further comprises a third region located between the first region and the second region. The plurality of external terminals further include a plurality of reference potential terminals capable of supplying a reference potential supplied from the outside to the first and second circuits, The semiconductor device is located within the third region, comprising the plurality of reference potential terminals.

4. In the semiconductor device described in claim 3, The first region and the third region are adjacent to each other without any other regions in between. The plurality of external terminals further include a plurality of pairs of first differential signal terminals capable of transmitting a first differential signal at a first signal transmission speed, The plurality of reference potential terminals are arranged so as to surround each of the plurality of first differential signal terminal pairs and so as to be adjacent to each of the plurality of first differential signal terminal pairs. A semiconductor device wherein some of the plurality of reference potential terminals arranged around each of the plurality of first differential signal terminal pairs are adjacent to any of the plurality of first power terminals arranged in the first region.

5. In the semiconductor device according to claim 4, The plurality of external terminals further include a plurality of first signal terminals capable of transmitting the first signal at a second signal transmission speed slower than the first signal transmission speed, The plurality of first signal terminals are arranged within the third region. A semiconductor device in which the reference potential terminal is interposed between the plurality of first signal terminals and the plurality of pairs of first differential signal terminals.

6. In the semiconductor device described in claim 5, A semiconductor device wherein the plurality of first signal terminals are adjacent to any of the plurality of first power terminals arranged in the first region.

7. In the semiconductor device according to claim 4, The interposer substrate comprises the first side, the second side located opposite the first side, the third side extending in a direction intersecting the first side and the second side, and the fourth side located opposite the third side. The terminal arrangement region includes a fourth region extending along the second side, a fifth region extending along the third side, and a sixth region extending along the fourth side. A semiconductor device in which some of the plurality of first differential signal terminal pairs are located in at least one of the fourth region, the fifth region, and the sixth region.

8. In the semiconductor device described in claim 3, The interposer substrate comprises the first side, the second side located opposite the first side, the third side extending in a direction intersecting the first side and the second side, and the fourth side located opposite the third side. The terminal arrangement region further includes a seventh region that is closest to the third side of the interposer substrate and extends along the third side. A semiconductor device wherein, in the seventh region, only the plurality of first power supply terminals among the plurality of external terminals are arranged adjacent to each other.

9. In the semiconductor device described in claim 2, The plurality of circuits provided in the semiconductor chip are CPU circuit and, Multiple memory circuits, Multiple input / output circuits, Includes, The first circuit is the CPU circuit, The second circuit is a semiconductor device that includes a circuit for controlling any of the plurality of memory circuits and the plurality of input / output circuits.

10. In the semiconductor device described in claim 2, The plurality of circuits provided in the semiconductor chip are It further includes a third circuit, The plurality of external terminals further include a plurality of third power supply terminals capable of supplying a third power supply potential supplied from an external source to the third circuit. The terminal arrangement region includes an eighth region whose distance from the first side of the interposer substrate is equal to that of the first region and which extends along the first side. In the eighth region, of the plurality of external terminals, only the plurality of third power supply terminals are arranged adjacent to each other. A semiconductor device wherein the power consumption of the third circuit is the same as that of the first circuit, or is the second largest among the power consumption of each of the multiple circuits provided by the semiconductor chip.

11. In the semiconductor device according to claim 10, The interposer substrate comprises the first side, the second side located opposite the first side, the third side extending in a direction intersecting the first side and the second side, and the fourth side located opposite the third side. The aforementioned terminal arrangement region is A seventh region is located closest to the third edge of the interposer substrate and extends along the third edge, A ninth region is closest to the fourth edge of the interposer substrate and extends along the fourth edge, It further includes, In the seventh region, of the plurality of external terminals, only the plurality of first power supply terminals are arranged adjacent to each other. A semiconductor device wherein, in the ninth region, only the plurality of third power supply terminals among the plurality of external terminals are arranged adjacent to each other.

12. In the semiconductor device according to claim 10, The first circuit is a first CPU circuit, The third circuit is a second CPU circuit that can be switched on and off independently of the first CPU circuit, and is a semiconductor device.

13. In the semiconductor device described in claim 2, The aforementioned terminal arrangement region is A third region located between the first region and the second region, A tenth region adjacent to the first region and located between the third region and the first region, Furthermore, The aforementioned tenth region extends along the aforementioned first region, A semiconductor device wherein, in the tenth region, only the plurality of first power supply terminals among the plurality of external terminals are arranged adjacent to each other.

14. A wiring board having a third surface and a fourth surface located opposite the third surface, A semiconductor device mounted on the third surface of the wiring board, It has, The aforementioned semiconductor device is A semiconductor chip comprising multiple circuits, including a first circuit, An interposer substrate having a first surface on which the semiconductor chip is mounted, and a second surface opposite to the first surface, wherein the shape of the second surface when viewed from above is rectangular, A plurality of external terminals arranged in alignment on the second surface of the interposer substrate, It has, The plurality of external terminals include a plurality of first power supply terminals capable of supplying a first power supply potential to the first circuit. The second surface includes a terminal arrangement region in which the plurality of external terminals are arranged, and a peripheral region surrounding the terminal arrangement region. The terminal arrangement region includes a first region that is closest to the first side of the interposer substrate and extends along the first side. In the first region, of the plurality of external terminals, only the plurality of first power supply terminals are arranged adjacent to each other. The electronic device wherein the power consumption of circuit C1 is the highest among the power consumption of each of the multiple circuits provided by the semiconductor chip.

15. In the electronic device according to claim 14, The plurality of circuits of the semiconductor chip further include a second circuit, The plurality of external terminals further include a plurality of second power supply terminals capable of supplying a second power supply potential to the second circuit. The terminal arrangement region includes a second region that is further away from the first region when viewed from the first side. The plurality of second power terminals are located in the second region of the electronic device.

16. In the electronic device according to claim 15, The aforementioned wiring board is A plurality of wiring layers stacked in the thickness direction of the aforementioned wiring substrate, Multiple through-hole wirings formed to penetrate the aforementioned multiple wiring layers, It has, Of the plurality of wiring layers, the first wiring layer formed closest to the first surface includes a first power plane, which is a conductor pattern electrically connected to the plurality of first power terminals. The aforementioned multiple through-hole wirings are A first through-hole wiring is positioned in a location that overlaps with the first power plane and is electrically isolated from the first power plane, A second through-hole wiring is positioned in a location that overlaps with the aforementioned semiconductor device, Includes, An electronic device in which the number of first through-hole wirings is less than the number of second through-hole wirings.

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