Etching method and method for manufacturing semiconductor device

Abstract

The present invention provides an etching method and a semiconductor device manufacturing method that can mitigate the phenomenon in which the diameter at the bottom of a hole becomes narrower than the diameter at the top. [Solution] According to one embodiment, the etching method includes etching the structure from within holes or slits provided in the structure with an etching solution containing an acid and a polymer. The pH of the acid is less than 5. The polymer is an anionic polymer.

Description

Technical Field

[0001] Embodiments of the present invention relate to an etching method and a method of manufacturing a semiconductor device.

Background Art

[0002] A semiconductor memory device such as a NAND type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. With the miniaturization and multilayerization of the memory cell array, the aspect ratios of memory holes, contact holes, etc. are increasing. In the process of forming holes such as high aspect ratio memory holes and contact holes, a phenomenon (so-called loading) occurs in which the diameter of the bottom of the hole becomes narrower than that of the upper part.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] Provided are an etching method and a method of manufacturing a semiconductor device capable of alleviating the phenomenon in which the diameter of the bottom of a hole becomes narrower than the diameter of the upper part.

Means for Solving the Problems

[0005] According to one embodiment, the etching method includes etching the structure from within holes or slits provided in the structure with an etching solution containing an acid and a polymer. The pH of the acid is less than 5. The polymer is an anionic polymer. [Brief explanation of the drawing]

[0006] [Figure 1] This is a block diagram showing an example configuration of a semiconductor device according to the first embodiment. [Figure 2] This is a circuit diagram showing an example of the circuit configuration of a memory cell array according to the first embodiment. [Figure 3] This is a plan view showing an example of a planar layout of a memory cell array according to the first embodiment. [Figure 4] This is a plan view showing an example of a planar layout of the memory area of ​​a memory cell array according to the first embodiment. [Figure 5] This figure shows an example of a cross-sectional structure of the memory area of ​​a memory cell array according to the first embodiment. [Figure 6] This figure shows an example of a cross-sectional structure of the memory area of ​​a memory cell array according to the first embodiment. [Figure 7] This figure shows an example of a cross-sectional structure of a memory pillar according to the first embodiment. [Figure 8] This is a cross-sectional view (1 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] This is a cross-sectional view (2 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] This is a cross-sectional view (3 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] This is a cross-sectional view (4 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] This is a cross-sectional view (5 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] This is a cross-sectional view (6 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] It is a cross-sectional view (7 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] It is a cross-sectional view (8 / 8) showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] It is a cross-sectional view (1 / 4) showing an example of a step of forming a memory hole according to the first embodiment. [Figure 17] It is a cross-sectional view (2 / 4) showing an example of a step of forming a memory hole according to the first embodiment. [Figure 18] It is a cross-sectional view (3 / 4) showing an example of a step of forming a memory hole according to the first embodiment. [Figure 19] It is a cross-sectional view (4 / 4) showing an example of a step of forming a memory hole according to the first embodiment. [Figure 20] It is a graph showing the relationship between the molecular weight of a polymer and the reverse loading effect. [Figure 21] It is a perspective view showing an example of the configuration of a lead-out region according to Modification Example 2 of the first embodiment. [Figure 22] It is a perspective view showing an example of the configuration of a lead-out region according to Modification Example 2 of the first embodiment.

Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIGS. 1 to 22, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0008] (First Embodiment) FIG. 1 is a block diagram showing a configuration example of a semiconductor device according to the first embodiment. The semiconductor device 1 is a NAND type flash memory capable of storing data non-volatilely and is controlled by an external memory controller 2.

[0009] The semiconductor device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0010] The memory cell array 10 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is a collection of multiple memory cells capable of storing data non-volatilely, and is used, for example, as a data erasure unit. The memory cell array 10 is also provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0011] The command register 11 holds the command CMD received by the semiconductor device 1 from the memory controller 2. The command CMD includes instructions that cause the sequencer 13 to perform read operations, write operations, erase operations, etc.

[0012] The address register 12 holds the address information ADD received by the semiconductor device 1 from the memory controller 2. The address information ADD includes, for example, the block address BAd, the page address PAD, and the column address CAD. For example, the block address BAd, the page address PAD, and the column address CAD are used for selecting the block BLK, word lines, and bit lines, respectively.

[0013] The sequencer 13 controls the operation of the entire semiconductor device 1. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16, etc., based on the command CMD held in the command register 11, to perform read operations, write operations, erase operations, etc.

[0014] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd held in the address register 12.

[0015] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address Bad held in the address register 12. Then, the row decoder module 15 transfers, for example, the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0016] During a write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. During a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transfers the determination result to the memory controller 2 as read data DAT.

[0017] The semiconductor device 1 and the memory controller 2 may be combined to form a single semiconductor device. Examples of such semiconductor devices include memory cards such as SD™ cards and SSDs (Solid State Drives).

[0018] Figure 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array according to the first embodiment. Figure 2 shows one of several block BLKs included in the memory cell array 10. The block BLK includes, for example, five string units SU0 to SU4.

[0019] Each string unit SU contains multiple NAND strings NS, each associated with a bit line BL0 to BLm (where m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage layer to hold data non-volatile. Selection transistors ST1 and ST2 are used to select the string unit SU during various operations.

[0020] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selection transistor ST2 is connected to the source line SL.

[0021] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of multiple selection transistors ST1 in string unit SU0 are connected to selection gate line SGD0. The gates of multiple selection transistors ST1 in string unit SU1 are connected to selection gate line SGD1. The gates of multiple selection transistors ST1 in string unit SU2 are connected to selection gate line SGD2. The gates of multiple selection transistors ST1 in string unit SU3 are connected to selection gate line SGD3. The gates of multiple selection transistors ST1 in string unit SU4 are connected to selection gate line SGD4. The gates of multiple selection transistors ST2 are connected to selection gate line SGS.

[0022] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared among multiple block BLKs by a NAND string NS that is assigned the same column address. Word lines WL0 to WL7 are provided for each block BLK. Source lines SL are shared, for example, among multiple block BLKs.

[0023] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0024] The circuit configuration of the memory cell array 10 provided in the semiconductor device 1 according to this embodiment may be any other circuit configuration. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can be designed to any number.

[0025] An example of the structure of the memory cell array 10 provided in the semiconductor device 1 according to this embodiment is described below. In the drawings referenced below, the X direction corresponds to the extension direction of the word line WL, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the perpendicular direction to the surface of the semiconductor substrate 20 used to form the semiconductor device 1. Hatching in the plan view is added to make the drawing easier to read and is not necessarily related to the material or characteristics of the components to which the hatching is added. In the cross-sectional view, the illustration of the components is omitted as appropriate to make the drawing easier to read. Also, the components shown in each drawing are simplified as appropriate.

[0026] Figure 3 is a plan view showing an example of a planar layout of a memory cell array according to the first embodiment. Figure 3 shows the regions corresponding to the four blocks BLK0 to BLK3 included in the memory cell array 10. The planar layout of the memory cell array 10 is divided, for example, in the X direction into a memory region MA and extraction regions HA1 and HA2. The memory cell array 10 also includes, for example, a plurality of slits SLT and a plurality of slits SHE. The semiconductor device 1 according to this embodiment is a non-volatile memory having a three-dimensional memory cell array.

[0027] The memory area MA contains multiple NAND strings NS. The memory area MA is sandwiched in the X direction by lead areas HA1 and HA2. Each of the lead areas HA1 and HA2 is used for connections between the stacked wiring (word lines WL and selected gate lines SGD and SGS) and the row decoder module 15. For example, each of the lead areas HA1 and HA2 includes portions (terrace portions) of the selected gate line SGS, word lines WL0 to WL7, and selected gate line SGD that do not overlap with the upper wiring layer (conductor layer). Multiple contacts are provided on the respective terrace portions of the selected gate line SGS, word lines WL0 to WL7, and selected gate lines SGD0 to SGD4 within each block BLK. Contacts for the stacked wiring are provided in lead area HA1 in even-numbered block BLKs, for example, and in lead area HA2 in odd-numbered block BLKs.

[0028] Multiple slit SLTs each have a portion extending along the X direction and are aligned in the Y direction. Each slit SLT crosses the memory area MA and the lead areas HA1 and HA2 in the X direction. Each slit SLT also has a structure in which, for example, an insulator or plate-shaped contact is embedded. Each slit SLT separates adjacent wiring (for example, word lines WL0 to WL7, and selection gate lines SGD and SGS) through it. The aspect ratio of the slit SLTs is, for example, 100 or more.

[0029] Each of the multiple slits SHE has a portion extending along the X direction and is arranged in the Y direction. In this example, four slits SHE are positioned between adjacent slits SLT. Each slit SHE crosses the memory area MA in the X direction, with one end of each slit SHE included in the lead-out area HA1 and the other end included in the lead-out area HA2. Each slit SHE also has a structure in which an insulator is embedded, for example. Each slit SHE separates adjacent wiring (at least the selected gate line SGD) through it.

[0030] In the planar layout of the memory cell array 10 described above, each region separated by the slit SLT corresponds to one block BLK. Furthermore, each region separated by the slit SLT and SHE corresponds to one string unit SU. The memory cell array 10 is arranged in a repeating manner in the Y direction, for example, as shown in Figure 3.

[0031] The planar layout of the memory cell array 10 may be any other layout. For example, the number of slits SHE placed between adjacent slits SLT can be designed to be any number. The number of string units SU formed between adjacent slits SLT can be changed based on the number of slits SHE placed between adjacent slits SLT.

[0032] Figure 4 is a plan view showing an example of a planar layout of the memory area of ​​a memory cell array according to the first embodiment. Figure 4 shows an area containing one block BLK (i.e., string units SU0 to SU4). The memory cell array 10 includes multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in the memory area MA. Each slit SLT also includes contacts LI and spacers SP.

[0033] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 24 rows, in the region between two adjacent slits SLT. Then, for example, counting from the top of the paper, one slit SHE overlaps each of the 5th, 10th, 15th, and 20th memory pillar MPs.

[0034] Multiple bit lines BL each have a portion extending in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are positioned to overlap with one memory pillar MP. One of the multiple bit lines BL overlapping with the memory pillar MP is electrically connected to that memory pillar MP via a contact CV.

[0035] For example, the contact CV between a memory pillar MP in contact with a slit SHE and a bit line BL is omitted. In other words, the contact CV between a memory pillar MP in contact with two different selected gate lines SGD and a bit line BL is omitted. The number and arrangement of memory pillars MP and slit SHE between adjacent slits SLT may be in other configurations and can be changed as appropriate. For example, the number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0036] Contact LI is a conductor having a portion extending in the X direction. Spacer SP is an insulator provided on the side surface of Contact LI. Contact LI is sandwiched between spacer SP. Contact LI and conductors adjacent to it in the Y direction (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) are separated and insulated by spacer SP.

[0037] Figure 5 shows an example of a cross-sectional structure of the memory region of a memory cell array according to the first embodiment. Figure 5 is a cross-sectional view along the VV line in Figure 4. The memory cell array 10 further includes, for example, a semiconductor substrate 20, conductive layers 21-25, and insulating layers 30-34.

[0038] Specifically, an insulating layer 30 is provided on the semiconductor substrate 20. Although not shown in the diagram, the insulating layer 30 includes circuits corresponding to, for example, a low decoder module 15 and a sense amplifier module 16.

[0039] A conductive layer 21 is provided on the insulating layer 30. The conductive layer 21 is formed, for example, in the shape of a plate extending along the XY plane and is used as a source wire SL. The conductive layer 21 contains, for example, phosphorus-doped silicon.

[0040] An insulating layer 31 is provided on the conductive layer 21. A conductive layer 22 is provided on the insulating layer 31. The conductive layer 22 is formed, for example, in the shape of a plate extending along the XY plane and is used as a selected gate wire SGS.

[0041] An insulating layer 32 and a conductive layer 23 are alternately stacked on a conductive layer 22. The conductive layer 23 is formed in a plate shape, for example, extending along the XY plane. The stacked conductive layers 23 are used as word lines WL0 to WL7, in order from the semiconductor substrate 20 side.

[0042] An insulating layer 33 is provided on top of the uppermost conductive layer 23. A conductive layer 24 is provided on top of the insulating layer 33. The conductive layer 24 is formed, for example, in the shape of a plate extending along the XY plane and is used as a selected gate line SGD.

[0043] An insulating layer 34 is provided on the conductive layer 24. A conductive layer 25 is provided on the insulating layer 34. The conductive layer 25 is formed in a line shape, for example, extending in the Y direction, and is used as a bit line BL. In other words, in a region not shown, multiple conductive layers 25 are arranged along the X direction. The conductive layer 25 contains, for example, copper.

[0044] Each memory pillar MP extends along the Z direction and penetrates the insulating layers 31-33 and the conductive layers 22-24. The bottom of each memory pillar MP is in contact with the conductive layer 21. The portion where the memory pillar MP intersects with the conductive layer 22 functions as a selection transistor ST2. The portion where the memory pillar MP intersects with one conductive layer 23 functions as one memory cell transistor MT. The portion where the memory pillar MP intersects with the conductive layer 24 functions as a selection transistor ST1.

[0045] Each memory pillar MP also includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is provided extending along the Z direction. For example, the upper end of the core member 40 is included in the layer above the conductive layer 24, and the lower end of the core member 40 reaches the conductive layer 21. The semiconductor layer 41 covers the periphery of the core member 40. At the bottom of the memory pillar MP, a portion of the semiconductor layer 41 is in contact with the conductive layer 21. The laminated film 42 covers the sides and bottom of the semiconductor layer 41, except for the portion where the semiconductor layer 41 and the conductive layer 21 are in contact. The core member 40 is made of an insulating material such as silicon oxide. The semiconductor layer 41 contains, for example, silicon.

[0046] A columnar contact CV is provided on the semiconductor layer 41 within the memory pillar MP. In the illustrated region, two contact CVs corresponding to two of the six memory pillar MPs are shown. In the memory region MA, contact CVs are connected in an area not shown to memory pillar MPs that do not overlap with the slit SHE and to which no contact CVs are connected.

[0047] One conductive layer 25, i.e., one bit line BL, is in contact with contact CV. One contact CV is connected to each of the spaces separated by slits SLT and SHE in one conductive layer 25. In other words, each conductive layer 25 is electrically connected to a memory pillar MP located between adjacent slits SLT and SHE, and to a memory pillar MP located between two adjacent slits SHE.

[0048] The slit SLT has a portion provided, for example, along the XZ plane, and divides the conductive layers 22-24. The contact LI within the slit SLT is provided along the slit SLT. A portion of the upper end of the contact LI is in contact with the insulating layer 34. The lower end of the contact LI is in contact with the conductive layer 21. The contact LI is used, for example, as part of the source wire SL. At least a spacer SP is provided between the contact LI and the conductive layers 22-24. The contact LI and the conductive layers 22-24 are separated and insulated by the spacer SP.

[0049] The slit SHE has a portion that is provided along the XZ plane, for example, and divides at least the conductive layer 24. The upper end of the slit SHE is in contact with the insulating layer 34. The lower end of the slit SHE is in contact with the insulating layer 33. The slit SHE contains an insulator, for example, silicon oxide. The upper end of the slit SHE and the upper end of the slit SLT may or may not be aligned. Also, the upper end of the slit SHE and the upper end of the memory pillar MP may or may not be aligned.

[0050] Figure 6 shows an example of the cross-sectional structure of the memory region MA of the memory cell array 10 according to the first embodiment. Figure 6 is an enlarged view of region VI in Figure 5. Specifically, Figure 6 shows the structures of the memory pillar MP and the conductive layer 23 at the point where the conductive layer 23 and the memory pillar MP intersect. The laminated film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a cover insulating film 45. The conductive layer 23 includes, for example, a conductor 50 and a barrier metal 51. The memory cell array 10 further includes a block insulating film 46.

[0051] The tunnel insulating film 43 is provided on the side surface of the semiconductor layer 41. The insulating film 44 is provided on the side surface of the tunnel insulating film 43. The cover insulating film 45 is provided on the side surface of the insulating film 44. The cover insulating film 45 is divided by a block insulating film 46 at the point where the memory pillar MP and the conductive layer 23 intersect. The block insulating film 46 is provided between the conductive layer 23 and the insulator layer 32, and between the conductive layer 23 and the insulating film 44. The conductor 50 is embedded in a space enclosed on three sides by the block insulating film 46. The conductor 50 and the block insulating film 46 are separated by a barrier metal 51.

[0052] As the tunnel insulating film 43, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride film are used. The cover insulating film 45 contains, for example, silicon oxide.

[0053] The insulating film 44 contains, for example, silicon nitride. The block insulating film 46 contains, for example, aluminum oxide (Al2O3). The block insulating film 46 is also used as a seed layer for forming the conductor 50. The conductor 50 contains molybdenum (Mo). The conductor 50 may contain impurities. Examples of impurities that may be contained in the conductor 50 include oxygen (O) and hydrogen (H). The barrier metal 51 contains, for example, titanium nitride (TiN).

[0054] The barrier metal 51 may be omitted. The block insulating film 46 may be provided on the side portion of the memory pillar MP instead of the cover insulating film 45. The structure of the conductive layer 22 and the memory pillar MP at the point where the conductive layer 22 and the memory pillar MP intersect, and the structure of the conductive layer 24 and the memory pillar MP at the point where the conductive layer 24 and the memory pillar MP intersect, are the same as the structure of the conductive layer 23 and the memory pillar MP at the point where the conductive layer 23 and the memory pillar MP intersect.

[0055] Figure 7 is a diagram showing an example of the cross-sectional structure of a memory pillar according to the first embodiment. Figure 7 is a cross-sectional view along the line VII-VII in Figure 5. Specifically, Figure 7 shows the cross-sectional structure of the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. In the cross-section including the conductive layer 23, the core member 40 is provided in the center of the memory pillar MP. The semiconductor layer 41 surrounds the side surface of the core member 40. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 46 surrounds the side surface of the insulating film 44. The barrier metal 51 surrounds the side surface of the block insulating film 46. The conductive layer 23 surrounds the side surface of the barrier metal 51.

[0056] The structure of the conductive layer 22 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 22, and the structure of the conductive layer 24 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 24, are the same as the structure of the conductive layer 23 and the memory pillar MP in a cross-section parallel to the surface of the semiconductor substrate 20 and including the conductive layer 23. In each of the memory pillar MPs described above, the semiconductor layer 41 is used as a channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The insulating film 44 is used as a charge storage layer for the memory cell transistor MT. The semiconductor device 1 can conduct current through the memory pillar MP between the bit line BL and the contact LI by turning on the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2.

[0057] Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described.

[0058] Figures 8 to 15 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment.

[0059] As shown in Figure 8, a CMOS (Complementary Metal Oxide Semiconductor) circuit (not shown) corresponding to a low decoder module 15, etc., is formed on the semiconductor substrate 20, and an insulating layer 30 covering the CMOS circuit is further formed. Note that the CMOS circuit may be formed on another semiconductor substrate (not shown). In this case, after forming a memory region MA on the semiconductor substrate 20, the semiconductor substrate of the CMOS circuit can be bonded to the semiconductor substrate of the memory region MA.

[0060] Next, a conductive layer 21 is formed on the insulating layer 30. An insulating layer 31 and a sacrificial member 60 are formed sequentially on the conductive layer 21. Sacrificial members 61 and insulating layers 32 are alternately stacked on top of the sacrificial member 60. An insulating layer 33 and a sacrificial member 62 are formed sequentially on top of the uppermost sacrificial member 61. An insulating layer 35 is formed on top of the sacrificial member 62. Sacrificial member 60 is associated with the selected gate line SGS. Sacrificial member 61 is associated with the word line WL. Sacrificial member 62 is associated with the selected gate line SGD. Each of the sacrificial members 60, 61, and 62 is, for example, a material containing nitrogen and silicon (e.g., silicon nitride). Insulating layers 30-33 and 35 are, for example, a material containing oxygen and silicon (e.g., silicon oxide film).

[0061] Next, as shown in Figure 9, memory holes MH are formed. Specifically, a mask (not shown) is formed with openings in areas corresponding to multiple memory pillars MP. Multiple memory holes MH are formed by anisotropic etching using this mask. The memory holes MH penetrate the insulating layers 31, 32, 33 and 35, as well as the sacrificial members 60, 61 and 62. The bottom of the memory holes MH reaches the conductive layer 21.

[0062] Next, as shown in Figure 10, memory pillars MP are formed. Specifically, a cover insulating film 45, an insulating film 44, and a tunnel insulating film 43 are formed sequentially on the side and bottom surfaces of multiple memory holes MH. This forms a laminated film of the cover insulating film 45, insulating film 44, and tunnel insulating film 43. A portion of the cover insulating film 45, insulating film 44, and tunnel insulating film 43 provided at the bottom of the memory hole MH is removed, and a semiconductor layer 41 and a core member 40 are formed inside the memory hole MH. Then, a portion of the core member 40 provided at the top of the memory hole is removed, and a semiconductor layer 41 is formed in the portion of the core member 40 from which the core member 40 was removed. This forms the structure of multiple memory pillars MP. Subsequently, an insulating layer 36 is formed on the insulating layer 35 and the multiple memory pillars MP. The insulating layer 36 protects the top of the memory pillars MP. The insulating layers 35 and 36 are included in the insulating layer 34 shown in Figure 5.

[0063] Next, as shown in Figure 11, slit SLTs are formed. Specifically, a mask with openings corresponding to the slit SLTs is formed by photolithography or the like. Then, anisotropic etching using this mask forms slit SLTs that separate the insulating layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62, respectively. The bottom of the slit SLTs reaches, for example, the conductive layer 21. After the formation of the slit SLTs, a process may be performed to form a protective film on the conductive layer 21 exposed at the bottom of the slit SLTs.

[0064] Next, as shown in Figure 12, the sacrificial members 60, 61, and 62 are removed. Specifically, a wet etching process using thermal phosphoric acid or the like is performed. More specifically, the sacrificial members 60, 61, and 62 are selectively removed by supplying thermal phosphoric acid or the like through the slit SLT. Although not shown in the figure, the cover insulating film 45 that was provided on the part of each memory pillar MP that was in contact with any of the sacrificial members 60, 61, and 62 is also removed. The structure from which the sacrificial members 60, 61, and 62 have been removed is supported by multiple memory pillars MP, etc.

[0065] Next, as shown in Figure 13, the conductor 50 is formed. Specifically, the block insulating film 46 and barrier metal 51 shown in Figure 6 are formed in sequence. For the formation of the block insulating film 46, for example, the thermal CVD (Chemical Vapor Deposition) method or the ALD (Atomic Layer Deposition) method is used. The conductor 50 is embedded in the space where the sacrificial members 60-62 have been removed. For the formation of the conductor 50, for example, the thermal CVD method or the ALD method is used. Note that the block insulating film 46, barrier metal 51, and conductor 50 are also formed on the side portions of the slit SLT and on the upper surface portion of the insulating layer 36. At this point, the conductor 50 formed in the space where the sacrificial members 60-62 have been removed is continuously provided and electrically connected.

[0066] Next, as shown in Figure 14, the conductor 50 is etched. Specifically, the conductor 50 formed on the side surface of the slit SLT and the conductor 50 formed on the upper surface of the insulating layer 36 are removed using a wet etching method. It is sufficient that the conductor 50 formed on adjacent wiring layers in the Z direction is separated. As a result, a conductor layer 22 that functions as a select gate line SGS, multiple conductor layers 23 that function as word lines WL0 to WL7 respectively, and a conductor layer 24 that functions as a select gate line SGD are formed.

[0067] Next, as shown in Figure 15, the slit SLT is filled. Specifically, an insulating film (spacer SP) is formed to cover the sides and bottom of the slit SLT. A portion of the spacer SP provided at the bottom of the slit SLT is removed, and a portion of the conductive layer 21 is exposed at the bottom of the slit SLT. A conductor (contact LI) is formed inside the slit SLT, and the conductor formed outside the slit SLT is removed, for example, by CMP (Chemical Mechanical Polishing). Subsequently, multiple grooves parallel to the slit SLT are formed between adjacent slit SLTs in the Y direction, and insulating film is embedded in each groove, thereby forming the slit SHE shown in Figure 5, which divides the conductive layer 24 in the Y direction.

[0068] The stacked wiring structure within the memory cell array 10 is formed by the manufacturing process described above. The series of processes for replacing the sacrificial members 60, 61, and 62 with conductive layers 22, 23, and 24 may be called the “replacement process.” It should be noted that the manufacturing process described above is merely an example and is not limited thereto. For example, other processes may be inserted between each manufacturing process, or some processes may be omitted or integrated. For example, a process for forming the stepped structure of the stacked wiring may be inserted between the processes shown in Figures 8 and 9.

[0069] Here, we will explain in more detail the process for forming the memory holes MH shown in Figure 9.

[0070] Figures 16 to 19 are cross-sectional views showing an example of the memory hole formation process according to the first embodiment.

[0071] The memory hole MH shown in Figure 9 is formed in a structure constructed by stacking sacrificial members 60, 61, 62 and insulating layers 31, 32, 33, 35 shown in Figure 8, using lithography and dry etching techniques such as RIE (Reactive Ion Etching). The memory hole MH is formed to extend and penetrate through this structure in the Z direction. The lower end of the memory hole MH reaches the conductive layer 21.

[0072] In this case, the diameter of the memory hole MH is narrower at the bottom and widens towards the top. Furthermore, the diameter of the memory hole MH is slightly narrower near the opening. The difference between the upper and lower diameters of the memory hole MH is more pronounced when the aspect ratio of the memory hole MH is high (e.g., 100 or more). The upper opening diameter of the memory hole MH is, for example, 110 nm to 120 nm, and its depth is, for example, 14 μm. In such a case, the difference between the upper and lower diameters of the memory hole MH becomes significantly large. A large difference between the upper and lower diameters of the memory hole MH can cause device failure. This tapering shape of the memory hole MH is thought to be caused by the loading effect during the etching process.

[0073] Therefore, in this embodiment, in order to reduce the difference between the upper diameter and the lower diameter of such a memory hole MH, the following wet etching process (recess process) is performed.

[0074] As shown in Figure 16, the structure is etched from within the memory hole MH using an etching solution for the recess process. This etching solution contains an acid ECH that functions as an etchant and a polymer PLM that protects the structure from the acid ECH. In this embodiment, the pH of the acid ECH is less than 5, and the polymer PLM is an anionic polymer. Examples of acid ECH include hydrofluoric acid (HF), hydrochloric acid (HCl), nitric acid (HNO3), sulfuric acid (H2SO4), hydrogen peroxide (H2O2), and ammonium fluoride (NH4F). Examples of hydrofluoric acid include dilute hydrofluoric acid (DHF) and buffered hydrofluoric acid (BHF). The polymer PLM is, for example, an organic polymer having a sulfo group or a carboxyl group. Examples of polymer PLM include sulfonic acid, acrylic acid, sulfonate, and acrylate, specifically polystyrene sulfonic acid, polyvinyl sulfonic acid, polyacrylic acid, polystyrene sulfonate, polyvinyl sulfonate, or polyacrylate. Other examples of polymer PLMs include sulfonated polyethersulfones, acrylic acid / maleic acid copolymers (or their salts), and acrylic acid / sulfonic acid monomer copolymers (or their salts).

[0075] The etching solution of this embodiment is produced, for example, by adding polystyrene sulfonic acid (PSS) as polymer PLM to dilute hydrofluoric acid (DHF) as acid ECH. The pH of the dilute hydrofluoric acid is, for example, about 3. Acid ECH may be a mixed acid containing dilute hydrofluoric acid, and the additive to acid ECH may be something other than polystyrene sulfonic acid. For example, the molecular weight of the polystyrene sulfonic acid (PSS molecular weight) is 50,000 or more (preferably 100,000 or more), and the concentration of the additive is adjusted to within the range of 1 wt% to 15 wt%. In the recess process using this etching solution, the acid ECH quickly reaches the bottom of the memory hole MH while the added polymer PLM protects the upper surface of the memory hole MH. The molecular weight of polymer PLM is large, 50,000 or more, and its diffusion is slower than that of acid ECH. Therefore, while polymer PLM coats the upper part of memory holes MH with an aspect ratio of 100 or more, it takes time for it to reach the lower part of the memory holes MH. On the other hand, acid ECH, as an etchant, diffuses faster than polymer PLM and quickly reaches the lower part of the memory holes MH. Thus, acid ECH etches the inner wall of the memory holes MH more at the lower part than at the upper part. As a result, as shown in Figure 17, etching of the upper part of the memory holes MH can be suppressed while etching of the lower part can be promoted.

[0076] Furthermore, as shown in Figures 18 and 19, as the polymer PLM gradually diffuses into the lower part of the memory hole MH, the polymer PLM gradually coats and protects the inner wall of the memory hole MH from top to bottom. As a result, the amount of etching in this recess process increases from the top to the bottom of the memory hole MH.

[0077] In other words, the recess process using the etching solution according to this embodiment acts to reduce the difference between the upper and lower diameters of the memory hole MH (reverse loading effect), thereby mitigating the tapering shape of the memory hole MH. As shown in Figure 19, the bottom opening diameter Wb of the memory hole MH can be made equal to or greater than the upper opening diameter Wt. As a result, the yield and reliability of the device can be improved.

[0078] Note that in Figure 19, for convenience, the inner wall of the memory hole MH is shown to have a step from the top to the bottom, but in reality, it is smooth.

[0079] The smaller the molecular weight of polymer PLM, the faster it diffuses to the bottom of the memory hole MH. In this case, the reverse loading effect becomes smaller, and it becomes impossible to adequately correct the tapered shape of the memory hole MH. Therefore, a large molecular weight of polymer PLM is preferable. For example, Figure 20 shows experimental results when polymer PLM is polyethyleneimine (PEI). According to Figure 20, the molecular weight of this polyethyleneimine (PEI molecular weight) is preferably 600 or more, more preferably 10,000 or more, and even more preferably 70,000 or more. A similar trend is expected to hold true for PSS molecular weight and the like.

[0080] Furthermore, whether or not polymer PLM is present in the etching solution can be determined by analysis using infrared spectroscopy (FT-IR) and nuclear magnetic resonance (NMR). The weight-average molecular weight of polymer PLM contained in the etching solution can be determined by gel permeation chromatography (GPC).

[0081] Figure 20 is a graph showing the relationship between the molecular weight of PEI and the reverse loading effect. The vertical axis represents the ratio of the etching amount at the bottom of the memory hole MH to the etching amount at the top (top etching amount / bottom etching amount). The horizontal axis represents the molecular weight of PEI. The etching amount ratio can be derived, for example, by performing the manufacturing method of the first embodiment under conditions where the etching rates for the insulating layer 33 and the insulating layer 32 are different, and determining the ratio of the step size resulting from the difference in etching rates between the insulating layer 33 and the insulating layer 32.

[0082] Referring to this graph, when the molecular weight of PEI exceeds 600, the etching amount ratio decreases significantly, and when the molecular weight of PEI exceeds a predetermined value of 10,000 to 70,000, the etching amount ratio becomes 1 or less. In other words, the etching amount at the bottom of the memory hole MH becomes greater than the etching amount at the top due to the reverse loading effect. Therefore, the molecular weight of PEI is preferably 600 or more, more preferably 10,000 or more, and even more preferably 70,000 or more.

[0083] As described above, the memory holes MH in this embodiment are formed by a two-stage etching process consisting of dry etching and wet etching. Dry etching is performed, for example, by RIE. Subsequent wet etching is performed, for example, using an etching solution as described above.

[0084] Experiments have shown that when etching a structure from a memory hole MH using an etching solution, the zeta potential of the inner wall of the memory hole MH during etching becomes negative when the pH of the acid ECH is greater than 5, and positive when the pH of the acid ECH is less than 5. For example, the zeta potential of the sides of insulating layers 32 (e.g., silicon oxide film) and sacrificial members 61 (e.g., silicon nitride film) shown in Figures 16 to 19 becomes negative when the pH of the acid ECH is greater than 5, and positive when the pH of the acid ECH is less than 5. Therefore, in this embodiment, an anionic polymer is used as the polymer PLM. Anionic polymers are polymers that are negatively charged in water, and cationic polymers are polymers that are positively charged in water. According to this embodiment, by using an anionic polymer as the polymer PLM, it is possible to make the polymer PLM act as an inhibitor of acid ECH with a pH less than 5. In other words, when the pH of the acid ECH is less than 5, the etching of the inner wall of the memory hole MH can be effectively suppressed by the polymer PLM.

[0085] (Variation 1) The above recess process can be applied to the slit SLT formation process shown in Figure 11. That is, the slit SLT is formed in the structure of the memory region MA so as to reach the conductive layer 21 using lithography and dry etching techniques such as the RIE method. The slit SLT is formed so as to divide the structures of the insulating layers 31, 32, 33, 35 and 36, and the sacrificial members 60, 61 and 62. At this time, in a cross-section parallel to the YZ plane, the difference between the diameter of the upper part and the diameter of the lower part of the slit SLT is large due to the loading effect, resulting in a tapered shape.

[0086] Next, in the recessing process, the slit SLT is etched using an etching solution containing the acid ECH and polymer PLM. This reduces the difference between the upper and lower diameters of the slit SLT (reverse loading effect), thereby mitigating the tapered shape of the slit SLT.

[0087] Thus, the recessing process according to this embodiment can also be applied to the slit SLT formation process.

[0088] (Modification 2) Figures 21 and 22 are perspective views showing an example of the configuration of a drawout region according to a modified example 2 of the first embodiment. Figures 21 and 22 show schematics of drawout regions HA1 and HA2 of a certain block BLK. The stepped sections SSA of the drawout regions HA1 and HA2 are provided at both ends in the X direction of the memory region MA in Figure 3. The stepped sections SSA are configured so that each conductive layer 23 (word line WL) is exposed from the memory region MA when viewed from the Z direction of the stacking direction. The stepped sections SSA are covered with an interlayer insulating film such as a silicon oxide film, although this is not shown.

[0089] In the stepped section SSA, as shown in Figure 22, multiple conductive layers 23 (word lines WL) are arranged in a stepped pattern. The contact plug CC extends in the Z direction within the interlayer insulating film and is connected to each of the multiple conductive layers 23 (word lines WL). For example, a conductive metal material such as tungsten is used for the contact plug CC.

[0090] The contact plug CC is electrically connected to a CMOS such as a row decoder located beneath the memory cell array 10 via upper layer wiring (not shown) and other contact plugs. This allows the row decoder to control the voltage of each conductive layer 23 (word line WL) via the contact plug CC.

[0091] The recess process described above can also be applied to the formation of such contact plugs CC. Specifically, the X-direction ends of the structures of the insulating layers 31, 32, 33, 35, and 36, and the sacrificial members 60, 61, and 62 are processed in a stepped manner, and then a replacement process is performed. The structures are covered with an interlayer insulating film (not shown). After the replacement process, contact holes CH are formed in the interlayer insulating film using lithography and dry etching techniques such as the RIE method, so that they reach each conductive layer 23. At this time, due to the loading effect, the difference between the diameter of the upper and lower parts of the contact holes CH is large, resulting in a tapered shape.

[0092] Next, in the recessing process, the contact hole CH is etched using an etching solution containing the acid ECH and polymer PLM. This reduces the difference between the upper and lower diameters of the contact hole CH (reverse loading effect), thereby mitigating the tapered shape of the contact hole CH.

[0093] Thus, the recess process according to this embodiment can also be applied to the contact plug CC formation process.

[0094] The recessing process according to this embodiment is not limited to the above process, but can be applied to processes for forming holes or slits with a high aspect ratio.

[0095] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel methods described herein can be carried out in a variety of other forms. Furthermore, various omissions, substitutions, and modifications can be made to the forms of the methods described herein, without departing from the spirit of the invention. The appended claims and equivalents are intended to include such forms and modifications that fall within the scope and spirit of the invention. [Explanation of Symbols]

[0096] 1: Semiconductor device, 2: Memory controller, 10: Memory cell array, 11: Command register, 12: Address register, 13: Sequencer, 14: Driver module, 15: Raw decoder module, 16: Sense amplifier module, 20: Semiconductor substrate, 21: Conductive layer, 22: Conductive layer, 23: Conductive layer, 24: Conductive layer, 25: Conductive layer, 30: Insulator layer, 31: Insulator layer, 32: Insulator layer, 33: Insulating layer, 34: Insulating layer, 35: Insulating layer, 36: Insulating layer, 40: Core component, 41: Semiconductor layer, 42: Multilayer film, 43: Tunnel insulating film, 44: Insulating film, 45: Cover insulating film, 46: Block insulating film, 50: Conductor, 51: Barrier metal, 60: Sacrificial member, 61: Sacrificial member, 62: Sacrificial member

Claims

1. This includes etching the structure with an etching solution containing an acid and a polymer from within a hole or slit provided in the structure, The pH of the acid is less than 5. The polymer is an anionic polymer. Etching method.

2. The etching method according to claim 1, wherein the polymer is an organic polymer.

3. The etching method according to claim 1, wherein the polymer has a sulfo group or a carboxyl group.

4. The etching method according to claim 1, wherein the polymer is a sulfonic acid, an acrylic acid, a sulfonate, or an acrylicate.

5. The etching method according to claim 1, wherein the polymer is polystyrene sulfonic acid, polyvinyl sulfonic acid, polyacrylic acid, polystyrene sulfonate, polyvinyl sulfonate, or polyacrylicate.

6. The etching method according to claim 1, wherein the molecular weight of the polymer is 50,000 or more.

7. The etching method according to claim 1, wherein the acid is hydrofluoric acid, hydrochloric acid, nitric acid, sulfuric acid, hydrogen peroxide, or ammonium fluoride.

8. The etching method according to claim 1, wherein the aspect ratio of the structure is 100 or more.

9. The etching method according to claim 1, wherein the structure is a laminate in which sacrificial members and insulating layers are alternately stacked in a first direction.

10. This includes etching the structure with an etching solution containing an acid and a polymer from within a hole or slit provided in the structure, The pH of the acid is less than 5. The polymer is an anionic polymer. A method for manufacturing a semiconductor device.

11. The manufacturing method according to claim 10, wherein the polymer is an organic polymer.

12. The method for manufacturing a semiconductor device according to claim 10, wherein the polymer has a sulfo group or a carboxyl group.

13. The method for manufacturing a semiconductor device according to claim 10, wherein the polymer is a sulfonic acid, an acrylic acid, a sulfonate, or an acrylicate.

14. The method for manufacturing a semiconductor device according to claim 10, wherein the polymer is polystyrene sulfonic acid, polyvinyl sulfonic acid, polyacrylic acid, polystyrene sulfonate, polyvinyl sulfonate, or polyacrylicate.

15. The method for manufacturing a semiconductor device according to claim 10, wherein the molecular weight of the polymer is 50,000 or more.

16. The method for manufacturing a semiconductor device according to claim 10, wherein the acid is hydrofluoric acid, hydrochloric acid, nitric acid, sulfuric acid, hydrogen peroxide, or ammonium fluoride.

17. The method for manufacturing a semiconductor device according to claim 10, wherein the aspect ratio of the structure is 100 or more.

18. The sacrificial member and the insulating layer are alternately stacked in the first direction to form the structure. A hole extending in the first direction is formed within the structure. The structure is etched from inside the hole using the etching solution, A columnar body including a laminated film and a semiconductor layer is formed in the aforementioned hole. Remove the aforementioned sacrificial member, The method for manufacturing a semiconductor device according to claim 10, further comprising: after removing the sacrificial member, filling the space where the sacrificial member was removed with a conductive material to form a conductive layer between adjacent insulating layers in the first direction.

19. After the formation of the columnar body, A slit is formed to divide the aforementioned structure, The method further comprises etching the structure from within the slit using the etching solution, The sacrificial member is etched away through the slit, The method for manufacturing a semiconductor device according to claim 18, wherein the conductive material is embedded in the space through the slit.

20. The end of the aforementioned structure is processed into a stepped shape, An interlayer insulating film is formed on the above structure, The interlayer insulating film is extended in the first direction to form contact holes that reach each conductive layer. The structure is etched from within the contact hole using the etching solution. The method for manufacturing a semiconductor device according to claim 19, further comprising forming a conductive material in the contact hole and forming a contact plug that is electrically connected to each conductive layer.

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