Semiconductor equipment

Abstract

Reduces the occurrence of delamination of the sealing material. [Solution] The semiconductor device includes a control terminal 25b including a joint 25b2 having an upper surface 25b3, a lower surface 25b5, and an end surface 25b4; a terminal block 21h having a wall surface 21h2 on which the joint 25b2 protrudes and the end surface 25b4 is exposed, and on which the upper surface 25b3 of the joint 25b2 is exposed; and an adhesive film applied to the upper surface 25b3, the end surface 25b4, and the lower surface 25b5 of the protruding portion of the joint 25b2 of the control terminal 25bb, as well as the wall surface 21h2 of the terminal block 21h and the terminal surface of the terminal block 21h. Furthermore, the wall surface 21h2 of the terminal block 21h includes a first region 21h4 whose upper end is in contact with the lower surface 25b5 and a second region 21h5 excluding the first region 21h4. The lower surface 25b5 of the joint 25h2 is perpendicular to the extension plane that extends from the lower surface 25b5 of the second region 21h5, and the first region 21h4 is inclined at an obtuse angle with respect to the second region 21h5.

Description

Technical Field

[0004] , , , , , , ,

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] A semiconductor device includes a semiconductor chip and a case in which the semiconductor chip is housed and external connection terminals are integrally formed. Inside the case, the semiconductor chip and the external connection terminals are electrically connected by wires, and these are sealed by a sealing member (see, for example, Patent Documents 1 to 8). At this time, by covering the inside of the case, the adhesion between the inside of the case and the sealing member is improved (see, for example, Patent Documents 7 and 8).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present invention is to provide a semiconductor device in which the occurrence of peeling of the sealing member is reduced.

Means for Solving the Problems

[0005] According to one aspect of the present invention, a semiconductor device is provided that includes a terminal including a joint having an upper surface, a lower surface, and an end surface; a terminal block having a wall surface from which the joint protrudes and the end surface is exposed, and from which the upper surface of the joint is exposed; and an adhesive member applied to the upper surface of the terminal block and the upper surface of the terminal block, together with the upper surface of the terminal, the end surface, and the lower surface of the protruding portion of the joint, wherein the wall surface of the terminal block comprises a first region whose upper end contacts the lower surface and a second region excluding the first region, the lower surface of the joint is perpendicular to an extension plane that extends from the lower surface of the second region, and the first region is inclined at an obtuse angle with respect to the second region.

[0006] Furthermore, the terminal block may include a projection that protrudes from the wall surface toward the end face of the terminal, with the protruding tip including the first region and contacting the lower surface of the terminal. Furthermore, the joint portion of the terminal may include a burr that extends downward toward the lower surface side relative to the end face, and the burr may overlap the first region of the protruding portion.

[0007] Furthermore, the upper surface of the joint portion of the terminal may include a sag connected to the end face. Furthermore, the device may have a case that is rectangular in shape in plan view and includes an inner wall facing an inner opening region, wherein the terminal block may be provided on the inner wall with the wall surface facing the opening region.

[0008] Furthermore, the adhesive member may further include a filling member that is applied to the inner wall of the case and fills the opening region. It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Effects of the Invention]

[0009] According to the disclosed technology, the occurrence of delamination of the sealing material is reduced.

Brief Description of the Drawings

[0010] [Figure 1] It is a plan view of the semiconductor device of the embodiment. [Figure 2] It is a cross-sectional view of the semiconductor device of the embodiment. [Figure 3] It is a plan view of the semiconductor unit included in the semiconductor device of the embodiment. [Figure 4] It is a side view of the semiconductor unit included in the semiconductor device of the embodiment. [Figure 5] It is a side view of the semiconductor device of the embodiment. [Figure 6] It is a front view of the inner wall of the case included in the semiconductor device of the embodiment. [Figure 7] It is a cross-sectional view (Part 1) of the control terminal of the semiconductor device of the embodiment. [Figure 8] It is a cross-sectional view (Part 2) of the control terminal of the semiconductor device of the embodiment. [Figure 9] It is a flowchart of the manufacturing method of the semiconductor device of the embodiment. [Figure 10] It is a front view of the control terminal included in the inner wall of the case of the embodiment. [Figure 11] It is a plan view of the control terminal included in the case of the embodiment. [Figure 12] It is a cross-sectional view of the control terminal included in the case of the embodiment. [Figure 13] It is a cross-sectional view for explaining the dicing of the manufacturing method of the semiconductor device of the embodiment. [Figure 14] It is a cross-sectional view for explaining the adhesive application process of the manufacturing method of the semiconductor device of the embodiment. [Figure 15] It is a cross-sectional view of the control terminal included in the case of the reference example. [Figure 16] It is a cross-sectional view for explaining the adhesive application process of the manufacturing method of the semiconductor device of the reference example.

Embodiments of the Invention

[0011] The embodiments will be described below with reference to the drawings. In the following description, "front surface" and "top surface" refer to the XY plane facing upwards (+Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. Similarly, "up" refers to the upward direction (+Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. "Back surface" and "bottom surface" refer to the XY plane facing downwards (-Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. Similarly, "down" refers to the downward direction (-Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. The same directionality will be used in other drawings as needed. "High position" and "upper position" refer to the upper position (+Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. Similarly, "low position" and "lower position" refer to the lower position (-Z direction) in the semiconductor device 1 of Figures 1, 2, and 5. The terms "front surface," "top surface," "top" and "back surface," "bottom surface," "bottom" and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "top" and "bottom" are not limited to the direction of gravity. Also, in the following explanation, "main component" refers to a case where it contains 80 vol% or more. Also, "approximately the same" means that it is within a range of ±10%. Also, "perpendicular," "orthogonal," and "parallel" mean that it is within a range of ±10°.

[0012] The semiconductor device 1 of the embodiment will be described using Figures 1 to 5. Figure 1 is a plan view of the semiconductor device of the embodiment. Figure 2 is a cross-sectional view of the semiconductor device of the embodiment. Figure 3 is a plan view of a semiconductor unit included in the semiconductor device of the embodiment. Figure 4 is a side view of a semiconductor unit included in the semiconductor device of the embodiment. Figure 5 is a side view of the semiconductor device of the embodiment.

[0013] Figure 2 is a cross-sectional view along the dashed line II in Figure 1. Figure 4 is a side view (XZ plane) of the semiconductor unit 10 in Figure 3, viewed in the +Y direction. Figure 5 is a side view (XZ plane) of the semiconductor device 1 in Figure 1, viewed in the +Y direction.

[0014] The semiconductor device 1 includes a semiconductor module 2 and a cooling module 3. The semiconductor module 2 also includes semiconductor units 10a, 10b, and 10c and a case 20 that houses the semiconductor units 10a, 10b, and 10c. The semiconductor units 10a, 10b, and 10c housed in the case 20 are sealed by a sealing member 29 (see Figure 2).

[0015] The semiconductor units 10a, 10b, and 10c all have the same configuration. Unless otherwise specified, the semiconductor units 10a, 10b, and 10c will be described simply as semiconductor unit 10. Details of semiconductor unit 10 will be described later.

[0016] Case 20 includes a frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, W-phase output terminal 24a, V-phase output terminal 24b, U-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0017] The frame portion 21 is roughly rectangular in plan view and includes outer walls 21a, 21b, 21c, 21d that surround it on all four sides in order, and inner walls 21a1, 21b1, 21c1, 21d1 that are opposite to the outer walls 21a, 21b, 21c, 21d, respectively. Furthermore, the frame portion 21 includes an upper surface 21f and a lower surface 21g that are connected to the outer walls 21a, 21b, 21c, 21d and the inner walls 21a1, 21b1, 21c1, 21d1. In addition, the outer walls 21a, 21c and the inner walls 21a1, 21c1 extend in the longitudinal direction corresponding to the long sides of the frame portion 21. The outer walls 21b, 21d and the inner walls 21b1, 21d1 extend in the short direction corresponding to the short sides of the frame portion 21. Furthermore, the connection points of the outer walls 21a, 21b, 21c, and 21d, as well as the corners of the connection points of the inner walls 21a1, 21b1, 21c1, and 21d1, do not necessarily have to be right angles, and may be rounded off as shown in Figure 1. Fastening holes 21i that penetrate the frame 21 in the ±Z direction may be formed at the corners of the upper surface 21f and lower surface 21g of the frame 21.

[0018] The frame portion 21 contains an opening 21e inside, which is surrounded on all four sides in order by inner walls 21a1, 21b1, 21c1, and 21d1. In plan view, the opening 21e is rectangular and is defined by the inner walls 21a1, 21b1, 21c1, and 21d1 (inner surfaces). The opening 21e opens from the upper surface 21f to the lower surface 21g of the frame portion 21.

[0019] The frame portion 21 further includes unit housing portions 21e1, 21e2, and 21e3 within the opening 21e, which are the housing areas for semiconductor units 10a, 10b, and 10c. The unit housing portions 21e1, 21e2, and 21e3 are provided sequentially along the outer walls 21a, 21c and inner walls 21a1, 21c1 of the opening 21e, which is divided into three sections in a plan view. A step may be provided in the inner wall 21c1 on the outer wall 21c side of the unit housing portions 21e1, 21e2, and 21e3. Details of the inner wall 21c1 will be described later.

[0020] The semiconductor units 10a, 10b, and 10c are each joined to the cooling surface 3a of the cooling module 3 by joining members 14a. When the frame 21 is attached to the cooling surface 3a of the cooling module 3, the semiconductor units 10a, 10b, and 10c are housed in the unit housing sections 21e1, 21e2, and 21e3 of the frame 21, respectively. The frame 21 may also be bonded to the cooling surface 3a of the cooling module 3 with an adhesive (not shown).

[0021] In plan view, the frame portion 21 is provided with positive first connection terminals 22a, 22b, 22c and negative second connection terminals 23a, 23b, 23c on the outer wall 21a side. The first connection terminals 22a, 22b, 22c include external connection portions 22a1, 22b1, 22c1 on one side and joint portions 22a2, 22b2, 22c2 on the other side. Similarly, the second connection terminals 23a, 23b, 23c include external connection portions 23a1, 23b1, 23c1 on one side and joint portions 23a2, 23b2, 23c2 on the other side.

[0022] One external connection part 22a1, 22b1, 22c1 and the other external connection parts 23a1, 23b1, 23c1 are located on the upper surface 21f of the outer wall 21a. These connection parts (not shown in numerals) may have openings. Nuts may be housed on the upper surface 21f of the frame part 21 where the connection parts are located, facing the openings of the connection parts.

[0023] The other joints 22a2, 22b2, 22c2 and 23a2, 23b2, 23c2 extend into the unit housing sections 21e1, 21e2, 21e3 and are electrically connected to the semiconductor units 10a, 10b, 10c.

[0024] Furthermore, a portion of the intermediate parts between the connection and joint portions of the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c is included within the frame portion 21, while the remainder is exposed in the unit housing portions 21e1, 21e2, 21e3 of the frame portion 21. The first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c may have similar configurations.

[0025] In a plan view, the frame portion 21 is provided with W-phase output terminals 24a, V-phase output terminals 24b, and U-phase output terminals 24c on the outer wall 21c side. The W-phase output terminals 24a, V-phase output terminals 24b, and U-phase output terminals 24c are provided with external connection portions 24a1, 24b1, and 24c1 on one end and joint portions 24a2, 24b2, and 24c2 on the other end.

[0026] One of the external connection parts 24a1, 24b1, and 24c1 is located on the upper surface 21f of the outer wall 21c. These connection parts may have openings. On the upper surface 21f of the frame part 21 on which these connection parts are located, nuts may be housed opposite the openings of the connection parts.

[0027] The other joints 24a2, 24b2, and 24c2 extend into the unit housing sections 21e1, 21e2, and 21e3 and are electrically connected to the semiconductor units 10a, 10b, and 10c. A portion of the intermediate part between the connection and joint between the W-phase output terminal 24a, the V-phase output terminal 24b, and the U-phase output terminal 24c is included within the frame section 21, and the remainder of this intermediate portion is exposed to the unit housing sections 21e1, 21e2, and 21e3 of the frame section 21. The W-phase output terminal 24a, the V-phase output terminal 24b, and the U-phase output terminal 24c may have similar configurations.

[0028] Therefore, in a plan view, the frame portion 21 includes a first connection terminal 22a and a second connection terminal 23a on the outer wall 21a side, and a W-phase output terminal 24a on the outer wall 21c side, flanking the unit housing portion 21e1. Similarly, in a plan view, the frame portion 21 includes a first connection terminal 22b and a second connection terminal 23b on the outer wall 21a side, flanking the unit housing portion 21e2, and a V-phase output terminal 24b on the outer wall 21c side. Similarly, in a plan view, the frame portion 21 includes a first connection terminal 22c and a second connection terminal 23c on the outer wall 21a side, flanking the unit housing portion 21e3, and a U-phase output terminal 24c on the outer wall 21c side.

[0029] The control terminals 25a, 25b, and 25c are provided on the upper surface 21f of the outer wall 21c, along the outer wall 21c, for each unit housing section 21e1, 21e2, and 21e3. One end of each control terminal 25a, 25b, and 25c extends from the upper surface 21f in the +Z direction. The other end (joint) is exposed to the unit housing sections 21e1, 21e2, and 21e3 from a step in the inner wall 21c1. The other end is electrically connected to the control electrodes of the semiconductor chips 12a and 12b, which will be described later, for example, via a wire 26. The wire 26 is mainly composed of a material with excellent conductivity. Such a material is, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the wire 26 may be an aluminum alloy containing a small amount of silicon. Details of the joints of the control terminals 25a, 25b, and 25c will be described later.

[0030] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, the U-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, the U-phase output terminal 24c, and the control terminals 25a, 25b, 25c may be plated. In this case, the plating material used is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0031] Such a frame portion 21 includes first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, W-phase output terminal 24a, V-phase output terminal 24b, U-phase output terminal 24c, and control terminals 25a, 25b, 25c, and is integrally molded by injection molding using a thermoplastic resin. Examples of thermoplastic resins include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0032] The sealing member 29 that seals the unit housing sections 21e1, 21e2, and 21e3 of the frame section 21 may be silicone gel or a thermosetting resin. Examples of thermosetting resins include epoxy resin, phenolic resin, maleimide resin, and polyester resin. The sealing member 29 only needs to be able to seal the entire semiconductor units 10a, 10b, and 10c housed in the unit housing sections 21e1, 21e2, and 21e3, and does not need to seal the entire unit housing sections 21e1, 21e2, and 21e3. It is desirable that the portions of the first connection terminals 22a, 22b, and 22c, the second connection terminals 23a, 23b, and 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, the U-phase output terminal 24c, and the control terminals 25a, 25b, and 25c that are exposed to the unit housing sections 21e1, 21e2, and 21e3 be sealed.

[0033] Furthermore, an adhesive film 28 (see Figure 14) is formed over the entire unit housing sections 21e1, 21e2, and 21e3 of the frame section 21, and a sealing member 29 is filled on top of it. The sealing member 29, filled via the adhesive film 28, is prevented from peeling into the interior of the unit housing sections 21e1, 21e2, and 21e3. The adhesive film 28 may be made of a heat-resistant insulating material, and may contain, for example, polyamide.

[0034] The semiconductor unit 10 may be a device that constitutes a single-phase inverter circuit. Such a semiconductor unit 10 includes an insulating circuit board 11, semiconductor chips 12a and 12b, and lead frames 13a and 13b. The semiconductor chips 12a and 12b are bonded to the insulating circuit board 11 by a bonding member 14b. The lead frames 13a and 13b are bonded to the main electrodes on the upper surfaces of the semiconductor chips 12a and 12b and to the upper surface of the insulating circuit board 11 by a bonding member 14c. In addition, the lead frames 13a and 13b may be bonded to the insulating circuit board 11 by ultrasonic bonding instead of bonding member 14c.

[0035] The insulated circuit board 11 includes an insulating plate 11a, conductive circuit patterns 11b1, 11b2, 11b3, and a metal plate 11c. The insulating plate 11a is rectangular in shape when viewed from above. The corners of the insulating plate 11a may be rounded (R-chamfered) or chamfered (C-chamfered).

[0036] The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. Such an insulating plate 11a may be made of ceramics. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride.

[0037] The insulating board 11a may be made of a resin. The resin may be a material with low thermal resistance and high insulating properties. Examples of such resins include thermosetting resins and thermoplastic resins. Such resins may further contain fillers. Examples of thermosetting resins include at least one of epoxy resins, cyanate resins, benzoxazine resins, unsaturated polyester resins, phenolic resins, melamine resins, silicone resins, and maleimide resins. Examples of thermoplastic resins include at least one of polyimide resins, acrylic resins, and polyamide resins. The filler is made of at least one of oxides and nitrides. Examples of oxides include silicon oxide and aluminum oxide. Examples of nitrides include silicon nitride, aluminum nitride, and boron nitride. Furthermore, hexagonal boron nitride may also be used as the filler.

[0038] The conductive circuit patterns 11b1, 11b2, and 11b3 are examples of conductive plates and are formed on the front surface of the insulating plate 11a. The conductive circuit patterns 11b1, 11b2, and 11b3 are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these. The surfaces of the conductive circuit patterns 11b1, 11b2, and 11b3 may be plated to improve corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0039] The conductive circuit pattern 11b1 occupies half of the +X-direction side of the front surface of the insulating plate 11a, and extends from the -Y-direction side to the +Y-direction side. The area enclosed by the dashed line shown in the conductive circuit pattern 11b1 is where the joints 22a2, 22b2, and 22c2 of the first connection terminals 22a, 22b, and 22c are joined. These may be joined by ultrasonic bonding.

[0040] The conductive circuit pattern 11b2 occupies half of the front surface of the insulating plate 11a in the -X direction. Furthermore, the conductive circuit pattern 11b2 occupies the front surface of the insulating plate 11a from the +Y direction edge to just before the -Y direction edge. The conductive circuit pattern 11b2 is joined to the junctions 24a2, 24b2, and 24c2 of the W-phase output terminal 24a, V-phase output terminal 24b, and U-phase output terminal 24c, respectively. These may be joined by ultrasonic bonding.

[0041] The conductive circuit pattern 11b3 is located on the -Y side of the -X direction edge of the front surface of the insulating plate 11a, on half of the area. That is, the conductive circuit pattern 11b3 occupies the area of ​​the upper surface of the insulating plate 11a excluding the conductive circuit patterns 11b1 and 11b2. The area enclosed by the dashed line shown in the conductive circuit pattern 11b3 is where the joints 23a2, 23b2, and 23c2 of the second connection terminals 23a, 23b, and 23c are joined. These may be joined by ultrasonic bonding.

[0042] The metal plate 11c is formed on the lower surface of the insulating plate 11a. The metal plate 11c is rectangular in shape. The area of ​​the metal plate 11c in plan view is smaller than the area of ​​the insulating plate 11a, and larger than the area of ​​the conductive circuit patterns 11b1, 11b2, and 11b3 formed thereon. The corners of the metal plate 11c may be rounded (R-chamfered) or chamfered (C-chamfered). The metal plate 11c is formed over the entire surface of the insulating plate 11a, excluding the edges. This metal is, for example, copper, aluminum, or an alloy containing at least one of these. The surface of the metal plate 11c may be plated to improve its corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0043] If the insulating plate 11a is made of ceramics, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used as the insulating circuit board 11. The insulating circuit board 11 may be attached to the cooling surface 3a of the cooling module 3 via a bonding member 14a. The heat generated by the semiconductor chips 12a and 12b can be conducted to the cooling module 3 via the conductive circuit patterns 11b1 and 11b2, the insulating plate 11a, and the metal plate 11c to dissipate the heat.

[0044] The joining member 14a may be a brazing material or a thermal interface material. The brazing material mainly consists of, for example, at least one of aluminum alloy, titanium alloy, magnesium alloy, zirconium alloy, or silicon alloy. The thermal interface material includes various materials such as thermally conductive grease, elastomer sheets, RTV (Room Temperature Vulcanization) rubber, gel, and phase change material. By attaching the semiconductor unit 10 to the cooling module 3 via such a brazing material or thermal interface material, the heat dissipation of the semiconductor unit 10 can be improved.

[0045] Furthermore, the joining members 14b and 14c may be solder. Lead-free solder is used. Lead-free solder mainly consists of an alloy containing at least two of the following elements: tin, silver, copper, zinc, antimony, indium, and bismuth. In addition, the solder may contain additives. Examples of additives include nickel, germanium, cobalt, or silicon. The inclusion of additives in the solder improves wettability, gloss, and bonding strength, thereby improving reliability. In particular, sintered bodies may be used for joining members 14a and 14b. When joining with sintered bodies, the sintered material may be, for example, powders of silver, iron, copper, aluminum, titanium, nickel, tungsten, or molybdenum.

[0046] The semiconductor chips 12a and 12b contain power device elements primarily composed of silicon. The power device elements are RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT combines the functions of an IGBT (switching element) and a FWD (Free Wheeling Diode). The upper surface of such semiconductor chips 12a and 12b is provided with control electrodes (gate electrodes, etc.) and output electrodes (emitter electrodes), which are the main electrodes. The lower surface of such semiconductor chips 12a and 12b is provided with input electrodes (collector electrodes), which are the main electrodes. The control electrodes may be provided along one side of the upper surface of the semiconductor chips 12a and 12b (or in the center of one side). The output electrodes may be provided in the center of the upper surface of the semiconductor chips 12a and 12b. The lead frames 13a and 13b are electrically and mechanically joined to the output electrodes of the semiconductor chips 12a and 12b.

[0047] Furthermore, the semiconductor chips 12a and 12b may include a switching element consisting of a power MOSFET mainly composed of silicon carbide. Such semiconductor chips 12a and 12b are provided on their front surface with a control electrode (gate electrode, etc.) and a main electrode, which is an output electrode (source electrode). The semiconductor chips 12a and 12b are provided on their back surface with a main electrode, which is an input electrode (drain electrode).

[0048] Furthermore, the semiconductor chips 12a and 12b may each use a pair of switching elements and diode elements, respectively, which are mainly composed of silicon or silicon carbide. The switching elements are, for example, IGBTs and power MOSFETs. Such semiconductor chips 12a and 12b have, for example, an input electrode (drain electrode or collector electrode) as the main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode), which is the main electrode, on the front surface. The diode elements are, for example, FWDs such as SBDs (Schottky Barrier Diodes) and PiN (P-intrinsic-N) diodes. Such semiconductor chips 12a and 12b have an output electrode (cathode electrode) as the main electrode on the back surface and an input electrode (anode electrode) as the main electrode on the front surface.

[0049] The lead frames 13a and 13b electrically connect and wire the semiconductor chips 12a and 12b and the conductive circuit patterns 11b2 and 11b3. Lead frame 13a directly connects the main electrode of semiconductor chip 12b to the conductive circuit pattern 11b3 via the aforementioned bonding member 14c. Lead frame 13b directly connects the main electrode of semiconductor chip 12a to the conductive circuit pattern 11b2 via the aforementioned bonding member 14c. Lead frames 13a and 13b may be joined to the conductive circuit patterns 11b3 and 11b2 by ultrasonic bonding.

[0050] The lead frames 13a and 13b are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy mainly composed of at least one of these. The surfaces of the lead frames 13a and 13b may be plated to improve corrosion resistance. The plating material used in this case is, for example, nickel, nickel-phosphorus alloy, or nickel-boron alloy.

[0051] The cooling module 3 has a cooling surface 3a on its front side where the semiconductor module 2 is placed. Specifically, as previously described, the frame portion 21 is attached to the cooling surface 3a of the cooling module 3 on which the semiconductor units 10a, 10b, and 10c are placed. The cooling surface 3a is wider than the back surface of the semiconductor unit 10 and is flat. The cooling module 3 may be, for example, a heat dissipation base equipped with heat dissipation fins, or a cooling device in which a refrigerant circulates inside.

[0052] Next, the details of the control terminals 25a, 25b, 25c and the inner wall 21c1 of the frame 21, which are integrally included in the frame 21, will be described. Note that the control terminals 25a, 25b, and 25c have the same configuration. Here, as an example, the control terminal 25b and the inner wall 21c1 containing the control terminal 25b will be described using Figures 6 to 8. Figure 6 is a front view of the inner wall of the case included in the semiconductor device of the embodiment. Figures 7 and 8 are cross-sectional views of the control terminals of the semiconductor device of the embodiment. Note that Figure 6 is a cross-sectional view taken along the dashed line II-II in Figures 1 and 2. Figure 7 is a cross-sectional view taken along the dashed line II in Figure 6, and Figure 8 is an enlarged cross-sectional view of the joint portion 25b2 of the control terminal 25b in Figure 7.

[0053] As previously described, the control terminal 25b is integrally included in the frame portion 21 (on the outer wall 21c side). Here, multiple (for example, five) control terminals 25b are included along the inner wall 21c1 (and outer wall 21c) with the joint portion 24b2 in between. The control terminal 25b, including the external connection portion 25b1 and the joint portion 25b2, is integrally molded with the frame portion 21. The thickness of the control terminal 25b is approximately uniform overall. The external connection portion 25b1 extends in the +Z direction relative to the frame portion 21.

[0054] The joint portion 25b2 is integrally connected to the external connection portion 25b1 at approximately a right angle. The outer and inner surfaces of the corner where the external connection portion 25b1 and the joint portion 25b2 connect may be rounded (R-shaped).

[0055] The joint 25b2 includes an upper surface 25b3, an end surface 25b4, and a lower surface 25b5. The upper surface 25b3 and the lower surface 25b5 may be substantially flat. The end surface 25b4 is integrally connected to the upper surface 25b3, and a sag D is present at the connection point. The joint 25b2 includes a burr B on the end surface 25b4 that extends downward toward the lower surface 25b5. The lower surface 25b5 is integrally connected to the lower end of the burr B on the end surface 25b4. The tip of the lower surface 25b5 has an R-shape. Therefore, this burr B overlaps the first region 21h4 of the protrusion 21h3 included in the terminal block 21h, which will be described later.

[0056] A terminal block 21h is provided on the inner wall 21c1 of the frame portion 21. The inner wall 21c1 is substantially flat and may be substantially parallel to the XZ plane. The terminal block 21h is substantially block-shaped and is integrally provided at the lower end of the inner wall 21c1, protruding from the inner wall 21c1 toward the unit housing portion 21e2.

[0057] The terminal block 21h has the joint portion 25b2 of the control terminal 25b embedded in its upper surface. The terminal block 21h has a step relative to the inner wall 21c1. The terminal block 21h includes a projection 21h3 at its upper part. The projection 21h3 protrudes into the unit housing portion 21e2. That is, the projection 21h3 protrudes toward the end face 25b4 of the joint portion 25b2 of the control terminal 25b. The projection 21h3 is in contact with the lower surface 25b5 of the joint portion 25b2.

[0058] Such a terminal block 21h includes a terminal surface 21h1 which is the top surface and a wall surface 21h2. The terminal surface 21h1 is parallel to the cooling surface 3a (XY plane) of the cooling module 3 and forms a step with respect to the inner wall 21c1. In plan view, the terminal surface 21h1 is, for example, rectangular in shape. The length of the terminal surface 21h1 in the direction along the inner wall 21c1 may be, for example, greater than or equal to the total width of the plurality of control terminals 25b arranged along the inner wall 21c1. The terminal surface 21h1 is provided with a joint portion 25b2 for the control terminals 25b. The joint portion 25b2 is embedded in the terminal block 21h, and the upper surface 25b3 of the joint portion 25b2 is exposed from the terminal surface 21h1. Here, the upper surface 25b3 of the joint portion 25b2 and the terminal surface 21h1 are substantially on the same plane. The upper surface 25b3 of the joint portion 25b2 may protrude in the +Z direction or be recessed in the -Z direction relative to the terminal surface 21h1, and must be exposed from the terminal surface 21h1. The upper surface 25b3 of the joint portion 25b2 and the control electrodes of the semiconductor chips 12a and 12b are connected by wires 26. The length (depth) of the terminal surface 21h1 in the direction perpendicular to the inner wall 21c1 may be a length that allows the joint portion 25b2 of the control terminal 25b to be positioned.

[0059] The wall surface 21h2 faces the unit housing section 21e2 and is integrally connected to the end of the terminal surface 21h1 on the unit housing section 21e2 side. The joint portion 25b2 of the wall surface 21h2 protrudes toward the unit housing section 21e2, exposing the end face 25b4 of the joint portion 25b2.

[0060] The wall surface 21h2 includes a first region 21h4 and a second region 21h5. The second region 21h5 is the area obtained by removing the first region 21h4 from the wall surface 21h2 and is substantially parallel to the inner wall 21c1. Assuming an extension plane that extends from the second region 21h5 to the lower surface 25b5 of the joint portion 25b2 of the control terminal 25b (described later), this extension plane is perpendicular to the lower surface 25b5 of the joint portion 25b2.

[0061] The first region 21h4 is the protruding tip of the protruding portion 21h3 on the side of the unit housing portion 21e2. The upper end of the first region 21h4 is in contact with the lower surface 25b5 of the joint portion 25b2 of the control terminal 25b. The first region 21h4 is also inclined at an obtuse angle with respect to the second region 21h5. Note that the first region 21h4 only needs to have an obtuse angle at the connection point with the second region 21h5, and may be flat or a curved surface that curves inward when viewed from the side. Figure 8 shows the case where the first region 21h4 is flat.

[0062] Next, the manufacturing method of the semiconductor device 1 will be explained using Figure 9. Figure 9 is a flowchart of the manufacturing method of the semiconductor device according to the embodiment. First, a preparation step is performed to prepare the components of the semiconductor device 1 (step P1 in Figure 9). Examples of components to be prepared include an insulating circuit board 11, semiconductor chips 12a and 12b, lead frames 13a and 13b, a cooling module 3, and a case 20. Other components necessary for the semiconductor device 1 may also be prepared. Manufacturing equipment used to manufacture the semiconductor device 1 may also be prepared.

[0063] Here, the manufacturing of the case 20 prepared in the preparation process will be explained using Figures 10 to 13. Figure 10 is a front view of the control terminal included in the inner wall of the case of the embodiment. Figure 11 is a plan view of the control terminal included in the case of the embodiment. Figure 12 is a cross-sectional view of the control terminal included in the case of the embodiment. Figure 13 is a cross-sectional view illustrating the tie bar cut of the semiconductor device manufacturing method of the embodiment. Note that Figure 10 corresponds to Figure 6 of the configuration made up in process P1a. Figure 11 is a plan view of the left side of the joint 24b2 in Figure 10. Figure 12 is a cross-sectional view along the dashed line II in Figures 10 and 11.

[0064] In manufacturing the case 20, first, a frame portion 21 including a frame member 27 to which multiple control terminals 25b are connected is integrally molded (step P1a in Figure 9). The frame member 27 is made by cutting and bending a conductive plate by press working. Such a frame member 27 includes multiple control terminals 25b and tie bars 25b6 that connect the multiple control terminals 25b. The tie bars 25b6 are integrally formed in a continuous manner at the tip portions of the joint portions 25b2 of the multiple control terminals 25b. The connection portion between the tie bar 25b6 and the tip portions of the joint portions 25b2 of the multiple control terminals 25b may be smaller than the width of the joint portion 25b2 (in the ±X direction).

[0065] Although not shown in the diagram, the first connection terminals 22a, 22b, 22c and the second connection terminals 23a, 23b, 23c may be connected by tie bars. The W-phase output terminal 24a, V-phase output terminal 24b, and U-phase output terminal 24c may also be connected by tie bars.

[0066] The frame member 27 and various terminals connected by tie bars are set in a predetermined mold and integrally molded by the case material filled in the mold. As a result, the control terminal 25b is integrally molded with the frame 21, as shown in Figures 10 to 12. The mold is configured such that a protruding portion 21h3 is formed on the terminal block 21h of the frame 21. In this process, the joint portion 25b2 of the control terminal 25b is integrally molded with the terminal block 21h up to the connection portion with the tie bar 25b6, and the connection portion and the tie bar 25b6 extend outward from the wall surface 21h2.

[0067] Next, the tie bar 25b6 is cut with the cutter 4 (step P1b in Figure 9). The cutter 4 cuts the connection portion between the tie bar 25b6, which is not included in the terminal block 21h of the frame member 27, and the joint portion 25b2 of the control terminal 25b. The cutter 4 cuts the portion of the connection portion outside the protrusion 21h3, where the lower surface 25b5 is supported by the protrusion 21h3 of the terminal block 21h. The cutter 4 bites in from the upper surface 25b3 of the connection portion and reaches the lower surface 25b5. At this time, as shown in Figure 13, burrs D are generated at the cut location of the upper surface 25b3, and burrs B are generated at the cut location of the lower surface 25b5.

[0068] Similarly, the tie bars are cut from the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, and the U-phase output terminal 24c. As a result, a case 20 is obtained in which multiple control terminals 25b are integrally molded into the frame portion 21 as shown in Figure 6.

[0069] Next, the semiconductor unit assembly process for manufacturing the semiconductor unit 10 is carried out (process P2 in Figure 9). First, semiconductor chips 12a and 12b are set on the conductive circuit patterns 11b1 and 11b2 of the insulating circuit board 11 via bonding members. Furthermore, lead frames 13b and 13a are set on the main electrode and conductive circuit pattern 11b2 on the front surface of semiconductor chip 12a, and on the main electrode and conductive circuit pattern 11b3 on the front surface of semiconductor chip 12b via bonding members.

[0070] The insulated circuit board 11, semiconductor chips 12a, 12b, and lead frames 13a, 13b, which are set in this manner, are heated to melt the bonding member. The melted bonding member hardens, and the semiconductor chips 12a, 12b are bonded to the conductive circuit patterns 11b1, 11b2 by the bonding member 14b. In addition, the lead frame 13a is bonded to the main electrode and conductive circuit pattern 11b3 of the semiconductor chip 12b by the bonding member 14c, and the lead frame 13b is bonded to the main electrode and conductive circuit pattern 11b2 of the semiconductor chip 12a by the bonding member 14c. As a result, the semiconductor unit 10 is obtained.

[0071] Next, a case mounting process is performed in which the case 20 is attached to the cooling module 3 (step P3 in Figure 9). First, the semiconductor units 10a, 10b, and 10c are attached to the cooling surface 3a of the cooling module 3 via a bonding member 14a along the longitudinal direction of the cooling surface 3a. Then, the case 20 is attached to the cooling surface 3a of the cooling module 3 using adhesive (not shown). At this time, the semiconductor units 10a, 10b, and 10c on the cooling surface 3a are housed in the unit housing sections 21e1, 21e2, and 21e3 of the case 20, respectively.

[0072] Next, a wiring process is performed to connect the semiconductor unit 10 (step P4 in Figure 9). First, the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the W-phase output terminal 24a, the V-phase output terminal 24b, and the U-phase output terminal 24c are joined to the conductive circuit pattern of the insulating circuit board 11. For example, ultrasonic bonding may be used for this joining. In addition, the control electrodes of the semiconductor chips 12a, 12b and the control terminals 25a, 25b, 25c are connected by wire 26.

[0073] Next, an adhesion agent is applied (step P5 in Figure 9). The steps after this application process will be explained using Figure 14. Figure 14 is a cross-sectional view illustrating the adhesion agent application step of the semiconductor device manufacturing method according to this embodiment. Note that Figure 14 shows the case in Figure 8 where the wire 26 has been bonded and the adhesion film 28 has been formed.

[0074] An adhesive is sprayed into the unit housing sections 21e1, 21e2, and 21e3 of case 20 to adhere the adhesive to the surfaces of the semiconductor units 10a, 10b, and 10c, the wires 26, the joints of each terminal, and the inner walls 21a1, 21b1, 21c1, and 21d1 that define the unit housing sections 21e1, 21e2, and 21e3. Then, by heating and drying the adhesive, an adhesive film 28 is formed on each surface. For example, as shown in Figure 14, after the coating process, an adhesive film 28 is formed on the surfaces of the wires 26, the control terminals 25b, the terminal surface 21h1 of the terminal block 21h, and the wall surface 21h2.

[0075] Next, a sealing process is performed in which the unit housing sections 21e1, 21e2, and 21e3 are sealed with a sealing member 29 (step P6 in Figure 9). The sealing member 29 is filled into the unit housing sections 21e1, 21e2, and 21e3, sealing the insulating circuit board 11, semiconductor chips 12a, 12b, lead frames 13a, 13b, and wires 26. The semiconductor device 1 is thus obtained.

[0076] Here, a reference example for semiconductor device 1 will be described. In the above embodiment, a protrusion 21h3 was provided on the terminal block 21h where the joint portion 25b2 of the control terminal 25b is located. In the reference example, the case in which the protrusion 21h3 is not provided will be explained using Figure 15. Figure 15 is a cross-sectional view of the control terminal included in the reference example case. Note that the semiconductor device in the reference example has the protrusion 21h3 removed from the terminal block 21h of semiconductor device 1, and otherwise has the same configuration as semiconductor device 1.

[0077] In the reference example, the joint 25b2 of the control terminal 25b is provided on the terminal block 21h, as shown in Figure 15. The entire wall surface 21h2 of the terminal block 21h is perpendicular to the lower surface 25b5 of the joint 25b2. In this case as well, the joint 25b2 of the control terminal 25b has burrs D and burrs B. The burrs B overlap the upper part of the wall surface 21h2.

[0078] Furthermore, the reference example semiconductor device can also be manufactured according to the flowchart shown in Figure 9. Here, the adhesion agent coating process (process P5) in Figure 9 will be explained using Figure 16. Figure 16 is a cross-sectional view illustrating the adhesion agent coating process in the manufacturing method of the reference example semiconductor device. Note that Figure 16 shows the case in Figure 15 where the wire 26 has been bonded and the adhesion film 28 has been formed.

[0079] Similar to the embodiment, steps P1 to P4 in Figure 9 are performed to spray an adhesive into the unit housing sections 21e1, 21e2, and 21e3 of the case 20, thereby adhering the adhesive to the surfaces of the semiconductor units 10a, 10b, and 10c, the wires 26, the joints of each terminal, and the inner walls 21a1, 21b1, 21c1, and 21d1 that define the unit housing sections 21e1, 21e2, and 21e3. Then, by heating and drying the adhesive, an adhesion film 28 is formed on each surface. For example, as shown in Figure 16, after the coating process, an adhesion film 28 is formed on the surfaces of the wires 26, the control terminals 25b, and the wall surface 21h2 of the terminal block 21h.

[0080] In this case, the burr B generated at the joint 25b2 of the control terminal 25b is covering the wall surface 21h2 of the terminal block 21h. As a result, the adhesive adhering to the gap between the burr B and the wall surface 21h2 (the area enclosed by the dashed line in Figure 16) hardens, creating an accumulation of adhesive.

[0081] Next, a sealing process is performed in which the inside of the unit housing sections 21e1, 21e2, and 21e3 is sealed with a sealing member 29 (step P6 in Figure 9). The sealing member 29 is filled into the unit housing sections 21e1, 21e2, and 21e3, sealing the insulating circuit board 11, semiconductor chips 12a, 12b, lead frames 13a, 13b, and wires 26. Because an accumulation of adhesive is formed in the gap between the burr B and the wall surface 21h2, the sealing member 29 and the lower end of the burr B are hindered from adhering properly. As a result, there is a high possibility that the sealing member 29 will delaminate from the wall surface 21h2, starting from the lower end of the burr B. If the delamination progresses from the sealing member 29 in the direction of the cooling module 3 or the control terminal 25b, the fixing of the wires 26 by the sealing member 29 weakens, stress is applied to the wires 26, and the wires 26 may break or detach from the control terminal 25b. If wire 26 breaks or becomes disconnected from control terminal 25b, the reliability of the semiconductor device will decrease.

[0082] Such accumulations of adhesive can occur when the burr B generated on the joint portion 25b2 of the control terminal 25b is small, or even if no burr B is present. For example, if the joint portion 25b2 of the control terminal 25b protrudes from the wall surface 21h2 of the terminal block 21h, adhesive can adhere to the corner formed by the lower surface 25b5 of the protruding joint portion 25b2 and the wall surface 21h2, which can then form an accumulation of adhesive.

[0083] Therefore, the semiconductor device 1 described above includes a control terminal 25b including a joint portion 25b2 having an upper surface 25b3, a lower surface 25b5, and an end surface 25b4; a terminal block 21h having a wall surface 21h2 on which the joint portion 25b2 protrudes and the end surface 25b4 is exposed, and on which the upper surface 25b3 of the joint portion 25b2 is exposed; and an adhesive film 28 applied to the upper surface 25b3, the end surface 25b4, and the lower surface 25b5 of the protruding portion of the joint portion 25b2 of the control terminal 25bb, as well as the wall surface 21h2 of the terminal block 21h and the terminal surface 21h1 of the terminal block 21h. Furthermore, the wall surface 21h2 of the terminal block 21h includes a first region 21h4 whose upper end contacts the lower surface 25b5 and a second region 21h5 excluding the first region 21h4. The lower surface 25b5 of the joint 25h2 is perpendicular to the extension plane that extends from the lower surface 25b5 of the second region 21h5, and the first region 21h4 is inclined at an obtuse angle with respect to the second region 21h5. When the adhesive is applied to the terminal block 21h including the wall surface 21h2 to form the adhesive film 28, the adhesive adheres to the wall surface 21h2 including the first region 21h4. Because the first region 21h4 is inclined, the adhesion is prevented from accumulating between the joint 25b2 protruding from the wall surface 21h2 and the first region 21h4 of the wall surface 21h2. In particular, even if the adhesion adheres to the gap between the burr B of the end surface 25b4 of the joint 25b2 and the first region 21h4 of the wall surface 21h2, the adhesion flows downward along the inclined first region 21h4, thus suppressing the accumulation of the adhesion in this gap. Therefore, the sealing member 29 adheres closely to the sag D of the joint portion 25b2 of the control terminal 25b, preventing delamination from occurring starting from this contact point. This prevents the wire 26 from breaking and the wire 26 from detaching from the control terminal 25b, thereby suppressing a decrease in the reliability of the semiconductor device 1. [Explanation of symbols]

[0084] 1 Semiconductor device 2 Semiconductor Modules 3 Cooling Module 3a Cooling surface 4 cutters 10, 10a, 10b, 10c Semiconductor Unit 11 Insulated circuit board 11a Insulating board 11b1, 11b2, 11b3 Conductive circuit patterns 11c metal plate 12a, 12b semiconductor chips 13a, 13b Lead Frames 14a, 14b, 14c Joining members 20 cases 21 Frame section 21a, 21b, 21c, 21d Exterior walls 21a1,21b1,21c1,21d1 Inner wall (inner surface) 21e opening Unit housing section for 21e1, 21e2, and 21e3. 21f top surface 21g bottom 21h terminal block 21h1 Terminal surface 21h2 Wall 21h3 Protrusion 21h4 1st area 21h5 2nd area 21i fastening hole 22a, 22b, 22c First connection terminal 22a1, 22b1, 22c1 External connection section 22a2,22b2,22c2 joint 23a, 23b, 23c Second connection terminal 23a1, 23b1, 23c1 External connection section 23a2,23b2,23c2 joint 24a W-phase output terminal 24a1 External connection section 24a2 joint 24b V phase output terminal 24b1 External connection section 24b2 joint 24c U phase output terminal 24c1 External connection section 24c2 joint 25a, 25b, 25c control terminals 25b1 External connection section 25b2 joint 25b3 Top 25b4 End face 25b5 Bottom side 25b6 Tie Bar 26 wires 27 Frame members 28. Adhesion film (adhesion member) 29 Sealing member B Bali D Dare

Claims

1. A terminal including a joint having an upper surface, a lower surface, and an end surface, A terminal block having a wall surface with the joint portion protruding and the end face exposed, and the upper surface of the joint portion exposed, The adhesive member applied to the upper surface, the end surface, and the lower surface of the protruding portion of the joint of the terminal, along with the wall surface and the upper surface of the terminal block, Includes, The wall surface of the terminal block comprises a first region whose upper end contacts the lower surface and a second region excluding the first region, the lower surface of the joint portion is perpendicular to an extension plane that extends from the lower surface of the second region, and the first region is inclined at an obtuse angle with respect to the second region. Semiconductor equipment.

2. The terminal block includes a projection that protrudes from the wall surface toward the end face of the terminal, and includes the first region at the protruding tip, and includes a projection that contacts the lower surface of the terminal. The semiconductor device according to claim 1.

3. The joint portion of the terminal includes a burr that extends downward toward the lower surface side relative to the end face. The burr covers the first region of the protruding portion. The semiconductor device according to claim 2.

4. The upper surface of the joint portion of the terminal includes a sag connected to the end face. The semiconductor device according to claim 3.

5. The case has a rectangular shape in plan view and further includes an inner wall facing an inner opening region. The case is such that the terminal block is provided on the inner wall with the wall surface facing the opening region. The semiconductor device according to claim 1.

6. The aforementioned adhesive member is further applied to the inner wall of the case, The filling member that fills the aforementioned opening region, The semiconductor device according to claim 5, further comprising

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