Semiconductor equipment

Abstract

To improve the performance of semiconductor devices. [Solution] The semiconductor device includes a semiconductor component SC1 mounted on a wiring board, a semiconductor component SC2 mounted on a wiring board, and a lid L1. The height of the upper surface of semiconductor component SC1 is lower than the height of the upper surface of semiconductor component SC2. The cover portion LCP of the lid L1 includes a portion 5CV that protrudes toward semiconductor component SC1 at a position opposite to semiconductor component SC1. The upper surface 5t of the cover portion LCP includes a bottom surface 5tb which is part of the portion 5CV, an upper surface 5tt positioned higher than the bottom surface 5tb, and a side surface 5ts, one end of which is connected to the bottom surface 5tb and the other end of which is connected to the upper surface 5tt.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] There is a semiconductor device having a lid that covers a plurality of semiconductor components mounted on a wiring board (see, for example, Patent Document 1). Further, there is a structure in which a semiconductor chip and a semiconductor package are mounted on a wiring board, the semiconductor chip is covered with a lid, and the semiconductor package is exposed from the lid (see, for example, Patent Document 2).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] A lid mounted to cover a semiconductor component functions as a heat dissipation path for releasing heat generated in the semiconductor component to the outside. However, it has been found that there is room for improvement in the case of a structure in which one lid is arranged to cover a plurality of semiconductor components. For example, due to the height difference between a plurality of semiconductor components, the heat dissipation characteristics of one semiconductor component may deteriorate.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] A semiconductor device according to one embodiment includes a first semiconductor component mounted on a wiring board and a second semiconductor component mounted on the wiring board. The semiconductor device includes a metal plate, a first adhesive layer disposed between the first semiconductor component and the metal plate, and a second adhesive layer disposed between the second semiconductor component and the metal plate. The height of the upper surface of the first semiconductor component is lower than the height of the upper surface of the second semiconductor component. The metal plate includes a flange portion bonded to the wiring board and a cover portion located above the first semiconductor component and the second semiconductor component. The cover portion of the metal plate includes a first portion that protrudes toward the first semiconductor component at a position facing the first semiconductor component. The upper surface of the cover portion includes a bottom surface which is part of the first portion, an upper surface located at a higher position than the bottom surface, and a side surface to which one end is connected to the bottom surface and the other end is connected to the upper surface. [Effects of the Invention]

[0007] According to the above embodiment, the performance of the semiconductor device can be improved. [Brief explanation of the drawing]

[0008] [Figure 1] This is a plan view of the mounting surface of a semiconductor device, which is one embodiment of the device. [Figure 2] This is a plan view showing the semiconductor device with the lid shown in Figure 1 removed. [Figure 3] This is a cross-sectional view of line AA in Figure 1. [Figure 4] Figure 3 is a cross-sectional view showing the lid with heat dissipation fins mounted on it. [Figure 5] This is an enlarged plan view showing the area around the portion of the lid shown in Figure 1 that protrudes toward the semiconductor component. [Figure 6] This is an enlarged cross-sectional view along line BB in Figure 5. [Figure 7] This is a plan view of a semiconductor device, which is a modified example of Figure 1. [Figure 8]Figure 7 is an enlarged plan view of the area around the recess shown. [Figure 9] Figure 7 is a cross-sectional view showing a semiconductor device with heat dissipation fins mounted on its lid. [Figure 10] This is a cross-sectional view showing another variation of Figure 4. [Modes for carrying out the invention]

[0009] (Explanation of format, basic terminology, and usage in this application) In this application, the descriptions of the embodiments are divided into multiple sections for convenience. These are not independent of each other, but rather one is a detail of the other, or one is a variation of the other. In principle, similar parts will be omitted from repeated explanations. Furthermore, each component in the embodiments is not essential unless it is explicitly indicated as an essential component, its number is theoretically limited, or it is clearly essential from the context.

[0010] Similarly, in descriptions of the implementation, etc., even if it says "X consisting of A" regarding materials, composition, etc., unless it is clearly limited or clearly limited from the context, elements other than A are not excluded. For example, in terms of components, it means "X containing A as the main component." For example, even if it says "silicon component," it is not limited to pure silicon, but also includes components containing SiGe (silicon-germanium) alloys, other multi-component alloys with silicon as the main component, and other additives. Also, even if it says gold plating, Cu layer, nickel plating, etc., unless it is specifically stated otherwise, it is meant to include not only pure materials but also components with gold, Cu, nickel, etc. as the main components, respectively.

[0011] Furthermore, when specific numbers or quantities are mentioned, unless explicitly limited or clearly limited by the context, those numbers are listed as examples only.

[0012] In addition, in each of the figures in the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and the description will not be repeated as a general rule.

[0013] In the accompanying drawings, on the other hand, when it becomes cumbersome or when the distinction from voids is clear, hatching or the like may be omitted even for a cross-section. In connection with this, in cases where it is clear from the description or the like, even a flatly closed hole may have its background contour line omitted. Further, in order to clarify that it is not a void or to clarify the boundary of a region, hatching or a dot pattern may be added even if it is not a cross-section.

[0014] <Semiconductor Device> First, the semiconductor device of this embodiment will be described. In the following description, a semiconductor chip is a structure having a semiconductor substrate and a plurality of terminals (electrodes) formed on the semiconductor substrate. A semiconductor package is a structure in which one or more semiconductor chips are sealed by a sealing body. The semiconductor package has a plurality of terminals (electrodes) on at least one of the upper surface and the lower surface. A semiconductor component is a general term for the above-described semiconductor chips and semiconductor packages. A semiconductor device is a structure having one or more semiconductor components and a wiring board on which the semiconductor components are mounted.

[0015] FIG. 1 is a plan view of the semiconductor device of this embodiment. FIG. 2 is a plan view showing the semiconductor device in a state where the lid shown in FIG. 1 is removed. FIG. 3 is a cross-sectional view taken along line A-A of FIG. 1. FIG. 4 is a cross-sectional view showing a state where a heat radiation fin is mounted on the lid shown in FIG. 3.

[0016] As shown in FIGS. 1 to 4, any one of the X direction (see FIGS. 1 to 4), the Y direction (see FIGS. 1 and 2), and the Z direction (see FIGS. 3 and 4) is described. The Y direction is a direction intersecting the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is a direction orthogonal to each of the X direction and the Y direction. In other words, the Z direction is the normal direction (i.e., the perpendicular direction) to the X - Y plane including the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Also, in the following description, "plan view" generally means the plan view seen from the X - Y plane.

[0017] The semiconductor device PKG1 of the present embodiment has a wiring substrate SUB1 (see FIG. 1), a semiconductor component SC1 (see FIG. 2), a semiconductor component SC2 (see FIG. 2), and a lid (metal plate) L1 (see FIG. 1).

[0018] As shown in FIG. 3, the wiring substrate SUB1 has an upper surface (surface, main surface, component mounting surface) 2t which is the mounting surface of the semiconductor component. Also, the wiring substrate SUB1 has a lower surface (surface, main surface, mounting surface) 2b on the opposite side of the upper surface 2t. The upper surface 2t and the lower surface 2b of the wiring substrate SUB1 are, for example, quadrilateral. As shown in FIGS. 1 and 2, in plan view, the wiring substrate SUB1 has four sides 2s.

[0019] The semiconductor component SC1 includes a lower surface 3b facing the upper surface 2t of the wiring substrate SUB1 and an upper surface 3t on the opposite side of the lower surface 3b. As shown in FIG. 2, the semiconductor component SC1 is mounted on the region R1 of the upper surface 2t of the wiring substrate SUB1.

[0020] As shown in FIG. 3, the semiconductor component SC2 includes a lower surface 4b facing the upper surface 2t of the wiring substrate SUB1 and an upper surface 4t on the opposite side of the lower surface 4b. As shown in FIG. 2, the semiconductor component SC2 is mounted on the region R2 of the upper surface 2t of the wiring substrate SUB1.

[0021] The lid L1 has a lower surface 5b facing the upper surface 3t of semiconductor component SC1 and the upper surface 4t of semiconductor component SC2, and an upper surface 5t on the opposite side of the lower surface 5b. The lid L1 is placed on the wiring board SUB1.

[0022] Furthermore, the semiconductor device PKG1 has adhesive layers BND1 and BND2. Adhesive layer BND1 is located between the upper surface 3t of semiconductor component SC1 and the lower surface 5b of lid L1. Adhesive layer BND2 is located between the upper surface 4t of semiconductor component SC2 and the lower surface 5b of lid L1.

[0023] As shown in Figure 3, the wiring board SUB1 has terminals (terminals 2PD) on the upper surface 2t, which is the component mounting surface, and terminals (lands 2LD) on the lower surface 2b, which is the mounting surface. The wiring board SUB1 has a plurality of wiring layers WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8 that electrically connect terminals 2PD and lands 2LD. Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern such as wiring, which is a path for supplying signals and power. An insulating film 2e is also placed between each wiring layer. Each wiring layer is electrically connected to each other via wiring 2v, which is an interlayer conductive path that penetrates the insulating film 2e, or through-hole wiring 2THW. In this embodiment, a wiring board with 8 wiring layers is shown as an example of a wiring board SUB1, but the number of wiring layers in the wiring board SUB1 is not limited to 8 layers. For example, a wiring board with 7 layers or fewer, or 9 layers or more, can be used as a modified example.

[0024] Furthermore, among the multiple wiring layers, the wiring layer WL1 located on the uppermost surface 2t side is covered with an insulating film SR1. The insulating film SR1 has openings, and the multiple terminals 2PD provided on the wiring layer WL1 are exposed from the insulating film SR1 at these openings. In addition, among the multiple wiring layers, the wiring layer WL8 located closest to the lower surface 2b side of the wiring substrate SUB1 has multiple lands, and the wiring layer WL8 is covered with an insulating film SR2. Both insulating films SR1 and SR2 are solder resist films. The multiple terminals 2PD provided on the wiring layer WL1 and the multiple lands 2LD provided on the wiring layer WL8 are electrically connected via conductor patterns formed on each wiring layer of the wiring substrate SUB1. The conductor patterns include wiring 2d, large-area conductor patterns, via wiring 2v, and through-hole wiring 2THW.

[0025] Furthermore, the wiring board SUB1 is formed by laminating multiple wiring layers on the upper surface 2Ct and lower surface 2Cb of the insulating layer 2CR, which is made of prepreg, for example. Wiring layer WL4 and wiring layer WL5 are electrically connected via multiple through-hole wiring 2THW embedded in multiple through-holes that penetrate from one of the upper surface 2Ct to the other of the lower surface 2Cb.

[0026] As a variation of Figure 3, a so-called coreless substrate may be used, which does not have an insulating layer 2CR made of a hard material such as prepreg, but is formed by sequentially stacking an insulating film 2e and a conductor pattern such as wiring 2d. When a coreless substrate is used, through-hole wiring 2THW is not formed, and each wiring layer is electrically connected via wiring 2v.

[0027] Furthermore, in the example shown in Figure 3, a solder ball (solder material, external terminal, electrode, external electrode) SB is connected to each of the multiple lands 2LD. The solder ball SB is a conductive component used to electrically connect multiple terminals on the motherboard (not shown) to multiple lands 2LD when mounting the semiconductor device PKG1 to a motherboard (not shown).

[0028] Furthermore, as described above, semiconductor components SC1 and SC2 are mounted on the upper surface 2t of the wiring board SUB1. As shown in Figure 2, in a plan view, semiconductor components SC1 and SC2 do not overlap and are mounted in different regions of the upper surface 2t.

[0029] In this embodiment, the semiconductor component SC1 is a semiconductor chip. More specifically, it is a System on Chip (SoC) in which an arithmetic processing circuit and a memory circuit, which are electrically connected to each other, are mounted on a single chip.

[0030] In this embodiment, the semiconductor component SC2 is a semiconductor package. Specifically, it comprises a semiconductor chip 41 (see Figure 3) on which a memory circuit is formed, an interposer substrate 42 (see Figure 3) on which the semiconductor chip 41 is mounted, and a encapsulant 43 (see Figure 3) that seals the semiconductor chip 41. A semiconductor chip that mainly has a memory circuit formed on it, like the semiconductor chip 41, is called a memory chip. Also, a semiconductor package that mainly has a memory chip mounted on it, like the semiconductor component SC1, is called a memory package.

[0031] Semiconductor component SC1 and semiconductor component SC2 are electrically connected via the wiring board SUB1.

[0032] As shown in Figure 3, the semiconductor component SC1 has a top surface (main surface) 3t and a bottom surface (main surface) 3b opposite to the top surface 3t. As shown in Figure 2, in plan view, the semiconductor component SC1 has four sides 3s. The planar shape of the semiconductor component SC1 is a quadrilateral. In the example shown in Figure 2, one of the four sides 3s of the semiconductor component SC1 extends along one of the four sides 2s of the wiring board SUB1.

[0033] Multiple electrodes (pads, electrode pads, bonding pads) 3PD are arranged on the lower surface 3b of the semiconductor component SC1. In the example shown in Figure 3, the semiconductor component SC1 is mounted on the wiring board SUB1 with its lower surface 3b, which is the electrode formation surface, facing the upper surface 2t of the wiring board SUB1. This mounting method is called the face-down mounting method or the flip-chip connection method.

[0034] Although not shown in the diagram, multiple semiconductor elements (circuit elements) are formed on the main surface of the semiconductor component SC1 (more specifically, the semiconductor element formation region provided on the element formation surface of the semiconductor substrate, which is the base material of the semiconductor component SC1). Multiple electrodes 3PD are electrically connected to these multiple semiconductor elements via wiring (not shown) formed on the wiring layer located inside the semiconductor component SC1.

[0035] The semiconductor component SC1 (more specifically, the semiconductor substrate that serves as the base material for the semiconductor component SC1) is made of, for example, silicon (Si). Furthermore, an insulating film is formed on the lower surface 3b, covering the substrate and wiring of the semiconductor component SC1. A portion of each of the multiple electrodes 3PD is exposed from this insulating film through openings formed in the film.

[0036] Furthermore, as shown in Figure 3, each of the multiple electrodes 3PD is connected to a protruding electrode 3BP. The multiple electrodes 3PD of the semiconductor component SC1 and the multiple terminals 2PD of the wiring board SUB1 are electrically connected via the multiple protruding electrodes 3BP. The protruding electrode (bump electrode) 3BP is a metal member (conductive member) formed to protrude from the lower surface 3b of the semiconductor component SC1.

[0037] Furthermore, as shown in Figure 3, an underfill resin (insulating resin) UF1 is placed between the semiconductor component SC1 and the wiring board SUB1. The underfill resin UF1 is positioned to fill the space between the lower surface 3b of the semiconductor component SC1 and the upper surface 2t of the wiring board SUB1. Each of the multiple protruding electrodes 3BP is sealed by the underfill resin UF1.

[0038] As shown in Figure 3, semiconductor component SC2 has an upper surface (main surface) 4t and a lower surface (main surface) 4b opposite to the upper surface 4t. As shown in Figure 2, in plan view, semiconductor component SC2 has four sides 4s. The planar shape of semiconductor component SC1 is a quadrilateral. In the example shown in Figure 2, one of the four sides 4s of semiconductor component SC2 extends along one of the four sides 2s of the wiring board SUB1. Also, in plan view, one of the other four sides 4s of semiconductor component SC2 faces one of the four sides 3s of semiconductor component SC1.

[0039] Multiple lands (electrodes, pads, bonding pads) 4PD are arranged on the lower surface 4b of the semiconductor component SC2. In the example shown in Figure 3, the semiconductor component SC1 is mounted on the wiring board SUB1 with its lower surface 4b, which is the surface for forming the external terminals, facing the upper surface 2t of the wiring board SUB1.

[0040] Although not shown in the diagram, the interposer substrate 42 has multiple wirings, and the semiconductor chip 41 is electrically connected to multiple lands 4PD via these multiple wirings.

[0041] As shown in Figure 3, each of the multiple lands 4PD is connected to a protruding electrode 4BP. The multiple lands 4PD of the semiconductor component SC2 and the multiple terminals 2PD of the wiring board SUB1 are electrically connected via the multiple protruding electrodes 4BP. The protruding electrode (bump electrode) 4BP is a metal member (conductive member) formed to protrude from the lower surface 4b of the semiconductor component SC1.

[0042] An underfill resin (insulating resin) UF2 is placed between the semiconductor component SC2 and the wiring board SUB1. The underfill resin UF2 is positioned to fill the space between the lower surface 4b of the semiconductor component SC1 and the upper surface 2t of the wiring board SUB1. Each of the multiple protruding electrodes 4BP is sealed by the underfill resin UF2.

[0043] Each of the semiconductor components SC1 and SC2 is covered by a lid L1. The lid L1 has a lower surface 5b facing the upper surface 3t of semiconductor component SC1 or the upper surface 4t of semiconductor component SC2, and an upper surface 5t on the opposite side of the lower surface 5b.

[0044] Lid L1 functions as a heat dissipation path to suppress the temperature rise of semiconductor components SC1 and SC2. Lid L1 is a metal plate made of a metal with high thermal conductivity. For example, Lid L1 is made of copper. The thermal conductivity of Lid L1 is higher than that of the semiconductor substrate on which semiconductor component SC1 is located. In addition to dissipating heat from Lid L1 itself to the outside, as shown in Figure 4, there are cases where additional heat dissipation fins (heat dissipation members) RDF are attached to Lid L1.

[0045] The semiconductor device PKG2 shown in Figure 4 further includes a heat dissipation fin RDF with an upper surface 5t of the lid L1 and a lower surface 6b facing it. The semiconductor device PKG2 also further includes an adhesive layer BND4 bonded to the upper surface 5t of the lid L1 and the lower surface 6b of the heat dissipation fin RDF, respectively. The heat generated in semiconductor component SC1 and the heat generated in semiconductor component SC2 are mainly released to the outside through the lid L1, the adhesive layer BND4, and the heat dissipation fin RDF.

[0046] As shown in Figure 1, the lid L1 comprises a flange portion LFP, a cover portion LCP, and a support portion LSP. The flange portion LFP is bonded to the upper surface 2t of the wiring board SUB1 via an adhesive layer BND3 (see Figure 3). The cover portion LCP is located above semiconductor components SC1 and SC2. The support portion LSP connects the flange portion LFP and the cover portion LCP. The support portion LSP is a member for supporting the cover portion LCP, which is positioned higher than the flange portion LFP.

[0047] For lid L1 to function efficiently as a heat dissipation path, it is necessary to thermally connect semiconductor components SC1 and SC2 to lid L1. Each of semiconductor components SC1 and SC2 is fixed to lid L1 via an adhesive layer.

[0048] More specifically, semiconductor component SC1 is fixed to lid L1 via adhesive layer BND1. Adhesive layer BND1 is located between the upper surface 3t of semiconductor component SC1 and the lower surface 5b of lid L1. Semiconductor component SC2 is fixed to lid L1 via adhesive layer BND2. Adhesive layer BND2 is located between the upper surface 3t of semiconductor component SC2 and the lower surface 5b of lid L1.

[0049] Each of the adhesive layers BND1 and BND2 has the function of fixing semiconductor components SC1 and SC2 to lid L1, as well as functioning as part of the heat dissipation path. Therefore, it is preferable that each of the adhesive layers BND1 and BND2 has high thermal conductivity.

[0050] From the above viewpoint, preferred materials for adhesive layers BND1 and BND2 include, for example, a conductive paste in which metal particles such as silver fillers are mixed into a resin paste. However, the thermal conductivity of adhesive layers BND1 and BND2 is lower than that of lid L1. <Heat dissipation characteristics> Next, we will examine the heat dissipation characteristics in the heat dissipation path including the lid L1. As shown in Figure 3, in this embodiment, multiple semiconductor components (semiconductor component SC1 and semiconductor component SC2) are connected to a single lid L1. In this case, if the heights of the upper surfaces of the multiple semiconductor components are different, the heat dissipation characteristics in some heat dissipation paths may be inferior to others due to this difference in height.

[0051] For example, in this embodiment, as shown in Figure 3, when the upper surface 2t of the wiring board SUB1 is used as the reference plane, the height of the upper surface 3t of semiconductor component SC1 (i.e., the mounting height of semiconductor component SC1) is lower than the height of the upper surface 4t of semiconductor component SC2 (i.e., the mounting height of semiconductor component SC2).

[0052] Although not shown in the diagram, as an example of consideration for this embodiment, let's consider the case where the lower surface 5b (see Figure 3) of the cover portion LCP (see Figure 1) is a flat surface. In this example, the shortest distance from the upper surface 3t of semiconductor component SC1 to the lid L1 is longer than the shortest distance from the upper surface 4t of semiconductor component SC2 to the lid L1. Therefore, the thickness of adhesive layer BND1 is greater than the thickness of adhesive layer BND2. In this case, the heat dissipation path via adhesive layer BND1 has lower heat conduction efficiency compared to the heat dissipation path via adhesive layer BND2. In other words, the heat dissipation characteristics of the heat dissipation path connected to semiconductor component SC1 are inferior to those of the heat dissipation path connected to semiconductor component SC2.

[0053] In this embodiment, the heat generated by the SoC semiconductor component SC1 is greater than that generated by the memory package semiconductor component SC2. In this case, it is particularly important to improve the heat dissipation characteristics of the heat dissipation path connected to the semiconductor component SC1. This is to prevent the circuitry of the semiconductor component SC1 from malfunctioning due to temperature rise, or from a decrease in the operating speed of the circuitry.

[0054] From the viewpoint of improving the heat dissipation efficiency in the heat dissipation path via the adhesive layer BND1, it is preferable that the thickness of the adhesive layer BND1 be thin. Therefore, in this embodiment, in order to reduce the distance between the upper surface 3t of the semiconductor component SC1 and the lower surface 5b of the lid L1, as shown in Figure 3, the lid L1 has the following structure.

[0055] In other words, as shown in Figure 1, the cover portion LCP of the lid L1 includes portion 5CV. As shown in Figure 3, portion 5CV has a shape that protrudes toward the semiconductor component SC1 at a position facing the upper surface 3t of the semiconductor component SC1.

[0056] As shown in Figure 4, when the upper surface 2t of the wiring board SUB1 is used as the reference plane, the lower surface 5CVb of portion 5CV is lower than the area of ​​the lower surface 5b of the cover portion LCP other than portion 5CV. Therefore, compared to the example in which the lower surface 5b of the cover portion LCP is a flat surface, the shortest distance between the lid L1 and the semiconductor component SC1 can be reduced. In other words, the thickness of the adhesive layer BND1 can be reduced. For example, in the example shown in Figure 4, the thickness of the adhesive layer BND1 is about 50 μm to 100 μm. Also, the thickness of the adhesive layer BND2 is about 50 μm to 100 μm.

[0057] By reducing the thickness of the adhesive layer BND1, the heat dissipation efficiency in the heat dissipation path via the adhesive layer BND1 is improved.

[0058] Incidentally, from the standpoint of reducing the thickness of the adhesive layer BND1, the shape of the portion 5CV only needs to be such that it protrudes toward the semiconductor component SC1. In other words, even if the shape of the upper surface 5t of the cover portion LCP is flat, the thickness of the adhesive layer BND1 can be reduced if the position of the lower surface 5CVb can be brought closer to the semiconductor component SC1.

[0059] However, in this embodiment, the lid L1 is formed by drawing (plastic deformation using press working) on ​​a flat metal plate. Therefore, the thickness of section 5CV and the thickness of the parts other than section 5CV are the same. However, due to the precision of the machining, there may be a slight difference between the thickness of section 5CV and the thickness of the parts other than section 5CV. In this paragraph, "the same" means that even if a slight difference occurs as described above, it is less than or equal to a difference that allows them to be considered substantially the same.

[0060] When forming the lid L1 by drawing, the cover portion LCP, flange portion LFP (see Figure 1), and support portion LSP (see Figure 1) can be formed together, in addition to the portion 5CV. In other words, it can be manufactured more easily compared to the case where a protrusion is formed on a flat cover portion LCP as the portion 5CV.

[0061] Another method for forming protrusions on a flat LCP cover is to remove a portion of the metal plate by etching. In this case, it is necessary to prepare a metal plate that is thicker than the metal plate used for the lid L1. On the other hand, if the lid L1 is formed by deep drawing, it is sufficient to prepare a metal plate of the same thickness as the metal plate used for the lid L1, thus reducing material costs.

[0062] For the reasons stated above, this embodiment uses a lid L1 formed by a drawing process. When a portion 5CV is formed by a drawing process, a protrusion is formed on the lower surface 5b of the cover portion LCP (see Figure 3), and a recess CCP is formed on the upper surface 5t (see Figure 1).

[0063] As shown in Figure 1, the upper surface 5t of the cover portion LCP includes the bottom surface 5tb, the upper surface 5tt, and the side surface 5ts. As shown in Figure 3, the bottom surface 5tb is part of portion 5CV and is located in the area overlapping with semiconductor component SC1. The upper surface 5tt includes the area overlapping with semiconductor component SC2 and is located at a higher position than the bottom surface 5tb when the upper surface 2t of the wiring board SUB1 is used as the reference plane in a cross-sectional view. The side surface 5ts shown in Figure 1 has one end connected to the bottom surface 5tb and the other end connected to the upper surface 5tt. In this embodiment, the side surface 5ts is inclined with respect to either the bottom surface 5tb or the upper surface 5tt, as shown in Figure 3.

[0064] Incidentally, as mentioned above, the semiconductor device PKG2 shown in Figure 4 has heat dissipation fins RDF mounted on the lid L1 via an adhesive layer BND4. The adhesive layer BND4 is bonded to the bottom surface 5tb, the side surface 5ts, and the top surface 5tt, respectively. In the case of the semiconductor device PKG2, the thickness of the adhesive layer BND4 located on the bottom surface 5tb is greater than the thickness of the adhesive layer BND4 located on the top surface 5tt. In other words, the thickness of the portion of the adhesive layer BND4 located on the bottom surface 5tb is greater than the thickness of the portion located on the top surface 5tt. In this case, the heat dissipation efficiency of the adhesive layer BND4 located on the bottom surface 5tb is inferior to that of the adhesive layer BND4 located on the top surface 5tt.

[0065] However, the lid L1 is a single unit including the bottom surface 5tb and the top surface 5tt. In this case, some of the heat generated from the semiconductor component SC1 is transferred to the heat dissipation fin RDF via the top surface 5tt of the lid L1.

[0066] Therefore, considering the heat dissipation path transmitted to the heat dissipation fin RDF via the portion 5CV of the lid L1 and the upper surface 5tt of the lid L1, the decrease in heat dissipation characteristics due to the formation of the recessed CCP (see Figure 1) can be suppressed.

[0067] Next, the details of the recess provided in the lid L1 of this embodiment will be described using Figures 5 and 6. Figure 5 is an enlarged plan view showing the area around the portion of the lid shown in Figure 1 that protrudes toward the semiconductor component. Figure 6 is an enlarged cross-sectional view along line BB in Figure 5.

[0068] As shown in Figure 5, in a plan view, the base 5tb forms a quadrilateral. More specifically, the base 5tb comprises a side 5tbs1 extending in the Y direction, a side 5tbs2 extending in the X direction, a side 5tbs3 opposite to side 5tbs2, and a side 5tbs4 opposite to side 5tbs1.

[0069] As shown in Figure 5, side 5ts (see Figure 1) includes side 5ts1 connected to edge 5tbs1, side 5ts2 connected to edge 5tbs2, side 5ts3 connected to edge 5tbs3, and side 5ts4 connected to edge 5tbs4.

[0070] As shown in Figure 1, the cover portion LCP of the lid L1 in this embodiment is rectangular in plan view. The flange portion LFP of the lid L1 is a frame shape that surrounds the periphery of the cover portion LCP. The portion 5CV is located inside the periphery of the cover portion LCP. In other words, the upper surface 5tt of the lid L1 (see Figure 6) is interposed between the portion 5CV and the flange portion LFP.

[0071] As in this embodiment, when a frame-shaped flange portion LFP is arranged around the cover portion LCP, the support strength of the heat dissipation fin RDF (see Figure 4) by the lid L1 is higher compared to the semiconductor device PKG3 described later as a modified example.

[0072] <Example 1> Next, we will describe modifications of semiconductor device PKG1 (see Figures 1 to 4) and semiconductor device PKG2 (see Figure 4), which were explained using Figures 1 to 6.

[0073] In the case of the semiconductor device PKG2 shown in Figure 4, as shown in Figure 5, the bottom surface 5tb is surrounded by sides 5ts1, 5ts2, 5ts3, and 5ts4. Therefore, when mounting the heat dissipation fins RDF onto the lid L1 via the adhesive layer BND4 as shown in Figure 4, there is a possibility that air bubbles (voids) may remain in the adhesive layer BND4 within the recessed CCP (see Figure 5).

[0074] If air bubbles remain in the adhesive layer BND4, they will expand as the temperature of the semiconductor device PKG2 rises. Conversely, as the temperature of the semiconductor device PKG2 decreases, the bubbles will contract. Depending on the location of the bubbles in the adhesive layer BND4 and the degree of volume change of the bubbles, delamination may occur at the adhesive interface between the adhesive layer BND4 and the lid L1, or at the adhesive interface between the adhesive layer BND4 and the lower surface 6b of the heat dissipation fin RDF.

[0075] Therefore, when mounting the heat dissipation fins RDF on the lid L1 via the adhesive layer BND4, it is preferable to ensure that no air bubbles remain in the adhesive layer BND4.

[0076] In the following section, a structure that can be manufactured without leaving air bubbles in the adhesive layer BND4 will be described as a modification of the above-described embodiment. Figure 7 is a plan view of a semiconductor device that is a modification of Figure 1. Figure 8 is an enlarged plan view of the area around the recess shown in Figure 7. Figure 9 is a cross-sectional view showing the semiconductor device shown in Figure 7 with heat dissipation fins mounted on the lid.

[0077] The semiconductor device PKG3 shown in Figure 7 differs from the semiconductor device PKG1 shown in Figure 1 in the shape of its lid L2. More specifically, as shown in Figure 8, the lid L2 does not have the side surface 5ts4 shown in Figure 5. In other words, the bottom surface 5tb has a side surface 5tbs4 that is not connected to the side surface 5ts (see Figure 7), and the side surface 5tbs4 is included in the outer edge of the top surface 5t of the lid L1.

[0078] In this modified example, the recessed CCP of the lid L2 does not have a side surface 5ts4 (see Figure 5). Therefore, the end of the recessed CCP of the lid L2 that includes side surface 5tbs4 is an open end.

[0079] For example, the manufacturing method of the semiconductor device PKG4 shown in Figure 9 includes a step of applying an adhesive layer BND4 onto the lid L2, followed by a step of pressing the heat dissipation fin RDF onto the adhesive layer BND4 to bond it. In this step of bonding the heat dissipation fin RDF, air bubbles in the adhesive layer BND4 can easily escape to the outside through the open end including the side 5tbs4 shown in Figure 8.

[0080] In other words, the lid L2 of the semiconductor device PKG3 in this modified example has a structure that makes it less likely for air bubbles to remain in the recessed CCP compared to the lid L1 shown in Figure 5.

[0081] Furthermore, as shown in Figure 7, the shape of the flange portion LFP of lid L2 differs from that of lid L1 shown in Figure 1. That is, in the case of lid L1 explained using Figure 1, the flange portion LFP forms a frame shape surrounding the cover portion LCP. On the other hand, the flange portion LFP of lid L2 shown in Figure 7 has a C shape.

[0082] As shown in Figure 9, the lid L2 has portions that are bonded to semiconductor components SC1 and SC2, in addition to the flange portion LFP. Therefore, even if the flange portion LFP is C-shaped, a certain degree of strength can be ensured.

[0083] However, from the viewpoint of improving the support strength of the heat dissipation fin RDF (see Figure 9), the semiconductor device PKG2 shown in Figure 4 is preferable to this modified example.

[0084] Furthermore, the semiconductor device PKG3 and semiconductor device PKG4 described in this modified example are the same as semiconductor device PKG1 and semiconductor device PKG2 described using Figures 1 to 6, except for the differences mentioned above.

[0085] For example, as shown in Figure 8, the bottom surface 5tb of lid L2 forms a quadrilateral in plan view. Furthermore, the side surface 5ts (see Figure 7) includes side surface 5ts1 connected to edge 5tbs1 of the bottom surface 5tb, side surface 5ts2 connected to edge 5tbs2 of the bottom surface 5tb, and side surface 5ts3 connected to edge 5tbs3 of the bottom surface 5tb. These points are the same as those of lid L1, as explained using Figure 5. Therefore, redundant explanations are omitted.

[0086] <Modification 2> Next, other modifications of the semiconductor device PKG2 described using Figure 4 will be explained. Figure 10 is a cross-sectional view showing another modification of Figure 4. Note that the semiconductor device PKG5 of this modification includes the semiconductor device PKG1 described using Figures 1 to 6. Therefore, the explanation of the semiconductor device PKG1 will be omitted, and as necessary, Figures 1 to 6 will be referenced and explained.

[0087] The semiconductor device PKG5 shown in Figure 10 differs from the semiconductor device PKG2 shown in Figure 4 in the shape of its heat dissipation fins RDF. In the case of the semiconductor device PKG5 shown in Figure 10, the heat dissipation fins RDF include a protruding portion PRP that protrudes toward the lid L1 at a position opposite the bottom surface 5tb of the lid L1. A portion of the protruding portion PRP is located within a recess CCP (see Figure 5) formed by the bottom surface 5tb, side surfaces 5ts1, 5ts2, 5ts3, and 5ts4.

[0088] For example, the manufacturing method of the semiconductor device PKG5 shown in Figure 10 includes a step of applying the adhesive layer BND4 onto the lid L2, followed by a step of pressing the heat dissipation fin RDF onto the adhesive layer BND4 to bond it.

[0089] In the process of bonding the heat dissipation fin RDF, the protruding PRP formed on the lower surface 6b of the heat dissipation fin RDF is inserted into the recessed CCP (see Figure 5) on the upper surface 5t of the lid L1. When the protruding PRP is inserted into the adhesive layer BND4, the adhesive layer BND4 is pressurized, so air bubbles within the adhesive layer BND4 are easily expelled to the outside by the pressure.

[0090] Therefore, the semiconductor device PKG5 shown in Figure 10 has a structure that makes it easier to suppress the retention of air bubbles between the heat dissipation fin RDF and the lid L1 compared to the semiconductor device PKG2 shown in Figure 4.

[0091] Furthermore, in this modified example, the semiconductor device PKG1 supporting the heat dissipation fin RDF has the same structure as the semiconductor device PKG1 shown in Figure 4. Therefore, from the viewpoint of improving the support strength of the heat dissipation fin RDF, the semiconductor device PKG5 shown in Figure 10 is preferable to the semiconductor device PKG4 shown in Figure 9.

[0092] Furthermore, in this modified example, as shown in Figure 10, a protruding PRP is provided on portion 5CV of the lid L1. For example, the shortest distance from the bottom surface 5tb of the recessed CCP (see Figure 5) to the protruding PRP is the same as (or approximately the same as) the shortest distance from the top surface 5tt of the lid L1 to the bottom surface 6b of the heat dissipation fin RDF. For example, in the example shown in Figure 10, the thickness of the adhesive layer BND4 placed between the bottom surface 5tb and the protruding PRP is approximately 50 μm to 100 μm. Also, the thickness of the adhesive layer BND4 placed between the top surface 5tt of the lid L1 and the heat dissipation fin RDF is approximately 50 μm to 100 μm.

[0093] In this case, the heat dissipation characteristics of the heat dissipation path for the heat generated in the semiconductor component SC1, specifically the path that passes through the lid L1 portion 5CV, the adhesive layer BND4, and the protruding portion PRP, can be improved.

[0094] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence.

[0095] For example, each of the semiconductor device packages 1 through 5 described above contains two semiconductor components. However, the number of semiconductor components is not limited to two; there may be three or more semiconductor components.

[0096] Furthermore, for example, the various modifications described above may be combined with each other. [Explanation of symbols]

[0097] 2b Bottom surface (surface, main surface, mounting surface) 2Cb bottom surface 2CR insulating layer (core material, core insulating layer) 2Ct top surface 2D wiring 2e, SR1, SR2 insulating film 2LD Land 2PD terminal 2s, 3s, 4s, 5tbs1, 5tbs2, 5tbs3, 5tbs4 sides 2t Top surface (surface, main surface, component mounting surface) 2THW Through-hole wiring 2V via wiring 3b,4b,5b,6b,5CVb Bottom surface (surface, main surface) 3BP, 4BD Protruding electrodes (bump electrodes) 3PD electrodes (pads, electrode pads, bonding pads) 3t,4t,5t,5tt Top surface (surface, main surface) 4PD Land (Electrode, Pad, Bonding Pad) 5CV part 5tb bottom 5ts,5ts1,5ts2,5ts3,5ts4 Side 41 Semiconductor chips 42 Interposer boards 43 Sealing body BND1,BND2,BND3,BND4 Adhesive layer CCP recess L1, L2 Lid (metal plate) LCP Cover Section LFP flange section LSP support part PKG1, PKG2, PKG3, PKG4, PKG5 Semiconductor device PRP protrusion R1,R2 area RDF heat dissipation fins (heat dissipation components) SB Solder Balls (Solder material, external terminals, electrodes, external electrodes) SC1, SC2 semiconductor components SUB1 Wiring board UF1, UF2 Underfil resin (insulating resin) WL1, WL2, WL3, WL4, WL5, WL6, WL7, WL8 wiring layers

Claims

1. A wiring board having a first surface, A first semiconductor component mounted on a first region of the wiring board comprises a second surface facing the first surface of the wiring board and a third surface opposite to the second surface, A second semiconductor component mounted on a second region of the wiring board, comprising a fourth surface facing the first surface of the wiring board and a fifth surface opposite to the fourth surface, A metal plate disposed on the wiring board, having a sixth surface facing the third surface of the first semiconductor component and the fifth surface of the second semiconductor component, and a seventh surface opposite to the sixth surface, A first adhesive layer is disposed between the third surface of the first semiconductor component and the sixth surface of the metal plate, A second adhesive layer is disposed between the fifth surface of the second semiconductor component and the sixth surface of the metal plate, It has, In a cross-sectional view, when the first surface of the wiring board is used as the reference plane, the height of the third surface of the first semiconductor component is lower than the height of the fifth surface of the second semiconductor component. The aforementioned metal plate is A flange portion bonded to the first surface of the wiring board via a third adhesive layer, A cover portion located above the first semiconductor component and the second semiconductor component, A support portion connecting the flange portion and the cover portion, Equipped with, The cover portion of the metal plate includes a first portion that, in cross-sectional view, has a shape that protrudes toward the first semiconductor component at a position facing the third surface of the first semiconductor component, The seventh surface of the cover portion is A bottom surface which is part of the first portion and is located in a region that overlaps with the first semiconductor component, An eighth surface, which includes an area overlapping with the second semiconductor component, and which is positioned higher than the bottom surface when the first surface of the wiring board is used as the reference surface in a cross-sectional view, One end of the side is connected to the bottom surface, and the other end is connected to the eighth surface, A semiconductor device that includes this component.

2. In the semiconductor device described in claim 1, In a plan view, the base is rectangular. A semiconductor device in which the side surface includes a first side surface connected to the first side of the bottom surface, a second side surface connected to the second side of the bottom surface, and a third side surface connected to the third side of the bottom surface.

3. In the semiconductor device described in claim 2, The aforementioned side surface further includes a fourth side surface connected to the fourth side of the bottom surface, In a plan view, The aforementioned cover portion is rectangular in shape. The flange portion forms a frame shape that surrounds the cover portion, in a semiconductor device.

4. In the semiconductor device described in claim 3, A heat dissipation member having a ninth surface facing the seventh surface of the metal plate, A fourth adhesive layer is bonded to the seventh surface of the metal plate and the ninth surface of the heat dissipation member, It further possesses, A semiconductor device wherein the fourth adhesive layer is bonded to the bottom surface, the side surface, and the eighth surface, respectively.

5. In the semiconductor device according to claim 4, The heat dissipation member includes a protruding portion that has a shape that protrudes toward the metal plate at a position facing the bottom surface of the metal plate, A semiconductor device in which a portion of the protruding portion is disposed within a recess formed by the bottom surface, the first side surface, the second side surface, the third side surface, and the fourth side surface.

6. In the semiconductor device described in claim 2, The bottom surface has a fourth side that is not connected to the side surface, The fourth side is included in the outer edge of the seventh surface of the metal plate, and is a semiconductor device.

7. In the semiconductor device described in claim 1, A heat dissipation member having a ninth surface facing the seventh surface of the metal plate, A fourth adhesive layer is bonded to the seventh surface of the metal plate and the ninth surface of the heat dissipation member, It further possesses, The fourth adhesive layer is bonded to the bottom surface, the side surface, and the eighth surface, A semiconductor device wherein the thickness of the portion of the fourth adhesive layer located on the bottom surface is greater than the thickness of the portion located on the eighth surface.

8. In the semiconductor device described in claim 1, The first semiconductor component is a semiconductor chip, The second semiconductor component is a semiconductor package equipped with a memory circuit, A semiconductor device in which the first semiconductor component and the second semiconductor component are electrically connected via the wiring board.

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