Semiconductor equipment
The integration of pull-up circuits with p-type MOSFETs and resistive elements addresses the challenge of detecting floating ground wires in semiconductor devices, improving reliability and reducing inspection costs by raising potential levels for accurate detection.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS CORP
- Filing Date
- 2024-12-17
- Publication Date
- 2026-06-29
AI Technical Summary
Existing semiconductor devices face challenges in accurately detecting open-circuit defects in ground wiring connections due to floating potential levels, which are difficult to distinguish from ground potential, leading to potential shipment of defective products and high inspection costs.
The implementation of pull-up circuits using p-type MOSFETs and resistive elements connected to ground wires, with controlled gate electrodes, allows for accurate detection of floating ground wires by raising their potential during a test mode, enabling reliable product inspection without extensive visual checks.
This method enhances the reliability of semiconductor devices by accurately identifying floating ground wires, reducing the risk of defective products and minimizing inspection costs through efficient sampling inspections.
Smart Images
Figure 2026106099000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device.
Background Art
[0002] In a semiconductor chip, a first ground wiring and a second ground wiring for supplying a ground potential are provided, and the first ground wiring and the second ground wiring may be individually used in different circuits. In that case, the first ground wiring is electrically connected to a first ground pad, and the second ground wiring is electrically connected to a second ground pad. Here, a double bonding technique is known in which the first ground pad is connected to a lead terminal for the ground potential by a first bonding wire, and the second ground pad is connected to the same lead terminal for the ground potential by a second bonding wire.
[0003] For example, in Patent Document 1, the first ground pad is connected to a lead terminal for the ground potential by a first bonding wire, and a bonding option pad is connected to the same lead terminal for the ground potential by a second bonding wire. Further, switching means having a Pch transistor and an Nch transistor is connected to the bonding option pad, and the on-state and off-state of the Pch transistor and the Nch transistor are alternately switched. The current flowing at that time is measured to detect a connection failure of the bonding wire.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] One of the product inspections for semiconductor devices is an open fault test, which determines whether the wiring is connected to a predetermined circuit and whether a predetermined potential is supplied to that circuit. When the double bonding technology described above is used, the ground potential is supplied to the first and second ground pads from the same lead terminal for the same ground potential.
[0006] Here, for example, due to some malfunction, the first bonding wire may not be connected to the first grounding pad. In that case, the ground potential is not supplied to the first grounding wire and the circuit connected to the first grounding wire, resulting in an open fault. In this case, the potential level of the first grounding wire is at the floating level.
[0007] However, since the floating level is close to the ground potential (0V), there is a problem in that it is difficult to detect open-circuit defects. In other words, there is a risk that semiconductor devices in which the first bonding wire is not connected to the first ground pad may be shipped as good products.
[0008] Another product inspection method is visual inspection, which uses X-rays to visually check the connection status of bonding wires, etc. However, if visual inspection is performed on all semiconductor devices and all bonding wires installed on them, the inspection costs will increase enormously.
[0009] Therefore, there is a need for technology that can accurately detect floating grounding wires and improve the reliability of semiconductor devices.
[0010] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]
[0011] A brief overview of some of the representative embodiments disclosed in this application is as follows:
[0012] In one embodiment, the semiconductor device comprises a semiconductor chip and a first lead terminal to which a ground potential is supplied. The semiconductor chip has a first wiring electrically connected to a first circuit and a first pad, a second wiring electrically connected to a second circuit and a second pad, and a first pull-up circuit including a p-type first MOSFET and a first resistive element. The first lead terminal and the first pad are electrically connected by a first wire, and the first lead terminal and the second pad are electrically connected by a second wire. The first MOSFET has an n-type first well region, a p-type first drain region formed in the first well region, a p-type first source region formed in the first well region, and a first gate electrode formed on the first well region via a first gate insulating film. The first source region and the first well region are supplied with a power supply potential. The first drain region is electrically connected to the first wiring via the first resistive element. The second gate electrode is electrically connected to the first wiring.
[0013] In one embodiment, the semiconductor device comprises a semiconductor chip and a first lead terminal to which a ground potential is supplied. The semiconductor chip has a first wiring electrically connected to a first circuit and a first pad, a second wiring electrically connected to a second circuit and a second pad, and a first pull-up circuit including a p-type first MOSFET and a first resistive element. The first lead terminal and the first pad are electrically connected by a first wire, and the first lead terminal and the second pad are electrically connected by a second wire. The first MOSFET has an n-type first well region, a p-type first drain region formed in the first well region, a p-type first source region formed in the first well region, and a first gate electrode formed on the first well region via a first gate insulating film. The first source region and the first well region are supplied with a power supply potential. The first drain region is electrically connected to the first wiring via the first resistive element. The semiconductor chip has a normal operating mode and a test mode. The first gate electrode is supplied with a test mode signal generated during the test mode. [Effects of the Invention]
[0014] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]
[0015] [Figure 1] Figure 1 is a schematic plan view showing a semiconductor device in Embodiment 1. [Figure 2] Figure 2 is an equivalent circuit diagram showing the pull-up circuit in Embodiment 1. [Figure 3] Figure 3 is a cross-sectional view showing the MOSFET in Embodiment 1. [Figure 4] Figure 4 is an equivalent circuit diagram showing the effect of the pull-up circuit in Embodiment 1. [Figure 5] Figure 5 is a graph showing the potential change when the product inspection was performed as shown in Figure 4. [Figure 6]FIG. 6 is an equivalent circuit diagram showing the effect of the pull-up circuit in Embodiment 1. [Figure 7] FIG. 7 is a graph showing the potential change when product inspection is performed in FIG. 6. [Figure 8] FIG. 8 is a schematic plan view for explaining product inspection. [Figure 9] FIG. 9 is an equivalent circuit diagram showing the pull-up circuit in Embodiment 2. [Figure 10] FIG. 10 is a schematic plan view showing the semiconductor device in Study Example 1. [Figure 11] FIG. 11 is an equivalent circuit diagram showing the pull-up circuit in Study Example 2. [Figure 12] FIG. 12 is an equivalent circuit diagram showing the pull-up circuit in Study Example 3.
MODE FOR CARRYING OUT THE INVENTION
[0016] Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same function are denoted by the same reference numerals, and repeated explanations thereof are omitted. In the following embodiments, explanations of the same or similar parts are not repeated in principle unless particularly necessary.
[0017] In addition, the X direction, Y direction, and Z direction described in the present application intersect each other and are orthogonal to each other. In the present application, the Z direction is described as the vertical direction, depth direction, or thickness direction of a certain structure. Also, expressions such as "plan view" or "plan view" used in the present application mean that the plane composed of the X direction and the Y direction is the "plane", and this "plane" is viewed from the Z direction.
[0018] (Embodiment 1) <Planar layout of semiconductor device> Hereinafter, the planar layout of the semiconductor device 100 in Embodiment 1 will be described with reference to FIG. 1.
[0019] As shown in Figure 1, the semiconductor device 100 comprises a semiconductor chip CHP, a plurality of lead terminals LD, a plurality of wires BW, and a sealing resin MR.
[0020] The semiconductor chip CHP comprises multiple circuits and multiple wirings. Figure 1 illustrates several of these circuits, including multiple port circuits C1, multiple circuits C2, and pull-up circuits PUC1 and PUC2. Circuit C2 is, for example, a port circuit or an analog circuit. Figure 1 also illustrates two of these wirings, grounding wiring VSS1 and VSS2.
[0021] The semiconductor chip CHP has multiple pads PA. The semiconductor chip CHP has a multilayer wiring layer above the semiconductor substrate SUB, and the multiple pads PA are part of multiple wirings provided in the uppermost layer of the multilayer wiring layer. Each of the multiple pads PA is electrically connected to multiple port circuits C1 and multiple circuits C2, and supplies the signals necessary for the operation of multiple port circuits C1 and multiple circuits C2. Among the multiple pads PA, ground pad PA1 and ground pad PA2 are provided to supply ground potential from outside the semiconductor chip CHP to the inside of the semiconductor chip CHP.
[0022] Grounding wire VSS1 is electrically connected to multiple port circuits C1 and grounding pad PA1. Ground potential is supplied to the multiple port circuits C1 from grounding pad PA1 via grounding wire VSS1. Grounding wire VSS2 is electrically connected to multiple circuits C2 and grounding pad PA2. Ground potential is supplied to the multiple circuits C2 from grounding pad PA2 via grounding wire VSS2. Grounding wires VSS1 and VSS2 are electrically isolated within the semiconductor chip CHP.
[0023] Furthermore, pull-up circuits PUC1 and PUC2 are electrically connected to grounding wires VSS1 and VSS2. The specific configurations of pull-up circuits PUC1 and PUC2 will be described in detail later.
[0024] Multiple lead terminals LD are arranged separately from each other outside the semiconductor chip CHP and are each made of a metallic material such as a copper alloy. Of the multiple lead terminals LD, the ground lead terminal LD1 is provided to supply ground potential to ground pads PA1 and PA2. Ground potential is supplied to the ground lead terminal LD1 from outside the semiconductor device 100.
[0025] Multiple lead terminals LD and multiple pads PA are electrically connected by multiple wires BW. Each of the multiple wires BW is made of, for example, gold, copper, or aluminum. The multiple wires BW include grounding wire BW1 and grounding wire BW2. Grounding lead terminal LD1 and grounding pad PA1 are electrically connected by grounding wire BW1. Grounding lead terminal LD1 and grounding pad PA2 are electrically connected by grounding wire BW2.
[0026] The semiconductor chip CHP, multiple lead terminals LD, and multiple wires BW are sealed by a sealing resin MR. A portion of each of the multiple lead terminals LD is exposed to the outside of the sealing resin MR. The sealing resin MR is made of a thermosetting resin material, such as epoxy resin.
[0027] The pull-up circuits PUC1 and PUC2 in Embodiment 1 will be described below with reference to Figure 2.
[0028] The pull-up circuit PUC1 includes a p-type MOSFET1Q and a resistor R1. The source region PS and well region NW1 of MOSFET1Q are supplied with the power supply potential Vdd. The drain region PD of MOSFET1Q is electrically connected to the ground wire VSS1 via the resistor R1. The gate electrode GEp of MOSFET1Q is electrically connected to the ground wire VSS2.
[0029] The pull-up circuit PUC2 includes a p-type MOSFET 2Q and a resistor R2. The source region PS and well region NW2 of MOSFET 2Q are supplied with the power supply potential Vdd. The drain region PD of MOSFET 2Q is electrically connected to the ground wire VSS2 via the resistor R2. The gate electrode GEp of MOSFET 2Q is electrically connected to the ground wire VSS1.
[0030] The cross-sectional structures of p-type MOSFET1Q, p-type MOSFET2Q, n-type MOSFET3Q, and n-type MOSFET4Q are described below with reference to Figure 3.
[0031] As shown in Figure 3, the semiconductor substrate SUB is made of, for example, p-type silicon. An element isolation section STI is formed in the semiconductor substrate SUB. The element isolation section STI includes a groove formed in the semiconductor substrate SUB so as to reach a predetermined depth from the upper surface of the semiconductor substrate SUB, and an insulating film embedded inside the groove. The insulating film is, for example, a silicon oxide film.
[0032] An n-type well region DNW is formed in the semiconductor substrate SUB. Within the well region DNW, a p-type well region PW1 and a p-type well region PW2 are formed. Within well region PW1, an n-type well region NW1 is formed. Within well region PW2, an n-type well region NW2 is formed. Well regions NW1 and NW2 are electrically isolated. Well regions PW1 and PW2 are electrically isolated.
[0033] A gate electrode Gep is formed on well region NW1 and well region NW2, respectively, via a gate insulating film GI. A gate electrode Gen is formed on well region PW1 and well region PW2, respectively, via a gate insulating film GI. The gate insulating film GI is, for example, a silicon oxide film. The gate electrode Gep is, for example, a p-type polycrystalline silicon film. The gate electrode Gen is, for example, an n-type polycrystalline silicon film.
[0034] In well region NW1 and well region NW2, a p-type source region PS and a p-type drain region PD are formed, respectively. In well region PW1 and well region PW2, an n-type source region NS and an n-type drain region ND are formed, respectively.
[0035] MOSFET1Q has a well region NW1, a gate insulating film GI, a gate electrode GEp, a source region PS, and a drain region PD. MOSFET2Q has a well region NW2, a gate insulating film GI, a gate electrode GEp, a source region PS, and a drain region PD. MOSFET3Q has a well region PW1, a gate insulating film GI, a gate electrode GEn, a source region NS, and a drain region ND. MOSFET4Q has a well region PW2, a gate insulating film GI, a gate electrode GEn, a source region NS, and a drain region ND.
[0036] The pull-up circuits PUC1 and PUC2 are provided to check whether the ground lead terminal LD1 and ground pad PA1 are connected by the ground wire BW1, and whether the ground lead terminal LD1 and ground pad PA2 are connected by the ground wire BW2, when double bonding technology is performed.
[0037] There is a challenge in how to set the control signals for controlling the on and off states of these pull-up circuits PUC1 and PUC2. The inventors of this invention have considered the following examples of their investigations into this issue.
[0038] <Example 1> In Example 1, control signals are supplied from outside the semiconductor device 100. As shown in Figure 10, additional components are provided to supply the control signals: a lead terminal LD3, a wire BW3, a pad PA3, and a port circuit C1. Control signals are supplied from outside the semiconductor device 100 via the lead terminal LD3, wire BW3, pad PA3, and port circuit C1 to the gate electrode Gep of MOSFET1Q of pull-up circuit PUC1 and the gate electrode Gep of MOSFET2Q of pull-up circuit PUC2.
[0039] However, in Example 1, a reassessment of the chip layout is necessary to implement the additional configuration. Furthermore, space is required to accommodate pad PA3 and lead terminal LD3; if such space is not already available, Example 1 cannot be applied.
[0040] <Example 2> In Example 2, as shown in Figure 11, not only the drain region PD of MOSFET1Q but also the gate electrode GEp of MOSFET1Q is electrically connected to the grounding wire VSS1.
[0041] In this state, if the ground lead terminal LD1 and ground pad PA1 are not connected, the potential of the ground wiring VSS1 becomes a floating level. In that case, a floating level potential is input to the gate electrode GEp of MOSFET1Q, and in that case, there is a risk that the pull-up circuit PUC1 will not function properly. Therefore, in Embodiment 1, as shown in Figure 2, the gate electrode GEp of MOSFET1Q is electrically connected to the ground wiring VSS2, and the gate electrode GEp of MOSFET2Q is electrically connected to the ground wiring VSS1.
[0042] <Example 3 of consideration> In Example 3, as shown in Figure 12, a bidirectional diode BD is provided between the grounding wire VSS1 and the grounding wire VSS2 to short-circuit them. The bidirectional diode BD consists of two diodes, for example, one with an anode electrically connected to the cathode of the other, and the other with an anode electrically connected to the cathode of the first diode.
[0043] If such a bidirectional diode BD is provided, the potentials of the grounding wires VSS1 and VSS2 will be made common. As a result, it will become impossible to check the connection status of the grounding lead terminal LD1 and the grounding pad PA1, and the connection status of the grounding lead terminal LD1 and the grounding pad PA2. Therefore, in Embodiment 1, as shown in Figure 2, a bidirectional diode BD is not provided between the grounding wires VSS1 and VSS2.
[0044] Furthermore, if MOSFET1Q and MOSFET2Q are formed in the same well region, the potentials of the grounding wires VSS1 and VSS2 are made common. Therefore, in Embodiment 1, as shown in Figure 3, well region NW1 and well region NW2 are electrically isolated.
[0045] <Effects of pull-up circuits> Figure 4 shows the state where the grounding lead terminal LD1 and grounding pad PA1 are disconnected, and the potential of the grounding wiring VSS1 is at a floating level.
[0046] The ground potential is supplied to the grounding wire VSS2. Consequently, MOSFET1Q of the pull-up circuit PUC1 turns on, and the potential of the grounding wire VSS1 rises, as shown in Figure 5. By performing a conventional product inspection in this state, the tester can determine if there is an abnormality in the input / output potential of the port circuit C1 connected to the grounding wire VSS1. Therefore, the grounding wire VSS1, which is at a floating level, can be accurately detected, and it can be determined that the grounding lead terminal LD1 and grounding pad PA1 are not connected.
[0047] Figure 6 shows the state where the grounding lead terminal LD1 and grounding pad PA2 are disconnected, and the potential of the grounding wiring VSS2 is at a floating level.
[0048] The ground potential is supplied to the grounding wire VSS1. Consequently, MOSFET2Q of the pull-up circuit PUC2 turns ON, and the potential of the grounding wire VSS2 rises, as shown in Figure 7. By performing a conventional product inspection in this state, the tester can determine if there is an abnormality in the input / output potential of circuit C2 connected to the grounding wire VSS2. Therefore, the grounding wire VSS2, which is at a floating level, can be accurately detected, and it can be determined that the grounding lead terminal LD1 and grounding pad PA2 are not connected.
[0049] In this way, the pull-up circuits PUC1 and PUC2 allow for accurate detection of the floating-level ground wire VSS1 or ground wire VSS2, thereby improving the reliability of the semiconductor device 100.
[0050] Furthermore, processes such as performing visual inspections on all semiconductor devices 100 and all wires BW provided on them can be simplified, for example, by implementing sampling inspections. Consequently, increases in inspection costs can be suppressed.
[0051] The following describes the test operations performed during product inspection using Figure 8. The semiconductor chip CHP includes multiple circuits C3, such as the CPU, memory, and peripheral circuits, in addition to the port circuits C1 and C2. These multiple circuits C3 operate by exchanging signals with each other via an address bus or data bus, etc. During product inspection, specific signals are supplied to the semiconductor chip CHP from an external tester device 10 of the semiconductor device 100, for example, via lead terminals LD, wires BW, pads PA, and port circuit C1.
[0052] The semiconductor chip CHP has a normal operating mode and a test mode for setting up multiple circuits in an operational state suitable for testing during product inspection. When a specific signal is supplied to the semiconductor chip CHP from the tester device 10, a "test mode signal" that indicates the selection of a test mode within the semiconductor chip CHP becomes active. The multiple circuits C3 that receive the "test mode signal" are set to test mode, and then the appropriate tests are performed.
[0053] (Embodiment 2) The semiconductor device 100 in Embodiment 2 will be described below with reference to Figure 9. Note that the following description will mainly focus on the differences from Embodiment 1, and will omit explanations of points that overlap with Embodiment 1.
[0054] As shown in Figure 9, in Embodiment 2, the test mode signal generated during test mode is used to drive the pull-up circuits PUC1 and PUC2.
[0055] During product inspection, a specific signal is supplied from an external tester device 10 to the semiconductor chip CHP of the semiconductor device 100, causing it to switch from normal operation mode to test mode. At that time, a test mode signal Vtes, which is, for example, at ground potential, is supplied to the gate electrodes Gep of MOSFET1Q and MOSFET2Q, causing MOSFET1Q and MOSFET2Q to turn on.
[0056] In Embodiment 2 as well, when the grounding lead terminal LD1 and grounding pad PA2 are disconnected, the pull-up circuit PUC2 raises the potential of the floating grounding wire VSS2. Therefore, the floating grounding wire VSS2 can be accurately detected during product inspection.
[0057] Furthermore, if the grounding lead terminal LD1 and grounding pad PA1 are disconnected, the pull-up circuit PUC1 raises the potential of the floating grounding wire VSS1. Therefore, the floating grounding wire VSS1 can be accurately detected during product inspection.
[0058] Furthermore, if the ground lead terminal LD1 and ground pad PA1 are disconnected, and the ground lead terminal LD1 and ground pad PA2 are also disconnected, both the ground wiring VSS1 and ground wiring VSS2 will be at a floating level. In this case, in the configuration of Embodiment 1, a floating-level potential is input to the gate electrode Gep of each of MOSFET1Q. That is, both the pull-up circuit PUC1 and the pull-up circuit PUC2 will have the configuration of Example 2 in Figure 11. Therefore, there is a risk that both the pull-up circuit PUC1 and the pull-up circuit PUC2 will not function properly.
[0059] In Embodiment 2, a test mode signal Vtes is used to drive MOSFET1Q and MOSFET2Q. Therefore, even if both grounding wires VSS1 and VSS2 are at a floating level, both pull-up circuits PUC1 and PUC2 can function normally. Pull-up circuit PUC1 raises the potential of grounding wire VSS1, which is at a floating level, and pull-up circuit PUC2 raises the potential of grounding wire VSS2, which is at a floating level. Thus, in product inspection, both grounding wires VSS1 and VSS2, which are at a floating level, can be accurately detected.
[0060] Except when a specific signal is supplied from the tester device 10 to the semiconductor chip CHP, the potentials of the gate electrodes Gep of MOSFET1Q and MOSFET2Q are at a floating level. Therefore, after the semiconductor device 100 is shipped, the pull-up circuits PUC1 and PUC2 will no longer function.
[0061] Although the present invention has been specifically described above based on the embodiments described above, the present invention is not limited to the embodiments described above and can be modified in various ways without departing from the spirit of the invention. [Explanation of Symbols]
[0062] 100 Semiconductor Equipment 10 Tester device 1Q, 2Q p-type MOSFETs 3Q, 4Q n-type MOSFETs BD bidirectional diode BW, BW3 Wire BW1, BW2 Grounding wires C1 port circuit C2, C3 circuit CHP semiconductor chip DNW n-type well region GEn n-type gate electrode GEp p-type gate electrode GI gate insulating film LD, LD3 lead terminals LD1 Ground lead terminal MR sealing resin ND n-type drain region Source area of type NS n NW1, NW2 n-type well regions PA, PA3 pads PA1, PA2 grounding pads PD p-type drain region PS p-type source area PUC1, PUC2 pull-up circuit PW1, PW2 p-type well regions R1, R2 Resistor elements SUB Semiconductor Substrate STI element isolation section VSS1, VSS2 grounding wiring
Claims
1. Semiconductor chips and A first lead terminal to which ground potential is supplied, Equipped with, The aforementioned semiconductor chip is The first circuit and The second circuit and First pad and, The second pad and The first circuit and the first pad are electrically connected to the first wiring, The second circuit and the second pad are electrically connected to the second wiring, A first pull-up circuit including a p-type first MOSFET and a first resistive element, It has, The first lead terminal and the first pad are electrically connected by a first wire. The first lead terminal and the second pad are electrically connected by the second wire. The first and second wirings are electrically isolated within the semiconductor chip. The first MOSFET is An n-type first well region formed in a semiconductor substrate, A p-type first drain region formed in the first well region, A p-type first source region formed in the first well region, A first gate electrode formed on the first well region via a first gate insulating film, It has, The first source region and the first well region are supplied with a power supply potential. The first drain region is electrically connected to the first wiring via the first resistive element. A semiconductor device in which the first gate electrode is electrically connected to the second wiring.
2. In the semiconductor device described in claim 1, The semiconductor chip further includes a second pull-up circuit comprising a p-type second MOSFET and a second resistive element. The second MOSFET is An n-type second well region formed in the semiconductor substrate, A p-type second drain region formed in the second well region, A p-type second source region formed in the second well region, A second gate electrode formed on the second well region via a second gate insulating film, It has, The second source region and the second well region are supplied with a power potential. The second drain region is electrically connected to the second wiring via the second resistive element. The second gate electrode is electrically connected to the first wiring in a semiconductor device.
3. In the semiconductor device described in claim 2, A semiconductor device in which the first well region and the second well region are electrically isolated.
4. In the semiconductor device described in claim 1, The first circuit is a port circuit, which is a semiconductor device.
5. In the semiconductor device according to claim 4, The second circuit is a port circuit or an analog circuit, and is a semiconductor device.
6. In the semiconductor device described in claim 1, A semiconductor device in which a bidirectional diode is not provided between the first wiring and the second wiring to short-circuit the first wiring and the second wiring.
7. In the semiconductor device described in claim 1, A semiconductor device in which the first pad and the second pad are each part of the wiring provided in the uppermost layer of a multilayer wiring layer formed above the semiconductor substrate.
8. Semiconductor chips and A first lead terminal to which ground potential is supplied, Equipped with, The aforementioned semiconductor chip is The first circuit and The second circuit and First pad and, The second pad and The first circuit and the first pad are electrically connected to the first wiring, The second circuit and the second pad are electrically connected to the second wiring, A first pull-up circuit including a p-type first MOSFET and a first resistive element, It has, The first lead terminal and the first pad are electrically connected by a first wire. The first lead terminal and the second pad are electrically connected by the second wire. The first and second wirings are electrically isolated within the semiconductor chip. The first MOSFET is An n-type first well region formed in a semiconductor substrate, A p-type first drain region formed in the first well region, A p-type first source region formed in the first well region, A first gate electrode formed on the first well region via a first gate insulating film, It has, The first source region and the first well region are supplied with a power supply potential. The first drain region is electrically connected to the first wiring via the first resistive element. The semiconductor chip has a normal operating mode and a test mode. A semiconductor device to which the first gate electrode is supplied with a test mode signal generated during the test mode.
9. In the semiconductor device described in claim 8, The semiconductor chip further includes a second pull-up circuit comprising a p-type second MOSFET and a second resistive element. The second MOSFET is An n-type second well region formed in the semiconductor substrate, A p-type second drain region formed in the second well region, A p-type second source region formed in the second well region, A second gate electrode formed on the second well region via a second gate insulating film, It has, The second source region and the second well region are supplied with a power potential. The second drain region is electrically connected to the second wiring via the second resistive element. A semiconductor device to which the test mode signal is supplied to the second gate electrode.
10. In the semiconductor device described in claim 9, A semiconductor device in which a specific signal is supplied to the semiconductor chip from an external tester device, causing it to switch from the normal operating mode to the test mode, and the test mode signal is supplied to the first gate electrode and the second gate electrode.
11. In the semiconductor device described in claim 9, A semiconductor device in which, except when the specific signal is supplied to the semiconductor chip from the tester device, the potentials of the first gate electrode and the second gate electrode are at a floating level.
12. In the semiconductor device described in claim 9, A semiconductor device in which the first well region and the second well region are electrically isolated.
13. In the semiconductor device described in claim 8, The first circuit is a port circuit, which is a semiconductor device.
14. In the semiconductor device according to claim 13, The second circuit is a port circuit or an analog circuit, and is a semiconductor device.
15. In the semiconductor device described in claim 8, A semiconductor device in which a bidirectional diode is not provided between the first wiring and the second wiring to short-circuit the first wiring and the second wiring.
16. In the semiconductor device described in claim 8, A semiconductor device in which the first pad and the second pad are each part of the wiring provided in the uppermost layer of a multilayer wiring layer formed above the semiconductor substrate.