Manufacturing method for semiconductor devices

Abstract

To improve the reliability of semiconductor devices. [Solution] The method for manufacturing a semiconductor device includes the steps of: forming a liner film LN so as to cover a first gate electrode and a second gate electrode; forming an insulating film on the liner film LN, and then performing anisotropic dry etching on the insulating film to expose the liner film LN located on the first gate electrode and the second gate electrode, thereby forming a buried layer BZ between the first gate electrode and the second gate electrode; forming an interlayer insulating film IL1 on the buried layer BZ; forming contact holes CH within the interlayer insulating film IL1, within the buried layer BZ, and within the liner film LN, and forming plug electrodes PG within the contact holes CH.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique effective when applied to a method for manufacturing a semiconductor device including a flash memory.

Background Art

[0002] As a nonvolatile memory that can be electrically written and erased, an EEPROM (Electrically Erasable and Programable Read Only Memory) is widely used. As an EEPROM incorporated in a microcontroller, there is an example using a split gate type MONOS (Metal Oxide Nitride Oxide Semiconductor) memory.

[0003] Japanese Patent Application Laid-Open No. 2018-56222 (Patent Document 1) describes a technique related to a split gate type MONOS (Metal Oxide Nitride Oxide Semiconductor) memory.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The inventor of the present application has confirmed the following problems in a semiconductor device including a plurality of split gate type MONOS memories arranged in a matrix.

[0006] A split-gate type MONOS memory comprises a drain region and a source region formed in a semiconductor substrate, a control gate electrode formed on the semiconductor substrate via a gate insulating film, and a memory gate electrode formed on the semiconductor substrate via a charge-holding film. An interlayer insulating film is formed on the semiconductor substrate, filling the spaces between adjacent control gate electrodes, and plug electrodes are formed within the interlayer insulating film. The plug electrodes electrically connect the drain region and the bit line. Between adjacent control gate electrodes, a plurality of plug electrodes are arranged at predetermined intervals along the extending direction of the control gate electrode.

[0007] As semiconductor devices become smaller, the spacing between adjacent control gate electrodes decreases. It has been confirmed that voids occur within the interlayer insulating film between adjacent control gate electrodes. When these voids occur between adjacent plug electrodes, adjacent bit lines short-circuit. This is because, during the process of forming the plug electrodes, a metal layer is also formed within the void. This issue is also recognized in the aforementioned Japanese Patent Application Publication No. 2018-56222 (Patent Document 1).

[0008] In split-gate MONOS memory, there is a need for technology to prevent short circuits between adjacent bit lines. In other words, there is a need for technology to improve the reliability of semiconductor devices.

[0009] Other challenges and novel features will become apparent from the description and accompanying drawings in this specification. [Means for solving the problem]

[0010] A method for manufacturing a semiconductor device in one embodiment includes the steps of forming a first insulating film so as to cover a first gate electrode and a second gate electrode, and forming a second insulating film on the first insulating film. Furthermore, the method for manufacturing a semiconductor device includes the step of exposing the first insulating film located on the first gate electrode and the second gate electrode by performing anisotropic dry etching on the second insulating film, and forming a buried layer between the first gate electrode and the second gate electrode. Furthermore, the method for manufacturing a semiconductor device includes the steps of forming a third insulating film on the buried layer, forming contact holes in the third insulating film, in the buried layer and in the first insulating film, and forming a conductive layer in the contact holes. [Effects of the Invention]

[0011] According to one embodiment, the reliability of semiconductor devices can be improved. [Brief explanation of the drawing]

[0012] [Figure 1] This is a cross-sectional view of a main part of a semiconductor device according to one embodiment. [Figure 2] This is a plan view of the main part of a semiconductor device according to one embodiment. [Figure 3] This is a cross-sectional view showing the manufacturing process of a semiconductor device according to one embodiment. [Figure 4] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 3. [Figure 5] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 4. [Figure 6] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 5. [Figure 7] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 6. [Figure 8] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 7. [Figure 9] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 8. [Figure 10] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 9. [Figure 11] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 10. [Figure 12] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 11. [Figure 13] It is a cross-sectional view showing the manufacturing process of the semiconductor device following FIG. 12. [Figure 14] It is a cross-sectional view showing the manufacturing process of the semiconductor device of Modification 1. [Figure 15] It is a cross-sectional view showing the manufacturing process of the semiconductor device of Modification 2.

Embodiments for Carrying Out the Invention

[0013] In all the drawings for explaining the embodiments, the same members are generally denoted by the same reference numerals, and the repeated explanations thereof are omitted.

[0014] Also, in the following embodiments, N-type means the N-type conductivity type, and P-type means the P-type conductivity type. Also, the P-type impurity region can be read as a P-type semiconductor region, and the N-type impurity region can be read as an N-type semiconductor region.

[0015] The X direction and the Y direction are along the main surface of the semiconductor substrate and are perpendicular to each other.

[0016] (Embodiment) The semiconductor device in the present embodiment includes a plurality of memory cells. Each of the plurality of memory cells is composed of a split-gate type MONOS memory, and the memory cell array is composed of a plurality of memory cells. On the main surface of the semiconductor substrate SB, the plurality of memory cells constituting the memory cell array are arranged in a matrix in the X direction and the Y direction. FIG. 2 is a plan view of the memory cell array. FIG. 1 shows a cross-sectional view of the semiconductor device along the bit line BL in the region AR and a cross-sectional view of the semiconductor device along the source line SL in the region BR.

[0017] As shown in Figure 2, on the main surface of the semiconductor substrate SB, multiple control gate electrodes CG and multiple memory gate electrodes MG extend in the Y direction. Multiple bit lines BL and multiple source lines SL extend in the X direction. The drain region DR of the memory cell is electrodeally connected to the bit line BL via a plug electrode PG. The source region SR of the memory cell is electrodeally connected to the source line SL via a plug electrode PG. In a plan view, the drain region DR is located between two adjacent control gate electrodes CG in the X direction and between two adjacent shallow groove isolation regions ST in the Y direction. In a plan view, the source region SR is located between two adjacent memory gate electrodes MG in the X direction and extends in the Y direction.

[0018] In region AR, two adjacent memory cells in the X direction share a drain region DR and are arranged symmetrically with respect to the drain region DR. Similarly, in region BR, two adjacent memory cells in the X direction share a source region SR and are arranged symmetrically with respect to the source region SR. To extend the source region SR in the Y direction, the source region SR is positioned between two adjacent shallow groove isolation sections ST in the X direction. Therefore, in the X direction, the distance D2 between two adjacent memory gate electrodes MG is greater than the distance D1 between two adjacent control gate electrodes CG (D2 > D1).

[0019] As shown in Figure 1, a memory cell includes a drain region DR, a source region SR, a gate insulating film GI, a control gate electrode CG, an insulating film MZ, a memory gate electrode MG, and a cap insulating film CP. The drain region DR and the source region SR are arranged at a predetermined interval within the semiconductor substrate SB. A channel formation region is located between the drain region DR and the source region SR. The control gate electrode CG and the memory gate electrode MG are formed on the channel formation region. The control gate electrode CG is formed on the main surface of the semiconductor substrate SB via the gate insulating film GI. The memory gate electrode MG is formed on the main surface of the semiconductor substrate SB via the insulating film MZ. In cross-sectional view, the insulating film MZ has an L-shape and is located between the control gate electrode CG and the memory gate electrode MG, and between the memory gate electrode MG and the main surface of the semiconductor substrate SB. While the insulating film MZ is formed between the semiconductor substrate SB and the memory gate electrode MG, an insulating film different from the insulating film MZ may be formed between the control gate electrode CG and the memory gate electrode MG. The control gate electrode CG is located between the drain region DR and the memory gate electrode MG, and the memory gate electrode MG is located between the control gate electrode CG and the source region SR. A cap insulating film CP is also formed on the control gate electrode CG. A stacked structure including a control gate electrode CG and a cap insulating film CP is called a "gate electrode." The drain region DR and source region SR each contain an N-type impurity region NM and an N-type impurity region NH, respectively. A silicide layer SC is formed on the drain region DR. A silicide layer SC is formed on the source region SR. Furthermore, a silicide layer SC is formed on the memory gate electrode MG.

[0020] The main surface and memory cells of the semiconductor substrate SB are covered with a liner film LN, an interlayer insulating film IL1, and an interlayer insulating film IL2. The liner film LN is formed on the gate electrode and the memory gate electrode MG so as to cover the memory cells. The interlayer insulating film IL1 is formed on the liner film LN. The interlayer insulating film IL2 is formed on the interlayer insulating film IL1.

[0021] In region AR, the bit line BL is electrically connected to the drain region DR via the plug electrode PG. In the region between two adjacent gate electrodes, the liner film LN, the embedding layer BZ, the interlayer insulating film IL1, and the interlayer insulating film IL2 are formed on the drain region DR. The embedding layer BZ, located on the drain region DR, covers the liner film LN and is formed between the liner film LN and the interlayer insulating film IL1. The plug electrode PG is formed in the contact hole CH that penetrates the interlayer insulating film IL2, the interlayer insulating film IL1, the embedding layer BZ, and the liner film LN. The bit line BL is formed on the interlayer insulating film IL2. The liner film LN located on the gate electrode is in contact with the interlayer insulating film IL1. In other words, the embedding layer BZ does not exist on the liner film LN located on the gate electrode.

[0022] In region BR, the source line SL is electrically connected to the source region SR via the plug electrode PG. In the region between two adjacent memory gate electrodes MG, a liner film LN, an interlayer insulating film IL1, and an interlayer insulating film IL2 are formed on the source region SR. The plug electrode PG is formed in a contact hole CH that penetrates the interlayer insulating film IL2, the interlayer insulating film IL1, and the liner film LN. As described above, the two memory cells share the source region SR and are arranged symmetrically with respect to the source region SR. Two memory cells are located on both sides of the plug electrode PG connected to the source region SR. Two insulating films IF3A are formed on the source region SR, and the plug electrode PG is positioned between the two insulating films IF3A. One insulating film IF3A is selectively formed on the liner film LN formed on the sidewall of the memory gate electrode MG of one memory cell. The other insulating film IF3A is selectively formed on the liner film LN formed on the sidewall of the memory gate electrode MG of the other memory cell. The two insulating films IF3A on the source region SR are separated from each other. As will be described later, the insulating film IF3A is formed during the formation process of the embedded layer BZ. In region BR, the distance D2 between two adjacent memory gate electrodes MG is greater than the distance D1 between two adjacent gate electrodes in region AR. Therefore, the two insulating films IF3A on the source region SR are formed separately.

[0023] Next, the manufacturing method of the semiconductor device according to this embodiment will be described with reference to Figures 1 and 3 to 13.

[0024] First, as shown in Figure 3, an insulating film IF1, a silicon film SF, and an insulating film IF2 are formed on the main surface of the semiconductor substrate SB. The semiconductor substrate SB is made of, for example, P-type single-crystal silicon. The insulating film IF1 is made of, for example, a silicon oxide film. The insulating film IF1 may include a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The silicon film SF is made of, for example, a polycrystalline silicon film, and the polycrystalline silicon film is deposited on the insulating film IF1 using the CVD method. The insulating film IF3 is made of, for example, a silicon nitride film, and the silicon nitride film is deposited on the silicon film SF using the CVD method.

[0025] Next, as shown in Figure 3, a mask layer MK1 having a desired pattern is formed on the insulating film IF2. The mask layer MK1 is made of, for example, a photoresist film. The mask layer MK1 has a pattern corresponding to the gate electrode.

[0026] Next, as shown in Figure 4, the insulating film IF2, silicon film SF, and insulating film IF1 exposed from the mask layer MK1 are removed using a dry etching method. Then, a gate electrode consisting of a control gate electrode CG and a cap insulating film CP formed on the control gate electrode CG is formed on the gate insulating film GI.

[0027] In region AR, a first gate electrode and a second gate electrode are formed on the main surface of the semiconductor substrate SB, from left to right. The first gate electrode includes a first sidewall and a second sidewall located opposite the first sidewall, and both the first and second sidewalls extend in the Y direction. The second gate electrode includes a third sidewall and a fourth sidewall located opposite the third sidewall, and both the third and fourth sidewalls extend in the Y direction. The second sidewall of the first gate electrode faces the third sidewall of the second gate electrode.

[0028] In region BR, a third gate electrode and a fourth gate electrode are formed on the main surface of the semiconductor substrate SB, from left to right. The third gate electrode includes a fifth sidewall and a sixth sidewall located opposite the fifth sidewall, with the fifth and sixth sidewalls extending in the Y direction. The fourth gate electrode includes a seventh sidewall and an eighth sidewall located opposite the seventh sidewall, with the seventh and eighth sidewalls extending in the Y direction. The sixth sidewall of the third gate electrode faces the seventh sidewall of the fourth gate electrode.

[0029] Next, as shown in Figure 5, an insulating film (also called a charge-holding film) MZ and a memory gate electrode MG are formed on the main surface of the semiconductor substrate SB. The insulating film MZ includes, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate electrode MG is made of, for example, a polycrystalline silicon film.

[0030] In region AR, the first memory gate electrode MG is formed on the first sidewall of the first gate electrode and on the main surface of the semiconductor substrate SB via an insulating film MZ. Furthermore, the second memory gate electrode MG is formed on the fourth sidewall of the second gate electrode and on the main surface of the semiconductor substrate SB via an insulating film MZ.

[0031] In region BR, the third memory gate electrode MG is formed on the sixth sidewall of the third gate electrode and on the main surface of the semiconductor substrate SB via an insulating film MZ. Furthermore, the fourth memory gate electrode MG is formed on the seventh sidewall of the fourth gate electrode and on the main surface of the semiconductor substrate SB via an insulating film MZ.

[0032] Next, as shown in Figure 6, a drain region DR and a source region SR are formed within the semiconductor substrate SB. In region AR, an N-type impurity region NM is formed between the first gate electrode and the second gate electrode in a plan view within the semiconductor substrate SB. Similarly, in region BR, an N-type impurity region NM is formed between the third memory gate electrode MG and the fourth memory gate electrode MG in a plan view within the semiconductor substrate SB. The N-type impurity region NM is formed using methods such as ion implantation. That is, for example, an N-type impurity such as As (arsenic) or P (phosphorus) is introduced into the semiconductor substrate SB.

[0033] Next, in region AR, a sidewall insulating film SW is formed on the second sidewall of the first gate electrode and on the third sidewall of the second gate electrode, respectively. Also, in region BR, a sidewall insulating film SW is formed on the sidewall of the third memory gate electrode MG and on the sidewall of the fourth memory gate electrode MG, respectively.

[0034] Next, in region AR, an N-type impurity region NH is formed within the semiconductor substrate SB between the sidewall insulating film SW on the second sidewall of the first gate electrode and the sidewall insulating film SW on the third sidewall of the second gate electrode in a plan view. Furthermore, in region BR, an N-type impurity region NH is formed within the semiconductor substrate SB between the sidewall insulating film SW on the sidewall of the third memory gate electrode MG and the sidewall insulating film SW on the sidewall of the fourth memory gate electrode MG in a plan view. The N-type impurity region NH is formed using methods such as ion implantation. That is, for example, an N-type impurity such as As (arsenic) or P (phosphorus) is introduced into the semiconductor substrate SB. The impurity concentration in the N-type impurity region NH is higher than the impurity concentration in the N-type impurity region NM.

[0035] Through the above process, in region AR, a drain region DR is formed between the first gate electrode and the second gate electrode in a plan view, and includes an N-type impurity region NM and an N-type impurity region NH within the semiconductor substrate SB. In region BR, a source region SR is formed between the third memory gate electrode MG and the fourth memory gate electrode MG in a plan view, and includes an N-type impurity region NM and an N-type impurity region NH within the semiconductor substrate SB.

[0036] Next, as shown in Figure 7, a silicide layer SC is formed. In region AR, the silicide layer SC is formed on the drain region DR, the first memory gate electrode MG, and the second memory gate electrode MG. In region BR, the silicide layer SC is formed on the source region SR, the third memory gate electrode MG, and the fourth memory gate electrode MG. The silicide layer SC is made of, for example, an alloy film of Ni (nickel) and Pt (platinum).

[0037] Next, as shown in Figure 8, a liner film LN is formed on the main surface of the semiconductor substrate SB so as to cover the memory cells. The liner film LN covers the first gate electrode, second gate electrode, third gate electrode, and fourth gate electrode. Furthermore, the liner film LN covers the first memory gate electrode, second memory gate electrode, third memory gate electrode, and fourth memory gate electrode. The liner film LN is made of an insulating film such as a silicon nitride film and is deposited on the main surface of the semiconductor substrate SB using the CVD method.

[0038] Next, as shown in Figure 9, an insulating film IF3 is formed on the liner film LN. The insulating film IF3 consists of a silicon oxide film and is deposited on the liner film LN using the CVD method. Preferably, an O3-TEOS (Tetraethyl orthosilicate) film with good step coverage is used as the insulating film IF3.

[0039] First, let's explain region AR. The space between the adjacent first gate electrode and second gate electrode is filled with an insulating film IF3. That is, in the region between the first gate electrode and the second gate electrode, the height of the top surface of the insulating film IF3 is equal to or greater than the height of the top surface of the cap insulating film CP, with respect to the main surface of the semiconductor substrate SB. In the region between the first gate electrode and the second gate electrode, the height of the lowest part of the top surface of the insulating film IF3 is equal to or greater than the height of the top surface of the cap insulating film CP. The thickness T2 of the insulating film IF3 used to fill the region between the first gate electrode and the second gate electrode is expressed by the following equation.

[0040] [Equation 1] T2 ≥ D1 / 2 - T1 In Equation 1, D1 is the distance between the first gate electrode and the second gate electrode, T1 is the thickness of the liner film LN located on the first gate electrode, and T2 is the thickness of the insulating film IF3 located on the first gate electrode. Note that in order to fill the region between the first gate electrode and the second gate electrode with the insulating film IF3, the thickness T1 of the liner film LN must be smaller than the thickness T2 of the insulating film IF3 (T1 <T2)。

[0041] Thus, since the region between the first gate electrode and the second gate electrode is filled with insulating film IF3, the insulating film IF3 in the region between the first gate electrode and the second gate electrode has a thickness T3. The thickness T3 of the insulating film IF3 in the region between the first gate electrode and the second gate electrode is greater than the thickness T2 of the insulating film IF3 located on the first gate electrode or the second gate electrode (T3 > T2). Here, thicknesses T1, T2, and T3 are thicknesses in the direction perpendicular to the main surface of the semiconductor substrate SB.

[0042] On the other hand, in region BR, the region between the adjacent third memory gate electrode and the fourth memory gate electrode is not filled with insulating film IF3. In the region between the third memory gate electrode and the fourth memory gate electrode, the upper surface of insulating film IF3 is lower than the height of the upper surface of the cap insulating film CP, relative to the main surface of the semiconductor substrate SB. In other words, the thickness of a portion of insulating film IF3 located on the source region SR is approximately equal to the thickness T2 of insulating film IF3 on the third gate electrode or the fourth gate electrode.

[0043] Next, as shown in Figure 10, anisotropic dry etching is performed on the insulating film IF3 to form the embedded layer BZ and the insulating film IF3A.

[0044] Region AR will now be described. In the anisotropic dry etching process for the insulating film IF3, the insulating film IF3 located on the first gate electrode and the second gate electrode is etched to expose the liner film LN. Meanwhile, in the region between the first gate electrode and the second gate electrode, a buried layer BZ is formed covering the liner film LN. As shown in Figure 9, the thickness T3 of the insulating film IF3 between the first gate electrode and the second gate electrode is greater than the thickness T2 of the insulating film IF3 on the first gate electrode or the second gate electrode. In cross-sectional view, the buried layer BZ has a first portion, a second portion, and a third portion. As shown in Figure 10, the first portion is formed on the liner film LN along the main surface of the semiconductor substrate SB. The second portion is formed along the liner film LN on the sidewall of the first gate electrode. The third portion is formed along the liner film LN on the sidewall of the second gate electrode. The second portion is connected to one end of the first portion, and the third portion is connected to the other end of the first portion. The second and third portions extend in a direction perpendicular to the main surface of the semiconductor substrate SB. In other words, an anisotropic dry etching process forms an embedded layer BZ on the liner film LN that is located on the drain region DR and has a concave shape in cross-section.

[0045] On the other hand, as shown in Figure 9, in region BR, the region between the adjacent third memory gate electrode MG and fourth memory gate electrode MG is not filled with insulating film IF3, so the embedded layer BZ is not formed. As shown in Figure 10, insulating film IF3A is formed on the liner film LN covering the side wall of the third memory gate electrode MG. Also, insulating film IF3A is formed on the liner film LN covering the side wall of the fourth memory gate electrode MG. The two insulating films IF3A formed between the third memory gate electrode MG and the fourth memory gate electrode MG are separated from each other. In other words, a portion of the liner film LN located on the source region SR is exposed from the insulating film IF3A.

[0046] Next, as shown in Figure 11, an interlayer insulating film IL1 is formed on the semiconductor substrate SB so as to cover the memory cell, liner film LN, embedded layer BZ, and insulating film IF3A. The interlayer insulating film IL1 consists of a silicon oxide film and is deposited on the liner film LN and embedded layer BZ using the CVD method. Preferably, an O3-TEOS film with good step coverage is used as the interlayer insulating film IL1.

[0047] In region AR, an embedded layer BZ is formed in the region between the first gate electrode and the second gate electrode. Therefore, the region between the first gate electrode and the second gate electrode can be filled with the interlayer insulating film IL1 without generating voids within the interlayer insulating film IL1 located on the drain region DR.

[0048] In region BR, the distance between the third memory gate electrode MG and the fourth memory gate electrode MG is greater than the distance between the first gate electrode and the second gate electrode; therefore, no voids occur within the interlayer insulating film IL1 located on the source region SR.

[0049] Next, as shown in Figure 12, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1. The interlayer insulating film IL2 consists of a silicon oxide film and is deposited on the interlayer insulating film IL1 using the CVD method. Preferably, a TEOS film, which has better mechanical properties than the interlayer insulating film IL1, is used as the interlayer insulating film IL2. Next, the interlayer insulating film IL2 is subjected to CMP (Chemical Mechanical Polishing) to flatten the upper surface of the interlayer insulating film IL2.

[0050] Next, as shown in Figure 13, a plug electrode PG is formed. In region AR, the interlayer insulating film IL2, interlayer insulating film IL1, embedding layer BZ, and liner film LN are etched. Then, a contact hole CH is formed that penetrates the interlayer insulating film IL2, interlayer insulating film IL1, embedding layer BZ, and liner film LN. The contact hole CH is formed on the drain region DR, and the plug electrode PG is formed within the contact hole CH. The plug electrode PG contacts the silicide layer SC formed on the upper surface of the drain region DR. In region BR, the interlayer insulating film IL2, interlayer insulating film IL1, and liner film LN are etched. Then, a contact hole CH is formed that penetrates the interlayer insulating film IL2, interlayer insulating film IL1, and liner film LN. The contact hole CH is formed on the source region SR, and the plug electrode PG is formed within the contact hole CH. The plug electrode PG contacts the silicide layer SC formed on the upper surface of the source region SR. The plug electrode PG includes a barrier conductor film and a main body film. The barrier conductive film consists of, for example, a titanium film, a titanium nitride film, or a laminated film of a titanium film and a titanium nitride film on top of the titanium film. The main body film is formed on the barrier film and consists of, for example, tungsten (W).

[0051] Next, as shown in Figure 1, a wiring layer including a bit line BL and a source line SL is formed on the interlayer insulating film IL2. The wiring layer is made of, for example, a copper (Cu) film or an aluminum (Al) film. The bit line BL is electrically connected to the drain region DR via a plug electrode PG. The source line SL is electrically connected to the source region SR via a plug electrode PG.

[0052] Note that the second gate electrode in region AR and the third gate electrode in region BR are the same gate electrode, as shown in Figure 2. The second gate electrode and the third gate electrode may be different gate electrodes. Also, the second memory gate electrode MG in region AR and the third memory gate electrode MG in region BR are the same memory gate electrode MG, as shown in Figure 2. The second memory gate electrode MG and the third memory gate electrode MG may be different memory gate electrode MGs.

[0053] The method for manufacturing the semiconductor device according to this embodiment has the following features.

[0054] In the region between the first gate electrode and the second gate electrode, after forming a embedding layer BZ on the liner film LN, the region between the first gate electrode and the second gate electrode is filled with an interlayer insulating film IL1. By forming the embedding layer BZ before forming the interlayer insulating film IL1, the region on the drain region DR between the first gate electrode and the second gate electrode can be filled with an interlayer insulating film IL1 without any gaps. Therefore, short circuits occurring between multiple plug electrodes PG formed within the interlayer insulating film IL1 can be prevented.

[0055] <Example 1> Modification 1 is a modification relating to Figure 10 of the above embodiment. As shown in Figure 14, after forming the insulating film IF3, a mask layer MK2 is formed, and then anisotropic dry etching is performed on the insulating film IF3. The mask layer MK2 has an opening in region AR that exposes the embedded layer BZ located on the drain region DR, the liner film LN located on a part of the first gate electrode, and the liner film LN located on a part of the second gate electrode. In a plan view, the drain region DR is located within the opening between a part of the first gate electrode and a part of the second gate electrode. In the anisotropic dry etching process, the insulating film IF3 located on a part of the first gate electrode and a part of the second gate electrode located within the opening in a plan view is removed, exposing the liner film LN. Furthermore, in the anisotropic dry etching process, an embedded layer BZ similar to that of the above embodiment is formed in the region between the first gate electrode and the second gate electrode.

[0056] On the other hand, in region BR, the insulating film IF3 on the source region SR is covered by the mask layer MK2, so the liner film LN on the source region SR is not exposed. In other words, the liner film LN on the source region SR has sufficient thickness to function as an etching stopper. In the above embodiment, the liner film LN on the source region SR may be exposed, and the thickness of the liner film LN may decrease. If the thickness of the liner film LN decreases, the liner film LN will no longer be able to function as an etching stopper in the etching process when forming the contact holes CH.

[0057] According to Modification 1, it is possible to prevent a reduction in the thickness of the liner film LN located on the source region SR. Therefore, when forming contact holes CH on the source region SR, it is possible to prevent the problem of the contact holes CH penetrating the source region SR. In other words, it is possible to prevent the problem of a short circuit between the source region SR and the semiconductor substrate SB.

[0058] <Modification 2> Modification 2 is a modification of Modification 1 described above. The difference from Modification 1 is the thickness of the liner film LN on the first gate electrode and the second gate electrode. Here, the liner film LN on the first gate electrode is described, but the same process is performed on the liner film LN on the second gate electrode. In the anisotropic dry etching process for the insulating film IF3 of Modification 1, the anisotropic dry etching was terminated when the liner film LN on the first gate electrode was exposed. As shown in Figure 15, in Modification 2, the anisotropic dry etching is continued even after the etching of the insulating film IF3 is completed and the liner film LN on the first gate electrode is exposed. Then, in the anisotropic dry etching process, the thickness of the liner film LN located within the opening of the mask layer MK2 is reduced. That is, the thickness of the liner film LNA exposed from the mask layer MK2 is made smaller than the thickness of the liner film LN covered by the mask layer MK2. The anisotropic dry etching process forms the liner film LNA on the first gate electrode located within the opening of the mask layer MK2. The thickness of the liner film LNA located on the first gate electrode and exposed through the opening is smaller than the thickness of the liner film LN located on the first gate electrode and covered by the insulating film IF3. Therefore, the generation of voids can be prevented in the process of filling the region between the first gate electrode and the second gate electrode with the interlayer insulating film IL1.

[0059] The present inventors have described the invention in detail based on its embodiments above, but it goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from its essence. [Explanation of symbols]

[0060] AR,BR area BL bit line BZ Embedding Layer CP cap insulating film CG Control Terminal CH Contact Hole DR drain area GI gate insulating film IF1, IF2, IF3, IF3A insulating film IL1, IL2 interlayer insulating film LN, LNA liner film MG memory gate MK1, MK2 mask layer MZ insulating film (charge-holding film) NM N-type impurity region NH N-type impurity region PG plug electrode SC silicide layer SF Silicone film SL Source Line SR Source Area ST shallow groove separation section (shallow groove separation membrane) SB Semiconductor Substrate SW sidewall insulating film

Claims

1. (a) A step of forming a first gate electrode and a second gate electrode on the main surface of a semiconductor substrate, (b) A step of forming an impurity region in the semiconductor substrate in the region between the first gate electrode and the second gate electrode, (c) A step of depositing a first insulating film on the main surface of the semiconductor substrate so as to cover the first gate electrode and the second gate electrode, (d) A step of depositing a second insulating film on the first insulating film, (e) The step of removing the second insulating film located on the first gate electrode and the second gate electrode by anisotropic dry etching of the second insulating film to expose the first insulating film, and forming an embedded layer in the region between the first gate electrode and the second gate electrode that covers the first insulating film and is made of the second insulating film. (f) A step of depositing a third insulating film on the main surface of the semiconductor substrate so as to cover the first gate electrode, the second gate electrode and the embedded layer, (g) A step of forming contact holes in the third insulating film, the embedding layer, and the first insulating film in the region between the first gate electrode and the second gate electrode, within the third insulating film, within the embedding layer, and within the first insulating film, and (h) A step of forming a plug electrode that is electrically connected to the impurity region by forming a conductive layer in the contact hole, A method for manufacturing a semiconductor device, including the method described above.

2. In the method for manufacturing a semiconductor device described in claim 1, The above step (a) is, (a1) A step of depositing a silicon film on the main surface of the semiconductor substrate, (a2) A step of depositing a fourth insulating film on the silicon film, and (a3) A step of forming a first gate electrode including a first control gate electrode made of the silicon film and a first cap insulating film made of the fourth insulating film, and a second gate electrode including a second control gate electrode made of the silicon film and a second cap insulating film made of the fourth insulating film, by processing the fourth insulating film and the silicon film. A method for manufacturing a semiconductor device, including the method described above.

3. In the method for manufacturing a semiconductor device described in claim 2, After step (h) above, (i) A step of forming a wiring layer on the third insulating film that is electrically connected to the plug electrode, A method for manufacturing a semiconductor device, including the method described above.

4. In the method for manufacturing a semiconductor device described in claim 2, In step (d) above, A method for manufacturing a semiconductor device, wherein the first thickness of the second insulating film formed in the region between the first gate electrode and the second gate electrode is greater than the second thickness of the second insulating film formed on the first gate electrode.

5. In the method for manufacturing a semiconductor device described in claim 2, A method for manufacturing a semiconductor device, wherein the fourth insulating film is made of a first silicon nitride film.

6. In the method for manufacturing a semiconductor device described in claim 2, The first insulating film consists of a second silicon nitride film. The second insulating film consists of the first silicon oxide film. A method for manufacturing a semiconductor device, wherein the third insulating film is a silicon oxide film.

7. In the method for manufacturing a semiconductor device described in claim 6, The second insulating film is the first O ３ - Consists of a TEOS film, The third insulating film is the second O ３ - A method for manufacturing a semiconductor device made of a TEOS film.

8. (a) A step of forming a first gate electrode having a first sidewall and a second sidewall, and a second gate electrode having a third sidewall and a fourth sidewall, on the main surface of a semiconductor substrate. (b) A step of forming a first memory gate electrode on the first side wall and the main surface of the first gate electrode via a first charge-retaining film, and forming a second memory gate electrode on the fourth side wall and the main surface of the second gate electrode via a second charge-retaining film, (c) A step of forming a first impurity region in the semiconductor substrate in a first region between the first gate electrode and the second gate electrode, (d) A step of depositing a first insulating film on the main surface of the semiconductor substrate so as to cover the first gate electrode, the first memory gate electrode, the second gate electrode, and the second memory gate electrode. (e) A step of depositing a second insulating film on the first insulating film, (f) A step of forming a mask layer that covers the first memory gate electrode and the second memory gate electrode and has an opening that exposes a part of the first gate electrode, the first region, and a part of the second gate electrode. (g) A step of exposing the first insulating film covering a part of the first gate electrode and a part of the second gate electrode within the opening of the mask layer by anisotropic dry etching of the second insulating film, and covering the first insulating film in the first region to form an embedded layer made of the second insulating film, (h) A step of depositing a third insulating film on the main surface of the semiconductor substrate so as to cover the first gate electrode, the second gate electrode and the embedded layer, (i) A step of forming a first contact hole in the third insulating film, the embedding layer and the first insulating film in the first region, and (j) A step of forming a first plug electrode that is electrically connected to the first impurity region by forming a first conductor layer in the first contact hole, Includes, The first gate electrode and the second gate electrode extend in a first direction along the main surface of the semiconductor substrate and are arranged in a second direction perpendicular to the first direction. The first side wall and the second side wall of the first gate electrode extend in the first direction, The second side wall of the first gate electrode faces the third side wall of the second gate electrode. A method for manufacturing a semiconductor device, wherein the third and fourth side walls of the second gate electrode extend in the first direction.

9. In the method for manufacturing a semiconductor device described in claim 8, In step (a) above, A third gate electrode having a fifth side wall and a sixth side wall, and a fourth gate electrode having a seventh side wall and an eighth side wall are formed on the main surface of the semiconductor substrate. In step (b) above, A third memory gate electrode is formed on the sixth side wall and the main surface of the third gate electrode via a third charge-retaining film, and a fourth memory gate electrode is formed on the seventh side wall and the main surface of the fourth gate electrode via a fourth charge-retaining film. In step (c) above, In the second region between the third memory gate electrode and the fourth memory gate electrode, a second impurity region is formed within the semiconductor substrate. In step (d) above, The first insulating film is deposited on the main surface of the semiconductor substrate so as to cover the third gate electrode, the third memory gate electrode, the fourth gate electrode, the fourth memory gate electrode, and the second region. In step (f) above, The mask layer covers the third memory gate electrode, the second region, and the fourth memory gate electrode. In step (h) above, The third insulating film covers the second insulating film, the third memory gate electrode, and the fourth memory gate electrode remaining in the second region. In step (i) above, In the second region, a second contact hole is formed within the third insulating film, the second insulating film, and the first insulating film. In step (j) above, By forming a second conductor layer within the second contact hole, a second plug electrode is formed that is electrically connected to the second impurity region. The third gate electrode and the fourth gate electrode extend in the first direction and are arranged in the second direction on the main surface of the semiconductor substrate. The fifth and sixth side walls of the third gate electrode extend in the first direction, The seventh and eighth side walls of the fourth gate electrode extend in the first direction, A method for manufacturing a semiconductor device, wherein the sixth side wall of the third gate electrode faces the seventh side wall of the fourth gate electrode.

10. In the method for manufacturing a semiconductor device described in claim 9, The above step (a) is, (a1) A step of depositing a silicon film on the main surface of the semiconductor substrate, (a2) A step of depositing a fourth insulating film on the silicon film, and (a3) A step of forming the following by processing the fourth insulating film and the silicon film: the first gate electrode including a first control gate electrode made of the silicon film and a first cap insulating film made of the fourth insulating film; the second gate electrode including a second control gate electrode made of the silicon film and a second cap insulating film made of the fourth insulating film; the third gate electrode including a third control gate electrode made of the silicon film and a third cap insulating film made of the fourth insulating film; and the fourth gate electrode including a fourth control gate electrode made of the silicon film and a fourth cap insulating film made of the fourth insulating film. A method for manufacturing a semiconductor device, including the method described above.

11. In the method for manufacturing a semiconductor device described in claim 10, After step (j) above, (k) A step of forming a first wiring layer electrically connected to the first plug electrode on the third insulating film located in the first region, and forming a second wiring layer electrically connected to the second plug electrode on the third insulating film located in the second region. Includes, A method for manufacturing a semiconductor device, wherein the first wiring layer and the second wiring layer extend in the second direction.

12. In the method for manufacturing a semiconductor device described in claim 10, In step (e) above, A method for manufacturing a semiconductor device, wherein in the first region, the first thickness of the second insulating film is greater than the second thickness of the second insulating film formed on the first gate electrode.

13. In the method for manufacturing a semiconductor device described in claim 10, A method for manufacturing a semiconductor device, wherein the fourth insulating film is made of a first silicon nitride film.

14. In the method for manufacturing a semiconductor device described in claim 10, The first insulating film consists of a second silicon nitride film. The second insulating film consists of the first silicon oxide film. A method for manufacturing a semiconductor device, wherein the third insulating film is a silicon oxide film.

15. In the method for manufacturing a semiconductor device described in claim 14, The second insulating film is the first O ３ - Consists of a TEOS film, The third insulating film is the second O ３ - A method for manufacturing a semiconductor device made of a TEOS film.

16. In the method for manufacturing a semiconductor device described in claim 10, A method for manufacturing a semiconductor device, wherein the first distance between the third memory gate electrode and the fourth memory gate electrode is greater than the second distance between the first gate electrode and the second gate electrode.

17. In the method for manufacturing a semiconductor device described in claim 8, In step (g) above, A method for manufacturing a semiconductor device, wherein the third thickness of the first insulating film, located on the first gate electrode and the second gate electrode and exposed from the opening of the mask layer, is made smaller than the fourth thickness of the first insulating film covered by the mask layer.

Images