Semiconductor device and method for manufacturing a semiconductor device

Abstract

The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can achieve a higher pressure resistance at the edge portion than at the active portion. [Solution] The semiconductor device has an active region 10 and a termination structure 30. It comprises a first semiconductor layer 3 of a first conductivity type and a second semiconductor layer 2 of a first conductivity type, provided on the front surface of a semiconductor substrate 1 of a first conductivity type. The active region 10 is provided with a first parallel pn structure 51 in which a first column region 52 of a first conductivity type and a second column region 53 of a second conductivity type are repeatedly and alternately arranged, and the termination structure 30 is provided with a second parallel pn structure 54 in which a third column region 55 of a first conductivity type and a fourth column region 56 of a second conductivity type are repeatedly and alternately arranged. The second semiconductor layer 2 of the termination structure 30 is thicker than the second semiconductor layer 2 of the active region 10, and the column length of the second parallel pn structure 54 is longer than the column length of the first parallel pn structure 51.

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] Conventionally, the thickness of the parallel pn layer in the active part is made thinner than the pn layer in the pressure-resistant structure, and a p is placed between the parallel pn layer in the active part and the p-type base region. + Superjunction semiconductor devices with a molded outer region are known (see, for example, Patent Document 1 below). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-139377 [Overview of the project] [Problems that the invention aims to solve]

[0004] Conventional semiconductor devices have faced the challenge of making the withstand voltage of the edge portion higher than that of the active portion. This disclosure aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can achieve a withstand voltage of the edge portion higher than that of the active portion. [Means for solving the problem]

[0005] To solve the problems described above and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: A semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region, wherein the semiconductor device has a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate on the front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer is provided on the upper surface of the first semiconductor layer. The active region is provided with a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in the second semiconductor layer in a direction parallel to the front surface. A first semiconductor region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region. A second semiconductor region of a first conductivity type is selectively provided on the surface layer of the first semiconductor region of the active region. A gate electrode is provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region. The termination structure is provided with a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in the second semiconductor layer in a direction parallel to the front surface. The second semiconductor layer of the termination structure is thicker than the second semiconductor layer of the active region, and the column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

[0006] According to the disclosure described above, the column length of the second parallel pn layer in the edge-terminating region is longer than the column length of the first parallel pn layer in the active region. This makes it possible to raise the breakdown voltage of the edge-terminating region to a higher level than that of the active region. Because the avalanche current when an avalanche occurs is shared by the active region, which has a larger area, the destruction of the semiconductor device can be suppressed. [Effects of the Invention]

[0007] The semiconductor device and method for manufacturing the semiconductor device according to this disclosure have the effect of making the withstand voltage of the edge portion higher than the withstand voltage of the active portion. [Brief explanation of the drawing]

[0008] [Figure 1] This is a cross-sectional view taken along line X-X' in Figure 2, showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 2] This is a top view showing the structure of a silicon carbide semiconductor device according to an embodiment. [Figure 3] This is a cross-sectional view taken along line X-X' in Figure 2, showing another structure of the silicon carbide semiconductor device according to the embodiment. [Figure 4] This is a flowchart of the method for manufacturing a semiconductor device according to the embodiment. [Figure 5] This is a cross-sectional view (part 1) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 6] This is a cross-sectional view (part 2) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 7] This is a cross-sectional view (part 3) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 8] This is a cross-sectional view (part 4) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 9] This is a cross-sectional view (part 5) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 10] This is a cross-sectional view (part 6) showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 11] Figure 12 shows a cross-sectional view taken along line X-X' of a conventional silicon carbide semiconductor device. [Figure 12] This is a top view showing the structure of a conventional silicon carbide semiconductor device. [Modes for carrying out the invention]

[0009] <Summary of the embodiments of this disclosure> To solve the problems described above and achieve the objectives of this disclosure, the semiconductor device according to this disclosure has the following features: A semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region, wherein the semiconductor device has a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate on the front surface of a semiconductor substrate of a first conductivity type. A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer is provided on the upper surface of the first semiconductor layer. The active region is provided with a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in the second semiconductor layer in a direction parallel to the front surface. A first semiconductor region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region. A second semiconductor region of a first conductivity type is selectively provided on the surface layer of the first semiconductor region of the active region. A gate electrode is provided via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region. The termination structure is provided with a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in the second semiconductor layer in a direction parallel to the front surface. The second semiconductor layer of the termination structure is thicker than the second semiconductor layer of the active region, and the column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

[0010] According to the disclosure described above, the column length of the second parallel pn layer in the edge-terminating region is longer than the column length of the first parallel pn layer in the active region. This makes it possible to raise the breakdown voltage of the edge-terminating region to a higher level than that of the active region. Because the avalanche current when an avalanche occurs is shared by the active region, which has a larger area, the destruction of the semiconductor device can be suppressed.

[0011] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the second parallel pn structure is longer on the side opposite to the semiconductor substrate than the first parallel pn structure.

[0012] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the first semiconductor region, the second semiconductor region, the gate insulating film, and the gate electrode are provided on the semiconductor substrate side from the front surface of the second semiconductor layer of the termination structure.

[0013] Furthermore, the semiconductor device according to the present disclosure comprises a third semiconductor region of a second conductivity type provided on the surface layer of the second parallel pn structure of the termination structure, wherein the second semiconductor layer of the termination structure has a region that is thicker than the second semiconductor layer of the active region and a region that is the same thickness as the second semiconductor layer of the active region, and the third semiconductor region is provided in the thicker region of the second semiconductor layer and the region of the same thickness of the second semiconductor layer.

[0014] Furthermore, the semiconductor device according to this disclosure is characterized in that, in the disclosure described above, the fourth column region of the second parallel pn structure is in contact with the first column region of the first parallel pn structure.

[0015] To solve the above-mentioned problems and achieve the objectives of this disclosure, the method for manufacturing a semiconductor device according to this disclosure has the following features: a method for manufacturing a semiconductor device having an active region and a termination structure disposed outside the active region and surrounding the periphery of the active region. First, a first step is performed to form a first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate on the front surface of a semiconductor substrate of a first conductivity type. Next, a second step is performed to form a second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer on the upper surface of the first semiconductor layer. Next, a third step is performed to form a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer of the active region, and a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer of the termination structure. Next, a fourth step is performed in which the surface of the second semiconductor layer on which the first parallel pn structure is formed is etched and excavated. Next, a fifth step is performed in which a first semiconductor region of the second conductivity type is formed on the surface of the second semiconductor layer excavated in the fourth step. Next, a sixth step is performed in which a second semiconductor region of the first conductivity type is selectively formed on the surface of the second semiconductor layer excavated in the fourth step. Next, a seventh step is performed in which a gate electrode is formed via a gate insulating film in contact with a part of the first semiconductor region and a part of the second semiconductor region. In the third step, the column length of the second parallel pn structure is formed to be longer than the column length of the first parallel pn structure.

[0016] <Knowledge forming the basis of this disclosure> Conventionally, semiconductor devices with a superjunction (SJ) structure are known, in which the drift layer is a parallel pn layer in which n-type and p-type regions are alternately and repeatedly arranged adjacent to each other in a direction parallel to the main surface of the substrate. The n-type and p-type regions constituting the parallel pn layer extend in a stripe-like manner parallel to the main surface of the semiconductor substrate (semiconductor chip). The n-type and p-type regions constituting the parallel pn layer are provided almost uniformly over almost the entire semiconductor substrate, from the active region in the center of the semiconductor substrate (center of the chip) to the edge of the semiconductor substrate (edge ​​of the chip).

[0017] The structure of a conventional silicon carbide semiconductor device with an SJ structure will be explained using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field-effect transistor with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor) as an example. Figure 11 is a cross-sectional view taken along line X-X' in Figure 12, showing the structure of a conventional silicon carbide semiconductor device. Figure 12 is a top view showing the structure of a conventional silicon carbide semiconductor device.

[0018] The conventional silicon carbide semiconductor device 150 shown in Figures 11 and 12 is a vertical MOSFET with an SJ structure, where the active region 110 of a silicon carbide semiconductor substrate (semiconductor chip) 140 has a general planar gate structure, and the n-type drift layer 102 is a parallel pn layer 151. The semiconductor substrate 140 has a rectangular planar shape. The active region 110 has a substantially rectangular planar shape and is located in the center of the semiconductor substrate 140 (center of the chip). The periphery of the active region 110 is surrounded by an edge termination region 130 via an intermediate region 120.

[0019] The semiconductor substrate 140 is made of n + n - The semiconductor substrate 140 is constructed by stacking an n-type buffer layer 103 and an n-type epitaxial layer 142 which will become an n-type drift layer 102. The main surface of the semiconductor substrate 140 on the side of the n-type epitaxial layer 142 is considered the front surface. + n is a type drain region 101. + The main surface on the mold starting substrate 141 side is considered the back surface. The n-type epitaxial layer 142 is the portion that becomes the n-type drift layer (drift region) 102 and includes the parallel pn layer 151.

[0020] n + On the front side (the side facing the n-type drift layer 102) of the starting substrate 141, p + Type base region 104, n +A MOS gate structure including a source region 105, a gate insulating film 108, and a gate electrode 109 is provided. The gate electrode 109 is electrically insulated from a source electrode (not shown) by an interlayer insulating film 114. In the intermediate region 120, p + type region 111 extends from the sidewall of the edge termination region 130 side of the p + type base region 104 to a JTE structure 132 described later.

[0021] In the intermediate region 120, a gate wiring layer (not shown) such as a gate runner is disposed. The edge termination region 130 is a region between the intermediate region 120 and the end portion (chip end portion) of the semiconductor substrate 140. In the edge termination region 130, as a breakdown voltage structure, a Junction Termination Extension (JTE) structure 132 and an n + type channel stopper region 134 are disposed. The JTE structure 132 surrounds the periphery of the active region 110 via the intermediate region 120.

[0022] n + type channel stopper region 134 is disposed outside (chip end portion side) of the JTE structure 132, separated from the JTE structure 132, and reaches the end portion of the semiconductor substrate 140. The n + type channel stopper region 134 extends along the end portion of the semiconductor substrate 140 and surrounds the periphery of the JTE structure 132.

[0023] The parallel pn layer 151 is uniformly provided substantially over the entire semiconductor substrate 140 from the active region 110 to the edge termination region 130. The parallel pn layer 151 is an SJ structure in which n-type regions 152 and p-type regions 153 are alternately and repeatedly adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 140. The n-type regions 152 and p-type regions 153 of the parallel pn layer 151 extend in a stripe shape in a second direction Y parallel to the front surface of the semiconductor substrate 140 and orthogonal to the first direction X.

[0024] The n-type regions 152 and p-type regions 153 of the parallel pn layer 151 are directly under the JTE structure 132 (n +It is arranged from the drain region 101 side to almost the entire edge termination region 130. The parallel pn layer 151 is in contact with the JTE structure 132 and is in contact with the JTE structure 132. + The channel stopper region 134 does not reach the front surface of the semiconductor substrate 140.

[0025] The n-type region 152 and p-type region 153 of the parallel pn layer 151 are arranged at equal intervals across approximately the entire semiconductor substrate 140, from the active region 110 to the edge termination region 130. The carrier concentration (impurity concentration) and width (width in the first direction X) of the n-type region 152 and p-type region 153 of the parallel pn layer 151 are set so that a charge balance is achieved between adjacent n-type region 152 and p-type region 153 of the parallel pn layer 151.

[0026] A charge balance means that the charge amount, expressed as the product of the carrier concentration and width in the n-type region 152, and the charge amount, expressed as the product of the carrier concentration and width in the p-type region 153, are approximately the same within a range that includes tolerances due to process variations.

[0027] As shown in Figure 11, in the conventional silicon carbide semiconductor device 150, the active region 110 and the edge termination region 130 use an SJ structure in which the n-type region 152 and p-type region 153 of the parallel pn layer 151 have the same column length. In the SJ structure, the depletion layer extends laterally across the parallel pn layer 151 which is aligned perpendicular to the semiconductor substrate 140, so the depletion layer thickness is equal to the column length of the SJ structure.

[0028] In conventional silicon carbide semiconductor devices 150, when an avalanche occurs, the avalanche current can be shared by causing the avalanche to occur in the large active region 110, thereby suppressing the breakdown of the silicon carbide semiconductor device 150. For this reason, the breakdown voltage of the edge termination region 130 is made higher than that of the active region 110.

[0029] However, in the SJ structure, the pressure resistance is mainly determined by the column length of the SJ structure. Therefore, when the column lengths of the SJ structure are the same in the active region 110 and the edge-terminal region 130, there is a challenge in making the pressure resistance of the edge-terminal region 130 higher than that of the active region 110.

[0030] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to this disclosure, which solve the problems of the conventional semiconductor devices described above, will be described in detail below with reference to the attached drawings. In this specification and the attached drawings, layers or regions prefixed with n or p mean that electrons or holes are the majority carriers, respectively. Furthermore, the + and - prefixes to n and p mean that they have a higher and lower impurity concentration than layers or regions without them, respectively. In the following description of embodiments and attached drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. It is preferable to include up to 5% in the description of the same or equivalent components to account for manufacturing variations.

[0031] (Embodiment) The structure of a silicon carbide semiconductor device according to the embodiment will be explained using a MOSFET as an example. Figure 1 is a cross-sectional view taken along line X-X' in Figure 2, showing the structure of a silicon carbide semiconductor device according to the embodiment. Figure 2 is a top view showing the structure of a silicon carbide semiconductor device according to the embodiment. In Figure 2, the number of n-type regions (first conductivity type regions) 52 and p-type regions (second conductivity type regions) 53 of the parallel pn layer 51 is simplified, which differs from Figure 1.

[0032] The silicon carbide semiconductor device 50 according to this embodiment is a vertical MOSFET with a planar gate structure (device structure) having an SJ structure in which an n-type drift layer (second semiconductor layer of the first conductivity type) 2 is arranged in parallel pn layers (first parallel pn layer 51, second parallel pn layer 54) extending from the active region 10 to the edge termination region 30. The active region 10 is the region through which the main current flows when the MOSFET is ON, and is located in the center of the semiconductor substrate 40 (center of the chip).

[0033] The intermediate region 20 is adjacent to the active region 10 and surrounds the active region 10. The edge termination region 30 is the region between the intermediate region 20 and the edge of the semiconductor substrate 40, and surrounds the active region 10 via the intermediate region 20.

[0034] The boundary between the active region 10 and the intermediate region 20 is the outer (edge ​​termination region 30 side) end of the interlayer insulating film 14, which will be described later. The boundary between the intermediate region 20 and the edge termination region 30 is the inner end (inner circumference) of the JTE structure 32, which will be described later. The inner end of the JTE structure 32 is the inner end of the innermost p-type region among the multiple p-type regions that make up the JTE structure 32, and is the p-end of the intermediate region 20, which will be described later. + This is the junction (interface) with the mold region 11.

[0035] The edge termination region 30 is the region between the active region 10 and the edge of the semiconductor substrate 40, and surrounds the intermediate region 20. The active region 10 and the intermediate region 20 have an SJ structure in which the n-type drift layer 2 is the first parallel pn layer 51. The edge termination region 30 has an SJ structure in which the first parallel pn layer 51 and the n-type drift layer 2 are the second parallel pn layer 54.

[0036] As shown in Figure 1, the silicon carbide semiconductor device 50 according to this embodiment has a general planar gate structure on the front side of the semiconductor substrate 40 in the active region 10. The planar gate structure is p + Type base region (first semiconductor region of the second conductivity type) 4, n + It consists of a type source region (second semiconductor region of the first conductivity type) 5, a gate insulating film 8, and a gate electrode 9. ++ A type contact region (not shown) may be provided. The semiconductor substrate 40 is made of n + An n-type epitaxial layer 42, which will become the n-type drift layer 2, is deposited on the front surface of a type starting substrate (a first-conductivity type semiconductor substrate) 41.

[0037] With the main surface of the semiconductor substrate 40 on the side of the n-type epitaxial layer 42 as the front surface, +The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). + The starting substrate 41 is n + This is a type drain region 1. In this embodiment, n + Between the drain region 1 and the parallel pn layers (first parallel pn layer 51, second parallel pn layer 54) n - This is a Semi-SJ structure in which a buffer layer (first semiconductor layer of the first conductivity type) 3 is provided. + n-type drift layer 2 and n + On the surface of the area sandwiched between type source region 5, adjacent p + A gate insulating film 8 is provided so as to extend into the region between the n-type base regions 4 (the so-called JFET region). The gate insulating film 8 consists of n-type drift layer 2 and n + It may be provided on the type source region 5. A gate electrode 9 is provided on the gate insulating film 8. The gate electrode 9 is electrically insulated from the source electrode (not shown) by the interlayer insulating film 14.

[0038] p + The base region 4 extends in a stripe pattern in the second direction Y. + Type source area 5 is p + These are selectively provided on the surface of the base region 4. ++ The contact area of ​​type p + The base region 4 may be selectively provided on the surface. In the outermost edge terminal region 30 of the active region 10, p + Type region 11 is p + It extends from the side wall on the edge termination region 30 side of the mold base region 4 to the JTE structure 32, which will be described later.

[0039] The edge termination region 30 has the function of mitigating the electric field on the front side (first main surface) of the semiconductor substrate 40 of the drift layer 2 in the active region 10 and intermediate region 20, thereby maintaining the breakdown voltage. Breakdown voltage is the limit voltage at which leakage current does not increase excessively and the element does not malfunction or break down. The edge termination region 30 has a breakdown voltage structure consisting of a junction termination extension (JTE) structure 32 and n +A channel stopper region 34 is located there. The JTE structure 32 surrounds the active region 10 via an intermediate region 20.

[0040] The JTE structure (third semiconductor region of the second conductivity type) 32 is a structure in which multiple p-type regions are arranged concentrically adjacent to each other around the active region 10 via an intermediate region 20, such that the p-type regions with lower impurity concentrations are arranged as they move away from the active region 10. The JTE structure 32 mitigates electric field concentration outside the intermediate region 20, preventing device failure due to the application of a voltage below a predetermined voltage (the breakdown voltage of the edge termination region 30). It is also possible to provide a guard ring instead of the JTE structure 32.

[0041] n + The channel stopper region 34 is located outside the JTE structure 32 and at a distance from the JTE structure 32, and reaches the edge of the semiconductor substrate 40, for example, along the four sides (straight sections) of the edge of the semiconductor substrate 40. + The channel stopper region 34 extends along the edge of the semiconductor substrate 40 and surrounds the JTE structure 32.

[0042] The first parallel pn layer (first parallel pn structure) 51 is an SJ structure in which n-type regions (first column regions of the first conductivity type) 52 and p-type regions (second column regions of the second conductivity type) 53 are alternately and repeatedly arranged adjacent to each other in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 52 and p-type regions 53 of the first parallel pn layer 51 extend in a stripe-like manner in a second direction Y parallel to the front surface of the semiconductor substrate 40 and perpendicular to the first direction X, up to near the edge of the edge termination region 30. Furthermore, the first parallel pn layer 51 is arranged in the active region 10, intermediate region 20, and edge termination region 30 in the first direction X. Therefore, the boundary between the first parallel pn layer 51 and the second parallel pn layer 54 is located within the edge termination region 30.

[0043] The adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are approximately charge-balanced. Charge balance means that the charge amount, expressed as the product of the carrier concentration (impurity concentration) and width of the n-type region of the parallel pn layer, and the charge amount, expressed as the product of the carrier concentration and width of the p-type region, are approximately the same within a range that includes tolerances due to process variations. Therefore, the carrier concentration and width (width in the first direction X) of the n-type region 52 and p-type region 53 are set so that the adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are approximately charge-balanced.

[0044] It is sufficient that the adjacent n-type region 52 and p-type region 53 of the first parallel pn layer 51 are roughly charge-balanced, and the carrier concentrations and widths of the n-type region 52 and p-type region 53 of the first parallel pn layer 51 are set as appropriate. For example, the widths of the n-type region 52 and p-type region 53 of the first parallel pn layer 51 may be approximately the same. In this case, the carrier concentrations of the n-type region 52 and p-type region 53 should be set to be approximately the same. "Approximately the same width and carrier concentration" means that they are the same width and the same carrier concentration, respectively, within a range that includes tolerances due to process variations.

[0045] The second parallel pn layer (second parallel pn structure) 54 is an SJ structure in which n-type regions (third column regions of the first conductivity type) 55 and p-type regions (fourth column regions of the second conductivity type) 56 are alternately and repeatedly arranged adjacently in a first direction X parallel to the front surface of the semiconductor substrate 40. The n-type regions 55 and p-type regions 56 of the second parallel pn layer 54 extend in a stripe shape in a second direction Y parallel to the n-type regions 52 and p-type regions 53 of the first parallel pn layer 51. The second parallel pn layer 54 is located in the edge termination region 30, connected to both sides of the first parallel pn layer 51 of the active region 10 in the second direction Y. The second parallel pn layer 54 is located in the edge termination region 30, adjacent to both sides of the first parallel pn layer 51 in the first direction X. The second parallel pn layer 54 is positioned such that the outermost n-type region 52 of the first parallel pn layer 51 in the first direction X is adjacent to the p-type region 53 outside the first direction X. Furthermore, the second parallel pn layer 54 extends beyond the outer edge (periphery) of the JTE structure 32 in the first direction X such that at least one p-type region 56 is positioned outside the outer edge (periphery) of the JTE structure 32 in the first direction X.

[0046] By positioning the p-type region 56 of the second parallel pn layer 54 beyond the outer edge of the JTE structure 32 in the first direction X, electric field concentration at the outer edge of the JTE structure 32 can be suppressed when the MOSFET is off. The outer edge of the JTE structure 32 refers to the outer edge of the outermost p-type region among the multiple p-type regions that constitute the JTE structure 32.

[0047] The range in which the second parallel pn layer 54 is placed is defined as the range from the outer edge of the JTE structure 32 in the first direction X, thereby reducing the number of floating p-type regions 56 placed in the edge termination region 30. This reduces the amount of accumulated charge of minority carriers (holes) that accumulate in the edge termination region 30 due to MOSFET switching, etc., and remain without being discharged to the outside. For this reason, it is preferable to have a small number of p-type regions 56 placed outside the outer edge of the JTE structure 32 in the first direction X.

[0048] The second parallel pn layer 54 is within the above range from the outer end of the JTE structure 32 in the first direction X, and in the first direction X, n + Directly below the type channel stopper region 34 (n + It may be arranged up to the drain region 1 side. A normal n-type drift region 2 may be arranged between the second parallel pn layer 54 and the edge of the semiconductor substrate 40 in the first direction X. The less this normal n-type drift region 2 is provided, or the narrower the width of this normal n-type drift region 2 is made, the smaller the semiconductor substrate 40 can be made.

[0049] The n-type region 55 and p-type region 56 of the second parallel pn layer 54 are in contact with the JTE structure 32 in the depth direction Z. The p-type region 56 of the second parallel pn layer 54, which is located outside the JTE structure 32, is located at a depth D1 from the surface of the semiconductor substrate 40 and is not exposed to the surface of the semiconductor substrate 40. The depth D1 is, for example, the same as the thickness of the JTE structure 32. Between the second parallel pn layer 54 located outside the JTE structure 32 and the surface of the semiconductor substrate 40, there is an n-type drift region 2 with a lower impurity concentration than the normal n-type drift region 2. - A layer 35 is positioned there. This makes it easier for the depletion layer to spread outwards.

[0050] The adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. The carrier concentrations and widths (width in the first direction X) of the n-type region 55 and p-type region 56 are set so that the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. The carrier concentrations and widths of the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are set as appropriate, provided that the adjacent n-type region 55 and p-type region 56 of the second parallel pn layer 54 are roughly charge-balanced. For example, the widths of the n-type region 55 and p-type region 56 of the second parallel pn layer 54 may be approximately the same. In this case, the carrier concentrations of the n-type region 55 and p-type region 56 should be set to be approximately the same.

[0051] In this embodiment, the entire active region 10 and the intermediate region 20, and a portion of the edge termination region 30, +The step T is excavated on the drain region 1 side, and in this portion the semiconductor substrate 40 is thinner by a height h. The step T is vertical, for example, as shown in Figure 1. Figure 3 is a cross-sectional view taken along X-X' in Figure 2, showing another structure of the silicon carbide semiconductor device according to the embodiment. As shown in Figure 3, the step T may have an inclination. Furthermore, it is preferable that the area where the step T is provided is a p-type region 56. That is, the p-type region 56 of the second parallel pn layer 54 is in contact with the n-type region 52 of the first parallel pn layer 51. This prevents the electric field from concentrating at the corners of the p-type region 56, where the impurity concentration is high, and prevents a decrease in breakdown voltage.

[0052] Thus, because the semiconductor substrate 40 is thinned by a height h across the entire active region 10 and intermediate region 20, and in part of the edge termination region 30, the column length of the second parallel pn layer 54 in the edge termination region 30 (length of the n-type region 55 and p-type region 56) is longer than the column length of the first parallel pn layer 51 in the active region 10 (length of the n-type region 52 and p-type region 53), resulting in an SJ structure. The n-type region 55 and p-type region 56 are n - From the front surface of type buffer layer 3, n - n of mold layer 35 or JTE structure 34 + The n-type drain region 52 and p-type region 53 are provided on the side of the drain region 1, and the n-type region 52 and p-type region 53 are n - From the front surface of type buffer layer 3, p + Type base region 4 or p + n of type region 11 + It extends to the side of the drain region 1. Therefore, the second parallel pn layer 54 of the edge termination region 30 is n + It is elongated on the opposite side of the drain region.

[0053] As shown in Figures 1 and 3, the column length L2 of the second parallel pn layer 54 is longer than the column length L1 of the first parallel pn layer 51 (L2 > L1). Furthermore, this difference in length (L2 - L1) is preferably 10% to 25% of the column length L1, and more preferably 15% to 20%. This is because if it is shorter than 10%, the effect of the embodiment will be reduced, and if it is longer than 25%, the on-resistance will increase, and the manufacturing cost will increase.

[0054] Since the breakdown voltage of the SJ structure is determined by the column length of the SJ structure, by making the column length of the edge-terminating region 30 longer than the column length of the active region 10, the breakdown voltage of the edge-terminating region 30 can be made higher than that of the active region 10. In this way, the avalanche current when avalanche occurs is shared by the active region 10, which has a larger area, thus suppressing the breakdown of the silicon carbide semiconductor device.

[0055] The first parallel pn layer 51 and n of the active region 10 + n between the type drain region 1 and the drain region 1 - A type buffer layer 3 is provided. - The buffer layer 3 provides a depletion layer extending beneath the SJ structure to the semiconductor substrate (n + It can be kept to the drain region 1). Also, in the edge termination region 30, the second parallel pn layer 54 and n + n between the type drain region 1 and the drain region 1 - A buffer layer 3 is provided.

[0056] As shown in Figures 1 and 3, the p-type region 53 on the intermediate region 20 side of the edge termination region 30 is partially located on the intermediate region 20 side. Therefore, the p-type region 53 is p + It is in contact with both the type region 11 and the JTE structure 32. For example, the approximate center of the p-type region 53 may be midway between the intermediate region 20 and the edge termination region 30.

[0057] Furthermore, as shown in Figures 1 and 3, at the outer ends of the JTE structure 32 in the first direction X and the second direction Y, the JTE structure 32 is in contact with the p-type region 56, but it may also be a structure that is in contact with the n-type region 55.

[0058] Furthermore, as shown in Figures 1 and 3, the JTE structure 32 is also provided in the region where the semiconductor substrate 40 is thinned by a height h. In other words, the edge termination region 30 has a region where the semiconductor substrate 40 is the same thickness as the active region 10, and a region where the semiconductor substrate 40 is thinned by a height h, and the JTE structure 32 is provided in both the region of the same thickness and the thinned region. By providing the JTE structure 32 in the thinned region, the electric field in the edge termination region 30 can be mitigated and the breakdown voltage can be increased.

[0059] Furthermore, since the semiconductor substrate 40 of the active region 10 is thinned by a height h, p provided in the active region 10 + Type base region 4, n + Type source region 5, gate insulating film 8, gate electrode 9 and p + The mold region 11 is n from the front surface of the semiconductor substrate 40 of the edge termination region 30. + It is provided on the drain region 1 side. Because the gate structure is formed lower than the edge termination region 30 in this way, the adhesion of the source electrode and the protective film provided on the source electrode is improved.

[0060] (Method for manufacturing a semiconductor device according to an embodiment) Next, a method for manufacturing the silicon carbide semiconductor device 50 according to the embodiment will be described. Figure 4 is a flowchart of the method for manufacturing the semiconductor device according to the embodiment. Figures 5 to 10 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.

[0061] First, n + n becomes type drain region 1 + On the front surface of the starting substrate (semiconductor wafer) 41, a first parallel pn layer 51 and a second parallel pn layer 54 are formed. - A type buffer layer 3 and an n-type drift layer 2 are formed (Step S1: First to Third Steps). The state up to this point is shown in Figure 5. For example, when using a multi-stage epitaxial method, n -Each time an n-type epitaxial layer 42, which will become an n-type drift layer 2, is epitaxially grown in multiple stages (for example, 9 stages) on the n-type buffer layer 3, n-type regions 52, 55 and p-type regions 53, 56 are selectively formed in the n-type epitaxial layer 42 by ion implantation so that regions of the same conductivity type are adjacent to each other in the depth direction Z. For example, the n-type regions in the final stage or the stage immediately preceding the final stage - After the growth of the n-type epitaxial layer 42 which becomes the type buffer layer 3, + By not performing p-type ion implantation in the portion where the type starting substrate 41 is drilled, the column length of the second parallel pn layer 54 in the edge-terminating region 30 can be made longer than the column length of the first parallel pn layer 51 in the active region 10. In p-type ion implantation, for example, by changing the acceleration energy between 60 keV and 700 keV, the average impurity concentration of aluminum in one stage of the p-type regions 53 and 56 can be increased to 9.0 × 10⁻⁶. 16 / cm 3 Multiple ion implantations are performed to create a box profile. Since the process of epitaxial growth and multi-stage ion implantation is repeated multiple times in the multi-stage epitaxial method, even if each stage of p-type regions 53 and 56 has a box profile, the cross-section will have one peak and two bottoms in terms of the concentration distribution in the depth direction. These p-type regions 53 and 56, each with one peak and two bottoms in the cross-section, are connected to form a periodic distribution in the depth direction. + The connection point with the p-type base region 4 should ideally extend in the depth direction from the bottom of the concentration in the p-type region 53.

[0062] Furthermore, the first parallel pn layer 51 and the second parallel pn layer 54 are, for example, n - After forming an n-type epitaxial layer 42 which will become an n-type buffer layer 3 and an n-type drift layer 2, trenches (hereinafter referred to as SJ trenches) may be formed in the n-type epitaxial layer 42 to leave portions which will become n-type regions 52 and 55, and the SJ trenches may be filled with p-type epitaxial layers which will become p-type regions 53 and 56, using a trench-filled epitaxial method. For example, n +By making the SJ trench length in the part where the mold starting substrate 41 is excavated shorter than the SJ trench length in other parts, the column length of the second parallel pn layer 54 in the edge termination region 30 can be made longer than the column length of the first parallel pn layer 51 in the active region 10.

[0063] Next, n + A mask 60 is formed with an opening for the part to be dug out on the type drain region 1 side (step S2). The state up to this point is shown in Figure 6. For example, the mask 60 is formed from an oxide film mask.

[0064] Next, the front surface of the semiconductor substrate 40 is etched (Step S3: 4th step). The etching can be either dry etching or wet etching. This etches the entire active region 10 and intermediate region 20 and a portion of the edge termination region 30. + The area is excavated towards the drain region 1 side. The state up to this point is shown in Figure 7.

[0065] Next, the edge structure is formed (step S4). For example, a resist 62 is formed in which the region where the JTE structure 32 is to be formed is opened, and the JTE structure 32 is formed on the front surface of the semiconductor substrate 40 by ion implantation of p-type impurities. The state up to this point is shown in Figure 8. Similarly, the previous resist 62 is removed, and n + A resist 62 is formed in which the region where the n-type channel stopper region 34 is formed is opened, and by ion implantation of n-type impurities, n-type impurities are implanted on the front surface of the semiconductor substrate 40. + A channel stopper region 34 is formed. Similarly, the previous resist 62 is removed, and n - A resist 62 is formed in which the region where the mold layer 35 is formed is open, and n-type impurities are ion-implanted on the front surface of the semiconductor substrate 40. - A mold layer 35 is formed. Next, the resist 62 is removed.

[0066] Next, p + Form the base region 4 (step S5: fifth step). For example, p +A resist 62 is formed in which the region where the p-type base region 4 is formed is open, and a p + type base region 4 is formed on the front surface of the semiconductor substrate 40 by ion implantation of p-type impurities. The p + type region 11 of the intermediate region 20 is also formed simultaneously. The state up to this point is described in FIG. 9. Next, the resist 62 is removed.

[0067] Next, an n + type source region 5 is formed (step S6: sixth step). For example, a resist 62 is formed in which the region where the n-type source region 5 is formed is open, and an n-type source region 5 is formed on the front surface of the semiconductor substrate 40 by ion implantation of n-type impurities. The state up to this point is described in FIG. 10. Next, the resist 62 is removed. Next, a heat treatment (annealing) is performed to activate the p + type base region 4 and the n + type source region 5. Also, the order of forming the p + type base region 4 and the n + type source region 5 can be changed variously. + type base region 4 and the n + type source region 5.

[0068] Next, a gate structure is formed (step S7: seventh step). For example, next, the front surface side of the semiconductor substrate 40 is thermally oxidized to form a gate insulating film 8. Next, a polycrystalline silicon layer doped with, for example, phosphorus is formed as the gate electrode 9 on the gate insulating film 8. Next, the polycrystalline silicon layer is patterned and selectively removed, and the polycrystalline silicon layer is left on the portion sandwiched between the n + type source region 5 of the p + type base region 4 and the n-type region 52. At this time, the polycrystalline silicon layer may be left on the n-type region.

[0069] Next, an interlayer insulating film 14, for example, phosphosilicate glass (PSG), is formed so as to cover the gate electrode 9. Next, the interlayer insulating film 14 and the gate insulating film 8 are patterned and selectively removed. For example, n +By removing the interlayer insulating film 14 and gate insulating film 8 on the mold source region 5, a contact hole is formed, n + The mold source region 5 is exposed. Next, heat treatment (reflow) is performed to flatten the interlayer insulating film 14.

[0070] Next, a source electrode (not shown) is deposited by sputtering, and the source electrode is patterned by photolithography and etching. At this time, the source electrode is embedded in the contact hole, n + The type source region 5 and the source electrode are electrically connected. A tungsten plug or the like may be embedded in the contact hole via a barrier metal.

[0071] Next, a nickel film, for example, is deposited on the surface (back side of the semiconductor substrate) of the semiconductor substrate 40 as a drain electrode (not shown). Then, heat treatment is performed to form an ohmic junction between the semiconductor substrate 40 and the drain electrode. This completes the silicon carbide semiconductor device shown in Figure 1.

[0072] As described above, according to this embodiment, the column length of the second parallel pn layer in the edge termination region is longer than the column length of the first parallel pn layer in the active region. This makes it possible to raise the breakdown voltage of the edge termination region to a higher level than that of the active region. Because the avalanche current when an avalanche occurs is shared by the active region with a larger area, the breakdown of the silicon carbide semiconductor device can be suppressed.

[0073] In the above description, the case where a MOS gate structure is formed on the first main surface of a silicon carbide substrate has been described as an example. However, the present disclosure is not limited to this, and various changes such as the surface orientation of the substrate main surface are possible. Further, in the embodiments of the present disclosure, a planar MOSFET has been described as an example. However, the present disclosure is not limited to this, and it can be applied to semiconductor devices having various configurations such as trench MOSFETs, planar IGBTs, trench IGBTs, and other MOS type semiconductor devices. Further, in each of the above-described embodiments, the case where silicon carbide is used as the semiconductor has been described as an example. However, the present disclosure is also applicable to semiconductors other than silicon carbide, such as silicon (Si) and gallium nitride (GaN). Further, in the present disclosure, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, the present disclosure also holds when the first conductivity type is p-type and the second conductivity type is n-type.

Industrial Applicability

[0074] As described above, the semiconductor device and the method of manufacturing the semiconductor device according to the present disclosure are useful for high-voltage-resistant semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Reference Numerals

[0075] 1, 101 n + type drain region 2, 102 n-type drift layer 3, 103 n - type buffer layer 4, 104 p + type base region 5, 105 n + type source region 8, 108 gate insulating film 9, 109 gate electrode 10, 110 active region 11, 111 p + type region 14, 114 interlayer insulating film 20, 120 intermediate region 30, 130 edge termination region 32, 132 JTE structure 34, 134 n +Type channel stopper region 35 n - mold layer 40, 140 semiconductor substrates 41, 141 n + Mold starting substrate 42, 142 n-type epitaxial layers 50, 150 Silicon Carbide Semiconductor Devices 51 1st parallel pn layer 52 n-type region of the first parallel pn layer 53 p-type region of the first parallel pn layer 54 2nd parallel pn layer 55 n-type region of the second parallel pn layer 56 p-type region of the second parallel pn layer 60 Oxide film 62 Resist 151 parallel pn layer 152 n-type region of parallel pn layer 153 p-type region of parallel pn layer X Direction parallel to the front surface of the semiconductor substrate (first direction) Y: A direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction (second direction). Z-direction (depth)

Claims

1. A semiconductor device having an active region and a terminal structure disposed outside the active region and surrounding the periphery of the active region, A first semiconductor layer of the first conductivity type, having a lower impurity concentration than the semiconductor substrate, is provided on the front surface of the first conductivity type semiconductor substrate. A second semiconductor layer of a first conductivity type having a higher impurity concentration than the first semiconductor layer is provided on the upper surface of the first semiconductor layer, Equipped with, In the aforementioned active region, A first parallel pn structure is provided in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer, A first semiconductor region of a second conductivity type is provided on the surface layer of the first parallel pn structure of the active region, A second semiconductor region of a first conductivity type is selectively provided on the surface layer of the first semiconductor region of the active region, A gate electrode is provided via a gate insulating film that is in contact with a part of the first semiconductor region and a part of the second semiconductor region, Equipped with, In the aforementioned terminal structure, The second semiconductor layer comprises a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface. The second semiconductor layer of the termination structure is thicker than the second semiconductor layer of the active region. A semiconductor device characterized in that the column length of the second parallel pn structure is longer than the column length of the first parallel pn structure.

2. The semiconductor device according to claim 1, characterized in that the second parallel pn structure is longer on the side opposite to the semiconductor substrate than the first parallel pn structure.

3. The semiconductor device according to claim 1, characterized in that the first semiconductor region, the second semiconductor region, the gate insulating film, and the gate electrode are provided on the semiconductor substrate side from the front surface of the second semiconductor layer of the termination structure.

4. The terminal structure comprises a third semiconductor region of a second conductivity type provided on the surface layer of the second parallel pn structure, The second semiconductor layer of the termination structure has a region that is thicker than the second semiconductor layer of the active region and a region that is the same thickness as the second semiconductor layer of the active region. The semiconductor device according to claim 1, characterized in that the third semiconductor region is provided in the thick region of the second semiconductor layer and the region of the second semiconductor layer having the same thickness.

5. The semiconductor device according to claim 1, characterized in that the fourth column region of the second parallel pn structure is in contact with the first column region of the first parallel pn structure.

6. A method for manufacturing a semiconductor device having an active region and a terminal structure disposed outside the active region and surrounding the periphery of the active region, A first step is to form a first semiconductor layer of the first conductivity type having a lower impurity concentration than the semiconductor substrate on the front surface of the first conductivity type semiconductor substrate, A second step involves forming a second semiconductor layer of a first conductivity type with a higher impurity concentration than the first semiconductor layer on the upper surface of the first semiconductor layer, A third step of forming a first parallel pn structure in which a first column region of a first conductivity type and a second column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer of the active region, and a second parallel pn structure in which a third column region of a first conductivity type and a fourth column region of a second conductivity type are repeatedly and alternately arranged in a direction parallel to the front surface within the second semiconductor layer of the terminal structure, A fourth step involves etching and deepening the surface of the second semiconductor layer on which the first parallel pn structure is formed, A fifth step is to form a first semiconductor region of a second conductivity type on the surface of the second semiconductor layer excavated in the fourth step, A sixth step is to selectively form a second semiconductor region of a first conductivity type on the surface of the second semiconductor layer excavated in the fourth step, A seventh step in which a gate electrode is formed via a gate insulating film that is in contact with a part of the first semiconductor region and a part of the second semiconductor region, Includes, A method for manufacturing a semiconductor device, characterized in that, in the third step, the column length of the second parallel pn structure is made longer than the column length of the first parallel pn structure.

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