Indication device

Abstract

Minimize short-circuit failures between connecting electrodes. [Solution] The device includes a first reflective electrode connected to a drive transistor and a second reflective electrode connected to power wiring, an adhesive layer placed on these, a first planarization layer placed on the adhesive layer so as to surround a portion of the sides of a plurality of light-emitting elements, a first connecting electrode placed on the first planarization layer to connect the first electrode and the drive transistor, a second connecting electrode placed on the first planarization layer at a distance from the first connecting electrode and connected to the second reflective electrode, a passivation layer placed on the first and second connecting electrodes, a second planarization layer placed on the passivation layer so as to surround a portion of the sides of a plurality of light-emitting elements, and a third connecting electrode placed on the second planarization layer to connect the second electrode and the power wiring, wherein the passivation layer exposes the end of the first connecting electrode placed so as to surround a portion of the sides of each of the plurality of light-emitting elements, and the second planarization layer covers the end of the first connecting electrode.

Description

[Technical Field]

[0001] This specification relates to a display device, and more particularly to a display device that minimizes short-circuit failures between connecting electrodes. [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc., include organic light-emitting displays (OLEDs) that emit light themselves, and liquid crystal displays (LCDs) that require a separate light source.

[0003] Display devices are no longer limited to computer monitors and TVs; their applications have diversified to include personal portable devices, and research is underway on display devices that have a large display area while having reduced volume and weight.

[0004] In recent years, display devices including LEDs (Light Emitting Diodes) have been attracting attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are highly reliable and have a longer lifespan compared to liquid crystal displays and organic light-emitting displays. In addition, LEDs not only have a fast illumination speed, but also excellent luminous efficiency, strong impact resistance, and superior stability, and can display high-brightness images. [Overview of the project] [Problems that the invention aims to solve]

[0005] The problem that this specification aims to solve is to provide a display device that minimizes the lifting of reflective electrodes due to moisture penetration.

[0006] The problem that this specification aims to solve is to provide a display device that reduces crystallization of the reflective electrode.

[0007] The problem that this specification aims to solve is to provide a display device that enables self-alignment of the first connecting electrode and the first electrode of the light-emitting element.

[0008] The problem that this specification aims to solve is to provide a display device that enables self-alignment of the third connecting electrode and the second electrode of the light-emitting element.

[0009] The problem that this specification aims to solve is to provide a display device that minimizes short-circuit failures between connecting electrodes.

[0010] The problem that this specification aims to solve is to provide a display device with reduced wiring resistance.

[0011] The problem that this specification aims to solve is to provide a display device that can detect whether or not there is a defect in the light-emitting element, regardless of whether or not there is a defect in the driving transistor.

[0012] The problem that this specification aims to solve is to provide a display device with improved electrical connectivity by minimizing connectivity defects caused by residual film generated during the process.

[0013] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0014] A display device according to one embodiment of this specification comprises a substrate on which a plurality of subpixels are defined, power wiring and a drive transistor disposed on the substrate, a first reflective electrode and a second reflective electrode disposed spaced apart from each other on the power wiring and the drive transistor, the first reflective electrode being connected to the drive transistor and the second reflective electrode being connected to the power wiring, an adhesive layer disposed on the first reflective electrode and the second reflective electrode, a plurality of light-emitting elements disposed on the adhesive layer for each of the plurality of subpixels and including the first electrode and the second electrode, a first planarization layer disposed on the adhesive layer so as to surround a part of the side surface of the plurality of light-emitting elements, and a first planarization layer The device includes a first connecting electrode positioned on top and connecting the first electrode and the drive transistor, a second connecting electrode positioned on the first planarization layer at a distance from the first connecting electrode and connected to the second reflective electrode, a passivation layer positioned on the first and second connecting electrodes, a second planarization layer positioned on the passivation layer and surrounding a portion of the sides of the plurality of light-emitting elements, and a third connecting electrode positioned on the second planarization layer and connecting the second electrode and the power supply wiring, wherein the passivation layer exposes the end of the first connecting electrode positioned to surround a portion of the sides of each of the plurality of light-emitting elements, and the second planarization layer covers the end of the first connecting electrode.

[0015] A display device according to one embodiment of this specification includes a substrate on which a plurality of pixels, each including a plurality of subpixels, are defined; power wiring and a drive transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed spaced apart from each other on the power wiring and the drive transistor, the first reflective electrode being connected to the drive transistor and the second reflective electrode being connected to the power wiring; an adhesive layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements, each of the plurality of subpixels, disposed on the adhesive layer and including a first electrode and a second electrode; a first planarization layer disposed on the adhesive layer so as to surround a part of the sides of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connecting the first electrode and the drive transistor; a second connecting electrode disposed spaced apart from the first connecting electrode on the first planarization layer and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and decreasing in height as it approaches the plurality of light-emitting elements; and a third connecting electrode disposed on the second planarization layer and connecting the second electrode and the power wiring. Therefore, short-circuit failures between connecting electrodes can be minimized.

[0016] Specific details of other embodiments are included in the detailed description and drawings.

[0017] According to the embodiments of this specification, by placing a passivation layer on a connecting electrode connected to a reflective electrode, the phenomenon of moisture penetration into the reflective electrode can be minimized.

[0018] According to the embodiments described herein, the lifting of the reflective electrode due to moisture penetration can be minimized.

[0019] According to the embodiments described herein, the display device can be driven at low power in terms of reducing production energy by minimizing potential failures due to wiring corrosion and improving the lifespan of the display device.

[0020] According to the embodiments of the present specification, through the ashing process of the first planarization layer and the second planarization layer, the first connection electrode and the third connection electrode can be connected to the light-emitting element in a self-aligned manner without a separate alignment process, thereby ensuring a light-emitting element transfer margin.

[0021] According to the embodiments of the present specification, by disposing a passivation layer on the first connection electrode so that the first connection electrode and the third connection electrode are separated, it is possible to prevent a short circuit failure between the first connection electrode and the third connection electrode.

[0022] According to the embodiments of the present specification, by reflowing the second planarization layer on the portion where the first connection electrode is exposed by the passivation layer, it is possible to separate the first connection electrode and the third connection electrode and prevent a short circuit failure in which the first connection electrode and the third connection electrode are connected.

[0023] According to the embodiments of the present specification, a lighting inspection signal can be applied to the light-emitting element without passing through the driving transistor, and the presence or absence of a defect in the light-emitting element can be detected regardless of the presence or absence of a defect in the driving transistor.

[0024] The effects according to the present specification are not limited to the contents exemplified above, and more various effects are included in the present specification.

Brief Description of the Drawings

[0025] [Figure 1] It is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 2] It is an enlarged plan view of a pixel of a display device according to an embodiment of the present specification. [Figure 3] It is a cross-sectional view taken along III-III' of FIG. 2. [Figure 4a] It is a process diagram of a manufacturing method of a display device according to an embodiment of the present specification. [Figure 4b] It is a process diagram of a manufacturing method of a display device according to an embodiment of the present specification. <​This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Figure 4d] This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Figure 4e] This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Figure 4f] This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Figure 4g] This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Figure 4h] This is a process diagram of a method for manufacturing a display device according to one embodiment of this specification. [Modes for carrying out the invention]

[0026] The advantages and features of this specification, and the methods for achieving them, will become clearer with reference to the examples described below in detail with the accompanying drawings. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to make the disclosure of this specification complete and to fully inform a person with ordinary skill in the art to which this specification belongs.

[0027] The shapes, areas, proportions, angles, numbers, etc. disclosed in the drawings illustrating the embodiments of this specification are illustrative and the specification is not limited to those illustrated. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a specific explanation of related prior art would unnecessarily obscure the gist of this specification, such detailed explanation will be omitted. Where "includes," "has," "is made," etc., are used in this specification, other parts may be added unless "only" is used. When a component is expressed singularly, it includes cases where it includes multiple components unless otherwise explicitly stated.

[0028] When interpreting the constituent elements, they shall be interpreted as including a margin of error, even if not explicitly stated otherwise.

[0029] When describing a spatial relationship, for example, when describing the positional relationship between two parts using phrases like "on top," "above," "below," or "next to," it is acceptable for one or more other parts to be located between the two parts, as long as "immediately" or "directly" is not used.

[0030] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0031] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0032] Throughout the specification, the same reference numeral refers to the same component.

[0033] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0034] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0035] In the following, this specification will be described with reference to the drawings.

[0036] Figure 1 is a schematic diagram of a display device according to one embodiment of this specification. In Figure 1, for the sake of explanation, only the display panel PN, gate drive unit GD, data drive unit DD, and timing controller TC are shown among the various components of the display device 100.

[0037] Referring to Figure 1, the display device 100 includes a display panel PN containing a plurality of subpixels SP, a gate drive unit GD and a data drive unit DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0038] The gate drive unit GD supplies multiple scan signals to multiple scan wirings SL based on multiple gate control signals provided by the timing controller TC. In Figure 1, one gate drive unit GD is shown spaced apart on one side of the display panel PN, but the number and arrangement of gate drive units GD are not limited to this.

[0039] The data drive unit DD converts video data input from the timing controller TC into data voltage using a reference gamma voltage, based on multiple data control signals provided by the timing controller TC. The data drive unit DD can then supply the converted data voltage to multiple data wirings DL.

[0040] The timing controller TC aligns the video data input from an external source and supplies it to the data drive unit DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals input from an external source, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then control the gate drive unit GD and the data drive unit DD by supplying the generated gate control signals and data control signals to the gate drive unit GD and the data drive unit DD, respectively.

[0041] The display panel PN is configured to display images to the user and includes multiple sub-pixels SP. Multiple scan lines SL and multiple data lines DL intersect within the display panel PN, and each of the multiple sub-pixels SP is connected to the scan lines SL and data lines DL. In addition, although not shown in the drawing, each of the multiple sub-pixels SP may be connected to high-potential power lines, low-potential power lines, reference lines, etc.

[0042] The display panel PN may define a display area AA and a non-display area NA that surrounds the display area AA.

[0043] Display area AA is the area where the image is displayed on the display device 100. Display area AA may contain multiple subpixels SP that constitute multiple pixels PX, and circuits for driving the multiple subpixels SP. Multiple subpixels SP are the smallest units that constitute display area AA, and n subpixels SP can form one pixel PX. Each of the multiple subpixels SP may contain a light-emitting element and a thin-film transistor or the like for driving the light-emitting element. Multiple light-emitting elements may be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting elements may be LEDs (Light-emitting Diodes) or micro-LEDs (Micro Light-emitting Diodes).

[0044] Multiple signal lines are arranged in the display area AA to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL that supply data voltage to each of the multiple sub-pixels SP, and multiple scan lines SL that supply gate voltage to each of the multiple sub-pixels SP. Multiple scan lines SL may extend from the display area AA in one direction and be connected to the multiple sub-pixels SP, and multiple data lines DL may extend from the display area AA in directions other than one direction and be connected to the multiple sub-pixels SP. In addition, low-potential power supply lines, high-potential power supply lines, etc., may be further arranged in the display area AA, but are not limited to these.

[0045] The non-display area NA is an area where no image is displayed and can be defined as an area extending from the display area AA. The non-display area NA may contain link wiring and pad electrodes for transmitting signals to the subpixels SP of the display area AA, as well as drive ICs such as gate driver ICs and data driver ICs. The non-display area NA may be located on the back of the display panel PN, i.e., the side without subpixels SP, or it may be omitted, and is not limited to what is shown in the drawing.

[0046] On the other hand, drive units such as the gate drive unit GD, data drive unit DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate drive unit GD may be implemented in the non-display area NA using the GIP (Gate In Panel) method, or it may be implemented in the display area AA between multiple sub-pixels SP using the GIA (Gate In Active Area) method. For example, the data drive unit DD and timing controller TC may be formed on a separate flexible film and printed circuit board, and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. If the gate drive unit GD is implemented using the GIP method, and the data drive unit DD and timing controller TC transmit signals to the display panel PN through the pad electrodes in the non-display area NA, it is necessary to secure an area in the non-display area NA to accommodate the gate drive unit GD and the pad electrodes, which may increase the bezel size.

[0047] In contrast, when the gate drive unit GD is implemented inside the display area AA using the GIA method, and side wiring is formed to connect the signal wiring on the front of the display panel PN to the pad electrodes on the back of the display panel PN, and a flexible film and printed circuit board are bonded to the back of the display panel PN, the non-display area NA on the front of the display panel PN can be minimized. That is, when the gate drive unit GD, data drive unit DD, and timing controller TC are connected to the display panel PN in the manner described above, it may be possible to realize a zero-bezel system where there is virtually no bezel.

[0048] Figure 2 is an enlarged plan view of a pixel of a display device according to one embodiment of this specification. Figure 3 is a cross-sectional view along line III-III' in Figure 2. In Figure 2, only the first reflective electrode RE1, the second reflective electrode RE2, the first connecting electrode CE1, the second connecting electrode CE2, and the light-emitting element LED are shown from the configuration of the display device 100. In Figure 3, a cross-sectional view of the first subpixel including the first light-emitting element 120 is shown, which is the same as the cross-section of the second subpixel including the second light-emitting element 130 and the cross-section of the third subpixel including the third light-emitting element 140.

[0049] First, referring to Figures 1 and 3, the display panel PN includes multiple pixels PX, each consisting of multiple subpixels SP. Each of the multiple subpixels SP includes a light-emitting element LED and a pixel circuit and can emit light independently. A single pixel PX may include a first subpixel, a second subpixel, and a third subpixel. For example, a single pixel PX may consist of one first subpixel, one second subpixel, and one third subpixel. In this case, the first subpixel may be a red subpixel, the second subpixel a green subpixel, and the third subpixel a blue subpixel, but is not limited to this.

[0050] Multiple subpixels SP may have multiple light-emitting LEDs. Specifically, the multiple light-emitting LEDs include a first light-emitting element 120, a second light-emitting element 130, and a third light-emitting element 140. The first subpixel may have the first light-emitting element 120, the second subpixel may have the second light-emitting element 130, and the third subpixel may have the third light-emitting element 140. For example, the first light-emitting element 120 may be a red light-emitting element, the second light-emitting element 130 may be a green light-emitting element, and the third light-emitting element 140 may be a blue light-emitting element.

[0051] On the other hand, referring to Figure 2, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 may have different shapes from each other. For example, the planar shape of the first light-emitting element 120 may be circular, and the planar shapes of the second light-emitting element 130 and the third light-emitting element 140 may be elliptical. In this case, the second light-emitting element 130 and the third light-emitting element 140 may be of different sizes and have different elliptical shapes from each other. On the other hand, the major axis directions of the second light-emitting element 130 and the third light-emitting element 140 may be the same, but are not limited to this.

[0052] Referring to Figure 3, the first light-emitting element 120 can include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126. On the other hand, although not shown in the drawing, the planar shape of the first semiconductor layer 121 of the first light-emitting element 120 can be circular, and the planar shape of the second semiconductor layer 123 can be semicircular. The planar shape of the first electrode 124 can be elliptical. The second electrode 125 can be semicircular, similar to the upper surface of the second semiconductor layer 123.

[0053] The second light-emitting element 130 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. On the other hand, although not shown in the drawings, the first semiconductor layer and the first electrode of the second light-emitting element 130 may have an elliptical planar shape. In this case, the direction of the major axis of the first semiconductor layer may be configured to be different from the direction of the major axis of the first electrode. For example, if the first semiconductor layer has an elliptical shape with its major axis in the transverse direction, the first electrode may have an elliptical shape with its major axis in the vertical direction. For example, the first electrode may be positioned on one side edge of the first semiconductor layer on its upper surface in the direction of its major axis. The planar shape of the second semiconductor layer and the second electrode may be a cut ellipse shape.

[0054] The third light-emitting element 140 may include a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a first electrode, a second electrode, and a passivation film. On the other hand, although not shown in the drawings, the first semiconductor layer and the first electrode of the third light-emitting element 140 may have an elliptical planar shape. Unlike the second light-emitting element, in the third light-emitting element 140, the long axis direction of the first semiconductor layer may be the same as the long axis direction of the first electrode. For example, the first electrode may be located on one side edge of the first semiconductor layer in the long axis direction on the upper surface of the first semiconductor layer. The planar shape of the second semiconductor layer and the second electrode may be a cut ellipse.

[0055] That is, in the display device 100 according to one embodiment of this specification, the first light-emitting element 120, the second light-emitting element 130, and the third light-emitting element 140 can each be configured with a different shape from one another, thereby separating the multiple light-emitting element LEDs. For example, when the light-emitting element LEDs are self-assembled, the multiple light-emitting element LEDs can be formed with different shapes from one another and self-assembled at positions corresponding to each of the multiple sub-pixels SP. However, the shapes of the multiple light-emitting element LEDs are illustrative and not limited thereto.

[0056] On the other hand, referring to Figure 2, a first contact area CA1, a second contact area CA2, and an illumination inspection area APA may be defined in a plurality of pixels PX of the display panel PN of the display device 100 according to one embodiment of this specification.

[0057] The first contact region CA1 and the second contact region CA2 may be regions to which the power supply wiring VDD and the third connecting electrode CE3 are electrically connected. For example, in the first contact region CA1, the third connecting electrode CE3 may be electrically connected to the power supply wiring through the second reflective electrode RE2 and the second connecting electrode CE2. In the second contact region CA2, the third connecting electrode CE3 extending from the first contact region CA1 may be electrically connected to the power supply wiring by further connecting it to the second connecting electrode CE2 extending from the first contact region CA1.

[0058] The lighting test area APA may be an area that transmits a lighting test signal to detect whether or not there is a defect in the light-emitting element LED. For example, in the lighting test area APA, the lighting test pattern can transmit the lighting test signal to the first electrode of the light-emitting element LED through the first connecting electrode CE1 without passing through the drive transistor DT. Therefore, it is possible to detect whether or not there is a defect in the light-emitting element LED regardless of the defect in the drive transistor DT. More detailed information related to this will be explained later with reference to Figure 3.

[0059] Next, referring to Figure 3, in the display panel PN of the display device 100 according to one embodiment of this specification, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a first passivation layer 114a, a second passivation layer 114b, an overcoating layer 115, an adhesive layer 116, a first planarization layer 117a, a second planarization layer 117b, a bank 118, a third planarization layer 119, a drive transistor DT, a light-emitting element LED, a reflective electrode RE, a light-shielding layer LS, an auxiliary electrode LE, a first connecting electrode CE1, a second connecting electrode CE2, a third connecting electrode CE3, a capacitor Cst, an intermediate electrode TM, and a lighting inspection pattern APP may be arranged on each of the multiple subpixels SP.

[0060] First, the substrate 110 is a structure for supporting the various components included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. Furthermore, the substrate 110 may contain polymers or plastics, and may be made of a flexible material.

[0061] A light-shielding layer LS may be placed on each of the multiple sub-pixels SP on the substrate 110. The light-shielding layer LS blocks the light incident on the active layer ACT of the drive transistor DT, which will be described later, at the bottom of the substrate 110. By blocking the light incident on the active layer ACT of the drive transistor DT with the light-shielding layer LS, leakage current can be minimized.

[0062] A buffer layer 111 can be placed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be made of, for example, silicon oxide (SiO2). x ) or silicon nitride (SiN x The circuit may consist of a single or multiple layer of the ) but is not limited thereto. However, the buffer layer 111 may be omitted depending on the type of substrate 110 and the type of transistor, but is not limited thereto.

[0063] A drive transistor DT may be placed on the buffer layer 111. The drive transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0064] An active layer ACT may be placed on the buffer layer 111. The active layer ACT may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0065] A gate insulating layer 112 may be placed on the active layer ACT. The gate insulating layer 112 is an insulating layer for insulating the active layer ACT from the gate electrode GE, and is made of silicon oxide (SiO x ) or silicon nitride (SiN x It may consist of a single layer or multiple layers, but is not limited to this.

[0066] A gate electrode GE may be placed on the gate insulating layer 112. The gate electrode GE may be composed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0067] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b may be placed on the gate electrode GE. Contact holes are formed in the gate insulating layer 112, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b for the source electrode SE and the drain electrode DE to connect to the active layer ACT, respectively. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers that protect the lower structure of the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, and are made of silicon oxide (SiO x ) or silicon nitride (SiN x It may consist of a single layer or multiple layers, but is not limited to this.

[0068] A source electrode SE and a drain electrode DE, electrically connected to the active layer ACT, may be arranged on the second interlayer insulating layer 113b. The source electrode SE and drain electrode DE may, but are not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0069] On the other hand, although this specification has described a configuration in which a first interlayer insulating layer 113a and a second interlayer insulating layer 113b, i.e., multiple insulating layers, are arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE, the specification is not limited to this configuration, and may also describe a configuration in which only one insulating layer is arranged between the gate electrode GE, the source electrode SE, and the drain electrode DE.

[0070] Although not shown in the drawings, the pixel circuit may also include, but is not limited to, a switching transistor, a sensing transistor, a light emission control transistor, etc., in addition to the driving transistor DT.

[0071] On the other hand, an intermediate electrode TM may be placed on the first interlayer insulating layer 113a. The intermediate electrode TM may be placed so as to overlap with the gate electrode GE of the drive transistor DT across the first interlayer insulating layer 113a, and together with the gate electrode GE of the drive transistor DT may form a capacitor, but is not limited to this.

[0072] An auxiliary electrode LE may be placed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE of the drive transistor DT on the second interlayer insulating layer 113b. For example, the light-shielding layer LS is electrically connected to either the source electrode SE or the drain electrode DE of the drive transistor DT through the auxiliary electrode LE and ceases to operate as a floating gate, thereby minimizing threshold voltage fluctuations of the drive transistor DT caused by the floating light-shielding layer LS. In the drawing, the light-shielding layer LS is shown to be connected to the source electrode SE of the drive transistor DT, but the light-shielding layer LS may also be connected to the drain electrode DE of the drive transistor DT, and is not limited to this.

[0073] A capacitor Cst may be placed on the gate insulating layer 112. The capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0074] First, a first capacitor electrode Cst1 may be placed on the gate insulating layer 112. The first capacitor electrode Cst1 may be placed on the same layer as the gate electrode GE and may be made of the same material, but is not limited to this.

[0075] A second capacitor electrode Cst2 may be placed on the first interlayer insulating layer 113a. The second capacitor electrode Cst2 may, but is not limited to, be placed on the same layer as the intermediate electrode TM and be made of the same material. The second capacitor electrode Cst2 may be placed so as to overlap the first capacitor electrode Cst1 with the first interlayer insulating layer 113a in between. The second capacitor electrode Cst2 may be connected to the source electrode SE of the drive transistor DT.

[0076] A power supply wiring VDD may be placed on the second interlayer insulating layer 113b. The power supply wiring VDD is electrically connected to the light-emitting element LED together with the drive transistor DT, thereby causing the light-emitting element LED to emit light. The power supply wiring VDD may, but is not limited to, a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0077] A first passivation layer 114a may be placed on the drive transistor DT and the power supply wiring VDD. The first passivation layer 114a can protect the drive transistor DT and the power supply wiring VDD from the penetration of moisture or impurities. The first passivation layer 114a may be made of, for example, silicon oxide (SiO2). x ) or silicon nitride (SiN x The first passivation layer 114a may be composed of a single or multiple layer, but is not limited thereto. However, the first passivation layer 114a may be omitted depending on the type of substrate 110 and the type of transistor, but is not limited thereto.

[0078] An overcoating layer 115 may be placed on the first passivation layer 114a. The overcoating layer 115 can planarize the upper part of the substrate 110 on which the drive transistor DT is located. The overcoating layer 115 may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0079] Multiple reflective electrodes RE can be arranged on the overcoating layer 115, spaced apart from each other. The multiple reflective electrodes RE can electrically connect the light-emitting element LED to the power supply wiring VDD and the drive transistor DT, and at the same time function as reflectors that reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED. The multiple reflective electrodes RE can be formed from a conductive material with excellent reflective properties, and can reflect the light emitted by the light-emitting element LED towards the top of the light-emitting element LED. Therefore, the multiple reflective electrodes RE can include various conductive layers, taking into account light reflection efficiency and resistance. For example, the reflectors can use opaque conductive layers such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, together with transparent conductive layers such as ITO (Indium Tin Oxide), but the structure and material of the reflective electrodes RE are not limited thereto.

[0080] Multiple reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 can electrically connect the drive transistor DT and the light-emitting element LED. The first reflective electrode RE1 can be connected to the source electrode SE or drain electrode DE of the drive transistor DT through contact holes formed in the first passivation layer 114a and the overcoating layer 115. The first reflective electrode RE1 can also be electrically connected to the first electrode 124 of the light-emitting element LED through a first connecting electrode CE1.

[0081] The second reflective electrode RE2 can electrically connect the power supply wiring VDD and the light-emitting element LED. The second reflective electrode RE2 is connected to the power supply wiring VDD through contact holes formed in the first passivation layer 114a and the overcoating layer 115, and can be electrically connected to the second electrode 125 of the light-emitting element LED through the second connecting electrode CE2 and the third connecting electrode CE3, which will be described later.

[0082] The adhesive layer 116 is formed on the front surface of the substrate 110 on multiple reflective electrodes RE, and the light-emitting element LEDs placed on the adhesive layer 116 can be fixed in place. The adhesive layer 116 may consist of a photocurable or thermosetting adhesive material that can be cured by light or heat. For example, the adhesive layer 116 may consist of an acrylic series material containing a photosensitive agent, but is not limited thereto.

[0083] Multiple light-emitting LEDs can be arranged on each of the multiple subpixels SP on the adhesive layer 116. The multiple light-emitting LEDs are elements that emit light when an electric current is applied, and may include light-emitting LEDs that emit red light, green light, blue light, etc., and various hues of light, including white, can be realized by combinations of these. For example, the multiple light-emitting LEDs may be LEDs (Light Emitting Diodes) or micro LEDs (micro LEDs), but are not limited to these.

[0084] The first light-emitting element 120 may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a passivation film 126.

[0085] A first semiconductor layer 121 may be placed on the adhesive layer 116, and a second semiconductor layer 123 may be placed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping specific materials with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be layers doped with n-type and p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited to these.

[0086] A portion of the first semiconductor layer 121 may be positioned to protrude outside the second semiconductor layer 123. The upper surface of the first semiconductor layer 121 may consist of a portion that overlaps with the lower surface of the second semiconductor layer 123 and a portion positioned outside the lower surface of the second semiconductor layer 123, and the light-emitting element LED may be a lateral light-emitting element LED. However, the size and shape of the first semiconductor layer 121 and the second semiconductor layer 123 can be varied and are not limited thereto.

[0087] For example, the first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 in certain directions. The first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 at some edges of the second semiconductor layer 123. A portion of the first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 in a specific direction.

[0088] A light-emitting layer 122 may be placed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123.

[0089] The light-emitting layer 122 may be a single layer or a multi-quantum well (MQW) structure, and may, for example, be made of indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0090] A first electrode 124 may be placed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the drive transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be placed on the upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. For example, the first electrode 124 may be placed along the periphery of the upper surface of the first semiconductor layer 121, and its planar shape may be ring-shaped. The first electrode 124 may be composed of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0091] A second electrode 125 may be placed on the second semiconductor layer 123. The second electrode 125 may be placed on the upper surface of the second semiconductor layer 123. In this case, since the second semiconductor layer 123 is placed on the first semiconductor layer 121, the second electrode 125, which is placed on the upper surface of the second semiconductor layer 123, may be placed at a higher position than the first electrode 124, which is placed on the upper surface of the first semiconductor layer 121. The second electrode 125 is an electrode for electrically connecting the power supply wiring VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be composed of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0092] Next, a passivation film 126 may be placed surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The passivation film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the passivation film 126 that expose the first electrode 124 and the second electrode 125, and the first connecting electrode CE1 and the third connecting electrode CE3, which are formed later, can be electrically connected to the first electrode 124 and the second electrode 125.

[0093] On the other hand, although not shown in Figure 3, the second light-emitting element 130 and the third light-emitting element 140 can be arranged substantially identically to the arrangement of the first light-emitting element 120.

[0094] A first planarization layer 117a may be placed on the adhesive layer 116. The first planarization layer 117a is positioned to surround a portion of the sides of the multiple light-emitting LEDs, thereby fixing and protecting the multiple light-emitting LEDs.

[0095] For example, the first planarization layer 117a may be positioned to surround the passivation film 126 located on the lower edge of the light-emitting element LED. This prevents the first connecting electrode CE1 from being disconnected due to the peeling of the passivation film 126. For example, during the process of separating the wafer from the light-emitting element LED, a portion of the passivation film 126 may be peeled off at the lower edge of the light-emitting element LED. As a result, the passivation film 126 may expose a portion of the first semiconductor layer 121 at the lower edge of the light-emitting element LED. Consequently, a step may be created at the lower edge of the light-emitting element LED due to the peeling of the passivation film 126. In this case, if the first connecting electrode CE1 is positioned to surround the side surface of the passivation film 126, the first connecting electrode CE1 may be disconnected due to the step created by the peeling of the passivation film 126.

[0096] Therefore, by positioning the first planarization layer 117a so as to surround the lower edge of the light-emitting LED before placing the first connecting electrode CE1, the lower edge of the light-emitting LED and the first connecting electrode CE1 can be separated. Thus, even if an undercut structure is formed on the lower edge of the light-emitting LED due to the peeling of the passivation film 126, the first planarization layer 117a contacts at least a portion of the side surface of the light-emitting LED and satisfies the undercut structure, thereby minimizing the phenomenon of the first connecting electrode CE1 being disconnected due to the undercut structure.

[0097] On the other hand, the first planarization layer 117a is positioned lower than the height of the first electrode 124, allowing the first electrode 124 to be exposed. Therefore, the first connecting electrode CE1, which is positioned on the first planarization layer 117a, can be easily connected to the first electrode 124. More detailed information related to this will be explained in detail with reference to Figures 4a to 4h, which will be described later.

[0098] Furthermore, the first planarization layer 117a may include a portion that is relatively lower in height in the area adjacent to the light-emitting element LED. For example, during the contact hole formation process of the passivation film 126 to expose the first electrode 124 and the second electrode 125, a portion of the first planarization layer 117a in the area adjacent to the light-emitting element LED may be removed, resulting in a portion that is relatively lower in height. More detailed information related to this will be explained in detail later with reference to Figures 4a to 4h.

[0099] The first planarization layer 117a may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0100] On the other hand, the first planarization layer 117a may be lower than the height of the first electrode 124. For example, the thickness of the first planarization layer 117a can be adjusted by performing an ashing process. For instance, after coating the material layer of the first planarization layer 117a to cover the light-emitting element LED, an ashing process can be performed to reduce the overall thickness of the material layer of the first planarization layer 117a, thereby forming the height of the first planarization layer 117a lower than the height of the first electrode 124. In this way, the first planarization layer 117a can expose the first electrode 124. Consequently, the first connecting electrode CE1 placed on the first planarization layer 117a can be easily connected to the first electrode 124 without the need for a separate contact hole. Thus, the first connecting electrode CE1 and the first electrode 124 can be self-aligned without the need to secure a process margin.

[0101] A first connecting electrode CE1 may be placed on the first planarization layer 117a. The first connecting electrode CE1 is placed on each of a plurality of subpixels SP and is an electrode for electrically connecting the light-emitting element LED and the drive transistor DT, and may be arranged in a manner that surrounds the light-emitting element LED. The first connecting electrode CE1 may be connected to the first reflective electrode RE1 through contact holes formed in the first planarization layer 117a and the adhesive layer 116. Thus, the first connecting electrode CE1 may be electrically connected to either the source electrode SE or the drain electrode DE of the drive transistor DT through the first reflective electrode RE1. For example, the first connecting electrode CE1 may connect the first electrode 124 of the light-emitting element LED to the source electrode SE of the drive transistor DT, but is not limited to this. The first connecting electrode CE1 may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited to this.

[0102] On the first planarization layer 117a, a second connection electrode CE2 can be disposed in the first contact region CA1 and the second contact region CA2. The second connection electrode CE2 is an electrode for electrically connecting the light-emitting element LED and the power supply wiring VDD. The second connection electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the first planarization layer 117a and the adhesive layer 116. For example, the second connection electrode CE2 can be electrically connected to the second reflective electrode RE2 through the first contact hole CH1 of the adhesive layer 116 disposed in the first contact region CA1 and the second contact hole CH2 of the first planarization layer 117a that overlaps with the first contact hole CH1. Therefore, the second connection electrode CE2 can be electrically connected to the power supply wiring VDD through the second reflective electrode RE2. For example, the second connection electrode CE2 can connect the second electrode 125 of the light-emitting element LED and the power supply wiring VDD, but is not limited thereto.

[0103] On the other hand, the second connection electrode CE2 can be disposed on the same layer as the first connection electrode CE1 and can be made of the same material, but is not limited thereto. The second connection electrode CE2 can be made of, for example, a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited thereto.

[0104] A second passivation layer 114b can be disposed on the plurality of first connection electrodes CE1 and the plurality of second connection electrodes CE2. The second passivation layer 114b is disposed on the plurality of first connection electrodes CE1 and the plurality of second connection electrodes CE2 and can block the penetration of moisture or impurities into the plurality of reflective electrodes RE1 connected to the plurality of first connection electrodes CE1 and the plurality of second connection electrodes CE2. The second passivation layer 114b can be composed of, for example, a single layer or multiple layers of silicon oxide (SiO x ) or silicon nitride (SiN x ), but is not limited thereto.

[0105] Furthermore, the second passivation layer 114b is positioned to cover at least a portion of the first connecting electrode CE1, so that the first connecting electrode CE1 and the third connecting electrode CE3 are separated from each other. Thus, the second passivation layer 114b can prevent a short circuit between the first connecting electrode CE1 and the third connecting electrode CE3.

[0106] The second passivation layer 114b may include a first opening OP1 that exposes the first planarization layer 117a. For example, the first opening OP1 may be located between the first connecting electrode CE1 and the second connecting electrode CE2.

[0107] A second planarization layer 117b may be placed on the second passivation layer 114b. The second planarization layer 117b, together with the first planarization layer 117a, can planarize the upper part of the substrate 110 on which the light-emitting element LED is placed, and together with the adhesive layer 116, can fix the light-emitting element LED on the substrate 110.

[0108] Furthermore, the second planarization layer 117b is positioned to cover the first connecting electrode CE1, so that the first connecting electrode CE1 and the third connecting electrode CE3 are separated from each other. Thus, a short circuit between the first connecting electrode CE1 and the third connecting electrode CE3 can be prevented.

[0109] In particular, the second planarization layer 117b can be positioned to cover the end of the first connecting electrode CE1 exposed by the second passivation layer 114b, so that the first connecting electrode CE1 and the third connecting electrode CE3 are separated from each other. For example, during the process of forming the second planarization layer 117b, the second planarization layer 117b can be reflowed through a curing process so that it flows down onto the end of the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, the height of the portion of the second planarization layer 117b that overlaps with the end of the first connecting electrode CE1 exposed by the second passivation layer 114b can be relatively low. In other words, the second planarization layer 117b may have a slope in the portion surrounding the end of the first connecting electrode CE1.

[0110] For example, the end of the first connecting electrode CE1 in contact with the light-emitting element LED may be exposed by the second passivation layer 114b. Therefore, the height of the second planarization layer 117b may decrease as it approaches the light-emitting element LED. However, since the second planarization layer 117b is positioned to cover the end of the first connecting electrode CE1 exposed by the second passivation layer 114b, the height of the lowest upper surface of the second planarization layer 117b may be higher than the height of the highest upper surface of the end of the first connecting electrode CE1 exposed by the second passivation layer 114b.

[0111] On the other hand, the second planarization layer 117b is positioned at the first opening OP1 and covers the ends of the first connecting electrode CE1 and the second connecting electrode CE2, thereby separating the first connecting electrode CE1 and the second connecting electrode CE2 from each other. Thus, a short circuit between the first connecting electrode CE1 and the second connecting electrode CE2 can be prevented.

[0112] Specifically, an opening is formed in the second planarization layer 117b that overlaps with the first opening OP1 of the second passivation layer 114b, and the second planarization layer 117b can be reflowed into the first opening OP1 through curing. Therefore, the width of the second opening OP2 formed by the reflow of the second planarization layer 117b may be smaller than the width of the first opening OP1. More detailed information related to this will be discussed later with reference to Figures 4a to 4h.

[0113] The second planarization layer 117b may be a single layer or a multi-layer structure, and may, for example, be made of a photoresist or an acrylic-based organic material, similar to the first planarization layer 117a, but is not limited thereto.

[0114] A third connecting electrode CE3 may be placed on the second planarization layer 117b. The third connecting electrode CE3 is an electrode for electrically connecting the light-emitting element LED and the power supply wiring VDD. The third connecting electrode CE3 can be connected to the second reflective electrode RE2 through contact holes formed in the second planarization layer 117b, the second passivation layer 114b, the first planarization layer 117a, and the adhesive layer 116. Thus, the third connecting electrode CE3 can be electrically connected to the power supply wiring VDD through the second reflective electrode RE2. For example, the third connecting electrode CE3 can connect the second electrode 125 of the light-emitting element LED to the power supply wiring VDD, but is not limited to this. For example, the third connecting electrode CE3 may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but is not limited to this.

[0115] For example, the third connecting electrode CE3 is located in the first contact hole CH1 of the adhesive layer 116 placed in the first contact region CA1, the second contact hole CH2 of the first planarization layer 117a, the third contact hole CH3 of the second passivation layer 114b superimposed on the first contact hole CH1 and the second contact hole CH2, and the fourth contact hole CH4 of the second planarization layer 117b superimposed on the first contact hole CH1, the second contact hole CH2, and the third contact hole CH3, and can contact the second connecting electrode CE2. Thus, the third connecting electrode CE3 can be electrically connected to the second reflective electrode RE2 through the second connecting electrode CE2 and electrically connected to the power supply wiring VDD through the second reflective electrode RE2.

[0116] In this case, the third connecting electrode CE3 can be further electrically connected to the second connecting electrode CE2 in the second contact region CA2. For example, the third connecting electrode CE3 can be arranged continuously in the first contact region CA1 and the second contact region CA2, and can be electrically connected to the second connecting electrode CE2 extending from the first contact region CA1 through the fifth contact hole CH5 of the second passivation layer 114b and the sixth contact hole CH6 of the second planarization layer 117b located in the second contact region CA2. That is, the third connecting electrode CE3 can receive the power supply voltage from the power supply wiring VDD not only in the first contact region CA1 but also in the second contact region CA2 through the second connecting electrode CE2. This reduces the resistance between the power supply wiring VDD and the third connecting electrode CE3.

[0117] In particular, the fifth contact hole CH5 and the sixth contact hole CH6 of the second contact region CA2 do not need to overlap with the first contact hole CH1 of the adhesive layer 116 and the second contact hole CH2 of the first planarization layer 117a, unlike the third contact hole CH3 and the fourth contact hole CH4 of the first contact region CA1. Therefore, defects due to residual films of the adhesive layer 116 and the first planarization layer 117a can be minimized, and the electrical connection between the third connecting electrode CE3 and the second connecting electrode CE2 can be improved.

[0118] Furthermore, even if electrical connection between the second connecting electrode CE2 and the third connecting electrode CE3 is not achieved in either the first contact region CA1 or the second contact region CA2, the second connecting electrode CE2 and the third connecting electrode CE3 can be connected in the remaining region. Therefore, the electrical connection between the second connecting electrode CE2 and the third connecting electrode CE3 can be improved.

[0119] On the other hand, the third connecting electrode CE3 is positioned on the second electrode 125 and is in direct contact with the second electrode 125. Therefore, during lighting inspection, the lighting inspection signal can be transmitted directly to the second electrode 125 without going through the drive transistor DT. As a result, there is no need to drive the drive transistor DT separately, and a defect in the light-emitting element LED can be detected regardless of a defect in the drive transistor DT.

[0120] Furthermore, the third connecting electrode CE3 can be formed before the formation process of the bank 118, which will be described later. Therefore, defects in the light-emitting LED can be detected before the formation process of the bank 118.

[0121] On the other hand, the third connecting electrode CE3 may be positioned within the first opening OP1 and the second opening OP2 and come into contact with the second planarization layer 117b. In this case, since the width of the second opening OP2 is smaller than the width of the first opening OP1, the third connecting electrode CE3 may not come into contact with the second passivation layer 114b, but is not limited to this.

[0122] In the lighting inspection area APA, a lighting inspection pattern APP may be placed on the second planarization layer 117b. The lighting inspection pattern APP can come into contact with the first connecting electrode CE1 through a seventh contact hole CH7 formed in the second passivation layer 114b and an eighth contact hole CH8 formed in the second planarization layer 117b.

[0123] Therefore, the lighting test pattern APP can be electrically connected to the first electrode 124 of the light-emitting element LED through the first connecting electrode CE1. Thus, the lighting test signal can be transmitted directly to the first electrode 124 of the light-emitting element LED without going through the drive transistor DT. Therefore, since there is no need to drive the drive transistor DT separately, a defect in the light-emitting element LED can be detected regardless of a defect in the drive transistor DT. The lighting test pattern APP may be placed on the same layer as the third connecting electrode CE3 and may be made of the same material, but is not limited to this. Therefore, since the lighting test pattern APP is formed before the formation process of the bank 118, which will be described later, similar to the third connecting electrode CE3, a defect in the light-emitting element LED can be detected before the formation process of the bank 118. For example, the lighting test pattern APP may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). Therefore, the lighting test pattern APP may also be called a conductive pattern, but is not limited to this.

[0124] A protective pattern PP may be placed on the second planarization layer 117b. The protective pattern PP may be positioned to cover the first reflective electrode RE1 exposed by the contact holes of the adhesive layer 116. Thus, the protective pattern PP can protect the first reflective electrode RE1. For example, during the ashing process of the second planarization layer 117b, the protective pattern PP can function like a mask to prevent oxidation of the first reflective electrode RE1 during the ashing process.

[0125] Furthermore, the protective pattern PP is connected to the first connecting electrode CE1, which can reduce the wiring resistance of the first connecting electrode CE1.

[0126] A bank 118 may be arranged on the second planarization layer 117b, the third connecting electrode CE3, and the second lighting inspection pattern APP. Thus, the bank 118 may, but is not limited to, direct contact with the second planarization layer 117b, the third connecting electrode CE3, and the second lighting inspection pattern APP. The bank 118 can be arranged so as not to overlap with the light-emitting element LEDs and can define a light-emitting region. For example, the bank 118 can define a light-emitting region by covering the edges of the third connecting electrode CE3 connected to each light-emitting element LED. That is, the bank 118 can partition multiple sub-pixels SP. The bank 118 may consist of an insulating material to insulate the second connecting electrodes CE3 of adjacent sub-pixels SP from each other. The bank 118 may also contain a black component with high light absorption to prevent color mixing between adjacent sub-pixels SP, and may consist of a black bank. Bank 118 may, but is not limited to, a polyimide resin, an acrylic resin, or a benzocyclobutene (BCB) resin.

[0127] A third planarization layer 119 may be arranged on the second planarization layer 117b and the bank 118. The third planarization layer 119 is arranged to cover the upper surface of the light-emitting element LED, and can planarize the upper part of the substrate 110 on which the light-emitting element LED is arranged, while simultaneously fixing and protecting the light-emitting element LED. Therefore, the third planarization layer 119 may be called a protective layer or a capping layer, but is not limited thereto. The third planarization layer 119 may be composed of a single layer or multiple layers, and may be made of, for example, a photoresist or an acrylic-based organic material, but is not limited thereto.

[0128] In the following, Figures 4a to 4h will be used together to explain the method for manufacturing a display device according to one embodiment of this specification.

[0129] Figures 4a to 4h are process diagrams of a method for manufacturing a display device according to one embodiment of this specification.

[0130] First, referring to Figure 4a, a light-emitting element LED is placed on the adhesive layer 116, and a first planarization layer 117a can be placed on the adhesive layer 116 so as to surround the light-emitting element LED.

[0131] A connecting electrode material layer CE' and a second-first passivation material layer 114b' can be sequentially arranged on the front surface of the substrate 110 on the first planarization layer 117a and the light-emitting element LED.

[0132] The connecting electrode material layer CE' can be positioned on the front surface of the substrate 110 so as to cover the light-emitting element LED and the first planarization layer 117a. Therefore, the connecting electrode material layer CE' can also be positioned in the second contact hole CH2 formed in the first planarization layer 117a and the first contact hole CH1 of the adhesive layer 116 superimposed on it. Furthermore, the connecting electrode material layer CE' can be positioned so as to cover all of the side and top surfaces of the light-emitting element LED.

[0133] A second-first passivation material layer 114b' may be placed on the front surface of the substrate 110 on the connecting electrode material layer CE'. The second-first passivation material layer 114b' may be placed apart from the light-emitting element LED, the first planarization layer 117a, and the adhesive layer 116 by the connecting electrode material layer CE'.

[0134] On the other hand, the second-first passivation material layer 114b' can be formed by a vapor deposition process. In this case, the temperature of the vapor deposition process for the second-first passivation material layer 114b' can be determined considering the connecting electrode material layer CE' located below the second-first passivation material layer 114b'. For example, if the connecting electrode material layer CE' is made of ITO (Indium Tin Oxide), a transparent conductive material, the connecting electrode material layer CE' may crystallize at approximately 250°C. To prevent this, the vapor deposition process for the second-first passivation material layer 114b' can be carried out at a relatively low temperature of 200°C or less, for example, about 180°C.

[0135] Next, referring to Figure 4b, a second-first planarization layer 117b' can be placed on the second-first passivation layer 114b' so as to surround the light-emitting element LED. The height of the second-first planarization layer 117b' can be lower than the height of the second electrode 125 of the light-emitting element LED. For example, the thickness of the second-first planarization layer 117b' can be adjusted by performing an ashing process. For example, after coating the second-first planarization layer 117b' to cover the light-emitting element LED, an ashing process can be performed to reduce the overall thickness of the second-first planarization layer 117b', thereby forming the height of the second-first planarization layer 117b' to be lower than the height of the second electrode 125. Thus, in a subsequent step, the third connecting electrode CE3 placed on the second-first planarization layer 117b' can be easily connected to the second electrode 125.

[0136] On the other hand, an initial second opening OP2' can be formed in the second-first planarization material layer 117b'. The initial second opening OP2' can expose the second-first passivation material layer 114b'.

[0137] Next, referring to Figure 4c, the second-first passivation material layer 114b' can be etched to form the second-second passivation material layer 114b''. The second-first passivation material layer 114b' exposed from the second-first planarization material layer 117b' can be etched to form the second-second passivation material layer 114b''.

[0138] For example, by forming the second-first planarization material layer 117b' to a thickness smaller than the thickness of the light-emitting element LED, the second-first passivation material layer 114b' covering the upper portion of the light-emitting element LED can be exposed from the second-first planarization material layer 117b'.

[0139] Furthermore, by opening the second-first planarization material layer 117b' at the initial second opening OP2', the second-first passivation material layer 114b' superimposed on the initial second opening OP2' can be exposed from the second-first planarization material layer 117b'. Therefore, the portion of the second-first passivation material layer 114b' that covers the upper part of the light-emitting element LED and the portion that superimposed on the initial second opening OP2' can be etched to form the second-second passivation material layer 114b''. Thus, the first opening OP1 superimposed on the initial second opening OP2' can be formed in the second-second passivation material layer 114b''.

[0140] For example, the second-second passivation material layer 114b'' may be formed by a wet etching process. In this case, not only the portion of the second-first passivation material layer 114b' exposed by the second-first planarization material layer 117b', but also a portion overlapping with the second-first planarization material layer 117b' may be partially removed. Thus, the edge of the second-second passivation material layer 114b'' may be positioned inward from the edge of the second-first planarization material layer 117b'. Consequently, the width of the first opening OP1 may be greater than, but is not limited to, the width of the initial second opening OP2'.

[0141] On the other hand, during the etching process of the second-second passivation material layer 114b'', the second-first planarization material layer 117b' may also be partially etched to form the second-second planarization material layer 117b''. For example, a portion of the second-first planarization material layer 117b' adjacent to the light-emitting element LED may be etched together, but is not limited to this.

[0142] Next, referring to Figure 4d, the connecting electrode material layer CE' can be etched to form the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP. The connecting electrode material layer CE' exposed from the second-first planarization material layer 117b'' ​​and the second-second passivation material layer 114b'' can be etched to form the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP.

[0143] Specifically, the second-second planarization material layer 117b'' ​​is opened at the initial second opening OP2', and the second-second passivation material layer 114b'' is opened at the first opening OP1, so that the connecting electrode material layer CE' superimposed on the initial second opening OP2' and the first opening OP1 can be exposed from the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b''. Therefore, the portion of the connecting electrode material layer CE' superimposed on the initial second opening OP2' and the first opening OP1 can be etched to form the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP, respectively.

[0144] For example, the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP may be formed by a wet etching process. Therefore, not only the portion of the connecting electrode material layer CE' exposed by the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b'' may be partially removed, but also the portion that overlaps with the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b'' may also be partially removed. Thus, the ends of the first connecting electrode CE1, the second connecting electrode CE2, and the protective pattern PP may, but are not limited to, being positioned inside the ends of the second-second planarization material layer 117b'' ​​and the second-second passivation material layer 114b''.

[0145] On the other hand, the second-second passivation material layer 114b'' may also be partially etched to form the second-third passivation layer 114b''''. For example, not only the connecting electrode material layer CE' arranged on the side of the light-emitting element LED, but also the second-second passivation material layer 114b'' may be exposed by the second-second planarization material layer 117b''. Therefore, the second-second passivation material layer 114b'' arranged on the side of the light-emitting element LED may be partially removed to form the second-third passivation layer 114b''''.

[0146] On the other hand, by partially removing the second-second passivation material layer 114b'' adjacent to the light-emitting element LED, the end of the first connecting electrode CE1 in contact with the light-emitting element LED may be exposed by the second-third passivation layer 114b'''', but is not limited to this.

[0147] Next, referring to Figure 4e, the second-2 planarization material layer 117b'' ​​can be partially ashed, for example, by halftone ashing, to form the second-3 planarization material layer 117b''''.

[0148] For example, the portion of the second-2 planarization material layer 117b'' ​​that overlaps with the second connecting electrode CE2 can be partially ashed. For example, the portion of the second-2 planarization material layer 117b'' ​​that overlaps with the first contact hole CH1 and the second contact hole CH2 can be ashed to form an initial fourth contact hole CH4'. Thus, the initial fourth contact hole CH4' can overlap the first contact hole CH1 and the second contact hole CH2. The initial fourth contact hole CH4' can be placed on the second connecting electrode CE2 so that the third connecting electrode CE3 and the second connecting electrode CE2 are connected in a subsequent step.

[0149] Furthermore, the portion of the second-2 planarization material layer 117b'' ​​that is superimposed on the second connecting electrode CE2 and does not superimpose on the first contact hole CH1 and the second contact hole CH2 can be ashing to form an initial sixth contact hole CH6'. The initial sixth contact hole CH6' is placed on the second connecting electrode CE2, so that the third connecting electrode CE3 and the second connecting electrode CE2 are further connected in a subsequent process.

[0150] Furthermore, the portion of the second-2 planarization material layer 117b'' ​​that overlaps with the first connecting electrode CE1 can be partially ashed to form an initial eighth contact hole CH8'. The initial eighth contact hole CH8' can be used to connect the lighting inspection pattern APP and the first connecting electrode CE1 in a subsequent process.

[0151] Next, referring to Figure 4f, the second-third passivation material layer 114b''' can be etched to form the second passivation layer 114b. The second passivation layer 114b''' exposed from the second-third planarization material layer 117b''' can be etched to form the second passivation layer 114b.

[0152] For example, by opening the second-third planarization material layer 117b'''' at the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8', the second-third passivation material layer 114b''' superimposed on the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8' can be exposed from the second-third planarization material layer 117b'''. Therefore, the second-third passivation material layer 114b'''' exposed by the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8' can be etched to form the second passivation layer 114b. Therefore, the second passivation layer 114b may have a third contact hole CH3 superimposed on the initial fourth contact hole CH4', a fifth contact hole CH5 superimposed on the initial sixth contact hole CH6', and a seventh contact hole CH7 superimposed on the initial eighth contact hole CH8'.

[0153] For example, the second passivation layer 114b can be formed by a dry etching process. Unlike wet etching, the portion of the second-third passivation material layer 114b''' that overlaps with the second-third planarization material layer 117b'''' is not removed, and only the portion exposed by the second-third planarization material layer 117b'''' can be removed. Therefore, the ends of the portions of the second passivation layer 114b opened by the third contact hole CH3, the fifth contact hole CH5, and the seventh contact hole CH7 may, but are not limited to, the ends of the portions of the second-third planarization material layer 117b''' that are opened by the initial fourth contact hole CH4', the initial sixth contact hole CH6', and the initial eighth contact hole CH8', respectively.

[0154] Next, referring to Figure 4g, the second planarization layer 117b can be formed by curing the second-third planarization material layer 117b'''. Specifically, by reflowing the second-third planarization material layer 117b''' through the curing process, it can be made to cover the end of the second passivation layer 114b located below the second-third planarization material layer.

[0155] Specifically, the second-third planarization material layer 117b''', opened by the initial fourth contact hole CH4', can be reflowed and placed within the third contact hole CH3. Thus, the second planarization layer 117b can be positioned to cover the edge of the second passivation layer 114b, which is opened by the third contact hole CH3. Consequently, the width of the fourth contact hole CH4 can be narrower than the width of the third contact hole CH3.

[0156] The second-third planarization material layer 117b''', opened by the initial sixth contact hole CH6', can be reflowed and placed within the fifth contact hole CH5. Thus, the second planarization layer 117b can be positioned to cover the edge of the second passivation layer 114b, which is opened by the fifth contact hole CH5. Consequently, the width of the sixth contact hole CH6 may be narrower than the width of the fifth contact hole CH5.

[0157] The second-third planarization material layer 117b''', opened by the initial eighth contact hole CH8', can be reflowed and placed within the seventh contact hole CH7. Thus, the second planarization layer 117b can be positioned to cover the edge of the second passivation layer 114b, which is opened by the seventh contact hole CH7. Consequently, the width of the eighth contact hole CH8 in the second planarization layer 117b can be narrower than the width of the seventh contact hole CH7.

[0158] The second-third planarization material layer 117b''', opened by the initial second opening OP2', can be reflowed and placed within the first opening OP1. Thus, the second planarization layer 117b can be positioned to cover the edge of the second passivation layer 114b, which is opened by the first opening OP1. Consequently, the width of the second opening OP2 of the second planarization layer 117b can be narrower than the width of the first opening OP1.

[0159] On the other hand, the second planarization layer 117b may be placed on the first planarization layer 117a which is reflowed onto the first opening OP1 and superimposed on the first opening OP1. In this case, since the first opening OP1 is located between the first connecting electrode CE1 and the second connecting electrode CE2, the second planarization layer 117b may be placed so as to cover the ends of the first connecting electrode CE1 and the second connecting electrode CE2, respectively. Thus, the second planarization layer 117b can be placed so as to separate the first connecting electrode CE1 and the second connecting electrode CE2.

[0160] In particular, the second planarization layer 117b may be positioned to cover not only the edges of the second passivation layer 114b, but also the edges of the first connecting electrode CE1 exposed by the second passivation layer 114b. Thus, the second planarization layer 117b can be positioned so that the first connecting electrode CE1 and the third connecting electrode CE3 are separated from each other in subsequent steps.

[0161] Specifically, as mentioned above, the end of the first connecting electrode CE1 in contact with the light-emitting element LED may be exposed by the second passivation layer 114b. At this time, the second planarization layer 117b may be reflowed through the curing process and placed on the end of the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, the second planarization layer 117b can be reflowed to cover the end of the first connecting electrode CE1 in contact with the light-emitting element LED. Consequently, the height of the second planarization layer 117b may decrease as it approaches the light-emitting element LED. The second planarization layer 117b may be arranged to cover the end of the first connecting electrode CE1 and the end of the second passivation layer 114b, which are arranged to surround a part of the side surface of the light-emitting element LED. The inclination direction of the end of the first connecting electrode CE1 and the end of the second passivation layer 114b on the side surface of the light-emitting element LED may be the same as the inclination direction of the second planarization layer 117b that covers the end of the first connecting electrode CE1 and the end of the second passivation layer 114b. In the portion where the second planarization layer 117b is in contact with the side surface of the light-emitting element LED, the second planarization layer 117b and the light-emitting element LED may form a V-shape.

[0162] Next, referring to Figure 4h, the third connecting electrode CE3 and the lighting inspection pattern APP may be arranged on the second planarization layer 117b at a distance from each other. The third connecting electrode CE3 may be placed on the light-emitting element LED, and the lighting inspection pattern APP may be placed so as to overlap with the eighth contact hole CH8.

[0163] As described above, the second planarization layer 117b is formed by continuing the ashing process only until the second electrode 125 of the light-emitting element LED is exposed. The third connecting electrode CE3, which is placed in the second planarization layer 117b, can only contact the upper surface of the second electrode 125 exposed in the second planarization layer 117b, and can be separated from the first connecting electrode CE1, the light-emitting layer 122, and the first semiconductor layer 121, which are located below the second planarization layer 117b. Therefore, the third connecting electrode CE3 and the second electrode 125 can be self-aligned without the need to secure a process margin.

[0164] On the other hand, the lighting test pattern APP is positioned on the second planarization layer 117b in the seventh contact hole CH7 and the eighth contact hole CH8, and can be electrically connected to the first connecting electrode CE1 exposed by the seventh contact hole CH7 and the eighth contact hole CH8.

[0165] At this time, a lighting test can be performed. For example, a lighting test signal can be applied to the lighting test pattern APP and the third connecting electrode CE3. The lighting test signal applied through the lighting test pattern APP can be transmitted to the first electrode 124 of the light-emitting element LED through the first connecting electrode CE1. The lighting test signal applied through the third connecting electrode CE3 can be transmitted to the second electrode 125 of the light-emitting element LED. Thus, the presence or absence of a defect in the light-emitting element LED can be detected regardless of whether or not there is a defect in the drive transistor DT.

[0166] Next, the manufacturing process of the display device 100 can be completed by arranging the bank 118 and the third planar layer 119 on the second planar layer 117b, the third connecting electrode CE3, and the lighting inspection pattern APP.

[0167] During the process of arranging or transferring multiple light-emitting elements onto a substrate, some of the light-emitting elements may be misaligned or mispositioned. If subsequent processes proceed with some of the light-emitting elements misaligned or mispositioned, a short-circuit failure between electrodes may occur. For example, if the light-emitting elements are misaligned and the same electrode is connected to both the first and second electrodes of the light-emitting element, or if the electrodes connected to the first and second electrodes of the light-emitting element are not positioned separately but superimposed, causing a short-circuit failure, the light-emitting elements may not emit light properly.

[0168] Therefore, in the display device 100 according to one embodiment of this specification, the first connecting electrode CE1 and the first electrode 124 of the light-emitting element LED can be self-aligned and connected. For example, after applying the material layer of the first planarization layer 117a so as to cover the light-emitting element LED, the material layer of the first planarization layer 117a can be ashed to expose the first electrode 124. Thus, the first connecting electrode CE1 placed on the first planarization layer 117a can be easily connected to the first electrode 124 without the need for a separate contact hole. Therefore, the first connecting electrode CE1 and the first electrode 124 can be self-aligned without the need to secure a process margin. Thus, short-circuit defects between the first connecting electrode CE1 and the third connecting electrode CE3 due to process errors can be minimized.

[0169] Similarly, in the display device 100 according to one embodiment of this specification, the third connecting electrode CE3 and the second electrode 125 of the light-emitting element LED can be self-aligned and connected. For example, after applying the material layer of the second planarization layer 117b so as to cover the second semiconductor layer 123 and the second electrode 125 of the light-emitting element LED, the material layer of the second planarization layer 117b can be ashed so that only the second electrode 125 is exposed. Therefore, even if the material layer of the second connecting electrode CE2 is formed and patterned on the front surface of the substrate 110 including the second planarization layer 117b to form the second connecting electrode CE2, the second connecting electrode CE2 can only contact the upper surface of the second electrode 125 exposed by the second planarization layer 117b. In other words, the third connecting electrode CE3 and the second electrode 125 can be self-aligned without the need to secure a process margin. Therefore, short-circuit defects between the first connecting electrode CE1 and the third connecting electrode CE3 due to process errors can be minimized.

[0170] Furthermore, in the display device 100 according to one embodiment of this specification, a second passivation layer 114b may be placed on the first connecting electrode CE1 and the second connecting electrode CE2. Since the second passivation layer 114b is placed so as to cover at least a portion of the first connecting electrode CE1, the second passivation layer 114b, together with the second planarization layer 117b, can separate the first connecting electrode CE1 and the third connecting electrode CE3 from each other. Accordingly, the second passivation layer 114b can prevent a short circuit between the first connecting electrode CE1 and the third connecting electrode CE3.

[0171] Furthermore, since the second passivation layer 114b is made of an inorganic insulating material, it can block moisture or impurities from penetrating the multiple reflective electrodes RE connected to the multiple first connecting electrodes CE1 and the multiple second connecting electrodes CE2. Therefore, it is possible to prevent the multiple reflective electrodes RE from lifting and corroding due to moisture penetration.

[0172] In particular, in the display device 100 according to one embodiment of this specification, if the first connecting electrode CE1 is exposed by the second passivation layer 114b, the first connecting electrode CE1 and the third connecting electrode CE3 can be separated by reflowing the second planarization layer 117b onto the exposed first connecting electrode CE1. For example, by reflowing the second planarization layer 117b through a curing process, the second planarization layer 117b can be positioned to cover the first connecting electrode CE1 exposed by the second passivation layer 114b. Therefore, in the display device 100 according to one embodiment of this specification, even if the first connecting electrode CE1 is exposed by the second passivation layer 114b during the process, the first connecting electrode CE1 and the third connecting electrode CE3 can be separated by reflowing the second planarization layer 117b, thereby preventing a short-circuit defect in which the first connecting electrode CE1 and the third connecting electrode CE3 are connected.

[0173] Embodiments of the present invention can also be described as follows.

[0174] According to an aspect of the present invention, the display device comprises a substrate on which a plurality of subpixels are defined, power wiring and a drive transistor disposed on the substrate, a first reflective electrode and a second reflective electrode and power wiring disposed spaced apart from each other on the power wiring and the drive transistor and connected to the drive transistor, an adhesive layer disposed on the first reflective electrode and the second reflective electrode, a plurality of light-emitting elements including a first electrode and a second electrode, disposed on the adhesive layer for each of the plurality of subpixels, a first planarization layer disposed on the adhesive layer so as to surround a part of the side surface of the plurality of light-emitting elements, and a first electrode and a drive transistor disposed on the first planarization layer The device includes a first connecting electrode that connects the stars, a second connecting electrode positioned on a first planarization layer at a distance from the first connecting electrode and connected to a second reflective electrode, a passivation layer positioned on the first and second connecting electrodes, a second planarization layer positioned on the passivation layer and surrounding a portion of the sides of the multiple light-emitting elements, and a third connecting electrode positioned on the second planarization layer and connecting the second electrode to the power supply wiring. The passivation layer exposes the end of the first connecting electrode positioned to surround a portion of the sides of each of the multiple light-emitting elements, and the second planarization layer covers the end of the first connecting electrode.

[0175] According to other features of this specification, the second planarization layer may be positioned to cover the ends of the first connecting electrodes, which are arranged to surround a portion of the side surface of the light-emitting element, and the ends of the passivation layer corresponding to the ends of the first connecting electrodes.

[0176] According to other features of this specification, the direction of the inclination of the end of the first connecting electrode and the end of the passivation layer, which are located on the side surface of the light-emitting element, is the same as the direction of the inclination of the second planarization layer, which covers the end of the first connecting electrode and the end of the passivation layer, and the second planarization layer may be V-shaped in the region in contact with the light-emitting element.

[0177] According to other features of this specification, the height of the portion of the second planarization layer that overlaps with the end of the first connecting electrode may be lower than the height of the portion of the second planarization layer that does not overlap with the end of the first connecting electrode.

[0178] According to other features of this specification, the passivation layer includes a first opening that exposes a first planarization layer, the second planarization layer includes a second opening that overlaps the first opening, the width of the first opening being greater than the width of the second opening, and the second planarization layer can be positioned in the first opening to cover the other end of the first connecting electrode and the end of the second connecting electrode, respectively.

[0179] According to other features of this specification, the third connecting electrode can be positioned within the first and second openings and in contact with the first planarization layer.

[0180] According to other features of this specification, the adhesive layer includes a first contact hole exposing a second reflective electrode, the first planarization layer overlaps the first contact hole and includes a second contact hole exposing a second reflective electrode, the second connecting electrode is positioned in the first and second contact holes and in contact with the second reflective electrode, the passivation layer overlaps the first and second contact holes and includes a third contact hole exposing a second connecting electrode, the second planarization layer overlaps the first, second and third contact holes and includes a fourth contact hole exposing a second connecting electrode, and the third connecting electrode can be positioned in the first, second, third and fourth contact holes and in contact with the second connecting electrode.

[0181] According to other features of this specification, the width of the third contact hole is greater than the width of the fourth contact hole, and the second planarization layer can be positioned in the third contact hole to cover the edge of the passivation layer.

[0182] According to other features of this specification, the adhesive layer includes a first contact hole exposing a second reflective electrode, the first planarization layer overlaps the first contact hole and includes a second contact hole exposing a second reflective electrode, the second connecting electrode is positioned in the first and second contact holes and in contact with the second reflective electrode, the passivation layer does not overlap the first and second contact holes and includes a fifth contact hole exposing a second connecting electrode, the second planarization layer includes a sixth contact hole overlapping the fifth contact hole, and the third connecting electrode can be positioned in the fifth and sixth contact holes and in contact with the second connecting electrode.

[0183] According to other features of this specification, the width of the fifth contact hole is greater than the width of the sixth contact hole, and the second planarization layer can be positioned in the fifth contact hole to cover the edge of the passivation layer.

[0184] According to other features of this specification, the display device further includes a conductive pattern disposed on a second planarization layer, the passivation layer includes a seventh contact hole exposing a first connecting electrode, the second planarization layer includes an eighth contact hole superimposed on the seventh contact hole, and the conductive pattern may be connected to the first connecting electrode through the seventh and eighth contact holes.

[0185] According to other features of this specification, the width of the seventh contact hole is greater than the width of the eighth contact hole, and the second planarization layer can be positioned in the seventh contact hole to cover the edge of the passivation layer.

[0186] According to other features of this specification, the height of the first planarization layer may be lower than the height of the first electrode, and the height of the second planarization layer may be lower than the height of the second electrode.

[0187] According to other features of this specification, the sides of the multiple light-emitting elements may be one or both of the two sides of the multiple light-emitting elements.

[0188] According to another aspect of the present invention, the display device includes a substrate on which a plurality of pixels are defined, each including a plurality of subpixels; power wiring and a drive transistor disposed on the substrate; a first reflective electrode and a second reflective electrode disposed spaced apart from each other on the power wiring and the drive transistor and connected to the drive transistor and connected to the power wiring; an adhesive layer disposed on the first reflective electrode and the second reflective electrode; a plurality of light-emitting elements, each of the plurality of subpixels, disposed on the adhesive layer and including a first electrode and a second electrode; a first planarization layer disposed on the adhesive layer so as to surround a portion of the sides of the plurality of light-emitting elements; a first connecting electrode disposed on the first planarization layer and connecting the first electrode and the drive transistor; a second connecting electrode disposed spaced apart from the first connecting electrode on the first planarization layer and connected to the second reflective electrode; a passivation layer disposed on the first connecting electrode and the second connecting electrode; a second planarization layer disposed on the passivation layer and whose height decreases as it approaches the plurality of light-emitting elements; and a third connecting electrode disposed on the second planarization layer and connecting the second electrode and the power wiring.

[0189] According to other features of this specification, the passivation layer exposes a portion of the first connecting electrode surrounding the multiple light-emitting elements, and the height of the lowest end of the upper surface of the second planarization layer may be higher than the height of the highest end of the upper surface of the exposed portion of the first connecting electrode.

[0190] According to other features of this specification, the passivation layer includes an opening that exposes the first planarization layer, the second planarization layer overlaps the opening of the passivation layer and includes an opening smaller in width than the opening of the passivation layer, and the second planarization layer is positioned in the opening of the passivation layer to separate the first and second connecting electrodes.

[0191] According to other features of this specification, a plurality of pixels include a first region to which a third connecting electrode and power wiring are electrically connected and a second region separated from the first region, wherein in the first region, the third connecting electrode is connected to the power wiring through a second reflective electrode and a second connecting electrode, and in the second region, the third connecting electrode may be connected to the power wiring through a second connecting electrode extending from the first region.

[0192] According to other features of this specification, the adhesive layer is located in a first region and includes contact holes that expose a second reflective electrode; the first planarization layer is located in the first region and includes contact holes that overlap with the contact holes of the adhesive layer; and the second connecting electrode can be connected to the second reflective electrode through the contact holes of the first planarization layer and the contact holes of the adhesive layer.

[0193] According to other features of this specification, the passivation layer is located in a first region and overlaps with the contact holes of the first planarization layer and the contact holes of the adhesive layer, and includes contact holes that expose the second connecting electrode; the second planarization layer is located in a first region and overlaps with the contact holes of the first planarization layer, the contact holes of the adhesive layer and the contact holes of the passivation layer, and includes contact holes that expose the second connecting electrode; and the third connecting electrode may be connected to the second connecting electrode through the contact holes of the second planarization layer, the contact holes of the passivation layer, the contact holes of the first planarization layer and the contact holes of the adhesive layer.

[0194] According to other features of this specification, the passivation layer further includes a contact hole located in a second region and exposing a second connecting electrode extending from a first region, the second planarization layer further includes a contact hole located in a second region and exposing a second connecting electrode extending from a first region, and a third connecting electrode may be connected to the second connecting electrode through the contact holes in the passivation layer located in the second region and the contact holes in the second planarization layer.

[0195] According to other features of this specification, the display device includes a lighting inspection area located in each of a plurality of pixels, further including a lighting inspection pattern located on a second planarization layer in the lighting inspection area, a passivation layer located in the lighting inspection area and including contact holes exposing a first connecting electrode, the second planarization layer overlapping the contact holes of the passivation layer and including contact holes exposing the first connecting electrode, and the lighting inspection pattern may be connected to the first connecting electrode through the contact holes of the second planarization layer and the contact holes of the passivation layer.

[0196] According to other features of this specification, the passivation layer and the first connecting electrode may be lower in height as they are closer to the multiple light-emitting elements.

[0197] According to other features of this specification, the sides of the multiple light-emitting elements may be one or both of the two sides of the multiple light-emitting elements.

[0198] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. A substrate in which multiple subpixels are defined, Power wiring and drive transistors arranged on the aforementioned substrate, A first reflective electrode and a second reflective electrode are arranged spaced apart from each other on the power supply wiring and the drive transistor, wherein the first reflective electrode is connected to the drive transistor and the second reflective electrode is connected to the power supply wiring. Adhesive layer disposed on the first reflective electrode and the second reflective electrode, A plurality of light-emitting elements, including a first electrode and a second electrode, are arranged on the adhesive layer, each of the plurality of subpixels. A first planarizing layer is disposed on the adhesive layer so as to surround a portion of the side surfaces of the plurality of light-emitting elements. A first connecting electrode, which is disposed on the first planarization layer and connects the first electrode and the drive transistor, A second connecting electrode is positioned on the first planarization layer at a distance from the first connecting electrode and is connected to the second reflective electrode, A passivation layer disposed on the first connecting electrode and the second connecting electrode, A second planarization layer is disposed on the passivation layer and is positioned to surround a portion of the sides of the plurality of light-emitting elements, and It includes a third connecting electrode that is disposed on the second planarization layer and connects the second electrode and the power supply wiring, The passivation layer exposes the ends of the first connecting electrodes, which are arranged to surround a portion of the side surface of each of the plurality of light-emitting elements. The second planarization layer covers the end of the first connecting electrode, and is a display device.

2. The display device according to claim 1, wherein the second planarization layer is arranged to cover the end of the first connecting electrode, which is arranged to surround a part of the side surface of the light-emitting element, and the end of the passivation layer corresponding to the end of the first connecting electrode.

3. The direction of inclination of the end of the first connecting electrode and the end of the passivation layer, which are arranged on the side surface of the light-emitting element, is the same as the direction of inclination of the second flattening layer that covers the end of the first connecting electrode and the end of the passivation layer. The display device according to claim 2, wherein the second planarization layer is V-shaped in the region in contact with the light-emitting element.

4. The display device according to claim 1, wherein the height of the portion of the second planarization layer that overlaps with the end of the first connecting electrode is lower than the height of the portion of the second planarization layer that does not overlap with the end of the first connecting electrode.

5. The passivation layer includes a first opening that exposes the first planarization layer. The second planarization layer includes a second opening that overlaps with the first opening. The width of the first opening is greater than the width of the second opening. The display device according to claim 1, wherein the second planarization layer is disposed in the first opening and covers the other end of the first connecting electrode and the end of the second connecting electrode.

6. The display device according to claim 5, wherein the third connecting electrode is disposed within the first and second openings and in contact with the first planarization layer.

7. The adhesive layer includes a first contact hole that exposes the second reflective electrode. The first planarization layer includes a second contact hole that overlaps with the first contact hole to expose the second reflective electrode. The second connecting electrode is positioned in the first contact hole and the second contact hole and in contact with the second reflective electrode. The passivation layer includes a third contact hole that overlaps with the first contact hole and the second contact hole to expose the second connecting electrode. The second planarization layer includes a fourth contact hole that overlaps with the first contact hole, the second contact hole, and the third contact hole to expose the second connecting electrode. The display device according to claim 1, wherein the third connecting electrode is positioned in the first contact hole, the second contact hole, the third contact hole, and the fourth contact hole and is in contact with the second connecting electrode.

8. The width of the third contact hole is greater than the width of the fourth contact hole. The display device according to claim 7, wherein the second planarization layer is disposed in the third contact hole and covers the end of the passivation layer.

9. The adhesive layer includes a first contact hole that exposes the second reflective electrode. The first planarization layer includes a second contact hole that overlaps with the first contact hole to expose the second reflective electrode. The second connecting electrode is positioned in the first contact hole and the second contact hole and in contact with the second reflective electrode. The passivation layer includes a fifth contact hole that exposes the second connecting electrode without overlapping with the first contact hole and the second contact hole. The second planarization layer includes a sixth contact hole that overlaps with the fifth contact hole. The display device according to claim 1, wherein the third connecting electrode is positioned in the fifth contact hole and the sixth contact hole and in contact with the second connecting electrode.

10. The width of the fifth contact hole is greater than the width of the sixth contact hole. The display device according to claim 9, wherein the second planarization layer is disposed in the fifth contact hole and covers the end of the passivation layer.

11. The second planarization layer further includes a conductive pattern disposed on the second planarization layer, The passivation layer includes a seventh contact hole that exposes the first connecting electrode. The second planarization layer includes an eighth contact hole that overlaps with the seventh contact hole. The display device according to claim 1, wherein the conductive pattern is connected to the first connecting electrode through the seventh contact hole and the eighth contact hole.

12. The width of the seventh contact hole is greater than the width of the eighth contact hole. The display device according to claim 11, wherein the second planarization layer is disposed in the seventh contact hole and covers the end of the passivation layer.

13. The height of the first planarization layer is lower than the height of the first electrode. The display device according to claim 1, wherein the height of the second planarization layer is lower than the height of the second electrode.

14. The display device according to claim 1, wherein the side surfaces of the plurality of light-emitting elements are one or both of the two side surfaces of the plurality of light-emitting elements.

15. A substrate in which multiple pixels are defined, each containing multiple subpixels, Power wiring and drive transistors arranged on the aforementioned substrate, A first reflective electrode and a second reflective electrode are arranged spaced apart from each other on the power supply wiring and the drive transistor, wherein the first reflective electrode is connected to the drive transistor and the second reflective electrode is connected to the power supply wiring. Adhesive layer disposed on the first reflective electrode and the second reflective electrode, A plurality of light-emitting elements, including a first electrode and a second electrode, are arranged on the adhesive layer, each of the plurality of subpixels. A first planarizing layer is disposed on the adhesive layer so as to surround a portion of the side surfaces of the plurality of light-emitting elements. A first connecting electrode, which is disposed on the first planarization layer and connects the first electrode and the drive transistor, A second connecting electrode is positioned on the first planarization layer at a distance from the first connecting electrode and is connected to the second reflective electrode, A passivation layer disposed on the first connecting electrode and the second connecting electrode, A second planarization layer is disposed on the passivation layer, the height of which decreases as it approaches the plurality of light-emitting elements, and A display device comprising a third connecting electrode disposed on the second planarization layer and connecting the second electrode and the power supply wiring.

16. The passivation layer exposes a portion of the first connecting electrode surrounding the plurality of light-emitting elements. The display device according to claim 15, wherein the height of the lowest end of the upper surface of the second planarization layer is higher than the height of the uppermost end of the upper surface of the exposed portion of the first connecting electrode.

17. The passivation layer includes an opening that exposes the first planarization layer. The second planarization layer overlaps with the opening of the passivation layer and includes an opening smaller in width than the opening of the passivation layer. The display device according to claim 15, wherein the second planarization layer is disposed at the opening of the passivation layer to separate the first connecting electrode and the second connecting electrode.

18. The plurality of pixels include a first region to which the third connecting electrode and the power supply wiring are electrically connected, and a second region separated from the first region. In the first region, the third connecting electrode is connected to the power supply wiring through the second reflecting electrode and the second connecting electrode. The display device according to claim 15, wherein in the second region, the third connecting electrode is connected to the power supply wiring through the second connecting electrode extending from the first region.

19. The adhesive layer includes a contact hole positioned in the first region to expose the second reflective electrode. The first planarization layer includes contact holes arranged in the first region and overlapping with the contact holes of the adhesive layer. The display device according to claim 18, wherein the second connecting electrode is connected to the second reflective electrode through the contact holes of the first planarization layer and the contact holes of the adhesive layer.

20. The passivation layer includes contact holes arranged in the first region, and these contact holes overlap with the contact holes of the first planarization layer and the contact holes of the adhesive layer, exposing the second connecting electrode. The second planarization layer includes contact holes arranged in the first region, and these contact holes overlap with the contact holes of the first planarization layer, the contact holes of the adhesive layer, and the contact holes of the passivation layer, exposing the second connecting electrode. The display device according to claim 19, wherein the third connecting electrode is connected to the second connecting electrode through the contact hole of the second planarization layer, the contact hole of the passivation layer, the contact hole of the first planarization layer, and the contact hole of the adhesive layer.

21. The passivation layer further includes a contact hole located in the second region, the contact hole exposing the second connecting electrode extending from the first region. The second planarization layer further includes contact holes located in the second region, the contact holes exposing the second connecting electrode extending from the first region. The display device according to claim 19, wherein the third connecting electrode is connected to the second connecting electrode through contact holes in the passivation layer and the second planarization layer arranged in the second region.

22. Each of the plurality of pixels is arranged in a lighting inspection area, The lighting inspection area further includes a lighting inspection pattern disposed on the second planarization layer, The passivation layer includes a contact hole positioned in the lighting inspection area to expose the first connecting electrode. The second planarization layer includes contact holes that overlap with the contact holes of the passivation layer to expose the first connecting electrode. The display device according to claim 15, wherein the lighting inspection pattern is connected to the first connecting electrode through the contact holes of the second planarization layer and the contact holes of the passivation layer.

23. The display device according to claim 15, wherein the passivation layer and the first connecting electrode have a lower height as they approach the plurality of light-emitting elements.

24. The display device according to claim 15, wherein the side surfaces of the plurality of light-emitting elements are one or both of the two side surfaces of the plurality of light-emitting elements.

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