Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can suppress potential fluctuations generated in the internal circuitry due to electrical discharge. [Solution] The semiconductor device 11 includes a first wiring F1 with a first potential V1, a second wiring F2 with a second potential V2 lower than the first potential V1, a third wiring F3 with a third potential V3 lower than the second potential V2, a series circuit of a first transistor Q1 and a second transistor Q2 connected between the second wiring F2 and the third wiring F3, an input / output terminal IO connected to the connection point of transistors Q1 and Q2, a first prebuffer B1 whose power supply terminals are connected to the first wiring F1 and the third wiring F3 respectively, and whose output terminal is connected to the control electrode of the first transistor Q1, and a second prebuffer B2 whose output terminal is connected to the control electrode of the second transistor Q2, and a protection circuit 31 that, when a discharge from the input / output terminal IO is detected, controls the potential of at least one of the control electrodes of transistors Q1 and Q2 so that it is equal to or greater than the third potential V3 and less than or equal to the potential Vf2 of the second wiring F2.

Description

Technical Field

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[0001] Embodiments of the present invention relate to semiconductor devices.

Background Art

[0002] In semiconductor devices such as semiconductor integrated circuits, semiconductor devices provided with protection circuits for protecting internal circuits from surges generated by discharges such as ESD (Electrostatic Discharge) from power supply terminals, input / output terminals, etc. are known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a two-power semiconductor device having a first power supply terminal to which a high-potential first power supply is connected and a second power supply terminal to which a second power supply having a lower potential than the first power supply is connected, a protection circuit may be provided for the second power supply terminal, but not for the first power supply terminal. In such a semiconductor device, when a discharge such as ESD occurs at the input / output terminal, the high-potential power supply potential supplied from the first power supply terminal varies with respect to the low-potential power supply potential supplied from the second power supply terminal and the ground. When a large potential fluctuation occurs in the internal circuit of the semiconductor device, the risk of overcurrent breakdown occurring in the electronic elements of the internal circuit increases.

[0005] The problem to be solved by the embodiments of the present invention is to provide a semiconductor device capable of suppressing potential fluctuations generated in an internal circuit due to discharges such as ESD in a semiconductor device having a first power supply terminal on the high-potential side and a second power supply terminal on the low-potential side.

Means for Solving the Problems

[0006] The semiconductor device according to the embodiment includes: a first wiring that receives a first potential during normal operation and has a first wiring potential; a second wiring that receives a second potential lower than the first potential during normal operation and has a second wiring potential; a third wiring that receives a third potential lower than the second potential; a switch circuit connected between the second and third wiring, which is a series circuit of a first transistor on the second wiring side and a second transistor on the third wiring side; input / output terminals connected to the connection point of the first and second transistors; a first pre-buffer whose positive power supply terminal is connected to the first wiring, whose negative power supply terminal is connected to the third wiring, and whose output terminal is connected to the control electrode of the first transistor; a second pre-buffer whose positive power supply terminal is connected to the first wiring, whose negative power supply terminal is connected to the third wiring, and whose output terminal is connected to the control electrode of the second transistor; and a protection circuit that, when a discharge from the input / output terminal is detected, controls the potential of at least one of the control electrodes of the first and second transistors to be greater than or equal to the third potential and less than or equal to the second wiring potential.

[0007] A semiconductor device according to another embodiment includes: a first wiring that receives a first potential during normal operation and has a first wiring potential; a second wiring that receives a second potential lower than the first potential during normal operation and has a second wiring potential; a third wiring that receives a third potential lower than the second potential; a first semiconductor switch; a fourth wiring connected to the first wiring via the first semiconductor switch; a second semiconductor switch connecting the second wiring and the fourth wiring; a switch circuit connected between the second wiring and the third wiring, which is a series circuit of a first transistor on the second wiring side and a second transistor on the third wiring side; and at the connection point of the first transistor and the second transistor... The system includes connected input / output terminals, a first pre-buffer whose positive power terminal is connected to the fourth wire, whose negative power terminal is connected to the third wire, and whose output terminal is connected to the control electrode of the first transistor, a second pre-buffer whose positive power terminal is connected to the fourth wire, whose negative power terminal is connected to the third wire, and whose output terminal is connected to the control electrode of the second transistor, and a protection circuit that controls the system to turn on the first semiconductor switch and turn off the second semiconductor switch when no discharge is detected from the input / output terminals, and to turn off the first semiconductor switch and turn on the second semiconductor switch when a discharge is detected from the input / output terminals. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram showing a partial configuration of a semiconductor device related to a reference example. [Figure 2] Figure 2 is a circuit diagram showing a partial configuration of a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a circuit diagram showing a partial configuration of the semiconductor device according to the second embodiment. [Figure 4] Figure 4 is a circuit diagram showing a partial configuration of a semiconductor device according to the third embodiment. [Figure 5] Figure 5 is a circuit diagram showing a partial configuration of the semiconductor device according to the fourth embodiment. [Figure 6] Figure 6 is a circuit diagram showing a partial configuration of the semiconductor device according to the fifth embodiment. [Figure 7] Figure 7 is a circuit diagram showing a partial configuration of a semiconductor device according to the sixth embodiment. [Figure 8] Figure 8 is a circuit diagram showing a partial configuration of the semiconductor device according to the seventh embodiment. [Modes for carrying out the invention]

[0009] The embodiments will be described with reference to the drawings. In the drawings described below, identical or similar parts are denoted by the same or similar reference numerals. The drawings are schematic. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical idea and do not specify the material, shape, structure, arrangement, etc. of the parts. Various modifications can be made to the embodiments.

[0010] (Reference example) Before describing the semiconductor device according to the embodiment, a reference example semiconductor device 10 will be described using Figure 1. Figure 1 is a circuit diagram showing a part of the output circuit configuration of the reference example semiconductor device 10. The semiconductor device 10 is, for example, a semiconductor memory device such as a NAND flash memory or a DRAM (Dynamic Random Access Memory).

[0011] As shown in Figure 1, the semiconductor device 10 includes a first power terminal VEXTQ, a second power terminal VEXTQL, a third power terminal VSS, and input / output terminals IO. The first power terminal VEXTQ is connected to a first wiring F1 inside the semiconductor device 10. The first power terminal VEXTQ is connected to a first external power supply (not shown) with a first potential V1. The first wiring potential Vf1, which is the potential of the first wiring F1, becomes the first potential V1. The second power terminal VEXTQL is connected to a second wiring F2 inside the semiconductor device 10. The second power terminal VEXTQL is connected to a second external power supply (not shown) with a second potential V2, which is lower than the first potential V1. The second wiring potential Vf2, which is the potential of the second wiring F2, becomes the second potential V2. The third power terminal VSS is connected to a third wiring F3 inside the semiconductor device 10. The third power terminal VSS is connected to a third potential V3 (for example, ground GND, which is 0V), which is an external reference potential lower than the second potential V2. The potential of the third wiring F3, which is the third wiring potential Vf3, becomes the third potential V3. The input / output terminal IO is shared with the input circuit (not shown).

[0012] The semiconductor device 10 is a dual-supply semiconductor device supplied with a first potential V1 and a second potential V2. The first potential V1 is, for example, 1.2V or 1.8V. The second potential V2 is, for example, 0.6V or 0.6~1.2V. The third potential V3 is, for example, 0V.

[0013] A switch circuit 21, acting as an OCD (off-chip driver) / ODT (on-die termination), is connected between the second wiring F2 and the third wiring F3. The switch circuit 21 is a series circuit of a high-side first transistor Q1 and a low-side second transistor Q2. The first transistor Q1 is a P-channel MOSFET. The second transistor Q2 is an N-channel MOSFET. The first main electrode (source) of the first transistor Q1 is connected to the second wiring F2. The second main electrode (drain) of the first transistor Q1 is connected to the second main electrode (drain) of the second transistor Q2. The first main electrode (source) of the second transistor Q2 is connected to the third wiring F3. The connection point between the first transistor Q1 and the second transistor Q2 is connected to the input / output terminal IO via the output wiring Fo. The switch circuit 21 is supplied with a dedicated power supply, the second wiring potential Vf2, which is the second potential V2.

[0014] A first diode D1 is connected in parallel to the first transistor Q1. The cathode of the first diode D1 is connected to the first main electrode of the first transistor Q1, and the anode of the first diode D1 is connected to the second main electrode of the first transistor Q1. The first diode D1 may be a parasitic diode of the first transistor Q1. A second diode D2 is connected in parallel to the second transistor Q2. The cathode of the second diode D2 is connected to the second main electrode of the second transistor Q2, and the anode of the second diode D2 is connected to the first main electrode of the second transistor Q2. The second diode D2 may be a parasitic diode of the second transistor Q2. The series circuit 22 of the first diode D1 and the second diode D2 functions as a protection diode to protect the internal circuit of the semiconductor device 10 from surges generated by discharges such as ESD (Electrostatic Discharge) from the input / output terminal IO.

[0015] The output terminal of the first inverter B1, which serves as a pre - buffer for the first transistor Q1, is connected to the control electrode (gate) of the first transistor Q1. The output terminal of the second inverter B2, which serves as a pre - buffer for the second transistor Q2, is connected to the control electrode (gate) of the second transistor Q2. The positive power supply terminals of the first inverter B1 and the second inverter B2 are connected to the first wiring F1, and the negative power supply terminals of the first inverter B1 and the second inverter B2 are connected to the third wiring F3. The first wiring potential Vf1, which is the first potential V1, is supplied as a power source to the first inverter B1 and the second inverter B2. The first wiring potential Vf1 is also supplied as a power source to the internal circuit of the semiconductor device 10 other than the first inverter B1 and the second inverter B2.

[0016] The input terminal of the first inverter B1 is connected to the first internal terminal S1, and the first internal signal Vs1 is input. When the first internal signal Vs1 is at the H level, the first inverter B1 outputs the third potential V3, which is a signal at the L level, as the first gate signal Vg1. When the first gate signal Vg1 is at the L level, the first transistor Q1 turns on (conducts). When the first internal signal Vs1 is at the L level, the first inverter B1 outputs the first potential V1, which is a signal at the H level, as the first gate signal Vg1. When the first gate signal Vg1 is at the H level, the first transistor Q1 turns off (opens).

[0017] The input terminal of the second inverter B2 is connected to the second internal terminal S2, and the second internal signal Vs2 is input. When the second internal signal Vs2 is at the H level, the second inverter B2 outputs the third potential V3, which is a signal at the L level, as the second gate signal Vg2. When the second gate signal Vg2 is at the L level, the second transistor Q2 turns off (opens). When the second internal signal Vs2 is at the L level, the second inverter B2 outputs the first potential V1, which is a signal at the H level, as the second gate signal Vg2. When the second gate signal Vg2 is at the H level, the second transistor Q2 turns on (conducts).

[0018] When the first internal signal Vs1 and the second internal signal Vs2 are at the H level, the first transistor Q1 is turned on and the second transistor Q2 is turned off. Therefore, the second potential V2 is output as the output signal Vo as a signal of the H level to the input / output terminal IO. When the first internal signal Vs1 and the second internal signal Vs2 are at the L level, the first transistor Q1 is turned off and the second transistor Q2 is turned on. Therefore, the third potential V3 is output as the output signal Vo as a signal of the L level to the input / output terminal IO. When the first internal signal Vs1 is at the L level and the second internal signal Vs2 is at the H level, both the first transistor Q1 and the second transistor Q2 are turned off. Therefore, the input / output terminal IO becomes a high impedance (Hi-Z) state.

[0019] A trigger MOS circuit 23 as a protection circuit for protecting the internal circuit of the semiconductor device 10 from a surge generated by a discharge such as ESD from the input / output terminal IO is connected between the second power supply terminal VEXTQL and the third power supply terminal VSS. Since the trigger MOS circuit 23 can be of a known configuration, the description thereof is omitted here.

[0020] In the two-power semiconductor device 10 configured as described above, when a surge is generated due to a discharge such as ESD from the input / output terminal IO, the potential of the input / output terminal IO rises to a potential higher than the second potential V2. Then, a current flows through the path in the order of the input / output terminal IO, the first diode D1, the trigger MOS circuit 23, the third power supply terminal VSS, and the ground GND.

[0021] Consequently, the current caused by this surge causes the second wiring potential Vf2 to rise above the second potential V2. On the other hand, when a surge such as ESD occurs from the input / output terminal IO, the first potential V1 may not be applied to the first power supply terminal VEXTQ. In this case, the first wiring potential Vf1 becomes lower than the second wiring potential Vf2, and in some cases even lower than the third wiring potential Vf3. As a result, the potentials of the first gate signal Vg1 and the second gate signal Vg2 also decrease. Since the drain potentials of the first transistor Q1 and the second transistor Q2 rise along with the potentials of the input / output terminal IO, the risk of overvoltage breakdown due to the rise in the drain-gate voltage of the first transistor Q1 and the drain-gate voltage of the second transistor Q2 increases.

[0022] In the embodiments described below, a semiconductor device is described that is equipped with a protection circuit that can suppress potential fluctuations in the internal circuit even when a surge occurs due to discharge such as ESD from the input / output terminal IO, compared to the semiconductor device 10 according to the reference example.

[0023] (First Embodiment) The semiconductor device 11 according to the first embodiment will be described using Figure 2. Figure 2 is a circuit diagram showing a part of the configuration of the semiconductor device 11 according to the first embodiment. The semiconductor device 11 according to the first embodiment has a configuration in which a protection circuit 31 is added to the semiconductor device 10 according to the reference example.

[0024] The protection circuit 31 comprises an RC circuit 41 and a third transistor Q3. The RC circuit 41 is a series circuit of a resistor R1 and a capacitor C1, with the first terminal of resistor R1 connected to the second wiring F2, the second terminal of resistor R1 connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 connected to the third wiring F3. The third transistor Q3 is a semiconductor switch and is composed of a P-channel MOSFET. The source and body of the third transistor Q3 are connected to the second wiring F2, the drain is connected to the connection point between the gate of the first transistor Q1 and the output terminal of the first inverter B1, and the gate is connected to the connection point between resistor R1 and capacitor C1.

[0025] The protection circuit 31 does not operate during normal operation when no ESD or other discharges occur at the input / output terminal IO, and therefore does not affect the operation of the semiconductor device 11. Specifically, the potential Vrc at the connection point of resistor R1 and capacitor C1 is at the high level of the second potential V2, and since the gate signal of the third transistor Q3 is at the high level, the third transistor Q3 is off. For this reason, when the first internal signal Vs1 is at the low level, the first gate signal Vg1 is at the high level of the first potential V1, and when the first internal signal Vs1 is at the high level, the first gate signal Vg1 is at the low level of the third potential V3.

[0026] On the other hand, if an ESD or other discharge occurs at the input / output terminal IO, the second wiring potential Vf2 rises. At this time, the RC circuit 41 of the protection circuit 31 detects the surge caused by the discharge and acts as follows: In the RC circuit 41, the propagation of the elevated second wiring potential Vf2 to the potential Vrc at the connection point of resistor R1 and capacitor C1 is delayed, and the potential Vrc at the connection point maintains the potential before the discharge occurred. That is, the second wiring potential Vf2 input to the source and body of the third transistor Q3 rises, and the gate signal potential is maintained. With the potential of the source of the third transistor Q3 as the reference, the gate signal switches from H level to L level, so the third transistor Q3 switches from off to on. Then, the first gate signal Vg1 is fixed at the second potential V2, regardless of whether the first internal signal Vs1 is at H level or L level, and fluctuations are suppressed.

[0027] After a predetermined period has elapsed since the discharge, the potential Vrc at the connection point rises to the potential Vf2 of the second wiring, and the gate signal of the third transistor Q3 switches from L level to H level. As a result, the third transistor Q3 switches from ON to OFF, returning to its normal operating state.

[0028] In this way, the protection circuit 31 can suppress fluctuations by fixing the first gate signal Vg1 to the second wiring potential Vf2 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the first gate signal Vg1 can be suppressed, thus preventing the first transistor Q1 from being overvoltage-damaged due to fluctuations in the first gate signal Vg1.

[0029] Furthermore, in the first embodiment, the third transistor Q3 is configured as a P-channel MOSFET, and the first gate signal Vg1 can be fixed to the high level of the second potential V2 to suppress fluctuations, but the embodiment is not limited to this. For example, the third transistor Q3 can be configured as an N-channel MOSFET, and by inverting the connections between the second wiring F2 and the third wiring F3 of the RC circuit 41, the first gate signal Vg1 can be fixed to the third potential V3 to suppress fluctuations. Even with such a configuration, when discharge such as ESD occurs at the input / output terminal IO, it is possible to suppress the first gate signal Vg1 from fluctuating to a potential lower than the third potential V3, thereby preventing the first transistor Q1 from being overvoltage-damaged due to fluctuations in the first gate signal Vg1.

[0030] (Second Embodiment) The semiconductor device 12 according to the second embodiment will be described using Figure 3. Figure 3 is a circuit diagram showing a part of the configuration of the semiconductor device 12 according to the second embodiment. The semiconductor device 12 according to the second embodiment has a configuration in which a protection circuit 32 is added to the semiconductor device 10 according to the reference example.

[0031] The protection circuit 32 comprises an RC circuit 41 and a third transistor Q3. The RC circuit 41 is a series circuit of a capacitor C1 and a first resistor R1, where the first terminal of capacitor C1 is connected to the second wiring F2, the second terminal of capacitor C1 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the third wiring F3. The protection circuit 32 further comprises a second resistor R2. The third transistor Q3 is an N-channel MOSFET. The drain of the third transistor Q3 is connected to the connection point between the gate of the second transistor Q2 and the second inverter B2, the source is connected to the third wiring F3 via the second resistor R2, and the gate is connected to the connection point between capacitor C1 and the first resistor R1.

[0032] The protection circuit 32 does not operate during normal operation when no ESD or other discharges occur at the input / output terminal IO, and therefore does not affect the operation of the semiconductor device 12. Specifically, the potential Vrc at the connection point of capacitor C1 and first resistor R1 is at the L level of the third potential V3, and since the gate signal of the third transistor Q3 is at the L level, the third transistor Q3 is off. For this reason, when the second internal signal Vs2 is at the L level, the second gate signal Vg2 is at the H level of the first potential V1, and when the second internal signal Vs2 is at the H level, the second gate signal Vg2 is at the L level of the third potential V3.

[0033] On the other hand, if an ESD or other discharge occurs at the input / output terminal IO, the RC circuit 41 of the protection circuit 32 detects the surge caused by the discharge and acts as follows: In the RC circuit 41, the propagation of the third potential V3 to the potential Vrc at the connection point of capacitor C1 and first resistor R1 is delayed, and the potential Vrc at the connection point rises from the L level of the third potential V3 as the second wiring potential Vf2 rises due to the capacitive coupling of capacitor C1. That is, the gate signal of the third transistor Q3 switches from the L level to the H level, so the third transistor Q3 switches from off to on. Then, the second gate signal Vg2 is fixed at the third potential V3, regardless of whether the second internal signal Vs2 is at the H level or the L level.

[0034] After a predetermined period has elapsed since discharge, the potential Vrc at the connection point drops to the third potential V3, and the gate signal of the third transistor Q3 switches from high level to low level. As a result, the third transistor Q3 switches from on to off, returning to its normal operating state.

[0035] In this way, the protection circuit 32 can suppress fluctuations by fixing the second gate signal Vg2 to the third potential V3 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, the fluctuation of the second gate signal Vg2 to a potential lower than the third potential V3 can be suppressed, thus preventing the second transistor Q2 from being overvoltage-damaged due to fluctuations in the second gate signal Vg2.

[0036] Furthermore, when an ESD discharge occurs at the input / output terminal IO, at least one of the displacement current and gate leakage current flows between the drain and gate of the second transistor Q2. These currents flow into the second resistor R2, generating a potential in the second resistor R2. Therefore, by using at least one of the displacement current and gate leakage current flowing between the drain and gate of the second transistor Q2, it is expected that the second gate signal Vg2 will be raised above the third potential V3, and suppressed to be above the third potential V3 and below the second wiring potential Vf2.

[0037] (Third embodiment) The semiconductor device 13 according to the third embodiment will be described using Figure 4. Figure 4 is a circuit diagram showing a part of the configuration of the semiconductor device 13 according to the third embodiment. The semiconductor device 13 according to the third embodiment has a configuration in which a protection circuit 33 is added to the semiconductor device 10 according to the reference example.

[0038] The protection circuit 33 comprises an RC circuit 41, a third transistor Q3, a fourth transistor Q4, a third inverter B3, a voltage divider circuit 42, wiring F2a, and wiring F2b. The RC circuit 41 is a series circuit of a resistor R1 and a capacitor C1, with the first terminal of resistor R1 connected to the second wiring F2, the second terminal of resistor R1 connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 connected to the third wiring F3. The third transistor Q3 is a P-channel MOSFET. The source and body of the third transistor Q3 are connected to the second wiring F2, the drain is connected to wiring F2a, and the gate is connected to the connection point of resistor R1 and capacitor C1.

[0039] The voltage divider circuit 42 is a series circuit of a first voltage divider resistor R31 and a second voltage divider resistor R32. The first terminal of the first voltage divider resistor R31 is connected to wiring F2a, the second terminal of the first voltage divider resistor R31 is connected to the first terminal of the second voltage divider resistor R32, and the second terminal of the second voltage divider resistor R32 is connected to the third wiring F3.

[0040] The third inverter B3 has its positive power supply terminal connected to wiring F2a, its negative power supply terminal connected to the third wiring F3, and its input terminal connected to the connection point of resistor R1 and capacitor C1. The fourth transistor Q4 is an N-channel MOSFET. The drain of the fourth transistor Q4 is connected via wiring F2b to the connection point between the gate of the second transistor Q2 and the output terminal of the second inverter B2, and its source is connected to the connection point of the first voltage divider resistor R31 and the second voltage divider resistor R32. The body of the fourth transistor Q4 is connected to the third wiring F3, and its gate is connected to the output terminal of the third inverter B3.

[0041] The protection circuit 33 does not operate during normal operation when no ESD or other discharges occur at the input / output terminal IO, and does not affect the operation of the semiconductor device 13. Specifically, the potential Vrc at the connection point of resistor R1 and capacitor C1 is at the H level of the second potential V2, and since the gate signal of the third transistor Q3 is at the H level, the third transistor Q3 is off. Therefore, the wiring potential Vf2a, which is the potential of wiring F2a, is equal to the third wiring potential Vf3 of the third wiring F3, i.e., the third potential V3. The third inverter B3 does not operate because both the positive and negative electrode terminals are at the third potential V3. The gate of the fourth transistor Q4 is at the L level of the third potential V3, so the fourth transistor Q4 is off. Therefore, the second gate signal Vg2, which is also the potential of wiring F2b, is at the H level of the first potential V1 when the second internal signal Vs2 is at the L level, and at the L level of the third potential V3 when the second internal signal Vs2 is at the H level.

[0042] On the other hand, if an ESD or other discharge occurs at the input / output terminal IO, the second wiring potential Vf2 input to the source and body of the third transistor Q3 rises. At this time, the RC circuit 41 of the protection circuit 33 detects the surge due to the discharge, and, as explained with reference to Figure 2, the potential Vrc at the connection point of resistor R1 and capacitor C1 switches from a high level to a low level, with the second wiring potential Vf2 as the reference. That is, the gate signal of the third transistor Q3 switches from a high level to a low level, so the third transistor Q3 switches from off to on. Then, wiring F2a and the second wiring F2 are connected, and the wiring potential Vf2a switches from the third potential V3 to the second wiring potential Vf2. Then, the third inverter B3 is supplied with the second wiring potential Vf2 to the positive electrode terminal, and an L level is input to the input terminal, so the output terminal becomes high level (second wiring potential Vf2), and the fourth transistor Q4 switches from off to on.

[0043] The voltage divide potential Vrr, which is the potential at the connection point of the first voltage divider resistor R31 and the second voltage divider resistor R32, is determined by the resistance values ​​of the first and second voltage divider resistors R31 and R32, and is a value between the third potential V3 and the second potential V2. The second gate signal Vg2 is fixed to the voltage divide potential Vrr, which is determined by the resistance values ​​of the first and second voltage divider resistors R31 and R32, and is between the third potential V3 and the second wiring potential Vf2, regardless of whether the second internal signal Vs2 is at an H level or an L level, thereby suppressing fluctuations.

[0044] In this way, when a discharge such as ESD occurs at the input / output terminal IO, the protection circuit 33 can fix the second gate signal Vg2 to the divided voltage potential Vrr, regardless of whether the second internal signal Vs2 is at a high or low level, thereby suppressing fluctuations. For this reason, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the second gate signal Vg2 can be suppressed, thus preventing the second transistor Q2 from being overvoltage-damaged due to fluctuations in the second gate signal Vg2.

[0045] Furthermore, when an ESD or other discharge occurs at the input / output terminal IO, if at least one of the displacement current and gate leakage current flows between the drain and gate of the second transistor Q2, these currents will flow into the second voltage divider resistor R32, thereby increasing the value of the voltage divider potential Vrr. For this reason, by using at least one of the displacement current and gate leakage current between the drain and gate of the second transistor Q2, an effect of increasing the value of the voltage divider potential Vrr can be expected.

[0046] (Fourth Embodiment) The semiconductor device 14 according to the fourth embodiment will be described using Figure 5. Figure 5 is a circuit diagram showing a part of the configuration of the semiconductor device 14 according to the fourth embodiment. The semiconductor device 14 according to the fourth embodiment has a configuration in which a protection circuit 34 is added to the semiconductor device 10 according to the reference example.

[0047] The protection circuit 34 includes an RC circuit 41, a third transistor Q3, a fourth transistor Q4, a two-input NOR gate N1 with an inverting function added to one of its inputs, a third inverter B3, a third diode D3, a fourth wire F4, and a fifth wire F5. The RC circuit 41 is a series circuit of a resistor R1 and a capacitor C1, with the first terminal of resistor R1 connected to the second wire F2, the second terminal of resistor R1 connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 connected to the third wire F3. The input terminal of the third inverter B3 is connected to the connection point of resistor R1 and capacitor C1. The positive power supply terminal of the third inverter B3 is connected to the second wire F2, and the negative power supply terminal is connected to the third wire F3.

[0048] The fourth transistor Q4 is a semiconductor switch and is composed of a P-channel MOSFET. The gate of the fourth transistor Q4 is connected to the output terminal of the third inverter B3 via the fifth wiring F5, the source and body are connected to the first wiring F1, and the drain is connected to the fourth wiring F4. The third diode D3 is a semiconductor switch, with its anode connected to the second wiring F2 and its cathode connected to the fourth wiring F4.

[0049] In the fourth embodiment, the positive power supply terminals of the first inverter B1 and the second inverter B2 are connected to the fourth wiring F4. The input terminal of the first inverter B1 is connected to the output terminal of the NOR gate N1. The positive power supply terminal of the NOR gate N1 is connected to the fourth wiring F4, and the negative power supply terminal is connected to the third wiring F3. The first input terminal of the NOR gate N1 is connected to the first internal terminal S1, and a signal obtained by inverting the first internal signal Vs1 is input to it. The second input terminal of the NOR gate N1 is connected to the first enable terminal E1, and is configured such that the first internal signal Vs1 is enabled when the first enable signal Ve1 is at a low level, and disabled when it is at a high level.

[0050] The reason for using the NOR gate N1 is that in the actual configuration of the semiconductor device 14, there are multiple pairs of first transistor Q1 and first inverter B1, and these are collectively controlled by the first enable signal Ve1 to enable and disable them.

[0051] The third transistor Q3 is a semiconductor switch and is composed of a P-channel MOSFET. The gate of the third transistor Q3 is connected to the connection point of resistor R1 and capacitor C1, the source is connected to the second wiring F2, the body is connected to the fourth wiring F4, and the drain is connected to the connection point of the second input terminal and first enable terminal E1 of the NOR gate N1.

[0052] The protection circuit 34 does not operate during normal operation when no ESD or other discharges occur at the input / output terminal IO, and does not affect the operation of the semiconductor device 14. Specifically, the potential Vrc at the connection point of resistor R1 and capacitor C1 is at the high level of the second potential V2, and the fifth wiring potential Vf5, which is the output signal of the third inverter B3, is at the low level of the third potential V3. At this time, the fourth transistor Q4 is on, so the first wiring F1 and the fourth wiring F4 are connected. Therefore, the fourth wiring potential Vf4, which is the potential of the fourth wiring F4, is equal to the first wiring potential Vf1, i.e., the first potential V1. The third diode D3 is off because its anode is at the second potential V2 and its cathode is at the first potential V1.

[0053] Furthermore, the third transistor Q3 is off because the gate signal, the potential Vrc at the connection point of resistor R1 and capacitor C1, is at the high level of the second potential V2. Therefore, when the first enable signal Ve1 from the first enable terminal E1 is at the low level, the first internal signal Vs1 is active. That is, when the first internal signal Vs1 is at the high level, the first gate signal Vg1 is at the low level of the third potential V3, and when the first internal signal Vs1 is at the low level, the first gate signal Vg1 is at the high level of the first potential V1. On the other hand, when the first enable signal Ve1 from the first enable terminal E1 is at the high level, the first internal signal Vs1 is inactive. That is, regardless of whether the first internal signal Vs1 is at the high level or low level, the first gate signal Vg1 is at the high level of the first potential V1.

[0054] On the other hand, if an ESD or other discharge occurs at the input / output terminal IO, the RC circuit 41 of the protection circuit 34 detects the surge caused by the discharge, and, as explained with reference to Figure 2, the potential Vrc at the connection point of resistor R1 and capacitor C1 switches from a high level to a low level, with the second wiring potential Vf2 as the reference.

[0055] When the potential Vrc at the connection point between resistor R1 and capacitor C1 switches from a high level to a low level, the output signal of the third inverter B3, the fifth wiring potential Vf5, switches from the low level of the third potential V3 to the high level of the second wiring potential Vf2. Then, the fourth transistor Q4 switches from on to off, disconnecting the first wiring F1 and the fourth wiring F4, and the third diode D3 turns on, causing the fourth wiring potential Vf4 of the fourth wiring F4 to switch from the first potential V1 to the second wiring potential Vf2. As a result, the potentials of the positive power supply terminals of the first inverter B1, the second inverter B2, and the NOR gate N1 switch from the first potential V1 to the second wiring potential Vf2.

[0056] The fourth transistor Q4 is a switch provided to prevent a delay in the switching of the fourth wiring potential Vf4 of the fourth wiring F4 from the first potential V1 to the second wiring potential Vf2 when the capacitance of the element connected to the first wiring F1 is large. Therefore, if the capacitance of the element connected to the first wiring F1 is sufficiently small, the first wiring F1 and the fourth wiring F4 may be connected directly without providing the fourth transistor Q4.

[0057] Furthermore, when the potential Vrc at the connection point between resistor R1 and capacitor C1 switches from a high level to a low level, the third transistor Q3 switches from off to on, the first enable signal Ve1 becomes high at the second wiring potential Vf2, and the first internal signal Vs1 is disabled. The third transistor Q3 and the NOR gate N1 are connected to the first inverter B1 and constitute a control switch that disables the first internal signal Vs1 when the RC circuit 41 detects discharge. Then, regardless of whether the first internal signal Vs1 is high or low, the first gate signal Vg1 is fixed at the second wiring potential Vf2 and fluctuations are suppressed.

[0058] In this way, the protection circuit 34 can suppress fluctuations by fixing the first gate signal Vg1 to the second wiring potential Vf2 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the first gate signal Vg1 can be suppressed, thus preventing the first transistor Q1 from being overvoltage-damaged due to fluctuations in the first gate signal Vg1.

[0059] (Fifth embodiment) The semiconductor device 15 according to the fifth embodiment will be described using Figure 6. Figure 6 is a circuit diagram showing a part of the configuration of the semiconductor device 15 according to the fifth embodiment. The semiconductor device 15 according to the fifth embodiment has a configuration in which a protection circuit 35 is added to the semiconductor device 10 according to the reference example.

[0060] The protection circuit 35 according to the fifth embodiment differs from the protection circuit 34 according to the fourth embodiment only in that the third diode D3, which acts as a semiconductor switch, is replaced with a fifth transistor Q5. The fifth transistor Q5 is an N-channel MOSFET. The drain of the fifth transistor Q5 is connected to the fourth wiring F4, the source is connected to the second wiring F2, and the gate is connected to the fifth wiring F5 via the sixth wiring F6.

[0061] Since the protection circuit 35 according to the fifth embodiment operates in the same manner as the protection circuit 34 according to the fourth embodiment, a detailed explanation thereof will be omitted.

[0062] The protection circuit 35 can suppress fluctuations in the first gate signal Vg1 by fixing it to the second wiring potential Vf2 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the first gate signal Vg1 can be suppressed, thus preventing the first transistor Q1 from being overvoltage-damaged due to fluctuations in the first gate signal Vg1.

[0063] (Sixth Embodiment) The semiconductor device 16 according to the sixth embodiment will be described using Figure 7. Figure 7 is a circuit diagram showing a part of the configuration of the semiconductor device 16 according to the sixth embodiment. The semiconductor device 16 according to the sixth embodiment has a configuration in which a protection circuit 36 ​​is added to the semiconductor device 10 according to the reference example.

[0064] The protection circuit 36 ​​includes an RC circuit 41, a third transistor Q3, a fourth transistor Q4, a two-input NAND gate N2 with an inverting function added to one input, a third inverter B3, a fourth inverter B4, a third diode D3, a fourth wire F4, and a fifth wire F5. The RC circuit 41 is a series circuit of a capacitor C1 and a resistor R1, with the first terminal of capacitor C1 connected to the second wire F2, the second terminal of capacitor C1 connected to the first terminal of resistor R1, and the second terminal of resistor R1 connected to the third wire F3. The input terminal of the third inverter B3 is connected to the connection point of capacitor C1 and resistor R1. The input terminal of the fourth inverter B4 is connected to the output terminal of the third inverter B3. The positive power supply terminals of the third inverter B3 and the fourth inverter B4 are connected to the second wire F2, and the negative power supply terminals are connected to the third wire F3.

[0065] The fourth transistor Q4 is a semiconductor switch and is composed of a P-channel MOSFET. The gate of the fourth transistor Q4 is connected to the output terminal of the fourth inverter B4 via the fifth wiring F5, the source and body are connected to the first wiring F1, and the drain is connected to the fourth wiring F4. The third diode D3 is a semiconductor switch, with its anode connected to the second wiring F2 and its cathode connected to the fourth wiring F4.

[0066] In the sixth embodiment, the positive power supply terminals of the first inverter B1 and the second inverter B2 are connected to the fourth wiring F4. The input terminal of the second inverter B2 is connected to the output terminal of the NAND gate N2. The positive power supply terminal of the NAND gate N2 is connected to the fourth wiring F4, and the negative power supply terminal is connected to the third wiring F3. The first input terminal of the NAND gate N2 is connected to the second internal terminal S2, and a signal obtained by inverting the second internal signal Vs2 is input. The second input terminal of the NAND gate N2 is connected to the second enable terminal E2, and the second internal signal Vs2 is enabled when the second enable signal Ve2 is at a high level, and disabled when it is at a low level.

[0067] The reason for using NAND gate N2 is that in the actual configuration of semiconductor device 16, there are multiple pairs of second transistor Q2 and second inverter B2, and these are collectively controlled by the second enable signal Ve2 to enable and disable them.

[0068] The third transistor Q3 is a semiconductor switch and is composed of an N-channel MOSFET. The gate of the third transistor Q3 is connected to the connection point of capacitor C1 and resistor R1, the drain is connected to the connection point of the second input terminal and second enable terminal E2 of the NAND gate N2, and the source is connected to the third wiring F3.

[0069] The protection circuit 36 ​​does not operate during normal operation when no ESD or other discharges occur at the input / output terminal IO, and does not affect the operation of the semiconductor device 16. Specifically, the potential Vrc at the connection point of capacitor C1 and resistor R1 is at the L level of the third potential V3, the output signal of the third inverter B3 is at the H level of the second potential V2, and the fifth wiring potential Vf5, which is the output signal of the fourth inverter B4, is at the L level of the third potential V3. At this time, the fourth transistor Q4 is ON, so the first wiring F1 and the fourth wiring F4 are connected. Therefore, the fourth wiring potential Vf4, which is the potential of the fourth wiring F4, is equal to the first wiring potential Vf1, i.e., the first potential V1. The third diode D3 is OFF because its anode is at the second potential V2 and its cathode is at the first potential V1.

[0070] The fourth transistor Q4 is a switch provided to prevent a delay in the switching of the fourth wiring potential Vf4 of the fourth wiring F4 from the first potential V1 to the second wiring potential Vf2 when the capacitance of the element connected to the first wiring F1 is large. Therefore, if the capacitance of the element connected to the first wiring F1 is sufficiently small, the first wiring F1 and the fourth wiring F4 may be connected directly without providing the fourth transistor Q4.

[0071] Furthermore, the third transistor Q3 is off because the gate signal, Vrc, at the connection point of capacitor C1 and resistor R1, is at the low level of the third potential V3. Therefore, when the second enable signal Ve2 from the second enable terminal E2 is at the high level, the second internal signal Vs2 is active. That is, when the second internal signal Vs2 is at the high level, the second gate signal Vg2 is at the low level of the third potential V3, and when the second internal signal Vs2 is at the low level, the second gate signal Vg2 is at the high level of the first potential V1. On the other hand, when the second enable signal Ve2 from the second enable terminal E2 is at the low level, the second internal signal Vs2 is inactive. That is, regardless of whether the second internal signal Vs2 is at the high or low level, the second gate signal Vg2 is at the low level of the third potential V3.

[0072] On the other hand, if an ESD or other discharge occurs at the input / output terminal IO, the RC circuit 41 of the protection circuit 36 ​​detects the surge caused by the discharge, and, as explained with reference to Figure 3, the potential Vrc at the connection point of capacitor C1 and resistor R1 switches from the L level of the third potential V3 to the H level, with the second wiring potential Vf2 as the reference.

[0073] When the potential Vrc at the connection point of capacitor C1 and resistor R1 switches from L level to H level, the output signal of the fourth inverter B4, the fifth wiring potential Vf5, switches from the L level of the third potential V3 to the H level of the second wiring potential Vf2. Then, the fourth transistor Q4 switches from on to off, disconnecting the first wiring F1 and the fourth wiring F4, and the third diode D3 turns on, causing the fourth wiring potential Vf4 of the fourth wiring F4 to switch from the first potential V1 to the second wiring potential Vf2. As a result, the potentials of the positive power supply terminals of the first inverter B1, the second inverter B2, and the NAND gate N2 switch from the first potential V1 to the second wiring potential Vf2.

[0074] Furthermore, when the potential Vrc at the connection point of capacitor C1 and resistor R1 switches from L level to H level, the third transistor Q3 switches from off to on, the second enable signal Ve2 becomes L level at the third potential V3, and the second internal signal Vs2 is disabled. The third transistor Q3 and NAND gate N2 are connected to the input terminal of the second inverter B2 and constitute a control switch that disables the second internal signal Vs2 when the RC circuit 41 detects discharge. Then, regardless of whether the second internal signal Vs2 is at H level or L level, the second gate signal Vg2 is fixed at the third potential V3 and fluctuations are suppressed.

[0075] In this way, the protection circuit 36 ​​can suppress fluctuations by fixing the second gate signal Vg2 to the third potential V3 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the second gate signal Vg2 can be suppressed, thus preventing the second transistor Q2 from being overvoltage-damaged due to fluctuations in the second gate signal Vg2.

[0076] (Seventh Embodiment) The semiconductor device 17 according to the seventh embodiment will be described using Figure 8. Figure 8 is a circuit diagram showing a part of the configuration of the semiconductor device 17 according to the seventh embodiment. The semiconductor device 17 according to the seventh embodiment has a configuration in which a protection circuit 37 is added to the semiconductor device 10 according to the reference example.

[0077] The protection circuit 37 according to the seventh embodiment differs from the protection circuit 36 ​​according to the sixth embodiment only in that the third diode D3, which acts as a semiconductor switch, is replaced with a fifth transistor Q5. The fifth transistor Q5 is an N-channel MOSFET. The drain of the fifth transistor Q5 is connected to the fourth wiring F4, the source is connected to the second wiring F2, and the gate is connected to the fifth wiring F5 via the sixth wiring F6.

[0078] Since the protection circuit 37 according to the seventh embodiment operates in the same manner as the protection circuit 36 ​​according to the sixth embodiment, a detailed explanation thereof will be omitted.

[0079] The protection circuit 37 can suppress fluctuations in the second gate signal Vg2 by fixing it to the third potential V3 when a discharge such as ESD occurs at the input / output terminal IO. Therefore, even when a discharge such as ESD occurs at the input / output terminal IO, fluctuations in the second gate signal Vg2 can be suppressed, thus preventing the second transistor Q2 from being overvoltage-damaged due to fluctuations in the second gate signal Vg2.

[0080] Furthermore, the protection circuits 31, 34, or 35 capable of protecting the first transistor Q1 and the protection circuits 32, 33, 36, or 37 capable of protecting the second transistor Q2 can be used in appropriate combinations.

[0081] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be carried out in various other forms, and various omissions, rewrites, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0082] 10-17 Semiconductor Equipment 21 Switch Circuit 22 Protection diodes 23 Trigger MOS Circuit 31-37 Protection circuit 41 RC circuit 42. Voltage divider circuit B1 First Inverter (First Pre-buffer) B2 Second Inverter (Second Pre-buffer) C1 Capacitor D1 First Diode D2 Second Bypass D3 Third Diode F1 First Wiring F2 Second Wiring F3 Third Wiring F4 4th wiring F5 Fifth Wiring IO input / output terminal Q1 First transistor Q2 Second transistor Q3 Third transistor Q4 4th transistor Q5 Fifth transistor Q6: 6th transistor R1 Resistor (First Resistor) R2 2nd resistor V1 First potential V2 2nd potential V3 3rd potential VEXTQ 1st power terminal VEXTQL 2nd power supply terminal VSS 3rd power supply terminal

Claims

1. During normal operation, a first potential is input to the first wiring, which has a first wiring potential, During normal operation, a second potential lower than the first potential is input to the second wiring, which has a second wiring potential. A third wiring that receives a third potential, which is a lower potential than the second potential, A switch circuit is connected between the second wiring and the third wiring, and is a series circuit of the first transistor on the second wiring side and the second transistor on the third wiring side. Input / output terminals connected to the connection point between the first transistor and the second transistor, A first prebuffer, the positive power supply terminal of which is connected to the first wiring, the negative power supply terminal of which is connected to the third wiring, and the output terminal of which is connected to the control electrode of the first transistor, A second pre-buffer, the positive power supply terminal of which is connected to the first wiring, the negative power supply terminal of which is connected to the third wiring, and the output terminal of which is connected to the control electrode of the second transistor, A protection circuit that, upon detecting a discharge from the input / output terminal, controls the potential of at least one of the control electrodes of the first transistor and the second transistor so that it is greater than or equal to the third potential and less than or equal to the second wiring potential, A semiconductor device equipped with a semiconductor device.

2. The first transistor further comprises a first diode connected in parallel with the first transistor to the first and second electrodes of the first transistor, and a second diode connected in parallel with the second transistor to the first and second electrodes of the second transistor. The first transistor is composed of a P-channel MOSFET, The second transistor is composed of an N-channel MOSFET. The semiconductor device according to claim 1.

3. The protection circuit includes an RC circuit, which is a series circuit of a first resistor and a capacitor, connected between the second wiring and the third wiring. The protection circuit, when the RC circuit detects the discharge from the input / output terminal, controls the potential of at least one of the control electrode of the first transistor and the control electrode of the second transistor so that it is greater than or equal to the third potential and less than or equal to the second wiring potential. The semiconductor device according to claim 2.

4. The protection circuit further comprises a third transistor composed of a P-channel MOSFET, The RC circuit is configured such that the terminal on the first resistor side is connected to the second wiring, and the terminal on the capacitor side is connected to the third wiring. The third transistor has a control electrode connected to the connection point of the first resistor and the capacitor, a first electrode connected to the second wiring, and a second electrode connected to the control electrode of the first transistor. The protection circuit controls the potential of the control electrode of the first transistor to the potential of the second wiring when the RC circuit detects the discharge from the input / output terminal. The semiconductor device according to claim 3.

5. The protection circuit further comprises a third transistor composed of an N-channel MOSFET and a second resistor. The RC circuit is configured such that the terminal on the capacitor side is connected to the second wiring, and the terminal on the first resistor side is connected to the third wiring. The third transistor has a control electrode connected to the connection point between the capacitor and the first resistor, a second electrode connected to the control electrode of the second transistor, and a first electrode connected to the third wiring via the second resistor. When the RC circuit detects the discharge from the input / output terminal, the protection circuit controls the potential of the control electrode of the second transistor so that it is equal to or greater than the third potential and less than or equal to the second wiring potential. The semiconductor device according to claim 3.

6. The protection circuit uses the potential generated in the second resistor by at least one of the displacement current and gate leakage current of the second transistor to control the potential of the control electrode of the second transistor so that it is greater than or equal to the third potential and less than or equal to the second wiring potential. The semiconductor device according to claim 5.

7. The protection circuit further comprises a voltage divider circuit which is a series circuit of a first voltage divider resistor and a second voltage divider resistor, a first semiconductor switch, and a second semiconductor switch. The voltage divider circuit has a first terminal connected to the second wiring via the first semiconductor switch, and a second terminal connected to the third wiring. The connection point between the first voltage divider resistor and the second voltage divider resistor is connected to the control electrode of the second transistor via the second semiconductor switch. The protection circuit controls the first semiconductor switch and the second semiconductor switch to turn off when the RC circuit does not detect the discharge from the input / output terminals, and to turn on the first semiconductor switch and the second semiconductor switch when the RC circuit detects the discharge from the input / output terminals. The semiconductor device according to claim 3.

8. The first diode is a parasitic diode of the first transistor, and the second diode is a parasitic diode of the second transistor. The semiconductor device according to any one of claims 2 to 7.

9. During normal operation, a first potential is input to the first wiring, which has a first wiring potential, A second wiring that receives a second potential lower than the first potential during normal operation, A third wiring that receives a third potential, which is a lower potential than the second potential, First semiconductor switch, A fourth wiring connected to the first wiring via the first semiconductor switch, A second semiconductor switch connecting the second wiring and the fourth wiring, A switch circuit is connected between the second wiring and the third wiring, and is a series circuit of the first transistor on the second wiring side and the second transistor on the third wiring side. Input / output terminals connected to the connection point between the first transistor and the second transistor, A first pre-buffer, the positive power supply terminal of which is connected to the fourth wiring, the negative power supply terminal of which is connected to the third wiring, and the output terminal of which is connected to the control electrode of the first transistor, A second pre-buffer, the positive power supply terminal of which is connected to the fourth wiring, the negative power supply terminal of which is connected to the third wiring, and the output terminal of which is connected to the control electrode of the second transistor, A protection circuit controls the first semiconductor switch to be turned on and the second semiconductor switch to be turned off when no discharge is detected from the input / output terminals, and to be turned off and the second semiconductor switch to be turned on when a discharge is detected from the input / output terminals. A semiconductor device equipped with a semiconductor device.

10. The protection circuit is connected to at least one input terminal of the first prebuffer and the second prebuffer, and further comprises a control switch that enables and disables the input signal to the input terminal. The protection circuit controls the control switch to disable the input signal when it detects a discharge from the input / output terminal. The semiconductor device according to claim 9.

11. The first transistor further comprises a first diode connected in parallel with the first transistor to the first and second electrodes of the first transistor, and a second diode connected in parallel with the second transistor to the first and second electrodes of the second transistor. The first transistor is composed of a P-channel MOSFET, The second transistor is composed of an N-channel MOSFET. The semiconductor device according to claim 10.

12. The protection circuit includes an RC circuit, which is a series circuit of a resistor and a capacitor, connected between the second wiring and the third wiring. The protection circuit detects the discharge from the input / output terminals using the RC circuit. The semiconductor device according to claim 11.

13. The semiconductor device according to any one of claims 9 to 12, wherein the second semiconductor switch is a diode.

14. The semiconductor device according to any one of claims 9 to 12, wherein the second semiconductor switch is a transistor.

15. The first diode is a parasitic diode of the first transistor, and the second diode is a parasitic diode of the second transistor. The semiconductor device according to claim 11 or 12.

16. During normal operation, a first potential is input to the first wiring, which has a first wiring potential, A second wiring that receives a second potential lower than the first potential during normal operation, A third wiring that receives a third potential, which is a lower potential than the second potential, A semiconductor switch connecting the second wiring and the first wiring, A switch circuit is connected between the second wiring and the third wiring, and is a series circuit of the first transistor on the second wiring side and the second transistor on the third wiring side. Input / output terminals connected to the connection point between the first transistor and the second transistor, A first prebuffer whose positive power supply terminal is connected to the first wiring, whose negative power supply terminal is connected to the third wiring, and whose output terminal is connected to the control electrode of the first transistor. and, A second pre-buffer, the positive power supply terminal of which is connected to the first wiring, the negative power supply terminal of which is connected to the third wiring, and the output terminal of which is connected to the control electrode of the second transistor, A protection circuit controls the semiconductor switch to turn off when no discharge is detected from the input / output terminals, and to turn on when a discharge is detected from the input / output terminals. A semiconductor device equipped with a semiconductor device.

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