Semiconductor devices and semiconductor memory devices

Abstract

The present invention provides a semiconductor device and a semiconductor memory device that can suppress oxygen deficiency in the channel material. [Solution] The semiconductor device of the embodiment is a semiconductor device comprising a channel containing an oxide semiconductor and an electrode in contact with the channel, wherein the electrode includes a metal layer containing at least one metal element from iridium, palladium, silver, osmium, and rhodium, and a first oxide layer in contact with the metal layer and disposed between the metal layer and the channel, and containing the metal element of the metal layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device.

Background Art

[0002] Semiconductor devices using an oxide semiconductor as a channel material are known. Examples of such an oxide semiconductor include IGZO (InGaZnO), and examples of the electrode material for source and drain electrodes include tungsten. The manufacturing process of such a semiconductor device involves heat treatment.

[0003] However, when heat treatment is performed on this semiconductor device, oxygen in the channel material diffuses into the electrode material, increasing oxygen vacancies in the channel. This causes defects in the semiconductor device and an increase in the channel resistance.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] As described above, conventional semiconductor devices and semiconductor memory devices have a problem that oxygen in the channel material can diffuse into the electrode material. The semiconductor device and memory device of the embodiment are made to solve such problems, and an object thereof is to provide a semiconductor device and a semiconductor memory device capable of suppressing oxygen vacancies in the channel material. [[ID=4九十]]

Means for Solving the Problems

[0006] The semiconductor device of the embodiment is a semiconductor device comprising a channel containing an oxide semiconductor and an electrode in contact with the channel, wherein the electrode includes a metal layer containing at least one metal element from iridium, palladium, silver, osmium, and rhodium, and a first oxide layer in contact with the metal layer and disposed between the metal layer and the channel, and containing the metal element of the metal layer. [Brief explanation of the drawing]

[0007] [Figure 1] This is a cross-sectional view showing the basic configuration of the semiconductor device according to the embodiment. [Figure 2] This figure shows how oxygen diffusion is suppressed in the semiconductor device 1 of the embodiment. [Figure 3] This figure shows the oxygen diffusion process in a comparative semiconductor device. [Figure 4] This figure shows the oxygen diffusion process in a comparative semiconductor device. [Figure 5] This figure shows the elemental distribution when iridium is used as the metal layer. [Figure 6] This figure shows the elemental distribution when iridium is used as the metal layer. [Figure 7] This figure shows the elemental distribution when titanium nitride is applied as the metal layer. [Figure 8] This figure shows the elemental distribution when ruthenium is used as the metal layer. [Figure 9] This figure shows the elemental distribution when ruthenium is used as the metal layer. [Figure 10] This figure shows an example of gate voltage characteristics in a semiconductor device. [Figure 11] This flowchart shows a method for generating the first oxide layer in a semiconductor device according to an embodiment. [Figure 12] This figure illustrates a method for generating the first oxide layer in a semiconductor device according to an embodiment. [Figure 13] This figure illustrates a method for generating the first oxide layer in a semiconductor device according to an embodiment. [Figure 14]This is a diagram for explaining a method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 15] This is a diagram for explaining a method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 16] This is a flowchart showing another method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 17] This is a diagram for explaining another method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 18] This is a diagram for explaining another method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 19] This is a diagram for explaining another method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 20] This is a diagram for explaining another method of forming a first oxide layer in a semiconductor device of an embodiment. [Figure 21] This is a circuit diagram for explaining a circuit configuration example of a memory cell array as a semiconductor memory device according to an embodiment. [Figure 22] This is a schematic cross-sectional view for explaining a structural example of a memory cell array as a semiconductor memory device according to an embodiment. [Figure 23] This is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment.

Embodiments for Carrying Out the Invention

[0008] (Configuration of the Semiconductor Device of the Embodiment) Hereinafter, a semiconductor device of an embodiment will be described with reference to the drawings. In the embodiment, substantially the same constituent parts are denoted by the same reference numerals, and the description thereof may be partially omitted. The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of each part, etc. may be different from the actual ones.

[0009] Figure 1 is a cross-sectional view showing the basic configuration of a semiconductor device according to an embodiment. The semiconductor device 1 shown in Figure 1 includes a conductor 50 as a source electrode or drain electrode, a conductor 30 as a drain electrode or source electrode, insulating layers 44 and 45 disposed between the conductor 50 and the conductor 30, an oxide semiconductor layer 41 as a channel with both ends joined to the conductor 50 and the conductor 30, a conductive layer 42 as a gate electrode disposed between the insulating layers 44 and 45 between the conductor 50 and the conductor 30 and near the oxide semiconductor layer 41, and an insulating film 43 disposed at the interface between the oxide semiconductor layer 41 and the insulating layers 44 and 45 and the conductive layer 42.

[0010] Specifically, the conductor 30, insulating layer 44, conductive layer 42, and insulating layer 45 form a laminate. In this laminate, an oxide semiconductor layer 41 is arranged so as to penetrate the insulating layer 45, conductive layer 42, and insulating layer 44. One end of the oxide semiconductor layer 41 is joined to one main surface of the conductor 30. An insulating film 43 is arranged on the circumferential surface of the oxide semiconductor layer 41 to insulate the oxide semiconductor layer 41 from the outer conductive layer 42. A conductor 50 is arranged on the surface of the insulating layer 45 opposite to the surface joined to the conductive layer 42. The other end of the oxide semiconductor layer 41 is joined to the conductor 50.

[0011] The conductor 50, the conductor 30, and the conductive layer 42 function as electrodes corresponding to the source, drain, and gate of the transistor element formed by the semiconductor device 1. This transistor element can constitute, for example, a switching transistor in a memory element.

[0012] The conductor 30 comprises a conductive layer 31 and a conductive oxide layer 32. The conductive layer 31 contains, for example, copper. The conductive oxide layer 32 is provided so as to be directly bonded to one end of the oxide semiconductor layer 41 within the junction surface of the conductor 30 and the insulating layer 44. The conductive oxide layer 32 contains a conductive oxide.

[0013] The oxide semiconductor layer 41 includes, for example, indium (In). The oxide semiconductor layer 41 includes, for example, indium oxide and gallium oxide, indium oxide and zinc oxide, or indium oxide and tin oxide. As an example, it includes an oxide containing indium, gallium, and zinc (indium-gallium-zinc oxide), so-called IGZO (InGaZnO).

[0014] The conductive layer 42 includes, for example, a metal, a metallic compound, or a semiconductor. The conductive layer 42 includes, for example, at least one material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0015] The insulating film 43 includes, for example, silicon and oxygen or nitrogen. The insulating film 43 may be a laminate of multiple insulating films. The insulating layers 44, 45 include, for example, silicon and oxygen or nitrogen. The insulating layers 44, 45 are made of, for example, silicon dioxide (SiO2).

[0016] The conductor 50 has an intermediate layer 51 and a conductive layer 52. The conductive layer 52 includes, for example, copper and tungsten (W). The intermediate layer 51 is provided so as to be directly bonded to the other end of the oxide semiconductor layer 41 within the junction surface of the conductor 50 and the insulating layer 45. The intermediate layer 51 has a metal layer 51a, a first oxide layer 51b, and a second oxide layer 51c.

[0017] The second oxide layer 51c is a layer that can be bonded to the oxide semiconductor layer 41 in the conductor 50. The second oxide layer 51c includes, for example, indium tin oxide (ITO). The metal layer 51a includes, for example, at least one of iridium (Ir), palladium (Pd), silver (Ag), osmium (Os), and rhodium (Rh). The metal layer 51a is disposed between the second oxide layer 51c and the conductive layer 52.

[0018] The first oxide layer 51b is disposed between the second oxide layer 51c and the metal layer 51a. The first oxide layer 51b contains oxides of the metal elements that make up the metal layer 51a. That is, the first oxide layer 51b includes, for example, iridium oxide (IrOx), palladium oxide (PdOx), silver oxide (AgOx), osmium oxide (OsOx), and rhodium oxide (RhOx). The metal layer 51a and the first oxide layer 51b function as a barrier layer that prevents oxygen (O) contained in the oxide semiconductor layer 41 from diffusing into the conductive layer 52.

[0019] The semiconductor device 1 shown in Figure 1 has a metal layer 51a, a first oxide layer 51b, and a second oxide layer 51c as an intermediate layer 51, but is not limited to this. The intermediate layer 51 may not include the second oxide layer 51c and may be composed of the metal layer 51a and the first oxide layer 51b. Furthermore, the structure of the conductor 30, which includes the conductive layer 31 and the conductive oxide layer 32, may be the same as the structure of the conductor 50 described above.

[0020] (Operation of the semiconductor device in the embodiment) The operation of the embodiment will be explained with reference to Figures 2 to 4. Figure 2 shows how oxygen diffusion is suppressed in the semiconductor device 1 of the embodiment. Figures 3 and 4 show how oxygen diffusion occurs in the semiconductor device of the comparative example.

[0021] In transistors using oxide semiconductors as channels, the thermal process during manufacturing causes the metal bit wire material to scavenge oxygen from the channel, significantly reducing the threshold voltage Vth. For example, as shown in Figure 3, if the conductor 50a in semiconductor device 9a does not have a metal layer 51a and a first oxide layer 51b, and ITO is used as the second oxide layer 51c and tungsten as the conductive layer 52, then oxygen in the oxide semiconductor layer 41 as the channel will diffuse to the tungsten via the ITO.

[0022] Furthermore, as shown in Figure 4, even when the conductor 50b in the semiconductor device 9b is provided with a metal layer 51a, if titanium nitride (TiN) is used as the metal layer 51a and ITO is used as the second oxide layer 51c, oxygen in the oxide semiconductor layer 41, which acts as a channel, diffuses into tungsten via ITO or titanium nitride. This diffusion of oxygen into the conductive layer 52 and the like increases the oxygen vacancy in the channel and is a factor that lowers the threshold voltage Vth.

[0023] Therefore, as shown in Figure 2, the semiconductor device 1 of the embodiment includes a metal layer 51a and a conductive oxygen barrier layer (first oxide layer 51b) between the conductive layer 52, which forms the source electrode and drain electrode, and the second oxide layer 51c. For example, when iridium (Ir) is used as the metal layer 51a, ITO as the second oxide layer 51c, and tungsten (W) as the conductive layer 52, a layer of iridium oxide (IrOx) as the first oxide layer 51b is formed at the interface between ITO and iridium. This iridium oxide, together with the iridium layer, suppresses oxygen diffusion from the channel to tungsten.

[0024] The same applies when the semiconductor device 1 does not have a second oxide layer 51c. When iridium is used as the metal layer 51a and tungsten as the conductive layer 52, a layer of iridium oxide as the first oxide layer 51b is formed at the interface between the channel and the iridium. This iridium oxide, together with the iridium layer, suppresses oxygen diffusion from the channel to the tungsten.

[0025] Thus, the semiconductor device 1 of this embodiment can prevent oxygen vacancies in the channel material and suppress a decrease in the threshold voltage Vth by appropriately selecting the metal element of the metal layer 51a and comprising the metal layer 51a and a first oxide layer 51b containing the said metal element.

[0026] (Formation of the first oxide layer and selection of metal elements for the metal layer) The first oxide layer 51b in the semiconductor device 1 of the embodiment can be formed by a heat treatment process related to the manufacturing of the semiconductor device 1. That is, a metal layer 51a containing an appropriate metal element is formed, and by heat treatment, a metal oxide containing the metal element that makes up the metal layer 51a is generated. Therefore, in the semiconductor device 1 of the embodiment, it is necessary to select a metal element for the metal layer 51a that has a high oxide generation energy so that a metal oxide can be generated by the heat treatment process. On the other hand, if the oxide generation energy of the metal is too high, the oxidation of the metal will proceed excessively, leading to oxygen removal or oxygen permeation. This is a factor that increases oxygen vacancies in the channels.

[0027] The oxide formation energies of platinum (Pt), silver (Ag), palladium (Pd), iridium (Ir), osmium (Os), and rhodium (Rh) are lower than those of ruthenium (Ru). Of these, platinum (Pt) has an oxide formation energy that is too low to be suitable for oxide layer formation. On the other hand, ruthenium (Ru) and copper (Cu), rhenium (Re), nickel (Ni), cobalt (Co), iron (Fe), etc., which have higher oxide formation energies than ruthenium (Ru), lead to excessive oxide layer formation. Therefore, in the semiconductor device 1 of this embodiment, it is preferable to select silver (Ag), palladium (Pd), iridium (Ir), osmium (Os), or rhodium (Rh) as the metal layer 51a.

[0028] Referring to Figures 5 to 9, the formation of oxide films and the diffusion of oxygen when an oxide annealing is performed after forming a conductive layer and a metal layer on an SiO2 substrate will be explained. Figures 5 to 6 show the elemental distribution when iridium is used as the metal layer. Figure 7 shows the elemental distribution when titanium nitride is used as the metal layer. Figures 8 to 9 show the elemental distribution when ruthenium is used as the metal layer. Figures 5 to 9 show the elemental composition ratio in the depth direction from the sample surface to the SiO2 substrate, analyzed by using X-ray photoelectron spectroscopy (XPS) in combination with ion etching. In other words, Figures 5 to 9 show the distribution of elemental amounts in the depth direction of the sample.

[0029] Figure 5 shows the oxide film formation when an oxygen annealing is performed on a sample in which a 30 nm thick tungsten layer is formed as a conductive layer 52 on a substrate (SiO2), and a 10 nm thick iridium layer is formed as a metal layer 51a on the surface of the tungsten layer. Figure 5 shows the elemental concentrations at various positions from the sample surface toward the substrate, from left to right, under three conditions: immediately after film formation, after oxygen annealing at 300°C, and after oxygen annealing at 350°C.

[0030] As shown in Figure 5, immediately after film deposition, the oxygen concentration on the sample surface is low while the iridium concentration is high. After oxygen annealing at 300°C, a region with overlapping high oxygen and low iridium concentrations can be observed near the sample surface. This indicates that iridium oxide was formed as the first oxide layer 51b in the overlapping area. The same is true when oxygen annealing is performed at 350°C, and the formation of iridium oxide can be observed near the sample surface. The oxygen observed on the sample surface is oxygen derived from iridium oxide. That is, the iridium oxide remains on the surface of the iridium layer, and the oxygen concentration in the iridium layer and tungsten layer is remarkably low. From this, it can be seen that oxygen was used to form iridium oxide, but did not diffuse into the tungsten layer.

[0031] Figure 6 shows the oxide film formation when an oxygen annealing is performed on a sample in which a 30 nm thick tungsten layer is formed as a conductive layer 52 on a substrate (SiO2), and a 30 nm thick iridium layer is formed as a metal layer 51a on the surface of the tungsten layer. Figure 6 shows the elemental concentrations at various positions from the sample surface toward the substrate, from left to right, under three conditions: immediately after film formation, after oxygen annealing at 300°C, and after oxygen annealing at 350°C.

[0032] As shown in Figure 6, immediately after film deposition, the oxygen concentration on the sample surface is low while the iridium concentration is high. After oxygen annealing at 300°C, a region with overlapping high oxygen and low iridium concentrations can be observed near the sample surface. This indicates that iridium oxide was formed as the first oxide layer 51b in the overlapping area. The same is true when oxygen annealing is performed at 350°C, and the formation of iridium oxide can be observed near the sample surface. The oxygen observed on the sample surface is oxygen derived from iridium oxide. That is, the iridium oxide remains on the surface of the iridium layer, and the oxygen concentration in the iridium layer and tungsten layer is remarkably low. As shown in Figures 5 and 6, when iridium is applied as the metal layer 51a, it can be seen that the diffusion of oxygen into the tungsten layer is suppressed regardless of its thickness.

[0033] Figure 7 shows the oxide film formation when an oxygen annealing is performed on a sample in which a 30 nm thick tungsten layer is formed as a conductive layer 52 on a substrate (SiO2), and a 10 nm thick titanium nitride layer is formed as a metal layer 51a on the surface of the tungsten layer. Figure 7 shows the elemental concentrations at various positions from the sample surface toward the substrate, from left to right, under two conditions: immediately after film formation and after oxygen annealing at 300°C.

[0034] As shown in Figure 7, immediately after film deposition, a constant oxygen concentration was observed not only on the sample surface but also within the titanium nitride layer. After oxygen annealing at 300°C, a high oxygen concentration was observed near the sample surface, while the titanium and nitrogen concentrations remained at approximately the same levels as immediately after film deposition. This indicates that no titanium nitride oxide film was formed, and oxygen diffused through the titanium nitride layer. From this, it can be seen that oxygen is not used to form titanium nitride oxide, but rather diffuses within the titanium nitride layer.

[0035] Figure 8 shows the oxide film formation when an oxygen annealing is performed on a sample in which a 30 nm thick tungsten layer is formed as a conductive layer 52 on a substrate (SiO2), and a 10 nm thick ruthenium layer is formed as a metal layer 51a on the surface of the tungsten layer. Figure 8 shows the elemental concentrations at various positions from the sample surface toward the substrate, from left to right, under three conditions: immediately after film formation, after oxygen annealing at 300°C, and after oxygen annealing at 350°C.

[0036] As shown in Figure 8, immediately after film deposition, the oxygen concentration on the sample surface is low, while the ruthenium concentration is high. Even after oxygen annealing at 300°C, the ruthenium concentration on the sample surface remained high, and high oxygen concentration was observed at the interface between the ruthenium layer and the tungsten layer. After oxygen annealing at 350°C, it was observed that oxygen had diffused into the region that was previously the tungsten layer. In other words, the oxygen concentration increased at the ruthenium-tungsten interface, indicating that oxygen had significantly diffused into the tungsten after the 350°C oxygen annealing.

[0037] Figure 9 shows the oxide film formation when an oxygen annealing is performed on a sample in which a 30 nm thick tungsten layer is formed as a conductive layer 52 on a substrate (SiO2), and a 30 nm thick ruthenium layer is formed as a metal layer 51a on the surface of the tungsten layer. Figure 9 shows the elemental concentrations at various positions from the sample surface toward the substrate, from left to right, under three conditions: immediately after film formation, after oxygen annealing at 300°C, and after oxygen annealing at 350°C.

[0038] As shown in Figure 9, immediately after film deposition, the oxygen concentration on the sample surface is low, while the ruthenium concentration is high. After oxygen annealing at 300°C, an increase in oxygen concentration was observed within the ruthenium layer, but the increase in oxygen concentration was more suppressed than that of the 10 nm thick ruthenium layer shown in Figure 8. After oxygen annealing at 350°C, the oxygen concentration within the ruthenium layer increased compared to after 300°C annealing, but little diffusion of oxygen into the tungsten layer was observed. This indicates that oxygen is not used for the formation of tungsten oxide. Although oxygen diffusion is suppressed as the ruthenium layer thickness increases, it can be seen that oxygen is diffusing within the ruthenium layer. Furthermore, when ruthenium is used as the metallic element in the metallic layer, it can be seen that oxygen diffusion is dependent on the film thickness.

[0039] Thus, it can be seen that the metal element used as the metal layer 51a affects whether or not the first oxide layer 51b is formed, and that the suppression of oxygen diffusion from the channel to the metal layer 51a and the conductive layer 52 cannot be achieved. Iridium (Ir) is preferred as the metal element to be selected, and at least one of palladium (Pd), silver (Ag), osmium (Os), and rhodium (Rh) is preferred.

[0040] (Changes in properties due to the metal elements and heat treatment of the metal layer) Referring to Figure 10, the relationship between the metal element of the metal layer 51a and its thermal resistance will be explained. Figure 10 shows the gate voltage characteristics of the semiconductor device shown in Figure 1 when there is no metal layer 51a, when ruthenium is used as the metal element of the metal layer 51a, and when iridium is used as the metal element of the metal layer 51a.

[0041] As shown in Figure 10, immediately after film deposition, all devices function as semiconductor devices. However, after nitrogen annealing at 400°C, it is shown that the devices do not function as semiconductor devices when there is no metal layer 51a and when ruthenium is used as the metal element of metal layer 51a. On the other hand, when iridium is used as the metal element of metal layer 51a, cutoff operation is maintained even after nitrogen annealing at 400°C. In other words, it can be seen that when iridium is used as the metal element of metal layer 51a, it exhibits superior heat resistance.

[0042] (Method for creating an embodiment 1) Next, the method for producing the metal layer 51a and the first oxide layer 51b in the semiconductor device 1 of the embodiment will be described with reference to Figures 11 to 15. Figure 11 is a flowchart showing the method for producing the metal layer 51a and the first oxide layer 51b in the semiconductor device of the embodiment. Figures 12 to 15 are conceptual diagrams showing cross-sections related to the method for producing the metal layer 51a and the first oxide layer 51b.

[0043] As shown in Figure 12, a conductor 30, an insulating layer 44, a conductive layer 42, and an insulating layer 45 are laminated, and holes are opened so as to penetrate the insulating layer 44, the conductive layer 42, and the insulating layer 45. Then, an insulating film 43 and an oxide semiconductor layer 41 are formed in the holes. Next, a second oxide layer 51c is formed on the surface of the insulating layer 45 so as to be bonded to the end face of the oxide semiconductor layer 41 (S100). For the second oxide layer 51c, for example, ITO can be used.

[0044] Next, as shown in Figure 13, oxygen annealing is performed to supply oxygen to the oxide semiconductor layer 41 (S110). For example, IGZO can be used as the oxide semiconductor layer 41.

[0045] Next, as shown in Figure 14, a metal layer 51a and a conductive layer 52 are deposited on the surface of the second oxide layer 51c to form the upper electrode (S120). Here, iridium is used as the metal layer 51a and tungsten is used as the conductive layer 52.

[0046] As shown in Figure 15, heat treatment is performed to form an iridium oxide layer as the first oxide layer 51b at the interface between the second oxide layer 51c and the metal layer 51a (S130).

[0047] (Method for creating an embodiment 2) Next, with reference to Figures 16 to 20, other examples of methods for producing the metal layer 51a and the first oxide layer 51b in the semiconductor device 1 of the embodiment will be described. Figure 16 is a flowchart showing other methods for producing the metal layer 51a and the first oxide layer 51b in the semiconductor device of the embodiment. Figures 17 to 20 are conceptual diagrams showing cross-sections related to other methods for producing the metal layer 51a and the first oxide layer 51b.

[0048] As shown in Figure 17, a conductor 30, an insulating layer 44, a conductive layer 42, and an insulating layer 45 are stacked, and after opening holes through the insulating layer 44, the conductive layer 42, and the insulating layer 45, an insulating film 43 and an oxide semiconductor layer 41 are formed inside the holes (S200).

[0049] Next, as shown in Figure 18, oxygen annealing is performed to supply oxygen to the oxide semiconductor layer 41 (S210). For example, IGZO can be used as the oxide semiconductor layer 41.

[0050] Next, as shown in Figure 19, a metal layer 51a is formed so as to bond with the end face of the oxide semiconductor layer 41 within the surface of the insulating layer 45, and then a conductive layer 52 is formed on the surface of the metal layer 51a to form the upper electrode (S220). Here, iridium is used as the metal layer 51a and tungsten is used as the conductive layer 52.

[0051] As shown in Figure 20, a heat treatment is performed to form an iridium oxide layer as the first oxide layer 51b at the interface between the oxide semiconductor layer 41 and the metal layer 51a (S230).

[0052] According to these methods for generating the first oxide layer 51b, an oxide film derived from the metal layer can be generated by a heat treatment process in the manufacturing process of a semiconductor device.

[0053] (Semiconductor devices as memory devices) Next, a semiconductor memory device having a semiconductor device 1 according to an embodiment will be described with reference to Figures 1, 21, and 22. Figure 21 is a circuit diagram illustrating an example of the circuit configuration of a memory cell array 2 as a semiconductor memory device according to an embodiment. Figure 21 shows a plurality of memory cells MC, a plurality of word lines WL (word line WLn, word line WLn+1, word line WLn+2, where n is an integer), a plurality of bit lines BL (bit line BLm, bit line BLm+1, bit line BLm+2, where m is an integer), and a power line VPL.

[0054] Multiple memory cells MC are arranged in a matrix direction to form a memory cell array 2. Each memory cell MC comprises a memory transistor MTR, which is a field-effect transistor (FET), and a memory capacitor MCP. The memory transistor MTR corresponds to the semiconductor device 1 of the embodiment. The gate (conductive layer 42) of the memory transistor MTR is connected to the corresponding word line WL, and either the source (conductor 50) or the drain (conductor 30) is connected to the corresponding bit line BL. The word line WL is connected to, for example, a row decoder. The bit line BL is connected to, for example, a sense amplifier. The first electrode of the memory capacitor MCP is connected to the other of the source or drain of the memory transistor MTR, and the second electrode is connected to a power line VPL that supplies a specific potential. The power line VPL is connected to, for example, a power supply circuit. The memory cell MC can store data by accumulating charge in the memory capacitor MCP from the bit line BL through switching of the memory transistor MTR by the word line WL. The memory cell MC can also read data based on the charge accumulated in the memory capacitor MCP to the bit line BL through switching of the memory transistor MTR by the word line WL. The number of memory cells (MCs) is not limited to the number shown in Figure 21.

[0055] Figure 22 is a schematic cross-sectional diagram illustrating an example of the structure of a memory cell array 2. Figure 22 shows a portion of the XZ cross-section, which consists of the X, Y, and Z axes that are perpendicular to each other. As shown in Figure 22, the memory cell array 2 comprises a conductor 21, a conductive layer 22, an electrical conductor 23, an insulator 24, a conductive layer 31, a conductive oxide layer 32, an oxide semiconductor layer 41, a conductive layer 42, an insulating film 43, an intermediate layer 51, a conductive layer 52, and a conductive layer 71.

[0056] The memory transistor MTR and memory capacitor MCP are provided above the insulating layer 11 on the semiconductor substrate 10, as shown in Figure 22. The memory transistor MTR can be the transistor of the embodiment described above. Peripheral circuits such as a low decoder, sense amplifier, and power supply circuit are formed on the semiconductor substrate 10. The peripheral circuits include field-effect transistors such as P-channel field-effect transistors (Pch-FETs) and N-channel field-effect transistors (Nch-FETs). Field-effect transistors can be formed using a semiconductor substrate 10 such as a single-crystal silicon substrate, and Pch-FETs and Nch-FETs have a channel region, a source region, and a drain region on the semiconductor substrate 10. The semiconductor substrate 10 may have a P-type conductivity. The insulating layer 11 is provided on the semiconductor substrate 10 and includes, for example, silicon (Si) and oxygen (O) or nitrogen (N). The insulating layer 11 may be a multilayer film.

[0057] The conductor 21, the conductive layer 22, the electrical conductor 23, and the insulator 24 form a memory capacitor MCP. The memory capacitor MCP is a three-dimensional capacitor, such as a pillar-type capacitor or a cylinder-type capacitor.

[0058] The conductor 21 is provided above the semiconductor substrate 10, with the insulating layer 11 in between. The conductive layer 22 is provided on a portion of the conductor 21. The conductor 21 and the conductive layer 22 form the second electrode of the memory capacitor MCP. The conductor 21 extends so as to overlap with a plurality of electrical conductors 23 when viewed from the Z-axis direction. The conductor 21 is also called a plate electrode. The electrical conductor 23 is provided above the conductor 21, with the insulator 24 in between, extends in the Z-axis direction, and forms the first electrode of the memory capacitor MCP. The insulator 24 is provided between the conductor 21 and the conductive layer 22 and the electrical conductor 23, and forms the dielectric of the memory capacitor MCP.

[0059] The conductor 21 and the conductive layer 22 include materials such as tungsten and titanium nitride. The electrical conductor 23 includes materials such as tungsten, titanium nitride, and amorphous silicon. The insulator 24 includes materials such as hafnium oxide, zirconium oxide, and aluminum oxide.

[0060] The conductive layer 31 is provided on the electrical conductor 23 and is electrically connected to the electrical conductor 23. The conductive layer 31 contains, for example, copper. Note that the conductive layer 31 is not necessarily required to be formed.

[0061] The conductive oxide layer 32 is provided on the conductive layer 31. The conductive oxide layer 32 contains the conductive oxide of the embodiment.

[0062] The conductive layer 31 and the conductive oxide layer 32 form a conductor 30. Multiple conductors 30 are provided for multiple electrical conductors 23. An insulating layer 33 is formed between the multiple conductors 30. The insulating layer 33 includes, for example, silicon and oxygen or nitrogen.

[0063] The oxide semiconductor layer 41, the conductive layer 42, and the insulating film 43 form a memory transistor (MTR). The memory transistor (MTR) is, for example, an N-channel field-effect transistor. The memory transistor (MTR) is provided above the memory capacitor (MCP). Multiple memory transistors (MTR) are provided corresponding to multiple memory capacitors (MCP). An insulating layer 44 and an insulating layer 45 are formed between the multiple memory transistors (MTR). The insulating layers 44 and 45 include, for example, silicon and oxygen or nitrogen.

[0064] The oxide semiconductor layer 41 is, for example, a columnar body extending in the Z-axis direction. The oxide semiconductor layer 41 penetrates the conductive layer 42 in the Z-axis direction. The oxide semiconductor layer 41 forms the channel of the memory transistor MTR. The oxide semiconductor layer 41 contains, for example, indium (In). The oxide semiconductor layer 41 contains, for example, indium oxide and gallium oxide, indium oxide and zinc oxide, or indium oxide and tin oxide. As an example, it includes an oxide containing indium, gallium, and zinc (indium-gallium-zinc oxide), so-called IGZO (InGaZnO).

[0065] One end of the oxide semiconductor layer 41 in the Z-axis direction is connected to the conductive layer 31 via the conductive oxide layer 32 and functions as the other source or drain of the memory transistor MTR. The conductive oxide layer 32 is provided between the electrical conductor 23 of the memory capacitor MCP and the oxide semiconductor layer 41 of the memory transistor MTR and functions as the other source electrode or drain electrode of the memory transistor MTR.

[0066] The conductive layer 42 includes a portion facing the oxide semiconductor layer 41 in the X-Y plane, with the insulating film 43 in between. The conductive layer 42 forms the gate electrode of the memory transistor MTR and also forms the word line WL as wiring. The conductive layer 42 includes, for example, a metal, a metal compound, or a semiconductor. The conductive layer 42 includes, for example, at least one material selected from the group consisting of tungsten (W), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), and ruthenium (Ru).

[0067] Multiple conductive layers 42 extend in the X-axis direction and are arranged parallel to each other. Each conductive layer 42 overlaps and connects to multiple memory cells MC in the X-axis direction.

[0068] The insulating film 43 is provided between the oxide semiconductor layer 41 and the conductive layer 42 in the X-Y plane. The insulating film 43 forms the gate insulating film of the memory transistor MTR. The insulating film 43 includes, for example, silicon and oxygen or nitrogen. The insulating film 43 may be a laminated film of multiple insulating films.

[0069] Memory transistors (MTRs) are so-called Surrounding Gate Transistors (SGTs), in which the gate electrode is arranged around the channel. SGTs allow for a reduction in the area of ​​semiconductor devices.

[0070] A field-effect transistor having a channel layer containing an oxide semiconductor has a lower off-leak current than a field-effect transistor provided on a semiconductor substrate 10. Therefore, for example, data held in a memory cell MC can be retained for a longer period, thus reducing the number of refresh operations. In addition, since a field-effect transistor having a channel layer containing an oxide semiconductor can be formed using a low-temperature process, thermal stress on the memory capacitor MCP can be suppressed.

[0071] The intermediate layer 51 is provided on the oxide semiconductor layer 41. The intermediate layer 51 contains the conductive oxide of the embodiment. As described above, the intermediate layer 51 has a metal layer 51a, a first oxide layer 51b, and a second oxide layer 51c.

[0072] The conductive layer 52 is provided on the intermediate layer 51 and is electrically connected to the intermediate layer 51. The conductive layer 52 contains, for example, copper.

[0073] The intermediate layer 51 and the conductive layer 52 form a conductor 50. The conductor 50 is electrically connected to the sense amplifier via the bit line BL. The conductor 50 functions as a conductive pad for connecting, for example, a memory transistor MTR to the bit line BL. Multiple conductors 50 are provided to correspond to multiple memory transistors MTR. An insulating layer 53 is formed between the multiple conductors 50. The insulating layer 53 includes, for example, silicon and oxygen or nitrogen.

[0074] The other end of the oxide semiconductor layer 41 in the Z-axis direction is connected to the conductive layer 52 via the intermediate layer 51 and functions as either the source or the drain of the memory transistor MTR. The intermediate layer 51 functions as either the source electrode or the drain electrode of the memory transistor MTR.

[0075] The conductive layer 71 is provided on the conductive layer 52 and connected to the conductor 50. The conductive layer 71 forms bit lines BL as wiring. An insulating layer 72 is formed between the multiple conductive layers 71. The insulating layer 72 includes, for example, silicon and oxygen or nitrogen.

[0076] Multiple memory cells (MCs) may form a staggered arrangement in the XY plane. A memory cell MC connected to one of multiple word lines (WLs) is positioned offset in the X-axis direction relative to memory cell MCs connected to adjacent word lines (WLs). This increases the integration density of memory cells (MCs).

[0077] Figure 23 is a block diagram showing an example configuration of a semiconductor memory device according to an embodiment. The semiconductor memory device 100 includes a memory cell array 110, a load driver 111, a column driver 112, a write circuit 113, a read circuit 114, a voltage generation circuit 115, and a control circuit 116. The memory cell array 110 includes the memory cell array 2 described in Figures 21 and 22, and includes the semiconductor device 1 according to the embodiment described above.

[0078] The low driver 111 controls multiple rows of the memory cell array 110. The low driver 111 receives a low address signal from the control circuit 116 based on the decoding result of an externally input address signal ADR. The low driver 111 sets the word line WL of the row selected by the low address signal to a selected state. The low driver 111 includes circuits such as a multiplexer (word line selection circuit) and a word line driver.

[0079] The column driver 112 controls multiple columns of the memory cell array 110. The column driver 112 receives a column address signal from the control circuit 116 based on the decoding result of the address signal ADR. The column driver 112 sets the bit line BL of the column selected by the column address signal to the selected state. The column driver 112 includes circuits such as a multiplexer (bit line selection circuit) and a bit line driver.

[0080] The writing circuit 113 performs various controls for the data writing operation. The writing circuit 113 receives a data signal DT input from an external source. During the writing operation, the writing circuit 113 supplies a write pulse formed by current and / or voltage to the memory cell array 110. This allows data to be written to the memory cell MC. The writing circuit 113 is electrically connected to the memory cell array 110 via the load driver 111. The writing circuit 113 includes circuits such as a voltage source and / or a current source, a pulse generation circuit, and a latch circuit.

[0081] The read circuit 114 performs various controls for the data read operation. During the read operation, the read circuit 114 supplies a read pulse (e.g., read voltage) to the memory cell array 110. The read circuit 114 senses the potential or current value of the bit line BL. Based on this sensing result, data in the memory cell MC can be read. The read circuit 114 transfers the read data signal to the outside. The read circuit 114 is connected to the memory cell array 110 via the column driver 112. The read circuit 114 includes circuits such as a voltage source and / or a current source, a pulse generation circuit, a latch circuit, and a sense amplifier circuit.

[0082] The write circuit 113 and the read circuit 114 are not limited to being independent circuits. For example, the write circuit 113 and the read circuit 114 may have common components that can be used together and may be arranged in the semiconductor memory device 100 as a single integrated circuit.

[0083] The voltage generation circuit 115 uses an externally supplied power supply voltage to generate voltages for various operations of the memory cell array 110. The voltage generation circuit 115 supplies the generated voltages to the load driver 111, the column driver 112, the write circuit 113, and the read circuit 114, respectively.

[0084] The control circuit 116 includes, for example, a command register and an address register. Based on, for example, an externally input command signal CMD, an address signal ADR, and a control signal CNT, the control circuit 116 controls the load driver 111, a column driver 112, a write circuit 113, a read circuit 114, and a voltage generation circuit 115 to perform operations such as read operations, write operations, and erase operations.

[0085] The command signal CMD is a signal indicating the operation that the semiconductor memory device 100 should perform. For example, the address signal ADR is a signal indicating the coordinates of one or more memory cells MC (called selected cells) to be operated on within the memory cell array 110. The address signal ADR includes the low address signal and column address signal of the memory cell MC. The control signal CNT is a signal for controlling, for example, the operation timing between the semiconductor memory device 100 and an external device and the operation timing within the semiconductor memory device 100.

[0086] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0087] 1, 9a, 9b… Semiconductor equipment, 2… Memory cell array 10... Semiconductor substrate, 11... Insulating layer 21...Conductor, 22...Conductive layer, 23...Electrical conductor, 24...Insulator 30...Conductive material, 31...Conductive layer, 32...Conductive oxide layer, 33...Insulating layer 41…Oxide semiconductor layer, 42…Conductive layer, 43…Insulating film, 44,45…Insulating layer 50, 50a, 50b...Conductive layer, 51...Intermediate layer, 51a...Metal layer, 51b...First oxide layer, 51c...Second oxide layer, 52...Conductive layer, 53...Insulating layer 71...Conductive layer, 72...Insulating layer 100... Semiconductor memory 110...Memory cell array, 111...Row driver, 112...Column driver, 113...Write circuit, 114...Read circuit, 115...Voltage generation circuit, 116...Control circuit ADR...Address signal, BL...Bit line, CMD...Command signal, CNT...Control signal, DT...Data signal MC...Memory cell, MCP...Memory capacitor, MTR...Memory transistor VPL...Power line, Vth...Threshold voltage, WL...Word line

Claims

1. A semiconductor device comprising a channel containing an oxide semiconductor and an electrode in contact with the channel, The electrode is A metallic layer containing at least one metallic element from iridium, palladium, silver, osmium, and rhodium, A first oxide layer is provided in contact with the metal layer and disposed between the metal layer and the channel, and includes the metal elements of the metal layer. Semiconductor equipment.

2. The electrode includes a second oxide layer between the first oxide layer and the channel. The semiconductor device according to claim 1.

3. The second oxide layer is an oxide layer containing indium and tin. The semiconductor device according to claim 2.

4. The oxide semiconductor contains at least one element from among indium, gallium, zinc, and tin. The semiconductor device according to claim 1.

5. The system comprises a source electrode and a drain electrode, wherein at least one of the source electrode and the drain electrode is the electrode. The semiconductor device according to claim 1.

6. A semiconductor memory device comprising a channel containing an oxide semiconductor and an electrode in contact with the channel, The electrode is A metallic layer containing at least one metallic element from iridium, palladium, silver, osmium, and rhodium, A first oxide layer is disposed in contact with the metal layer and between the metal layer and the channel, and contains the metal elements of the metal layer. The channel and a capacitor electrically connected to it include Semiconductor memory device.

7. The electrode includes a second oxide layer between the first oxide layer and the channel. The semiconductor memory device according to claim 6.

8. The second oxide layer is an oxide layer containing indium and tin. The semiconductor memory device according to claim 7.

9. The oxide semiconductor contains at least one element from among indium, gallium, zinc, and tin. The semiconductor memory device according to claim 6.

10. The system comprises a source electrode and a drain electrode, wherein at least one of the source electrode and the drain electrode is the electrode. The semiconductor memory device according to claim 6.

11. The capacitor is electrically connected to the channel via the electrodes. The semiconductor memory device according to claim 6.

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