Memory device

Abstract

To provide a memory device having a switching element with excellent characteristics. [Solution] The memory device of the embodiment includes a memory cell comprising a switching layer between a first conductive layer and a third conductive layer, and a resistive switching layer between the third conductive layer and the second conductive layer. The switching layer includes a first oxide of a first element selected from Mg, Y, La, Ce, Zr, Hf, Al, Ti, and Si, a second element selected from Zn, Ga, In, Sn, and Bi, a third element selected from P, As, Sb, Bi, S, Se, and Te, and a fourth element selected from the group consisting of V, Nb, Ta, Cr, B, Ga, and Si. The switching layer includes a first region, a second region, and a third region, the first region being provided between the second region and the third region. The first region includes the first oxide, and the second and third regions include a fourth oxide of the fourth element.

Description

Technical Field

[0006] , , ,

[0007] , ,

[0001] Embodiments of the present invention relate to a memory device.

Background Art

[0002] As a large-capacity non-volatile memory device, there is a cross-point type two-terminal memory device. The cross-point type two-terminal memory device is easy to miniaturize and highly integrate memory cells.

[0003] A memory cell of the cross-point type two-terminal memory device has, for example, a resistance change element and a switching element. By having a switching element in the memory cell, the current flowing through memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as a low leakage current, a high on-current, and high reliability.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The problem to be solved by the present invention is to provide a memory device having a switching element with excellent characteristics.

Means for Solving the Problems

[0007] The memory device of the embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer, wherein the switching layer comprises: a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si); at least one second element, different from the first element, selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi); and phosphorus (P), different from the first and second elements. The switching layer comprises at least one third element selected from the group consisting of arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), and at least one fourth element, different from the first, second, and third elements, selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), wherein the switching layer comprises a first region, a second region, and a third region in a cross section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross section, the first region is provided between the second region and the third region, the first region comprises the first oxide, and the second and third regions comprises the fourth oxide of the fourth element. [Brief explanation of the drawing]

[0008] [Figure 1] Block diagram of the storage device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the memory cell of the first embodiment of the storage device. [Figure 3] A diagram showing the standard formation energies of elemental oxides. [Figure 4]A schematic cross-sectional view showing a method for manufacturing a memory cell of a first embodiment of a storage device. [Figure 5] A schematic cross-sectional view showing a method for manufacturing a memory cell of a first embodiment of a storage device. [Figure 6] A schematic cross-sectional view showing a method for manufacturing a memory cell of a first embodiment of a storage device. [Figure 7] A schematic cross-sectional view showing a method for manufacturing a memory cell of a first embodiment of a storage device. [Figure 8] A diagram illustrating the problems of the storage device according to the first embodiment. [Figure 9] A diagram illustrating the current-voltage characteristics of the switching element according to the first embodiment. [Figure 10] A schematic cross-sectional view of a memory cell of a first modified memory device according to the first embodiment. [Figure 11] A schematic cross-sectional view of a memory cell of a second modified memory device according to the first embodiment. [Figure 12] A schematic cross-sectional view of a memory cell of a third modified memory device according to the first embodiment. [Figure 13] A schematic cross-sectional view of a memory cell of the second embodiment of the storage device. [Figure 14] A schematic cross-sectional view of a memory cell of the third embodiment of the storage device. [Figure 15] A diagram illustrating the current-voltage characteristics of the memory element according to the third embodiment. [Figure 16] A diagram illustrating a first example of the memory operation of the storage device according to the third embodiment. [Figure 17] A diagram illustrating a second example of the memory operation of the storage device according to the third embodiment. [Figure 18] A diagram illustrating the current-voltage characteristics of the memory element in the first modified example of the third embodiment. [Figure 19] A diagram illustrating a third example of the memory operation of the storage device of the first modified example of the third embodiment. [Figure 20] A diagram illustrating a fourth example of the memory operation of the storage device in the first modified example of the third embodiment. [Figure 21] A diagram illustrating the current-voltage characteristics of a memory element in a second modified example of the third embodiment. [Figure 22] Explanatory diagram of the fifth operation example of the memory operation of the memory device according to the second modification of the third embodiment. [Figure 23] Explanatory diagram of the sixth operation example of the memory operation of the memory device according to the second modification of the third embodiment. [Figure 24] Explanatory diagram of the current-voltage characteristics of the memory element according to the third modification of the third embodiment. [Figure 25] Explanatory diagram of the seventh operation example of the memory operation of the memory device according to the third modification of the third embodiment. [Figure 26] Explanatory diagram of the eighth operation example of the memory operation of the memory device according to the third modification of the third embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] It should be noted that in the above translation, for the tag "

[0009] ", since it is not clear what the specific meaning or expected translation rule for it is, it is left unchanged as per the requirement. If there are specific instructions for this tag, the translation can be adjusted accordingly.For qualitative and quantitative analysis of the chemical composition constituting the memory device described herein, methods such as Rutherford backscattering spectroscopy (RBS), secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and electron energy loss spectroscopy (EELS) can be used. Furthermore, for measuring the thickness of the components constituting the memory device, the distance between components, etc., a transmission electron microscope (TEM) can be used, for example. Furthermore, for identifying the constituent materials of the components constituting the memory device, measuring the relative abundance of the constituent materials, identifying the bonding state of the constituent materials, identifying the local structure (interatomic distance, coordination number) of the constituent materials, measuring the chemical state of the constituent materials, and comparing the concentrations of the constituent materials, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure analysis (XAFS), Raman spectroscopy (Raman), scanning transmission electron microscope (STEM), or EELS can be used.

[0011] (First Embodiment) The memory device of the first embodiment includes a memory cell comprising: a first conductive layer; a second conductive layer; a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; and a resistive switching layer provided between the third conductive layer and the second conductive layer. The switching layer comprises a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si); and at least one second element, different from the first element, selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi); and Unlike the first and second elements, it includes at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), and at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si). The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region, the first region contains a first oxide, and the second and third regions contain a fourth oxide of a fourth element.

[0012] Furthermore, the storage device of the first embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0013] Figure 1 is a block diagram of the storage device according to the first embodiment.

[0014] The memory cell array 100 of the first embodiment of the memory device includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102, separated by an insulating layer on a semiconductor substrate 101. The bit lines 103 are provided, for example, on top of the word lines 102. In addition, peripheral circuits such as a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100.

[0015] Word line 102 is an example of the first wiring. Bit line 103 is an example of the second wiring.

[0016] Multiple memory cells MC are provided in the region where the word line 102 and the bit line 103 intersect. The memory device of the first embodiment is a two-terminal magnetoresistive memory having a crosspoint structure.

[0017] Multiple word lines 102 are each connected to the first control circuit 104. Multiple bit lines 103 are each connected to the second control circuit 105. The sense circuit 106 is connected to both the first control circuit 104 and the second control circuit 105.

[0018] The first control circuit 104 and the second control circuit 105 have functions such as selecting a desired memory cell MC, writing data to the memory cell MC, reading data from the memory cell MC, and erasing data from the memory cell MC. When reading data, the data from the memory cell MC is read out as the amount of current flowing between the word line 102 and the bit line 103, or as a change in the potential of the bit line 103. The sense circuit 106 has a function to determine the polarity of the data by determining the amount of current. For example, it determines whether the data is "0" or "1".

[0019] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are composed of electronic circuits using semiconductor devices formed on a semiconductor substrate 101, for example.

[0020] Figure 2 is a schematic cross-sectional view of a memory cell of the first embodiment of the storage device. Figure 2 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, for example, indicated by a dotted circle. Figure 2 is a cross-section parallel to a first direction connecting the lower electrode 10 to the upper electrode 20.

[0021] As shown in Figure 2, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive switching layer 50, and a sidewall insulating layer 55. The switching layer 40 includes an internal region 41, a first sidewall region 42a, and a second sidewall region 42b. Hereinafter, the first sidewall region 42a and the second sidewall region 42b may be referred to as the sidewall region 42, either individually or collectively. The resistive switching layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b.

[0022] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The internal region 41 is an example of the first region. The first sidewall region 42a is an example of the second region. The second sidewall region 42b is an example of the third region.

[0023] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0024] The lower electrode 10 is connected to the word wire 102. The lower electrode 10 is, for example, a metal. The lower electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The lower electrode 10 may also be part of the word wire 102.

[0025] The upper electrode 20 is connected to the bit wire 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride. The upper electrode 20 may also be part of the bit wire 103.

[0026] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0027] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 toward the upper electrode 20 is, for example, 5 nm to 50 nm. More preferably, the thickness of the switching layer 40 in the first direction from the lower electrode 10 toward the upper electrode 20 is, for example, 5 nm to 20 nm. The length of the switching layer 40 in the second direction perpendicular to the first direction is, for example, 10 nm to 50 nm.

[0028] The switching layer 40 has a function to suppress the increase in semi-selective leakage current flowing to the semi-selective cell. The switching layer 40 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0029] The switching layer 40 contains a first oxide of the first element, a second element, a third element, and a fourth element.

[0030] The first element is at least one element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si). The first oxide is, for example, magnesium oxide, yttrium oxide, lanthanum oxide, cerium oxide, zirconium oxide, hafnium oxide, aluminum oxide, titanium oxide, or silicon oxide.

[0031] The second element is different from the first element. The second element is at least one element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi).

[0032] The third element is different from the first and second elements. The third element is at least one element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te).

[0033] The switching layer 40 includes, for example, a first compound of a second element and a third element. The first compound of a second element and a third element is, for example, zinc telluride when the second element is zinc (Zn) and the third element is tellurium (Te).

[0034] The fourth element is different from the first, second, and third elements. The fourth element is at least one element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si).

[0035] The fourth element is less easily oxidized than the first element, but more easily oxidized than the second and third elements. In other words, the standard energy of formation of the oxide of the fourth element is greater than that of the first element, but less than that of the second and third elements.

[0036] The standard formation energy of an oxide can be rephrased as the standard Gibbs free energy of formation of an oxide. The standard Gibbs free energy of formation of an oxide is the Gibbs free energy required to form an oxide from an element in its elemental form. The unit of the standard Gibbs free energy of formation of an oxide is kJ / mol.

[0037] Figure 3 shows the standard formation energies of oxides of various elements. Figure 3 displays the standard formation energies of oxides for each element. The values ​​shown are normalized for the case where there is one oxygen atom in the oxide. Because these values ​​are normalized for the case where there is one oxygen atom in the oxide, the unit is expressed as kJ / mol·O.

[0038] As shown in Figure 3, the standard formation energy of the oxide of the fourth element is greater than that of the first element, and less than that of the second and third elements.

[0039] For example, if the first element is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B), then, as shown in Figure 3, the standard formation energy of the oxide of boron (B) is greater than that of the oxide of zirconium (Zr), and less than that of the oxides of zinc (Zn) and tellurium (Te).

[0040] The switching layer 40 includes, for example, a second compound of a second element and a fourth element, or a third compound of a third element and a fourth element. For example, if the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B), the switching layer 40 includes boron telluride as the third compound.

[0041] The bond energies of the second compound between the second and fourth elements, and the bond energies of the third compound between the third and fourth elements, are, for example, smaller than the bond energies of the first compound between the second and third elements. When the bond energies of the second and third compounds are smaller than the bond energies of the first compound, the first compound is less likely to decompose in the presence of the first compound and the fourth element.

[0042] The bond energy of a compound refers to the energy required for the compound to separate into its elemental components. The unit of bond energy is kJ / mol. The bond energy of a compound can be determined if its constituent elements are identified.

[0043] For example, if the second element is zinc (Zn) and the third element is tellurium (Te), and the first compound is zinc telluride (ZnTe), then the bond energy of the first compound is the energy required for zinc telluride (ZnTe) to separate into zinc (Zn) and tellurium (Te). For example, if the second element is zinc (Zn) and the third element is tellurium (Te), and the first compound is zinc telluride, then, unless the fourth element is gallium (Ga), the condition that the bond energies of the second compound and the third compound are smaller than the bond energy of the first compound is satisfied.

[0044] Furthermore, the bond energy of a compound can be determined if its constituent elements are identified.

[0045] The sum of the atomic concentrations of the first element, the second element, the third element, the fourth element, and oxygen (O) in the switching layer 40 is, for example, between 80% and 100%.

[0046] In the switching layer 40, the ratio of the sum of the atomic concentrations of the first element and oxygen (O) to the sum of the atomic concentrations of the first element, the second element, the third element, the fourth element, and oxygen (O) is, for example, 5% or more and 90% or less.

[0047] In the switching layer 40, the ratio of the sum of the atomic concentrations of the fourth element to the sum of the atomic concentrations of the first, second, third, and fourth elements is, for example, 1% to 20%, preferably 1% to 10%.

[0048] In the switching layer 40, the atomic concentration of the fourth element is lower than, for example, the atomic concentrations of the second element and the third element.

[0049] In the switching layer 40, the atomic concentration of the fourth element is, for example, lower than the atomic concentration of the first element.

[0050] The switching layer 40 includes, for example, at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N). The fifth element is different from the first, second, third, and fourth elements.

[0051] The atomic concentration of the fifth element in the switching layer 40 is, for example, lower than the atomic concentrations of the first, second, and third elements. The atomic concentration of the fifth element in the switching layer 40 is, for example, between 1% and 10%.

[0052] The atomic concentration of each element in the switching layer 40 can be obtained, for example, by performing line analysis of atomic concentrations in a second direction between the ends of the switching layer 40 in a cross section parallel to the first direction connecting the lower electrode 10 to the upper electrode 20, and calculating the average value of the atomic concentrations.

[0053] The switching layer 40 includes an internal region 41 and a sidewall region 42. The sidewall region 42 includes a first sidewall region 42a and a second sidewall region 42b.

[0054] In a cross-section parallel to the first direction connecting the lower electrode 10 to the upper electrode 20, and in a second direction perpendicular to the first direction, the internal region 41 is provided between the first sidewall region 42a and the second sidewall region 42b. The first sidewall region 42a and the second sidewall region 42b are provided, for example, between the lower electrode 10 and the intermediate electrode 30 in the first direction. The first sidewall region 42a and the second sidewall region 42b are in contact with the lower electrode 10 and the intermediate electrode 30, respectively, in the first direction.

[0055] The internal region 41 contains a first oxide, a second element, a third element, and a fourth element.

[0056] The internal region 41 may or may not contain the fourth oxide of the fourth element. The internal region 41 may or may not contain the second oxide of the second element. The internal region 41 may or may not contain the third oxide of the third element.

[0057] The internal region 41 includes, for example, a first compound of a second element and a third element. The internal region 41 also includes, for example, a second compound of a second element and a fourth element, or a third compound of a third element and a fourth element.

[0058] The sidewall region 42 contains the fourth oxide of the fourth element. The sidewall region 42 may or may not contain the first element, the second element, and the third element, respectively. The sidewall region 42 may or may not contain the second oxide of the second element or the third oxide of the third element.

[0059] The sidewall region 42 may or may not contain a second compound of the second and fourth elements. The sidewall region 42 may or may not contain a third compound of the third and fourth elements.

[0060] The atomic concentration of the fourth element in the sidewall region 42 is, for example, higher than the atomic concentration of the fourth element in the interior region 41. The concentration of the fourth oxide in the sidewall region 42 is, for example, higher than the concentration of the fourth oxide in the interior region 41.

[0061] The concentration of the fourth oxide in the sidewall region 42 is higher than, for example, the concentration of the second oxide in the sidewall region 42. The concentration of the fourth oxide in the sidewall region 42 is higher than, for example, the concentration of the third oxide in the sidewall region 42.

[0062] If the internal region 41 contains the second compound, the concentration of the second compound in the sidewall region 42 is lower, for example, than the concentration of the second compound in the internal region 41. If the internal region 41 contains the third compound, the concentration of the third compound in the sidewall region 42 is lower, for example, than the concentration of the third compound in the internal region 41.

[0063] The oxygen concentration in the sidewall region 42 is, for example, higher than the oxygen concentration in the internal region 41.

[0064] Note that the concentrations of oxides and compounds are expressed as, for example, molar concentrations.

[0065] The thickness of the first sidewall region 42a and the second sidewall region 42b in the second direction is, for example, 0.5 nm or more and 5 nm or less.

[0066] The resistive change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistive change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistive change layer 50 includes a magnetic tunnel junction composed of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0067] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0068] The fixed layer 51 is a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined writing voltage, and the magnetization direction is fixed in a specific direction.

[0069] The tunnel layer 52 is an insulator. Electrons pass through the tunnel layer 52 by the tunneling effect.

[0070] The free layer 53 is a ferromagnetic material. In the free layer 53, the magnetization direction changes in response to a predetermined writing voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and flowing a current between the intermediate electrode 30 and the upper electrode 20.

[0071] By changing the magnetization direction of the free layer 53, the electrical resistance of the resistance-changing layer 50 changes. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high-resistance state is achieved where current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low-resistance state is achieved where current is easy to flow. Note that the arrangement of the fixed layer 51 and the free layer 53 can be reversed. In other words, the layers may be stacked in the order of intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20.

[0072] The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b. In the second direction, the lower electrode 10, the switching layer 40, and the intermediate electrode 30 are provided between the first portion 55a and the second portion 55b. For example, the first sidewall region 42a is in contact with the first portion 55a, and the second sidewall region 42b is in contact with the second portion 55b.

[0073] The chemical composition of the sidewall insulating layer 55 is, for example, different from the chemical composition of the sidewall region 42. The sidewall insulating layer 55 is, for example, silicon oxide.

[0074] Next, a method for manufacturing the memory cell of the first embodiment of the storage device will be described.

[0075] Figures 4, 5, 6, and 7 are schematic cross-sectional views showing a method for manufacturing memory cells of a first embodiment of a storage device. Figures 4, 5, 6, and 7 are cross-sectional views corresponding to Figure 2.

[0076] The following explanation will use the example where the first element is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), the fourth element is boron (B), and the first oxide is zirconium oxide.

[0077] First, a first carbon film 2, a zirconium oxide film 3 containing zinc (Zn), tellurium (Te), and boron (B), and a second carbon film 4 are formed on the substrate 1 (Figure 4).

[0078] The zirconium oxide film 3 contains zinc telluride, a compound of zinc (Zn) and tellurium (Te). Zinc telluride is an example of the first compound. Boron (B) exists in its elemental form, for example, within the zirconium oxide film 3.

[0079] The substrate 1 is, for example, a conductive layer. The first carbon film 2, the zirconium oxide film 3, and the second carbon film 4 are formed, for example, by sputtering. The first carbon film 2, the zirconium oxide film 3, and the second carbon film 4 ultimately become the lower electrode 10, the switching layer 40, and the intermediate electrode 30, respectively.

[0080] Next, a resist pattern is formed on the second carbon film 4 using lithography. Then, using the resist as a mask, reactive ion etching (RIE) is performed to process the second carbon film 4, the zirconium oxide film 3, and the first carbon film 2 (Figure 5).

[0081] Next, an oxidation treatment is performed to oxidize the sides of the zirconium oxide film 3 (Figure 6). The oxidation treatment is, for example, a heat treatment in an atmosphere containing an oxidizing gas. The oxidation treatment is performed, for example, in the same chamber as the RIE. For example, the RIE and the oxidation treatment are performed consecutively in the same chamber. For example, the RIE and the oxidation treatment are performed without exposing the substrate 1 to the atmosphere outside the chamber.

[0082] Through oxidation treatment, oxidation regions 5 are formed on the sides of the zirconium oxide film 3 containing zinc (Zn), tellurium (Te), and boron (B). In oxidation regions 5, for example, oxides of boron (B), which are more easily oxidized than zinc (Zn) and tellurium (Te), are formed. That is, boron oxide is formed in oxidation regions 5. Boron oxide is an example of a fourth oxide. Oxidation regions 5 eventually become sidewall regions 42.

[0083] Furthermore, through oxidation treatment, for example, some zinc (Zn), which is more easily oxidized than tellurium (Te), is oxidized, causing zinc telluride to decompose and form zinc oxide. For example, elemental tellurium (Te) formed by the decomposition of zinc telluride combines with boron (B), forming boron telluride within the zirconium oxide film 3. Boron telluride is an example of a third compound.

[0084] Furthermore, through oxidation treatment, for example, boron (B) inside the zirconium oxide film 3 diffuses toward the sides of the zirconium oxide film 3, and the atomic concentration of boron (B) in the oxidation region 5 becomes higher than the atomic concentration of boron (B) inside the zirconium oxide film 3.

[0085] Next, silicon oxide films 6 are formed on the sides of the first carbon film 2, the zirconium oxide film 3, and the second carbon film 4 (Figure 7). The silicon oxide films 6 are formed, for example, by chemical vapor deposition. The silicon oxide films 6 ultimately become the sidewall insulating layer 55.

[0086] Subsequently, the resistive layer 50 and the upper electrode 20 are formed by a known manufacturing method. The memory cell of the first embodiment is formed by the above manufacturing method.

[0087] Next, the operation and effects of the storage device according to the first embodiment will be described.

[0088] In the first embodiment of the memory device, as described above, the resistance of the resistance change layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, it becomes a high-resistance state in which current is difficult to flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, it becomes a low-resistance state in which current is easy to flow.

[0089] For example, the high-resistance state of the resistive change layer 50 is defined as data "1," and the low-resistance state is defined as data "0." The memory cell MC can maintain different resistance states, enabling it to store 1-bit data of "0" and "1." Writing to a single memory cell MC is performed by applying a voltage and current between the bit line 103 and the word line 102 connected to that memory cell MC.

[0090] Figure 8 is an explanatory diagram of the problems of the memory device according to the first embodiment. Figure 8 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. The intersections of the word line and the bit line represent each memory cell MC.

[0091] The selected memory cell MC is memory cell A (selected cell). The write voltage Vwrite is applied to the word line connected to memory cell A. Also, 0V is applied to the bit line connected to memory cell A.

[0092] The following explanation will use the example where a voltage half the write voltage (Vwrite / 2) is applied to the word line and bit line that are not connected to memory cell A.

[0093] The voltage applied to memory cell C (unselected cell), which is connected to the word line and bit line not connected to memory cell A, is 0V. In other words, no voltage is applied.

[0094] On the other hand, a voltage half the write voltage Vwrite (Vwrite / 2) is applied to memory cell B (a semi-selective cell) that is connected to the word line or bit line connected to memory cell A. Therefore, a semi-selective leakage current flows through memory cell B (a semi-selective cell).

[0095] In addition, as an alternative application method, a method may be used in which a voltage half the write voltage (Vwrite / 2) is applied to the word line connected to memory cell A, a negative voltage half the write voltage (-Vwrite / 2) is applied to the bit line, and 0V is applied to the word line and bit line not connected to memory cell A.

[0096] Figure 9 is an explanatory diagram of the current-voltage characteristics of the switching element in the first embodiment. The horizontal axis represents the voltage applied to the switching element, and the vertical axis represents the current flowing through the switching element.

[0097] A switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth. The threshold voltage Vth is, for example, between 0.5V and 3V.

[0098] The write voltage Vwrite is set such that the write voltage Vwrite is higher than the threshold voltage Vth, and half the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on current (Ion in Figure 9). The current that flows through the switching element when half the write voltage Vwrite (Vwrite / 2) is applied is the semi-selective leakage current (Ihalf in Figure 9).

[0099] Furthermore, the read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in Figure 9. Therefore, the semi-selective leakage current flowing through the semi-selective cell can also be suppressed when reading from the memory cell MC.

[0100] A high semi-selective leakage current can lead to increased power consumption of the chip, for example. Also, an increased voltage drop in the wiring can prevent a sufficiently high voltage from being applied to the selected cell, resulting in unstable writing operations to the memory cell MC. Furthermore, a low on-current can lead to insufficient current flowing to the selected cell, resulting in incomplete writing to the memory cell MC. Therefore, the current-voltage characteristics of a switching element require a balance between low semi-selective leakage current and high on-current.

[0101] Furthermore, high reliability is required for the current-voltage characteristics of the switching element. Specifically, it is necessary to suppress characteristic fluctuations such as fluctuations in semi-selective leakage current and on-current when data is repeatedly written to the memory cell MC, thereby achieving high reliability.

[0102] For example, consider a switching element in the comparative example in which the switching layer does not contain the fourth element. The switching layer that does not contain the fourth element can be formed, for example, by using an oxide film of the first element that contains the second and third elements. In other words, it can be formed by using an oxide film that differs from that of the first embodiment in that it does not contain the fourth element. The switching element in the comparative example has problems such as high semi-selective leakage current and large characteristic fluctuations when data is repeatedly written to the memory cell MC.

[0103] One of the causes of the above-mentioned problems occurring in the comparative switching element is thought to be that the second and third elements exist locally as elemental substances rather than as a compound in the sidewall region of the switching layer. The presence of the second and third elements as elemental substances rather than as a compound in the sidewall region of the switching layer forms a current leakage path, increasing the semi-selective leakage current. Furthermore, the presence of the second and third elements as elemental substances in the sidewall region of the switching layer is thought to accelerate the aggregation of the second or third element when data is repeatedly written to the memory cell MC, leading to greater characteristic fluctuations.

[0104] The oxidation treatment performed after processing the oxide film that will serve as the switching layer using RIE has the effect of restoring etching damage remaining on the sides of the switching layer. If etching damage remains, for example, the semi-selective leakage current will increase.

[0105] On the other hand, oxidation treatment causes the second or third element to oxidize near the side surface of the switching layer, forming an oxide of the second or third element. In this case, the first compound decomposes. If the second oxide is formed, the third element remains as an elemental substance. If the third oxide is formed, the second element remains as an elemental substance. Of the second and third elements, the element that is less susceptible to oxidation will remain as an elemental substance.

[0106] For example, consider the case where the switching layer of the comparative example switching element has zirconium (Zr) as the first element, zinc (Zn) as the second element, and tellurium (Te) as the third element. The switching layer contains zinc telluride as the first compound in zirconium oxide. When the side surface of the switching layer is oxidized, zinc (Zn), which is more easily oxidized than tellurium (Te) near the side surface of the switching layer, is oxidized to form zinc oxide. As zinc telluride decomposes, tellurium (Te) remains in its elemental form. The remaining tellurium (Te) forms a current leakage path, increasing the semi-selective leakage current. In addition, when data is repeatedly written to the memory cell MC, the aggregation of tellurium (Te) is accelerated, and the characteristic fluctuations become larger.

[0107] The switching layer 40 of the first embodiment contains a fourth element. The sidewall region 42 of the switching layer 40 contains a fourth oxide obtained by oxidizing the fourth element. By including the fourth oxide, the first compound of the second and third elements is decomposed, and the existence of the second and third elements as individual substances in the sidewall region 42 of the switching layer 40 is suppressed.

[0108] For example, consider the case where, in the switching layer 40 of the switching element of the first embodiment, the first element is zirconium (Zr), the second element is zinc (Zn), the third element is tellurium (Te), and the fourth element is boron (B). Similar to the comparative example, the switching layer 40 contains zinc telluride as the first compound in the zirconium oxide. Boron (B) is more easily oxidized than either zinc (Zn) or tellurium (Te). Therefore, when the side surface of the switching layer 40 is oxidized, boron (B), which is more easily oxidized than zinc (Zn) and tellurium (Te), is oxidized near the side surface of the switching layer 40, forming boron oxide, which is the fourth oxide. Consequently, the decomposition of zinc telluride is suppressed, and the presence of tellurium (Te) in its elemental form, as in the comparative example, is suppressed.

[0109] Furthermore, the standard formation energy of the oxide of the fourth element is greater than that of the oxide of the first element. In other words, the first element is more easily oxidized than the fourth element. Therefore, even if the fourth element is present in the switching layer 40, the first oxide of the first element can remain stable without being reduced.

[0110] According to the switching element of the first embodiment, low semi-selective leakage current and suppression of characteristic fluctuations can be achieved. According to the first embodiment, a memory device having a switching element with excellent characteristics can be provided.

[0111] In the switching layer 40, the ratio of the sum of the atomic concentrations of the fourth element to the sum of the atomic concentrations of the first, second, third, and fourth elements is preferably 1% or more and 10% or less. Satisfying the lower limit enables low semi-selective leakage current and suppression of characteristic fluctuations in the switching element. Satisfying the upper limit prevents the remaining fourth element from degrading the characteristics of the switching element.

[0112] In the switching layer 40, the atomic concentration of the fourth element is preferably lower than that of the second and third elements. Furthermore, the atomic concentration of the fourth element in the switching layer 40 is preferably lower than that of the first element. This helps to suppress the degradation of the switching element's characteristics caused by an excess of the fourth element.

[0113] From the viewpoint of recovering etching damage remaining on the side surface of the switching layer 40 and achieving a low semi-selective leakage current of the switching element, it is preferable that the sidewall region 42 is sufficiently oxidized. Therefore, it is preferable that the oxygen concentration in the sidewall region 42 is higher than the oxygen concentration in the internal region 41. Furthermore, it is preferable that the concentration of the fourth oxide in the sidewall region 42 is higher than the concentration of the fourth oxide in the internal region 41.

[0114] The atomic concentration of the fourth element in the sidewall region 42 is preferably higher than the atomic concentration of the fourth element in the interior region 41. According to the above embodiment, sufficient oxidation of the sidewall region 42 can be achieved. This embodiment can be achieved by the diffusion of the fourth element through oxidation treatment.

[0115] From the viewpoint of realizing a switching element with excellent properties without the presence of the second or third element as a single substance in the sidewall region 42, it is preferable that the oxidation of the fourth element proceeds more than the oxidation of the second or third element. Therefore, it is preferable that the concentration of the fourth oxide in the sidewall region 42 is higher than the concentration of the second oxide in the sidewall region 42. Furthermore, it is preferable that the concentration of the fourth oxide in the sidewall region 42 is higher than the concentration of the third oxide in the sidewall region 42.

[0116] From the viewpoint of realizing a switching element with excellent properties, where the second or third element does not exist as an elemental substance when the second or third element is oxidized and the first compound decomposes, it is preferable that the switching layer 40 contains a second compound of the second and fourth elements, or a third compound of the third and fourth elements. The formation of the second or third compound suppresses the existence of the second or third element as an elemental substance.

[0117] Preferably, the bond energy of the second compound between the second and fourth elements, and the bond energy of the third compound between the third and fourth elements, are smaller than the bond energy of the first compound between the second and third elements. By satisfying the above conditions, the decomposition of the first compound due to bonding between the fourth and second elements or between the fourth and third elements is suppressed.

[0118] From the viewpoint of suppressing leakage current at the sidewall of the switching layer 40 and improving the characteristics of the switching element, it is preferable that the sidewall region 42 is in contact with the lower electrode 10 and the intermediate electrode 30 in the first direction.

[0119] The switching layer 40 preferably contains at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N). The inclusion of the fifth element in the switching layer 40 suppresses crystallization of the switching layer 40, thereby reducing, for example, semi-selective leakage current.

[0120] (First variation) The first modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0121] Figure 10 is a schematic cross-sectional view of a memory cell of a first modified memory device of the first embodiment. Figure 10 corresponds to Figure 2 of the first embodiment.

[0122] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0123] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0124] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0125] In the first modified memory device of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 does not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0126] As described above, according to the first modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0127] (Second variation) The second modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion and a second portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0128] Figure 11 is a schematic cross-sectional view of a memory cell of a second modified storage device of the first embodiment. Figure 11 corresponds to Figure 2 of the first embodiment.

[0129] The lower electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0130] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0131] The second part 12 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0132] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0133] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0134] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0135] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0136] In the second modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0137] As described above, according to the second modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0138] (Third variation) The third modified memory device of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer comprises a first portion, a second portion, and a fifth portion, the first portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer comprises a third portion and a fourth portion, the fourth portion comprising at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0139] Figure 12 is a schematic cross-sectional view of a memory cell of a third modified memory device of the first embodiment. Figure 12 corresponds to Figure 2 of the first embodiment.

[0140] The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

[0141] The first part 11 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first part 11 comprises, for example, a boride of the above elements. The first part 11 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0142] The second part 12 and the fifth part 13 include, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0143] The upper electrode 20 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 contains, for example, a boride of the above elements. The upper electrode 20 contains, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0144] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0145] The third part 31 includes, for example, at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

[0146] The fourth portion 32 comprises at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 comprises, for example, borides of the above elements. The fourth portion 32 comprises, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0147] In the third modified memory device of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing the degradation of the characteristics of the resistive switching element. Furthermore, since the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 do not come into contact with the switching layer 40, the desorption of oxygen (O) from the switching layer 40 is suppressed, thereby suppressing the degradation of the characteristics of the switching element.

[0148] As described above, according to the third modification of the first embodiment, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first embodiment.

[0149] According to the first embodiment and its modifications, a switching element with excellent characteristics such as low semi-selective leakage current and high reliability can be realized. Therefore, according to the first embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized.

[0150] (Second embodiment) The storage device of the second embodiment differs from the storage device of the first embodiment in that it is a resistive random-access memory (ReRAM). Some parts of the description that overlap with the first embodiment will be omitted below.

[0151] Figure 13 is a schematic cross-sectional view of a memory cell of a second embodiment of a storage device. Figure 13 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0152] As shown in Figure 13, the memory cell MC comprises a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, a resistive transition layer 50, and a sidewall insulating layer 55. The switching layer 40 includes an internal region 41, a first sidewall region 42a, and a second sidewall region 42b. The resistive transition layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b.

[0153] The lower electrode 10 is an example of the first conductive layer. The upper electrode 20 is an example of the second conductive layer. The intermediate electrode 30 is an example of the third conductive layer. The internal region 41 is an example of the first region. The first sidewall region 42a is an example of the second region. The second sidewall region 42b is an example of the third region.

[0154] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute the switching element of the memory cell MC. The intermediate electrode 30, the resistive switching layer 50, and the upper electrode 20 constitute the resistive switching element of the memory cell MC.

[0155] The configuration of the switching layer 40 is the same as that of the storage device in the first embodiment.

[0156] The resistance-changing layer 50 includes a high-resistance layer 50x and a low-resistance layer 50y.

[0157] The high-resistance layer 50x is, for example, a metal oxide. The high-resistance layer 50x is, for example, aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0158] The low-resistance layer 50y is, for example, a metal oxide. The low-resistance layer 50y is, for example, titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0159] The resistive layer 50 has the function of storing data by changing resistance. The resistive layer 50 has the characteristic that its electrical resistance changes when a predetermined voltage is applied.

[0160] By applying a voltage to the resistance-changing layer 50, the resistance-changing layer 50 changes from a high-resistance state to a low-resistance state, or from a low-resistance state to a high-resistance state. The application of voltage to the resistance-changing layer 50 causes oxygen ions to move between the high-resistance layer 50x and the low-resistance layer 50y, changing the amount of oxygen vacancies in the low-resistance layer 50y. The conductivity of the resistance-changing layer 50 changes in accordance with the amount of oxygen vacancies in the low-resistance layer 50y. The low-resistance layer 50y is a so-called vacancy-modulated conductive oxide.

[0161] For example, a high-resistance state is defined as data "1," and a low-resistance state as data "0." The memory cell MC can then store 1-bit data, either "0" or "1."

[0162] As described above, the storage device of the second embodiment can realize a switching element with excellent characteristics such as low semi-selective leakage current and high reliability, similar to the first embodiment. Therefore, the second embodiment can realize a storage device having a switching element with excellent characteristics.

[0163] (Third embodiment) The memory device of the third embodiment includes a memory cell comprising a first conductive layer, a second conductive layer, and a memory layer provided between the first conductive layer and the second conductive layer. The memory layer comprises a first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si), and at least one second element, different from the first element, selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), and a first Unlike the first and second elements, it includes at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), and unlike the first, second, and third elements, it includes at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si). The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region, the first region contains a first oxide, and the second region and the third region contain a fourth oxide of a fourth element.

[0164] Furthermore, the storage device of the third embodiment further comprises a plurality of first wirings and a plurality of second wirings that intersect with the plurality of first wirings. The memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

[0165] The third embodiment of the storage device differs from the storage devices of the first and second embodiments in that the memory cells do not include a third conductive layer and a resistive switching layer, and instead include a memory layer with the same configuration as the switching layer of the first and second embodiments. Hereafter, some descriptions that overlap with the first or second embodiment will be omitted.

[0166] Figure 14 is a schematic cross-sectional view of a memory cell of a third embodiment of a storage device. Figure 14 shows a cross-section of a single memory cell MC in the memory cell array 100 of Figure 1, indicated, for example, by a dotted circle.

[0167] As shown in Figure 14, the memory cell MC comprises a lower electrode 10, an upper electrode 20, a sidewall insulating layer 55, and a memory layer 60. The sidewall insulating layer 55 includes a first portion 55a and a second portion 55b. The memory layer 60 includes an internal region 61, a first sidewall region 62a, and a second sidewall region 62b.

[0168] The lower electrode 10 is an example of a first conductive layer. The upper electrode 20 is an example of a second conductive layer.

[0169] The lower electrode 10, the memory layer 60, and the upper electrode 20 constitute the memory element of the memory cell MC. The memory element of the memory cell MC has a switching function and a function to store information.

[0170] The memory layer 60 has the same configuration as the switching layer 40 in the first and second embodiments. The internal region 61, the first sidewall region 62a, and the second sidewall region 62b of the memory layer 60 have the same configuration as the internal region 41, the first sidewall region 42a, and the second sidewall region 42b of the switching layer 40 in the first and second embodiments, respectively.

[0171] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. Furthermore, the memory layer 60 has a characteristic in which the threshold voltage changes when a predetermined voltage is applied. The memory layer 60 also has a characteristic in which its electrical resistance changes when a predetermined voltage is applied. In the third embodiment, the high-resistance state is a state in which the resistance of the memory layer 60 is relatively high at the read voltage. Also, in the third embodiment, the low-resistance state is a state in which the resistance of the memory layer 60 is relatively low at the read voltage.

[0172] The memory layer 60 has the function of suppressing the increase in semi-selective leakage current flowing to the semi-selective cells. The memory layer 60 also has the function of storing data by resistance changes. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 in the first and second embodiments.

[0173] Figure 15 is an explanatory diagram of the current-voltage characteristics of the memory element in the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 15, the horizontal axis shows the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. Figure 15 shows the current-voltage characteristics of the memory layer 60 in the third embodiment. Figure 15 shows the current-voltage characteristics of the memory cell MC in the third embodiment.

[0174] The memory element of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 15, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0175] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0176] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0177] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0178] The memory element of the third embodiment can take on both a high-resistance state and a low-resistance state under both positive and negative voltage conditions. When a predetermined positive voltage is applied to the upper electrode 20, it enters a high-resistance state under both positive and negative voltage conditions. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a low-resistance state under both positive and negative voltage conditions. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0179] Figure 16 is an explanatory diagram of a first example of the memory operation of the storage device according to the third embodiment. Figure 16 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0180] In the first operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the first operational example, the negative side read voltage Vrn is used as the read voltage.

[0181] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0182] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0183] In the first example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0184] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0185] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0186] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0187] In the first example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the first example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0188] Figure 17 is an explanatory diagram of a second example of memory operation of the storage device according to the third embodiment. Figure 17 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0189] In the second operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the second operating example, the positive side read voltage Vrp is used as the read voltage.

[0190] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0191] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0192] In the second example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0193] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0194] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0195] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0196] In the second example of operation, if the data in the selected cell is "1", no data corruption occurs when the positive read voltage Vrp is applied. In other words, in the second example of operation, if the data in the selected cell is "1", non-destructive reading is possible.

[0197] On the other hand, if the data in the selected cell is "0", applying a positive read voltage Vrp higher than the second positive voltage threshold voltage Vtnp may cause current to flow, potentially changing the data in the selected cell to "1". In other words, in the second example of operation, if the data in the selected cell is "0", a destructive read may occur. Therefore, if the data in the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data in the selected cell in order to maintain the data in the selected cell.

[0198] (First variation) The first modified memory device of the third embodiment differs from the memory device of the third embodiment in that the current-voltage characteristics of the memory elements are different.

[0199] Figure 18 is an explanatory diagram of the current-voltage characteristics of the memory element of the first modified example of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 18, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 18 shows the current-voltage characteristics of the memory layer 60 of the first modified example of the third embodiment. Figure 18 shows the current-voltage characteristics of the memory cell MC of the first modified example of the third embodiment.

[0200] The memory element of the first modified example of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 18, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0201] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0202] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0203] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0204] The memory element of the first modification of the third embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it enters a low-resistance state on both the positive and negative voltage sides. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it enters a high-resistance state on both the positive and negative voltage sides. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0205] Figure 19 is an explanatory diagram of a third example of the memory operation of the storage device of the first modification of the third embodiment. Figure 19 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0206] In the third operational example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the third operational example, the negative side read voltage Vrn is used as the read voltage.

[0207] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0208] When writing the data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0209] In the third example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0210] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0211] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0212] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0213] In the third example of operation, if the data in the selected cell is "1", no data corruption occurs due to the application of the negative read voltage Vrn. In other words, in the third example of operation, if the data in the selected cell is "1", non-destructive readout is possible.

[0214] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the third example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0215] Figure 20 is an explanatory diagram of a fourth example of the memory operation of the storage device of the first modification of the third embodiment. Figure 20 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0216] In the fourth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the fourth operating example, the positive side read voltage Vrp is used as the read voltage.

[0217] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0218] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0219] In the fourth example of operation, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0220] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0221] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0222] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0223] In the fourth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fourth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0224] (Second variation) The second modified memory device of the third embodiment differs from the memory device of the third embodiment in that the current-voltage characteristics of the memory elements are different.

[0225] Figure 21 is an explanatory diagram of the current-voltage characteristics of a memory element in a second modified example of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 21, the horizontal axis shows the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. Figure 21 shows the current-voltage characteristics of the memory layer 60 in a second modified example of the third embodiment. Figure 21 shows the current-voltage characteristics of the memory cell MC in a second modified example of the third embodiment.

[0226] The memory element of the second modified example of the third embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 21, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0227] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0228] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0229] The first positive voltage threshold voltage Vtpp is lower than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is lower than the second negative voltage threshold voltage Vtnn.

[0230] The memory element of the second modification of the third embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0231] Figure 22 is an explanatory diagram of a fifth example of the memory operation of a storage device in the second modification of the third embodiment. Figure 22 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0232] In the fifth operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the fifth operating example, the negative side read voltage Vrn is used as the read voltage.

[0233] When writing the data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0234] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0235] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0236] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0237] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0238] In the fifth example of operation, data corruption does not occur by applying the negative read voltage Vrn, regardless of whether the data in the selected cell is "1" or "0". In other words, in the fifth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0239] Figure 23 is an explanatory diagram of a sixth example of memory operation of a storage device in the second modification of the third embodiment. Figure 23 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0240] In the sixth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the sixth operating example, the positive side read voltage Vrp is used as the read voltage.

[0241] When writing the data "1" to the selected cell, a negative writing voltage Vwn is applied to the upper electrode 20. The negative writing voltage Vwn is lower than the first negative voltage threshold voltage Vtpn. By applying the negative writing voltage Vwn to the upper electrode 20, a high resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0242] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0243] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the first positive voltage threshold voltage Vtpp. Voltage Vwn / 2 is higher than the second negative voltage threshold voltage Vtnn.

[0244] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0245] When reading data from a selected cell, a positive readout voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0246] In the sixth example of operation, data corruption does not occur by applying the positive read voltage Vrp, regardless of whether the data in the selected cell is "1" or "0". In other words, in the sixth example of operation, non-destructive reading is possible regardless of whether the data in the selected cell is "1" or "0".

[0247] (Third variation) The third modified memory device of the third embodiment differs from the memory device of the third embodiment in that the current-voltage characteristics of the memory elements are different.

[0248] Figure 24 is an explanatory diagram of the current-voltage characteristics of a memory element in a third modified example of the third embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In Figure 24, the horizontal axis shows the voltage applied to the upper electrode 20 with reference to the potential of the lower electrode 10. Figure 24 shows the current-voltage characteristics of the memory layer 60 in a third modified example of the third embodiment. Figure 24 shows the current-voltage characteristics of the memory cell MC in a third modified example of the third embodiment.

[0249] The memory element of the third modified embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Figure 24, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0250] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a first positive voltage threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a first negative voltage threshold voltage Vtpn.

[0251] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at a second positive voltage threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at a second negative voltage threshold voltage Vtnn.

[0252] The first positive voltage threshold voltage Vtpp is higher than the second positive voltage threshold voltage Vtnp. Also, the first negative voltage threshold voltage Vtpn is higher than the second negative voltage threshold voltage Vtnn.

[0253] The memory element of the third modified embodiment can take on both a high-resistance state and a low-resistance state on both the positive and negative voltage sides. When a predetermined positive voltage is applied to the upper electrode 20, it takes on a high-resistance state on the positive voltage side and a low-resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it takes on a low-resistance state on the positive voltage side and a high-resistance state on the negative voltage side. Hereinafter, the high-resistance state is defined as data "1" and the low-resistance state as data "0". The memory cell MC can store 1-bit data of "0" and "1".

[0254] Figure 25 is an explanatory diagram of a seventh example of memory operation of a storage device in a third modification of the third embodiment. Figure 25 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing memory operation.

[0255] In the seventh operating example, the high-resistance and low-resistance states on the negative voltage side are used for memory operation. In the seventh operating example, the negative side read voltage Vrn is used as the read voltage.

[0256] When writing the data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is achieved on the negative voltage side, and the data "1" is written to the selected cell.

[0257] When writing the data "0" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive-side threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a low-resistance state is achieved on the negative voltage side, and the data "0" is written to the selected cell.

[0258] In the seventh example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0259] Furthermore, in the seventh example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0260] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0261] Therefore, even when the semi-selective cell is in a low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0262] When reading data from a selected cell, a negative readout voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between the case of data "1" and the case of data "0".

[0263] In the case of the seventh operating example, if the data in the selected cell is "1", no data corruption will occur due to the application of the negative read voltage Vrn. In other words, in the case of the seventh operating example, if the data in the selected cell is "1", non-destructive readout is possible.

[0264] On the other hand, if the data of the selected cell is "0", applying a negative read voltage Vrn lower than the first negative voltage threshold voltage Vtpn may cause current to flow, potentially changing the data of the selected cell to "1". In other words, in the seventh example of operation, if the data of the selected cell is "0", a destructive read may occur. Therefore, if the data of the selected cell is "0", it may be necessary to rewrite the data to "0" after reading the data of the selected cell in order to maintain the data.

[0265] Figure 26 is an explanatory diagram of the eighth example of memory operation of a storage device in the third modified form of the third embodiment. Figure 26 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0266] In the eighth operating example, the high-resistance and low-resistance states on the positive voltage side are used for memory operation. In the eighth operating example, the positive side read voltage Vrp is used as the read voltage.

[0267] When writing the data "1" to the selected cell, a positive-side writing voltage Vwp is applied to the upper electrode 20. The positive-side writing voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive-side writing voltage Vwp to the upper electrode 20, a high-resistance state is achieved on the positive voltage side, and the data "1" is written to the selected cell.

[0268] When writing the data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is achieved on the positive voltage side, and the data "0" is written to the selected cell.

[0269] In the eighth example of operation, when writing data "1" to the selected cell, if the data stored in the selected cell is data "0", current will flow even if the positive write voltage Vwp is lower than the first positive voltage threshold voltage Vtpp, as long as it is higher than the second positive voltage threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Accordingly, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage threshold voltage Vtnp and the first positive voltage threshold voltage Vtpp, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0270] Furthermore, in the eighth example of operation, when writing data "0" to the selected cell, if the data stored in the selected cell is data "1", current will flow even if the negative write voltage Vwn is higher than the second negative voltage threshold voltage Vtnn, as long as it is lower than the first negative voltage threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Accordingly, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage threshold voltage Vtnn and the first negative voltage threshold voltage Vtpn, it is possible to achieve lower power consumption or higher reliability of the memory device.

[0271] When the positive write voltage Vwp is applied to the selected cell, the voltage Vwp / 2 is applied to the semi-selected cell. Similarly, when the negative write voltage Vwn is applied to the selected cell, the voltage Vwn / 2 is applied to the semi-selected cell. Voltage Vwp / 2 is lower than the second positive voltage threshold voltage Vtnp. Voltage Vwn / 2 is higher than the first negative voltage threshold voltage Vtpn.

[0272] Therefore, even when the semi-selective cell is in the low-resistance state, the semi-selective leakage current flowing through the semi-selective cell can be suppressed. Thus, the memory element also functions as a switching element.

[0273] When reading the data of the selective cell, a positive-side read voltage Vrp is applied to the selective cell. The data of the selective cell can be determined by detecting a current change or a potential change caused by the difference in the current flowing between the case of data "1" and the case of data "0".

[0274] In addition, in the case of the eighth operation example, when the data of the selective cell is data "1", data destruction does not occur by applying the positive-side read voltage Vrp. In other words, in the case of the eighth operation example, non-destructive reading is possible if the data of the selective cell is data "1".

[0275] On the other hand, when the data of the selective cell is data "0", by applying a positive-side read voltage Vrp higher than the second positive voltage-side threshold voltage Vtnp, a current may flow and the data of the selective cell may change to data "1". In other words, in the case of the eighth operation example, when the data of the selective cell is data "0", there is a possibility of destructive reading. Therefore, when the data of the selective cell is data "0", after reading the data of the selective cell, in order to maintain the data of the selective cell, it may be necessary to rewrite the data "0".

[0276] In the memory device of the third embodiment and its modified example, the memory element of the memory cell MC has a switching function and a function of storing information. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment and the second embodiment. By the memory layer 60 of the third embodiment being a single layer and having a switching function and a memory function, the structure of the memory cell MC can be made extremely simple.

[0277] Furthermore, the memory layer 60 of the storage device in the third embodiment and its modified form has the same configuration as the switching layer 40 of the first and second embodiments. Therefore, according to the third embodiment and its modified form, a storage device with excellent switching characteristics such as low semi-selective leakage current and high reliability can be realized, similar to the first and second embodiments.

[0278] Furthermore, the multiple current-voltage characteristics of the memory element shown in the third embodiment and its modified form can be achieved, for example, by employing a memory layer 60 having an appropriate chemical composition.

[0279] In the first embodiment, a magnetoresistive memory was described as a two-terminal storage device, and in the second embodiment, a resistive random-access memory was described as an example of a storage device. However, the present invention can be applied to other two-terminal storage devices. For example, the present invention can be applied to phase-change memory (PCM) or ferroelectric random-access memory (FeRAM).

[0280] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0281] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 40 Switching Layer 41. Internal region (first region) 42a First side wall region (second region) 42b Second side wall region (third region) 50 Resistivity change layer 55. Sidewall insulating layer (insulating layer) 55a Part 1 55b Part 2 60 memory layers 61. Internal region (first region) 62a First side wall region (second region) 62b Second sidewall region (third region) 102 Word line (first wiring) 103-bit line (second wiring) MC memory cell

Claims

1. A first conductive layer and A second conductive layer, A third conductive layer is provided between the first conductive layer and the second conductive layer, A switching layer provided between the first conductive layer and the third conductive layer, A memory cell comprising a resistive change layer provided between the third conductive layer and the second conductive layer, The aforementioned switching layer is A first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si), Unlike the first element, at least one second element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), Unlike the first and second elements, at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), Unlike the first element, the second element, and the third element, it includes at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), The switching layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. A memory device wherein the first region contains the first oxide, and the second and third regions contain the fourth oxide of the fourth element.

2. The storage device according to claim 1, wherein the first region contains or does not contain the fourth oxide, and the concentration of the fourth oxide in the second region and the concentration of the fourth oxide in the third region are higher than the concentration of the fourth oxide in the first region.

3. The second region may or may not contain the second oxide of the second element, and the concentration of the fourth oxide in the second region is higher than the concentration of the second oxide in the second region. The second region may or may not contain the third oxide of the third element, and the concentration of the fourth oxide in the second region is higher than the concentration of the third oxide in the second region. The third region may or may not contain the second oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the second oxide in the third region. The storage device according to claim 1, wherein the third region may or may not contain the third oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the third oxide in the third region.

4. The storage device according to claim 1, wherein the ratio of the atomic concentration of the fourth element to the sum of the atomic concentrations of the first element, the second element, the third element, and the fourth element in the switching layer is 1% or more and 20% or less.

5. The storage device according to claim 1, wherein the atomic concentration of the fourth element in the second region and the atomic concentration of the fourth element in the third region are higher than the atomic concentration of the fourth element in the first region.

6. The storage device according to claim 1, wherein the switching layer comprises a first compound of the second element and the third element.

7. The storage device according to claim 1, wherein the switching layer comprises a second compound of the second element and the fourth element, or a third compound of the third element and the fourth element.

8. When the first region contains the second compound, The second region may or may not contain the second compound, and the concentration of the second compound in the second region is lower than the concentration of the second compound in the first region. The third region may or may not contain the second compound, and the concentration of the second compound in the third region is lower than the concentration of the second compound in the first region. When the first region contains the third compound, The second region may or may not contain the third compound, and the concentration of the third compound in the second region is lower than the concentration of the third compound in the first region. The storage device according to claim 7, wherein the third region contains or does not contain the third compound, and the concentration of the third compound in the third region is lower than the concentration of the third compound in the first region.

9. The storage device according to claim 1, wherein the atomic concentration of the fourth element in the switching layer is lower than the atomic concentration of the second element and the atomic concentration of the third element.

10. The memory device according to claim 1, wherein the atomic concentration of the fourth element in the switching layer is lower than the atomic concentration of the first element.

11. The storage device according to claim 1, wherein the switching layer further comprises at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N), in contrast to the first element, the second element, the third element, and the fourth element.

12. The storage device according to claim 1, wherein the second region and the third region are provided between the first conductive layer and the third conductive layer in the first direction.

13. The storage device according to claim 1, wherein the oxygen concentration in the second region and the oxygen concentration in the third region are higher than the oxygen concentration in the first region.

14. The storage device according to claim 1, wherein the length of the cross-section of the second region and the third region in the second direction is 0.5 nm or more and 5 nm or less.

15. Further comprising an insulating layer including the first part and the second part, In the second direction of the cross-section, the first conductive layer, the third conductive layer, and the switching layer are provided between the first portion and the second portion. The storage device according to claim 1, wherein the second region is in contact with the first portion, and the third region is in contact with the second portion.

16. The memory device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, tungsten nitride, titanium, titanium nitride, tantalum, tantalum carbide, and tantalum nitride.

17. The storage device according to claim 1, wherein the first conductive layer, the second conductive layer, or the third conductive layer comprises at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

18. The storage device according to claim 1, wherein the resistance change layer includes a magnetic tunnel junction.

19. The resistance-changing layer changes in electrical resistance when a predetermined voltage is applied. The storage device according to claim 1, wherein the switching layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage.

20. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The memory device according to claim 1, wherein the memory cell is provided in a region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

21. A first conductive layer and A second conductive layer, A memory cell comprising a memory layer provided between the first conductive layer and the second conductive layer, The aforementioned memory layer is A first oxide of at least one first element selected from the group consisting of magnesium (Mg), yttrium (Y), lanthanum (La), cerium (Ce), zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and silicon (Si), Unlike the first element, at least one second element selected from the group consisting of zinc (Zn), gallium (Ga), indium (In), tin (Sn), and bismuth (Bi), Unlike the first and second elements, at least one third element selected from the group consisting of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), sulfur (S), selenium (Se), and tellurium (Te), Unlike the first element, the second element, and the third element, it includes at least one fourth element selected from the group consisting of vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), boron (B), gallium (Ga), and silicon (Si), The memory layer includes a first region, a second region, and a third region in a cross-section parallel to a first direction connecting the first conductive layer and the second conductive layer, and in a second direction perpendicular to the first direction of the cross-section, the first region is provided between the second region and the third region. A memory device wherein the first region contains the first oxide, and the second and third regions contain the fourth oxide of the fourth element.

22. The storage device according to claim 21, wherein the first region contains or does not contain the fourth oxide, and the concentration of the fourth oxide in the second region and the concentration of the fourth oxide in the third region are higher than the concentration of the fourth oxide in the first region.

23. The second region may or may not contain the second oxide of the second element, and the concentration of the fourth oxide in the second region is higher than the concentration of the second oxide in the second region. The second region may or may not contain the third oxide of the third element, and the concentration of the fourth oxide in the second region is higher than the concentration of the third oxide in the second region. The third region may or may not contain the second oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the second oxide in the third region. The storage device according to claim 21, wherein the third region may or may not contain the third oxide, and the concentration of the fourth oxide in the third region is higher than the concentration of the third oxide in the third region.

24. The storage device according to claim 21, wherein the ratio of the atomic concentration of the fourth element to the sum of the atomic concentrations of the first element, the second element, the third element, and the fourth element in the memory layer is 1% or more and 20% or less.

25. The storage device according to claim 21, wherein the atomic concentration of the fourth element in the second region and the atomic concentration of the fourth element in the third region are higher than the atomic concentration of the fourth element in the first region.

26. The memory device according to claim 21, wherein the memory layer comprises a first compound of the second element and the third element.

27. The memory device according to claim 21, wherein the memory layer comprises a second compound of the second element and the fourth element, or a third compound of the third element and the fourth element.

28. When the first region contains the second compound, The second region may or may not contain the second compound, and the concentration of the second compound in the second region is lower than the concentration of the second compound in the first region. The third region may or may not contain the second compound, and the concentration of the second compound in the third region is lower than the concentration of the second compound in the first region. When the first region contains the third compound, The second region may or may not contain the third compound, and the concentration of the third compound in the second region is lower than the concentration of the third compound in the first region. The storage device according to claim 27, wherein the third region contains or does not contain the third compound, and the concentration of the third compound in the third region is lower than the concentration of the third compound in the first region.

29. The storage device according to claim 21, wherein the atomic concentration of the fourth element in the memory layer is lower than the atomic concentration of the second element and the atomic concentration of the third element.

30. The memory device according to claim 21, wherein the atomic concentration of the fourth element in the memory layer is lower than the atomic concentration of the first element.

31. The memory device according to claim 21, wherein the memory layer further comprises at least one fifth element selected from the group consisting of carbon (C), boron (B), and nitrogen (N), which is different from the first element, the second element, the third element, and the fourth element.

32. The storage device according to claim 21, wherein the second region and the third region are provided between the first conductive layer and the second conductive layer in the first direction.

33. The storage device according to claim 21, wherein the oxygen concentration in the second region and the oxygen concentration in the third region are higher than the oxygen concentration in the first region.

34. The storage device according to claim 21, wherein the length of the cross-section of the second region and the third region in the second direction is 0.5 nm or more and 5 nm or less.

35. The memory layer has a nonlinear current-voltage characteristic in which the current rises at a specific threshold voltage, and the threshold voltage changes when a predetermined voltage is applied, as described in claim 21.

36. Multiple first wires and The system further comprises a plurality of second wirings that intersect with the plurality of first wirings, The storage device according to claim 21, wherein the memory cell is provided in the region where one of the plurality of first wirings and one of the plurality of second wirings intersect.

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